2 * drivers/video/cirrusfb.c - driver for Cirrus Logic chipsets
4 * Copyright 1999-2001 Jeff Garzik <jgarzik@pobox.com>
6 * Contributors (thanks, all!)
9 * Overhaul for Linux 2.6
12 * Major contributions; Motorola PowerStack (PPC and PCI) support,
13 * GD54xx, 1280x1024 mode support, change MCLK based on VCLK.
16 * Excellent code review.
19 * Amiga updates and testing.
21 * Original cirrusfb author: Frank Neumann
23 * Based on retz3fb.c and cirrusfb.c:
24 * Copyright (C) 1997 Jes Sorensen
25 * Copyright (C) 1996 Frank Neumann
27 ***************************************************************
29 * Format this code with GNU indent '-kr -i8 -pcs' options.
31 * This file is subject to the terms and conditions of the GNU General Public
32 * License. See the file COPYING in the main directory of this archive
37 #include <linux/module.h>
38 #include <linux/kernel.h>
39 #include <linux/errno.h>
40 #include <linux/string.h>
42 #include <linux/slab.h>
43 #include <linux/delay.h>
45 #include <linux/init.h>
46 #include <asm/pgtable.h>
49 #include <linux/zorro.h>
52 #include <linux/pci.h>
55 #include <asm/amigahw.h>
57 #ifdef CONFIG_PPC_PREP
58 #include <asm/machdep.h>
59 #define isPReP machine_is(prep)
64 #include <video/vga.h>
65 #include <video/cirrus.h>
67 /*****************************************************************
69 * debugging and utility macros
73 /* disable runtime assertions? */
74 /* #define CIRRUSFB_NDEBUG */
76 /* debugging assertions */
77 #ifndef CIRRUSFB_NDEBUG
78 #define assert(expr) \
80 printk("Assertion failed! %s,%s,%s,line=%d\n", \
81 #expr, __FILE__, __func__, __LINE__); \
87 #define MB_ (1024 * 1024)
89 /*****************************************************************
102 BT_PICASSO4, /* GD5446 */
103 BT_ALPINE, /* GD543x/4x */
105 BT_LAGUNA, /* GD546x */
109 * per-board-type information, used for enumerating and abstracting
110 * chip-specific information
111 * NOTE: MUST be in the same order as enum cirrus_board in order to
112 * use direct indexing on this array
113 * NOTE: '__initdata' cannot be used as some of this info
114 * is required at runtime. Maybe separate into an init-only and
117 static const struct cirrusfb_board_info_rec {
118 char *name; /* ASCII name of chipset */
119 long maxclock[5]; /* maximum video clock */
120 /* for 1/4bpp, 8bpp 15/16bpp, 24bpp, 32bpp - numbers from xorg code */
121 bool init_sr07 : 1; /* init SR07 during init_vgachip() */
122 bool init_sr1f : 1; /* write SR1F during init_vgachip() */
123 /* construct bit 19 of screen start address */
124 bool scrn_start_bit19 : 1;
126 /* initial SR07 value, then for each mode */
128 unsigned char sr07_1bpp;
129 unsigned char sr07_1bpp_mux;
130 unsigned char sr07_8bpp;
131 unsigned char sr07_8bpp_mux;
133 unsigned char sr1f; /* SR1F VGA initial register value */
134 } cirrusfb_board_info[] = {
139 /* the SD64/P4 have a higher max. videoclock */
140 135100, 135100, 85500, 85500, 0
144 .scrn_start_bit19 = true,
151 .name = "CL Piccolo",
154 90000, 90000, 90000, 90000, 90000
158 .scrn_start_bit19 = false,
165 .name = "CL Picasso",
168 90000, 90000, 90000, 90000, 90000
172 .scrn_start_bit19 = false,
179 .name = "CL Spectrum",
182 90000, 90000, 90000, 90000, 90000
186 .scrn_start_bit19 = false,
193 .name = "CL Picasso4",
195 135100, 135100, 85500, 85500, 0
199 .scrn_start_bit19 = true,
208 /* for the GD5430. GD5446 can do more... */
209 85500, 85500, 50000, 28500, 0
213 .scrn_start_bit19 = true,
216 .sr07_1bpp_mux = 0xA7,
218 .sr07_8bpp_mux = 0xA7,
224 135100, 200000, 200000, 135100, 135100
228 .scrn_start_bit19 = true,
238 135100, 135100, 135100, 135100, 135100,
242 .scrn_start_bit19 = true,
247 #define CHIP(id, btype) \
248 { PCI_VENDOR_ID_CIRRUS, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (btype) }
250 static struct pci_device_id cirrusfb_pci_table[] = {
251 CHIP(PCI_DEVICE_ID_CIRRUS_5436, BT_ALPINE),
252 CHIP(PCI_DEVICE_ID_CIRRUS_5434_8, BT_ALPINE),
253 CHIP(PCI_DEVICE_ID_CIRRUS_5434_4, BT_ALPINE),
254 CHIP(PCI_DEVICE_ID_CIRRUS_5430, BT_ALPINE), /* GD-5440 is same id */
255 CHIP(PCI_DEVICE_ID_CIRRUS_7543, BT_ALPINE),
256 CHIP(PCI_DEVICE_ID_CIRRUS_7548, BT_ALPINE),
257 CHIP(PCI_DEVICE_ID_CIRRUS_5480, BT_GD5480), /* MacPicasso likely */
258 CHIP(PCI_DEVICE_ID_CIRRUS_5446, BT_PICASSO4), /* Picasso 4 is 5446 */
259 CHIP(PCI_DEVICE_ID_CIRRUS_5462, BT_LAGUNA), /* CL Laguna */
260 CHIP(PCI_DEVICE_ID_CIRRUS_5464, BT_LAGUNA), /* CL Laguna 3D */
261 CHIP(PCI_DEVICE_ID_CIRRUS_5465, BT_LAGUNA), /* CL Laguna 3DA*/
264 MODULE_DEVICE_TABLE(pci, cirrusfb_pci_table);
266 #endif /* CONFIG_PCI */
269 static const struct zorro_device_id cirrusfb_zorro_table[] = {
271 .id = ZORRO_PROD_HELFRICH_SD64_RAM,
272 .driver_data = BT_SD64,
274 .id = ZORRO_PROD_HELFRICH_PICCOLO_RAM,
275 .driver_data = BT_PICCOLO,
277 .id = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_II_II_PLUS_RAM,
278 .driver_data = BT_PICASSO,
280 .id = ZORRO_PROD_GVP_EGS_28_24_SPECTRUM_RAM,
281 .driver_data = BT_SPECTRUM,
283 .id = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_IV_Z3,
284 .driver_data = BT_PICASSO4,
289 static const struct {
292 } cirrusfb_zorro_table2[] = {
294 .id2 = ZORRO_PROD_HELFRICH_SD64_REG,
298 .id2 = ZORRO_PROD_HELFRICH_PICCOLO_REG,
302 .id2 = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_II_II_PLUS_REG,
306 .id2 = ZORRO_PROD_GVP_EGS_28_24_SPECTRUM_REG,
314 #endif /* CONFIG_ZORRO */
316 struct cirrusfb_regs {
320 #ifdef CIRRUSFB_DEBUG
321 enum cirrusfb_dbg_reg_class {
325 #endif /* CIRRUSFB_DEBUG */
327 /* info about board */
328 struct cirrusfb_info {
330 enum cirrus_board btype;
331 unsigned char SFR; /* Shadow of special function register */
333 struct cirrusfb_regs currentmode;
335 u32 pseudo_palette[16];
337 void (*unmap)(struct fb_info *info);
340 static int noaccel __devinitdata;
341 static char *mode_option __devinitdata = "640x480@60";
343 /****************************************************************************/
344 /**** BEGIN PROTOTYPES ******************************************************/
346 /*--- Interface used by the world ------------------------------------------*/
347 static int cirrusfb_init(void);
349 static int cirrusfb_setup(char *options);
352 static int cirrusfb_open(struct fb_info *info, int user);
353 static int cirrusfb_release(struct fb_info *info, int user);
354 static int cirrusfb_setcolreg(unsigned regno, unsigned red, unsigned green,
355 unsigned blue, unsigned transp,
356 struct fb_info *info);
357 static int cirrusfb_check_var(struct fb_var_screeninfo *var,
358 struct fb_info *info);
359 static int cirrusfb_set_par(struct fb_info *info);
360 static int cirrusfb_pan_display(struct fb_var_screeninfo *var,
361 struct fb_info *info);
362 static int cirrusfb_blank(int blank_mode, struct fb_info *info);
363 static void cirrusfb_fillrect(struct fb_info *info,
364 const struct fb_fillrect *region);
365 static void cirrusfb_copyarea(struct fb_info *info,
366 const struct fb_copyarea *area);
367 static void cirrusfb_imageblit(struct fb_info *info,
368 const struct fb_image *image);
370 /* function table of the above functions */
371 static struct fb_ops cirrusfb_ops = {
372 .owner = THIS_MODULE,
373 .fb_open = cirrusfb_open,
374 .fb_release = cirrusfb_release,
375 .fb_setcolreg = cirrusfb_setcolreg,
376 .fb_check_var = cirrusfb_check_var,
377 .fb_set_par = cirrusfb_set_par,
378 .fb_pan_display = cirrusfb_pan_display,
379 .fb_blank = cirrusfb_blank,
380 .fb_fillrect = cirrusfb_fillrect,
381 .fb_copyarea = cirrusfb_copyarea,
382 .fb_imageblit = cirrusfb_imageblit,
385 /*--- Internal routines ----------------------------------------------------*/
386 static void init_vgachip(struct fb_info *info);
387 static void switch_monitor(struct cirrusfb_info *cinfo, int on);
388 static void WGen(const struct cirrusfb_info *cinfo,
389 int regnum, unsigned char val);
390 static unsigned char RGen(const struct cirrusfb_info *cinfo, int regnum);
391 static void AttrOn(const struct cirrusfb_info *cinfo);
392 static void WHDR(const struct cirrusfb_info *cinfo, unsigned char val);
393 static void WSFR(struct cirrusfb_info *cinfo, unsigned char val);
394 static void WSFR2(struct cirrusfb_info *cinfo, unsigned char val);
395 static void WClut(struct cirrusfb_info *cinfo, unsigned char regnum,
396 unsigned char red, unsigned char green, unsigned char blue);
398 static void RClut(struct cirrusfb_info *cinfo, unsigned char regnum,
399 unsigned char *red, unsigned char *green,
400 unsigned char *blue);
402 static void cirrusfb_WaitBLT(u8 __iomem *regbase);
403 static void cirrusfb_BitBLT(u8 __iomem *regbase, int bits_per_pixel,
404 u_short curx, u_short cury,
405 u_short destx, u_short desty,
406 u_short width, u_short height,
407 u_short line_length);
408 static void cirrusfb_RectFill(u8 __iomem *regbase, int bits_per_pixel,
409 u_short x, u_short y,
410 u_short width, u_short height,
411 u_char color, u_short line_length);
413 static void bestclock(long freq, int *nom, int *den, int *div);
415 #ifdef CIRRUSFB_DEBUG
416 static void cirrusfb_dbg_reg_dump(struct fb_info *info, caddr_t regbase);
417 static void cirrusfb_dbg_print_regs(struct fb_info *info,
419 enum cirrusfb_dbg_reg_class reg_class, ...);
420 #endif /* CIRRUSFB_DEBUG */
422 /*** END PROTOTYPES ********************************************************/
423 /*****************************************************************************/
424 /*** BEGIN Interface Used by the World ***************************************/
426 static int opencount;
428 /*--- Open /dev/fbx ---------------------------------------------------------*/
429 static int cirrusfb_open(struct fb_info *info, int user)
431 if (opencount++ == 0)
432 switch_monitor(info->par, 1);
436 /*--- Close /dev/fbx --------------------------------------------------------*/
437 static int cirrusfb_release(struct fb_info *info, int user)
439 if (--opencount == 0)
440 switch_monitor(info->par, 0);
444 /**** END Interface used by the World *************************************/
445 /****************************************************************************/
446 /**** BEGIN Hardware specific Routines **************************************/
448 /* Check if the MCLK is not a better clock source */
449 static int cirrusfb_check_mclk(struct fb_info *info, long freq)
451 struct cirrusfb_info *cinfo = info->par;
452 long mclk = vga_rseq(cinfo->regbase, CL_SEQR1F) & 0x3f;
454 /* Read MCLK value */
455 mclk = (14318 * mclk) >> 3;
456 dev_dbg(info->device, "Read MCLK of %ld kHz\n", mclk);
458 /* Determine if we should use MCLK instead of VCLK, and if so, what we
459 * should divide it by to get VCLK
462 if (abs(freq - mclk) < 250) {
463 dev_dbg(info->device, "Using VCLK = MCLK\n");
465 } else if (abs(freq - (mclk / 2)) < 250) {
466 dev_dbg(info->device, "Using VCLK = MCLK/2\n");
473 static int cirrusfb_check_var(struct fb_var_screeninfo *var,
474 struct fb_info *info)
477 /* memory size in pixels */
478 unsigned pixels = info->screen_size * 8 / var->bits_per_pixel;
480 switch (var->bits_per_pixel) {
484 var->green = var->red;
485 var->blue = var->red;
491 var->green = var->red;
492 var->blue = var->red;
498 var->green.offset = -3;
499 var->blue.offset = 8;
501 var->red.offset = 10;
502 var->green.offset = 5;
503 var->blue.offset = 0;
506 var->green.length = 5;
507 var->blue.length = 5;
513 var->green.offset = 16;
514 var->blue.offset = 24;
516 var->red.offset = 16;
517 var->green.offset = 8;
518 var->blue.offset = 0;
521 var->green.length = 8;
522 var->blue.length = 8;
526 dev_dbg(info->device,
527 "Unsupported bpp size: %d\n", var->bits_per_pixel);
529 /* should never occur */
533 if (var->xres_virtual < var->xres)
534 var->xres_virtual = var->xres;
535 /* use highest possible virtual resolution */
536 if (var->yres_virtual == -1) {
537 var->yres_virtual = pixels / var->xres_virtual;
539 dev_info(info->device,
540 "virtual resolution set to maximum of %dx%d\n",
541 var->xres_virtual, var->yres_virtual);
543 if (var->yres_virtual < var->yres)
544 var->yres_virtual = var->yres;
546 if (var->xres_virtual * var->yres_virtual > pixels) {
547 dev_err(info->device, "mode %dx%dx%d rejected... "
548 "virtual resolution too high to fit into video memory!\n",
549 var->xres_virtual, var->yres_virtual,
550 var->bits_per_pixel);
555 if (var->xoffset < 0)
557 if (var->yoffset < 0)
560 /* truncate xoffset and yoffset to maximum if too high */
561 if (var->xoffset > var->xres_virtual - var->xres)
562 var->xoffset = var->xres_virtual - var->xres - 1;
563 if (var->yoffset > var->yres_virtual - var->yres)
564 var->yoffset = var->yres_virtual - var->yres - 1;
567 var->green.msb_right =
568 var->blue.msb_right =
571 var->transp.msb_right = 0;
574 if (var->vmode & FB_VMODE_DOUBLE)
576 else if (var->vmode & FB_VMODE_INTERLACED)
577 yres = (yres + 1) / 2;
580 dev_err(info->device, "ERROR: VerticalTotal >= 1280; "
581 "special treatment required! (TODO)\n");
588 static int cirrusfb_decode_var(const struct fb_var_screeninfo *var,
589 struct cirrusfb_regs *regs,
590 struct fb_info *info)
594 int maxclockidx = var->bits_per_pixel >> 3;
595 struct cirrusfb_info *cinfo = info->par;
597 switch (var->bits_per_pixel) {
599 info->fix.line_length = var->xres_virtual / 8;
600 info->fix.visual = FB_VISUAL_MONO10;
604 info->fix.line_length = var->xres_virtual;
605 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
610 info->fix.line_length = var->xres_virtual * maxclockidx;
611 info->fix.visual = FB_VISUAL_TRUECOLOR;
615 dev_dbg(info->device,
616 "Unsupported bpp size: %d\n", var->bits_per_pixel);
618 /* should never occur */
622 info->fix.type = FB_TYPE_PACKED_PIXELS;
624 /* convert from ps to kHz */
625 freq = PICOS2KHZ(var->pixclock);
627 dev_dbg(info->device, "desired pixclock: %ld kHz\n", freq);
629 maxclock = cirrusfb_board_info[cinfo->btype].maxclock[maxclockidx];
630 regs->multiplexing = 0;
632 /* If the frequency is greater than we can support, we might be able
633 * to use multiplexing for the video mode */
634 if (freq > maxclock) {
635 switch (cinfo->btype) {
638 regs->multiplexing = 1;
642 dev_err(info->device,
643 "Frequency greater than maxclock (%ld kHz)\n",
649 /* TODO: If we have a 1MB 5434, we need to put ourselves in a mode where
650 * the VCLK is double the pixel clock. */
651 switch (var->bits_per_pixel) {
654 if (var->xres <= 800)
655 /* Xbh has this type of clock for 32-bit */
663 static void cirrusfb_set_mclk_as_source(const struct fb_info *info, int div)
665 struct cirrusfb_info *cinfo = info->par;
666 unsigned char old1f, old1e;
668 assert(cinfo != NULL);
669 old1f = vga_rseq(cinfo->regbase, CL_SEQR1F) & ~0x40;
672 dev_dbg(info->device, "Set %s as pixclock source.\n",
673 (div == 2) ? "MCLK/2" : "MCLK");
675 old1e = vga_rseq(cinfo->regbase, CL_SEQR1E) & ~0x1;
679 vga_wseq(cinfo->regbase, CL_SEQR1E, old1e);
681 vga_wseq(cinfo->regbase, CL_SEQR1F, old1f);
684 /*************************************************************************
685 cirrusfb_set_par_foo()
687 actually writes the values for a new video mode into the hardware,
688 **************************************************************************/
689 static int cirrusfb_set_par_foo(struct fb_info *info)
691 struct cirrusfb_info *cinfo = info->par;
692 struct fb_var_screeninfo *var = &info->var;
693 struct cirrusfb_regs regs;
694 u8 __iomem *regbase = cinfo->regbase;
697 const struct cirrusfb_board_info_rec *bi;
698 int hdispend, hsyncstart, hsyncend, htotal;
699 int yres, vdispend, vsyncstart, vsyncend, vtotal;
703 dev_dbg(info->device, "Requested mode: %dx%dx%d\n",
704 var->xres, var->yres, var->bits_per_pixel);
705 dev_dbg(info->device, "pixclock: %d\n", var->pixclock);
709 err = cirrusfb_decode_var(var, ®s, info);
711 /* should never happen */
712 dev_dbg(info->device, "mode change aborted. invalid var.\n");
716 bi = &cirrusfb_board_info[cinfo->btype];
718 hsyncstart = var->xres + var->right_margin;
719 hsyncend = hsyncstart + var->hsync_len;
720 htotal = (hsyncend + var->left_margin) / 8 - 5;
721 hdispend = var->xres / 8 - 1;
722 hsyncstart = hsyncstart / 8 + 1;
723 hsyncend = hsyncend / 8 + 1;
726 vsyncstart = yres + var->lower_margin;
727 vsyncend = vsyncstart + var->vsync_len;
728 vtotal = vsyncend + var->upper_margin;
731 if (var->vmode & FB_VMODE_DOUBLE) {
736 } else if (var->vmode & FB_VMODE_INTERLACED) {
737 yres = (yres + 1) / 2;
738 vsyncstart = (vsyncstart + 1) / 2;
739 vsyncend = (vsyncend + 1) / 2;
740 vtotal = (vtotal + 1) / 2;
753 if (regs.multiplexing) {
759 /* unlock register VGA_CRTC_H_TOTAL..CRT7 */
760 vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, 0x20); /* previously: 0x00) */
762 /* if debugging is enabled, all parameters get output before writing */
763 dev_dbg(info->device, "CRT0: %d\n", htotal);
764 vga_wcrt(regbase, VGA_CRTC_H_TOTAL, htotal);
766 dev_dbg(info->device, "CRT1: %d\n", hdispend);
767 vga_wcrt(regbase, VGA_CRTC_H_DISP, hdispend);
769 dev_dbg(info->device, "CRT2: %d\n", var->xres / 8);
770 vga_wcrt(regbase, VGA_CRTC_H_BLANK_START, var->xres / 8);
772 /* + 128: Compatible read */
773 dev_dbg(info->device, "CRT3: 128+%d\n", (htotal + 5) % 32);
774 vga_wcrt(regbase, VGA_CRTC_H_BLANK_END,
775 128 + ((htotal + 5) % 32));
777 dev_dbg(info->device, "CRT4: %d\n", hsyncstart);
778 vga_wcrt(regbase, VGA_CRTC_H_SYNC_START, hsyncstart);
781 if ((htotal + 5) & 32)
783 dev_dbg(info->device, "CRT5: %d\n", tmp);
784 vga_wcrt(regbase, VGA_CRTC_H_SYNC_END, tmp);
786 dev_dbg(info->device, "CRT6: %d\n", vtotal & 0xff);
787 vga_wcrt(regbase, VGA_CRTC_V_TOTAL, vtotal & 0xff);
789 tmp = 16; /* LineCompare bit #9 */
794 if (vsyncstart & 256)
796 if ((vdispend + 1) & 256)
802 if (vsyncstart & 512)
804 dev_dbg(info->device, "CRT7: %d\n", tmp);
805 vga_wcrt(regbase, VGA_CRTC_OVERFLOW, tmp);
807 tmp = 0x40; /* LineCompare bit #8 */
808 if ((vdispend + 1) & 512)
810 if (var->vmode & FB_VMODE_DOUBLE)
812 dev_dbg(info->device, "CRT9: %d\n", tmp);
813 vga_wcrt(regbase, VGA_CRTC_MAX_SCAN, tmp);
815 dev_dbg(info->device, "CRT10: %d\n", vsyncstart & 0xff);
816 vga_wcrt(regbase, VGA_CRTC_V_SYNC_START, vsyncstart & 0xff);
818 dev_dbg(info->device, "CRT11: 64+32+%d\n", vsyncend % 16);
819 vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, vsyncend % 16 + 64 + 32);
821 dev_dbg(info->device, "CRT12: %d\n", vdispend & 0xff);
822 vga_wcrt(regbase, VGA_CRTC_V_DISP_END, vdispend & 0xff);
824 dev_dbg(info->device, "CRT15: %d\n", (vdispend + 1) & 0xff);
825 vga_wcrt(regbase, VGA_CRTC_V_BLANK_START, (vdispend + 1) & 0xff);
827 dev_dbg(info->device, "CRT16: %d\n", vtotal & 0xff);
828 vga_wcrt(regbase, VGA_CRTC_V_BLANK_END, vtotal & 0xff);
830 dev_dbg(info->device, "CRT18: 0xff\n");
831 vga_wcrt(regbase, VGA_CRTC_LINE_COMPARE, 0xff);
834 if (var->vmode & FB_VMODE_INTERLACED)
836 if ((htotal + 5) & 64)
838 if ((htotal + 5) & 128)
845 dev_dbg(info->device, "CRT1a: %d\n", tmp);
846 vga_wcrt(regbase, CL_CRT1A, tmp);
848 freq = PICOS2KHZ(var->pixclock);
849 bestclock(freq, &nom, &den, &div);
851 dev_dbg(info->device, "VCLK freq: %ld kHz nom: %d den: %d div: %d\n",
852 freq, nom, den, div);
855 /* hardware RefClock: 14.31818 MHz */
856 /* formula: VClk = (OSC * N) / (D * (1+P)) */
857 /* Example: VClk = (14.31818 * 91) / (23 * (1+1)) = 28.325 MHz */
859 if (cinfo->btype == BT_ALPINE) {
860 /* if freq is close to mclk or mclk/2 select mclk
863 int divMCLK = cirrusfb_check_mclk(info, freq);
866 cirrusfb_set_mclk_as_source(info, divMCLK);
873 /* 6 bit denom; ONLY 5434!!! (bugged me 10 days) */
874 if ((cinfo->btype == BT_SD64) ||
875 (cinfo->btype == BT_ALPINE) ||
876 (cinfo->btype == BT_GD5480))
879 dev_dbg(info->device, "CL_SEQR1B: %d\n", (int) tmp);
880 /* Laguna chipset has reversed clock registers */
881 if (cinfo->btype == BT_LAGUNA) {
882 vga_wseq(regbase, CL_SEQRE, tmp);
883 vga_wseq(regbase, CL_SEQR1E, nom);
885 vga_wseq(regbase, CL_SEQRB, nom);
886 vga_wseq(regbase, CL_SEQR1B, tmp);
892 vga_wcrt(regbase, VGA_CRTC_MODE, 0xc7);
894 /* mode control: VGA_CRTC_START_HI enable, ROTATE(?), 16bit
895 * address wrap, no compat. */
896 vga_wcrt(regbase, VGA_CRTC_MODE, 0xc3);
898 /* HAEH? vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, 0x20);
899 * previously: 0x00 unlock VGA_CRTC_H_TOTAL..CRT7 */
901 /* don't know if it would hurt to also program this if no interlaced */
902 /* mode is used, but I feel better this way.. :-) */
903 if (var->vmode & FB_VMODE_INTERLACED)
904 vga_wcrt(regbase, VGA_CRTC_REGS, htotal / 2);
906 vga_wcrt(regbase, VGA_CRTC_REGS, 0x00); /* interlace control */
908 vga_wseq(regbase, VGA_SEQ_CHARACTER_MAP, 0);
910 /* adjust horizontal/vertical sync type (low/high) */
911 /* enable display memory & CRTC I/O address for color mode */
913 if (var->sync & FB_SYNC_HOR_HIGH_ACT)
915 if (var->sync & FB_SYNC_VERT_HIGH_ACT)
917 WGen(cinfo, VGA_MIS_W, tmp);
919 /* Screen A Preset Row-Scan register */
920 vga_wcrt(regbase, VGA_CRTC_PRESET_ROW, 0);
921 /* text cursor on and start line */
922 vga_wcrt(regbase, VGA_CRTC_CURSOR_START, 0);
923 /* text cursor end line */
924 vga_wcrt(regbase, VGA_CRTC_CURSOR_END, 31);
926 /******************************************************
932 /* programming for different color depths */
933 if (var->bits_per_pixel == 1) {
934 dev_dbg(info->device, "preparing for 1 bit deep display\n");
935 vga_wgfx(regbase, VGA_GFX_MODE, 0); /* mode register */
938 switch (cinfo->btype) {
946 vga_wseq(regbase, CL_SEQR7,
948 bi->sr07_1bpp_mux : bi->sr07_1bpp);
952 vga_wseq(regbase, CL_SEQR7,
953 vga_rseq(regbase, CL_SEQR7) & ~0x01);
957 dev_warn(info->device, "unknown Board\n");
961 /* Extended Sequencer Mode */
962 switch (cinfo->btype) {
964 /* setting the SEQRF on SD64 is not necessary
968 vga_wseq(regbase, CL_SEQR1F, 0x1a);
973 /* ### ueberall 0x22? */
974 /* ##vorher 1c MCLK select */
975 vga_wseq(regbase, CL_SEQR1F, 0x22);
976 /* evtl d0 bei 1 bit? avoid FIFO underruns..? */
977 vga_wseq(regbase, CL_SEQRF, 0xb0);
981 /* ##vorher 22 MCLK select */
982 vga_wseq(regbase, CL_SEQR1F, 0x22);
983 /* ## vorher d0 avoid FIFO underruns..? */
984 vga_wseq(regbase, CL_SEQRF, 0xd0);
995 dev_warn(info->device, "unknown Board\n");
999 /* pixel mask: pass-through for first plane */
1000 WGen(cinfo, VGA_PEL_MSK, 0x01);
1001 if (regs.multiplexing)
1002 /* hidden dac reg: 1280x1024 */
1005 /* hidden dac: nothing */
1007 /* memory mode: odd/even, ext. memory */
1008 vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, 0x06);
1009 /* plane mask: only write to first plane */
1010 vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0x01);
1011 offset = var->xres_virtual / 16;
1014 /******************************************************
1020 else if (var->bits_per_pixel == 8) {
1021 dev_dbg(info->device, "preparing for 8 bit deep display\n");
1022 switch (cinfo->btype) {
1030 vga_wseq(regbase, CL_SEQR7,
1032 bi->sr07_8bpp_mux : bi->sr07_8bpp);
1036 vga_wseq(regbase, CL_SEQR7,
1037 vga_rseq(regbase, CL_SEQR7) | 0x01);
1041 dev_warn(info->device, "unknown Board\n");
1045 switch (cinfo->btype) {
1048 vga_wseq(regbase, CL_SEQR1F, 0x1d);
1054 /* ### vorher 1c MCLK select */
1055 vga_wseq(regbase, CL_SEQR1F, 0x22);
1056 /* Fast Page-Mode writes */
1057 vga_wseq(regbase, CL_SEQRF, 0xb0);
1062 /* ### INCOMPLETE!! */
1063 vga_wseq(regbase, CL_SEQRF, 0xb8);
1065 /* vga_wseq(regbase, CL_SEQR1F, 0x1c); */
1069 /* We already set SRF and SR1F */
1078 dev_warn(info->device, "unknown board\n");
1082 /* mode register: 256 color mode */
1083 vga_wgfx(regbase, VGA_GFX_MODE, 64);
1084 /* pixel mask: pass-through all planes */
1085 WGen(cinfo, VGA_PEL_MSK, 0xff);
1086 if (regs.multiplexing)
1087 /* hidden dac reg: 1280x1024 */
1090 /* hidden dac: nothing */
1092 /* memory mode: chain4, ext. memory */
1093 vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, 0x0a);
1094 /* plane mask: enable writing to all 4 planes */
1095 vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0xff);
1096 offset = var->xres_virtual / 8;
1099 /******************************************************
1105 else if (var->bits_per_pixel == 16) {
1106 dev_dbg(info->device, "preparing for 16 bit deep display\n");
1107 switch (cinfo->btype) {
1109 /* Extended Sequencer Mode: 256c col. mode */
1110 vga_wseq(regbase, CL_SEQR7, 0xf7);
1112 vga_wseq(regbase, CL_SEQR1F, 0x1e);
1117 vga_wseq(regbase, CL_SEQR7, 0x87);
1118 /* Fast Page-Mode writes */
1119 vga_wseq(regbase, CL_SEQRF, 0xb0);
1121 vga_wseq(regbase, CL_SEQR1F, 0x22);
1125 vga_wseq(regbase, CL_SEQR7, 0x27);
1126 /* Fast Page-Mode writes */
1127 vga_wseq(regbase, CL_SEQRF, 0xb0);
1129 vga_wseq(regbase, CL_SEQR1F, 0x22);
1133 vga_wseq(regbase, CL_SEQR7, 0x27);
1134 /* vga_wseq(regbase, CL_SEQR1F, 0x1c); */
1138 vga_wseq(regbase, CL_SEQR7, 0xa7);
1142 vga_wseq(regbase, CL_SEQR7, 0x17);
1143 /* We already set SRF and SR1F */
1147 vga_wseq(regbase, CL_SEQR7,
1148 vga_rseq(regbase, CL_SEQR7) & ~0x01);
1152 dev_warn(info->device, "unknown Board\n");
1156 /* mode register: 256 color mode */
1157 vga_wgfx(regbase, VGA_GFX_MODE, 64);
1158 /* pixel mask: pass-through all planes */
1159 WGen(cinfo, VGA_PEL_MSK, 0xff);
1161 WHDR(cinfo, 0xc0); /* Copy Xbh */
1162 #elif defined(CONFIG_ZORRO)
1163 /* FIXME: CONFIG_PCI and CONFIG_ZORRO may be defined both */
1164 WHDR(cinfo, 0xa0); /* hidden dac reg: nothing special */
1166 /* memory mode: chain4, ext. memory */
1167 vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, 0x0a);
1168 /* plane mask: enable writing to all 4 planes */
1169 vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0xff);
1170 offset = var->xres_virtual / 4;
1173 /******************************************************
1179 else if (var->bits_per_pixel == 32) {
1180 dev_dbg(info->device, "preparing for 32 bit deep display\n");
1181 switch (cinfo->btype) {
1183 /* Extended Sequencer Mode: 256c col. mode */
1184 vga_wseq(regbase, CL_SEQR7, 0xf9);
1186 vga_wseq(regbase, CL_SEQR1F, 0x1e);
1191 vga_wseq(regbase, CL_SEQR7, 0x85);
1192 /* Fast Page-Mode writes */
1193 vga_wseq(regbase, CL_SEQRF, 0xb0);
1195 vga_wseq(regbase, CL_SEQR1F, 0x22);
1199 vga_wseq(regbase, CL_SEQR7, 0x25);
1200 /* Fast Page-Mode writes */
1201 vga_wseq(regbase, CL_SEQRF, 0xb0);
1203 vga_wseq(regbase, CL_SEQR1F, 0x22);
1207 vga_wseq(regbase, CL_SEQR7, 0x25);
1208 /* vga_wseq(regbase, CL_SEQR1F, 0x1c); */
1212 vga_wseq(regbase, CL_SEQR7, 0xa9);
1216 vga_wseq(regbase, CL_SEQR7, 0x19);
1217 /* We already set SRF and SR1F */
1221 vga_wseq(regbase, CL_SEQR7,
1222 vga_rseq(regbase, CL_SEQR7) & ~0x01);
1226 dev_warn(info->device, "unknown Board\n");
1230 /* mode register: 256 color mode */
1231 vga_wgfx(regbase, VGA_GFX_MODE, 64);
1232 /* pixel mask: pass-through all planes */
1233 WGen(cinfo, VGA_PEL_MSK, 0xff);
1234 /* hidden dac reg: 8-8-8 mode (24 or 32) */
1236 /* memory mode: chain4, ext. memory */
1237 vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, 0x0a);
1238 /* plane mask: enable writing to all 4 planes */
1239 vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0xff);
1240 offset = var->xres_virtual / 4;
1243 /******************************************************
1245 * unknown/unsupported bpp
1250 dev_err(info->device,
1251 "What's this? requested color depth == %d.\n",
1252 var->bits_per_pixel);
1254 vga_wcrt(regbase, VGA_CRTC_OFFSET, offset & 0xff);
1257 tmp |= 0x10; /* offset overflow bit */
1259 /* screen start addr #16-18, fastpagemode cycles */
1260 vga_wcrt(regbase, CL_CRT1B, tmp);
1262 /* screen start address bit 19 */
1263 if (cirrusfb_board_info[cinfo->btype].scrn_start_bit19)
1264 vga_wcrt(regbase, CL_CRT1D, 0x00);
1266 if (cinfo->btype == BT_LAGUNA ||
1267 cinfo->btype == BT_GD5480) {
1270 if ((htotal + 5) & 256)
1274 if (hsyncstart & 256)
1278 if (vdispend & 1024)
1280 if (vsyncstart & 1024)
1283 vga_wcrt(regbase, CL_CRT1E, tmp);
1284 dev_dbg(info->device, "CRT1e: %d\n", tmp);
1288 /* text cursor location high */
1289 vga_wcrt(regbase, VGA_CRTC_CURSOR_HI, 0);
1290 /* text cursor location low */
1291 vga_wcrt(regbase, VGA_CRTC_CURSOR_LO, 0);
1292 /* underline row scanline = at very bottom */
1293 vga_wcrt(regbase, VGA_CRTC_UNDERLINE, 0);
1295 /* controller mode */
1296 vga_wattr(regbase, VGA_ATC_MODE, 1);
1297 /* overscan (border) color */
1298 vga_wattr(regbase, VGA_ATC_OVERSCAN, 0);
1299 /* color plane enable */
1300 vga_wattr(regbase, VGA_ATC_PLANE_ENABLE, 15);
1302 vga_wattr(regbase, CL_AR33, 0);
1304 vga_wattr(regbase, VGA_ATC_COLOR_PAGE, 0);
1306 /* [ EGS: SetOffset(); ] */
1307 /* From SetOffset(): Turn on VideoEnable bit in Attribute controller */
1310 /* set/reset register */
1311 vga_wgfx(regbase, VGA_GFX_SR_VALUE, 0);
1312 /* set/reset enable */
1313 vga_wgfx(regbase, VGA_GFX_SR_ENABLE, 0);
1315 vga_wgfx(regbase, VGA_GFX_COMPARE_VALUE, 0);
1317 vga_wgfx(regbase, VGA_GFX_DATA_ROTATE, 0);
1318 /* read map select */
1319 vga_wgfx(regbase, VGA_GFX_PLANE_READ, 0);
1320 /* miscellaneous register */
1321 vga_wgfx(regbase, VGA_GFX_MISC, 1);
1322 /* color don't care */
1323 vga_wgfx(regbase, VGA_GFX_COMPARE_MASK, 15);
1325 vga_wgfx(regbase, VGA_GFX_BIT_MASK, 255);
1327 /* graphics cursor attributes: nothing special */
1328 vga_wseq(regbase, CL_SEQR12, 0x0);
1330 /* finally, turn on everything - turn off "FullBandwidth" bit */
1331 /* also, set "DotClock%2" bit where requested */
1334 /*** FB_VMODE_CLOCK_HALVE in linux/fb.h not defined anymore ?
1335 if (var->vmode & FB_VMODE_CLOCK_HALVE)
1339 vga_wseq(regbase, VGA_SEQ_CLOCK_MODE, tmp);
1340 dev_dbg(info->device, "CL_SEQR1: %d\n", tmp);
1342 cinfo->currentmode = regs;
1344 /* pan to requested offset */
1345 cirrusfb_pan_display(var, info);
1347 #ifdef CIRRUSFB_DEBUG
1348 cirrusfb_dbg_reg_dump(info, NULL);
1354 /* for some reason incomprehensible to me, cirrusfb requires that you write
1355 * the registers twice for the settings to take..grr. -dte */
1356 static int cirrusfb_set_par(struct fb_info *info)
1358 cirrusfb_set_par_foo(info);
1359 return cirrusfb_set_par_foo(info);
1362 static int cirrusfb_setcolreg(unsigned regno, unsigned red, unsigned green,
1363 unsigned blue, unsigned transp,
1364 struct fb_info *info)
1366 struct cirrusfb_info *cinfo = info->par;
1371 if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
1373 red >>= (16 - info->var.red.length);
1374 green >>= (16 - info->var.green.length);
1375 blue >>= (16 - info->var.blue.length);
1379 v = (red << info->var.red.offset) |
1380 (green << info->var.green.offset) |
1381 (blue << info->var.blue.offset);
1383 cinfo->pseudo_palette[regno] = v;
1387 if (info->var.bits_per_pixel == 8)
1388 WClut(cinfo, regno, red >> 10, green >> 10, blue >> 10);
1394 /*************************************************************************
1395 cirrusfb_pan_display()
1397 performs display panning - provided hardware permits this
1398 **************************************************************************/
1399 static int cirrusfb_pan_display(struct fb_var_screeninfo *var,
1400 struct fb_info *info)
1405 unsigned char tmp, xpix;
1406 struct cirrusfb_info *cinfo = info->par;
1408 dev_dbg(info->device,
1409 "virtual offset: (%d,%d)\n", var->xoffset, var->yoffset);
1411 /* no range checks for xoffset and yoffset, */
1412 /* as fb_pan_display has already done this */
1413 if (var->vmode & FB_VMODE_YWRAP)
1416 info->var.xoffset = var->xoffset;
1417 info->var.yoffset = var->yoffset;
1419 xoffset = var->xoffset * info->var.bits_per_pixel / 8;
1420 yoffset = var->yoffset;
1422 base = yoffset * info->fix.line_length + xoffset;
1424 if (info->var.bits_per_pixel == 1) {
1425 /* base is already correct */
1426 xpix = (unsigned char) (var->xoffset % 8);
1429 xpix = (unsigned char) ((xoffset % 4) * 2);
1432 cirrusfb_WaitBLT(cinfo->regbase); /* make sure all the BLT's are done */
1434 /* lower 8 + 8 bits of screen start address */
1435 vga_wcrt(cinfo->regbase, VGA_CRTC_START_LO,
1436 (unsigned char) (base & 0xff));
1437 vga_wcrt(cinfo->regbase, VGA_CRTC_START_HI,
1438 (unsigned char) (base >> 8));
1440 /* 0xf2 is %11110010, exclude tmp bits */
1441 tmp = vga_rcrt(cinfo->regbase, CL_CRT1B) & 0xf2;
1442 /* construct bits 16, 17 and 18 of screen start address */
1450 vga_wcrt(cinfo->regbase, CL_CRT1B, tmp);
1452 /* construct bit 19 of screen start address */
1453 if (cirrusfb_board_info[cinfo->btype].scrn_start_bit19)
1454 vga_wcrt(cinfo->regbase, CL_CRT1D, (base >> 12) & 0x80);
1456 /* write pixel panning value to AR33; this does not quite work in 8bpp
1458 * ### Piccolo..? Will this work?
1460 if (info->var.bits_per_pixel == 1)
1461 vga_wattr(cinfo->regbase, CL_AR33, xpix);
1463 cirrusfb_WaitBLT(cinfo->regbase);
1468 static int cirrusfb_blank(int blank_mode, struct fb_info *info)
1471 * Blank the screen if blank_mode != 0, else unblank. If blank == NULL
1472 * then the caller blanks by setting the CLUT (Color Look Up Table)
1473 * to all black. Return 0 if blanking succeeded, != 0 if un-/blanking
1474 * failed due to e.g. a video mode which doesn't support it.
1475 * Implements VESA suspend and powerdown modes on hardware that
1476 * supports disabling hsync/vsync:
1477 * blank_mode == 2: suspend vsync
1478 * blank_mode == 3: suspend hsync
1479 * blank_mode == 4: powerdown
1482 struct cirrusfb_info *cinfo = info->par;
1483 int current_mode = cinfo->blank_mode;
1485 dev_dbg(info->device, "ENTER, blank mode = %d\n", blank_mode);
1487 if (info->state != FBINFO_STATE_RUNNING ||
1488 current_mode == blank_mode) {
1489 dev_dbg(info->device, "EXIT, returning 0\n");
1494 if (current_mode == FB_BLANK_NORMAL ||
1495 current_mode == FB_BLANK_UNBLANK)
1496 /* clear "FullBandwidth" bit */
1499 /* set "FullBandwidth" bit */
1502 val |= vga_rseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE) & 0xdf;
1503 vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, val);
1505 switch (blank_mode) {
1506 case FB_BLANK_UNBLANK:
1507 case FB_BLANK_NORMAL:
1510 case FB_BLANK_VSYNC_SUSPEND:
1513 case FB_BLANK_HSYNC_SUSPEND:
1516 case FB_BLANK_POWERDOWN:
1520 dev_dbg(info->device, "EXIT, returning 1\n");
1524 vga_wgfx(cinfo->regbase, CL_GRE, val);
1526 cinfo->blank_mode = blank_mode;
1527 dev_dbg(info->device, "EXIT, returning 0\n");
1529 /* Let fbcon do a soft blank for us */
1530 return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
1533 /**** END Hardware specific Routines **************************************/
1534 /****************************************************************************/
1535 /**** BEGIN Internal Routines ***********************************************/
1537 static void init_vgachip(struct fb_info *info)
1539 struct cirrusfb_info *cinfo = info->par;
1540 const struct cirrusfb_board_info_rec *bi;
1542 assert(cinfo != NULL);
1544 bi = &cirrusfb_board_info[cinfo->btype];
1546 /* reset board globally */
1547 switch (cinfo->btype) {
1566 /* disable flickerfixer */
1567 vga_wcrt(cinfo->regbase, CL_CRT51, 0x00);
1569 /* from Klaus' NetBSD driver: */
1570 vga_wgfx(cinfo->regbase, CL_GR2F, 0x00);
1571 /* put blitter into 542x compat */
1572 vga_wgfx(cinfo->regbase, CL_GR33, 0x00);
1574 vga_wgfx(cinfo->regbase, CL_GR31, 0x00);
1578 /* from Klaus' NetBSD driver: */
1579 vga_wgfx(cinfo->regbase, CL_GR2F, 0x00);
1583 /* Nothing to do to reset the board. */
1587 dev_err(info->device, "Warning: Unknown board type\n");
1591 /* make sure RAM size set by this point */
1592 assert(info->screen_size > 0);
1594 /* the P4 is not fully initialized here; I rely on it having been */
1595 /* inited under AmigaOS already, which seems to work just fine */
1596 /* (Klaus advised to do it this way) */
1598 if (cinfo->btype != BT_PICASSO4) {
1599 WGen(cinfo, CL_VSSM, 0x10); /* EGS: 0x16 */
1600 WGen(cinfo, CL_POS102, 0x01);
1601 WGen(cinfo, CL_VSSM, 0x08); /* EGS: 0x0e */
1603 if (cinfo->btype != BT_SD64)
1604 WGen(cinfo, CL_VSSM2, 0x01);
1606 /* reset sequencer logic */
1607 vga_wseq(cinfo->regbase, CL_SEQR0, 0x03);
1609 /* FullBandwidth (video off) and 8/9 dot clock */
1610 vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, 0x21);
1611 /* polarity (-/-), disable access to display memory,
1612 * VGA_CRTC_START_HI base address: color
1614 WGen(cinfo, VGA_MIS_W, 0xc1);
1616 /* "magic cookie" - doesn't make any sense to me.. */
1617 /* vga_wgfx(cinfo->regbase, CL_GRA, 0xce); */
1618 /* unlock all extension registers */
1619 vga_wseq(cinfo->regbase, CL_SEQR6, 0x12);
1622 vga_wgfx(cinfo->regbase, CL_GR31, 0x04);
1624 switch (cinfo->btype) {
1626 vga_wseq(cinfo->regbase, CL_SEQRF, 0x98);
1631 vga_wseq(cinfo->regbase, CL_SEQRF, 0xb8);
1634 vga_wseq(cinfo->regbase, CL_SEQR16, 0x0f);
1635 vga_wseq(cinfo->regbase, CL_SEQRF, 0xb0);
1639 /* plane mask: nothing */
1640 vga_wseq(cinfo->regbase, VGA_SEQ_PLANE_WRITE, 0xff);
1641 /* character map select: doesn't even matter in gx mode */
1642 vga_wseq(cinfo->regbase, VGA_SEQ_CHARACTER_MAP, 0x00);
1643 /* memory mode: chain-4, no odd/even, ext. memory */
1644 vga_wseq(cinfo->regbase, VGA_SEQ_MEMORY_MODE, 0x0e);
1646 /* controller-internal base address of video memory */
1648 vga_wseq(cinfo->regbase, CL_SEQR7, bi->sr07);
1650 /* vga_wseq(cinfo->regbase, CL_SEQR8, 0x00); */
1651 /* EEPROM control: shouldn't be necessary to write to this at all.. */
1653 /* graphics cursor X position (incomplete; position gives rem. 3 bits */
1654 vga_wseq(cinfo->regbase, CL_SEQR10, 0x00);
1655 /* graphics cursor Y position (..."... ) */
1656 vga_wseq(cinfo->regbase, CL_SEQR11, 0x00);
1657 /* graphics cursor attributes */
1658 vga_wseq(cinfo->regbase, CL_SEQR12, 0x00);
1659 /* graphics cursor pattern address */
1660 vga_wseq(cinfo->regbase, CL_SEQR13, 0x00);
1662 /* writing these on a P4 might give problems.. */
1663 if (cinfo->btype != BT_PICASSO4) {
1664 /* configuration readback and ext. color */
1665 vga_wseq(cinfo->regbase, CL_SEQR17, 0x00);
1666 /* signature generator */
1667 vga_wseq(cinfo->regbase, CL_SEQR18, 0x02);
1670 /* MCLK select etc. */
1672 vga_wseq(cinfo->regbase, CL_SEQR1F, bi->sr1f);
1674 /* Screen A preset row scan: none */
1675 vga_wcrt(cinfo->regbase, VGA_CRTC_PRESET_ROW, 0x00);
1676 /* Text cursor start: disable text cursor */
1677 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_START, 0x20);
1678 /* Text cursor end: - */
1679 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_END, 0x00);
1680 /* Screen start address high: 0 */
1681 vga_wcrt(cinfo->regbase, VGA_CRTC_START_HI, 0x00);
1682 /* Screen start address low: 0 */
1683 vga_wcrt(cinfo->regbase, VGA_CRTC_START_LO, 0x00);
1684 /* text cursor location high: 0 */
1685 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_HI, 0x00);
1686 /* text cursor location low: 0 */
1687 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_LO, 0x00);
1689 /* Underline Row scanline: - */
1690 vga_wcrt(cinfo->regbase, VGA_CRTC_UNDERLINE, 0x00);
1691 /* mode control: timing enable, byte mode, no compat modes */
1692 vga_wcrt(cinfo->regbase, VGA_CRTC_MODE, 0xc3);
1693 /* Line Compare: not needed */
1694 vga_wcrt(cinfo->regbase, VGA_CRTC_LINE_COMPARE, 0x00);
1695 /* ### add 0x40 for text modes with > 30 MHz pixclock */
1696 /* ext. display controls: ext.adr. wrap */
1697 vga_wcrt(cinfo->regbase, CL_CRT1B, 0x02);
1699 /* Set/Reset registes: - */
1700 vga_wgfx(cinfo->regbase, VGA_GFX_SR_VALUE, 0x00);
1701 /* Set/Reset enable: - */
1702 vga_wgfx(cinfo->regbase, VGA_GFX_SR_ENABLE, 0x00);
1703 /* Color Compare: - */
1704 vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_VALUE, 0x00);
1705 /* Data Rotate: - */
1706 vga_wgfx(cinfo->regbase, VGA_GFX_DATA_ROTATE, 0x00);
1707 /* Read Map Select: - */
1708 vga_wgfx(cinfo->regbase, VGA_GFX_PLANE_READ, 0x00);
1709 /* Mode: conf. for 16/4/2 color mode, no odd/even, read/write mode 0 */
1710 vga_wgfx(cinfo->regbase, VGA_GFX_MODE, 0x00);
1711 /* Miscellaneous: memory map base address, graphics mode */
1712 vga_wgfx(cinfo->regbase, VGA_GFX_MISC, 0x01);
1713 /* Color Don't care: involve all planes */
1714 vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_MASK, 0x0f);
1715 /* Bit Mask: no mask at all */
1716 vga_wgfx(cinfo->regbase, VGA_GFX_BIT_MASK, 0xff);
1717 if (cinfo->btype == BT_ALPINE)
1718 /* (5434 can't have bit 3 set for bitblt) */
1719 vga_wgfx(cinfo->regbase, CL_GRB, 0x20);
1721 /* Graphics controller mode extensions: finer granularity,
1722 * 8byte data latches
1724 vga_wgfx(cinfo->regbase, CL_GRB, 0x28);
1726 vga_wgfx(cinfo->regbase, CL_GRC, 0xff); /* Color Key compare: - */
1727 vga_wgfx(cinfo->regbase, CL_GRD, 0x00); /* Color Key compare mask: - */
1728 vga_wgfx(cinfo->regbase, CL_GRE, 0x00); /* Miscellaneous control: - */
1729 /* Background color byte 1: - */
1730 /* vga_wgfx (cinfo->regbase, CL_GR10, 0x00); */
1731 /* vga_wgfx (cinfo->regbase, CL_GR11, 0x00); */
1733 /* Attribute Controller palette registers: "identity mapping" */
1734 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE0, 0x00);
1735 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE1, 0x01);
1736 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE2, 0x02);
1737 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE3, 0x03);
1738 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE4, 0x04);
1739 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE5, 0x05);
1740 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE6, 0x06);
1741 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE7, 0x07);
1742 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE8, 0x08);
1743 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE9, 0x09);
1744 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEA, 0x0a);
1745 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEB, 0x0b);
1746 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEC, 0x0c);
1747 vga_wattr(cinfo->regbase, VGA_ATC_PALETTED, 0x0d);
1748 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEE, 0x0e);
1749 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEF, 0x0f);
1751 /* Attribute Controller mode: graphics mode */
1752 vga_wattr(cinfo->regbase, VGA_ATC_MODE, 0x01);
1753 /* Overscan color reg.: reg. 0 */
1754 vga_wattr(cinfo->regbase, VGA_ATC_OVERSCAN, 0x00);
1755 /* Color Plane enable: Enable all 4 planes */
1756 vga_wattr(cinfo->regbase, VGA_ATC_PLANE_ENABLE, 0x0f);
1757 /* ### vga_wattr(cinfo->regbase, CL_AR33, 0x00); * Pixel Panning: - */
1758 /* Color Select: - */
1759 vga_wattr(cinfo->regbase, VGA_ATC_COLOR_PAGE, 0x00);
1761 WGen(cinfo, VGA_PEL_MSK, 0xff); /* Pixel mask: no mask */
1763 if (cinfo->btype != BT_ALPINE && cinfo->btype != BT_GD5480)
1764 /* polarity (-/-), enable display mem,
1765 * VGA_CRTC_START_HI i/o base = color
1767 WGen(cinfo, VGA_MIS_W, 0xc3);
1769 /* BLT Start/status: Blitter reset */
1770 vga_wgfx(cinfo->regbase, CL_GR31, 0x04);
1771 /* - " - : "end-of-reset" */
1772 vga_wgfx(cinfo->regbase, CL_GR31, 0x00);
1775 WHDR(cinfo, 0); /* Hidden DAC register: - */
1779 static void switch_monitor(struct cirrusfb_info *cinfo, int on)
1781 #ifdef CONFIG_ZORRO /* only works on Zorro boards */
1782 static int IsOn = 0; /* XXX not ok for multiple boards */
1784 if (cinfo->btype == BT_PICASSO4)
1785 return; /* nothing to switch */
1786 if (cinfo->btype == BT_ALPINE)
1787 return; /* nothing to switch */
1788 if (cinfo->btype == BT_GD5480)
1789 return; /* nothing to switch */
1790 if (cinfo->btype == BT_PICASSO) {
1791 if ((on && !IsOn) || (!on && IsOn))
1796 switch (cinfo->btype) {
1798 WSFR(cinfo, cinfo->SFR | 0x21);
1801 WSFR(cinfo, cinfo->SFR | 0x28);
1806 default: /* do nothing */ break;
1809 switch (cinfo->btype) {
1811 WSFR(cinfo, cinfo->SFR & 0xde);
1814 WSFR(cinfo, cinfo->SFR & 0xd7);
1819 default: /* do nothing */
1823 #endif /* CONFIG_ZORRO */
1826 /******************************************/
1827 /* Linux 2.6-style accelerated functions */
1828 /******************************************/
1830 static void cirrusfb_fillrect(struct fb_info *info,
1831 const struct fb_fillrect *region)
1833 struct fb_fillrect modded;
1835 struct cirrusfb_info *cinfo = info->par;
1836 int m = info->var.bits_per_pixel;
1837 u32 color = (info->fix.visual == FB_VISUAL_TRUECOLOR) ?
1838 cinfo->pseudo_palette[region->color] : region->color;
1840 if (info->state != FBINFO_STATE_RUNNING)
1842 if (info->flags & FBINFO_HWACCEL_DISABLED) {
1843 cfb_fillrect(info, region);
1847 vxres = info->var.xres_virtual;
1848 vyres = info->var.yres_virtual;
1850 memcpy(&modded, region, sizeof(struct fb_fillrect));
1852 if (!modded.width || !modded.height ||
1853 modded.dx >= vxres || modded.dy >= vyres)
1856 if (modded.dx + modded.width > vxres)
1857 modded.width = vxres - modded.dx;
1858 if (modded.dy + modded.height > vyres)
1859 modded.height = vyres - modded.dy;
1861 cirrusfb_RectFill(cinfo->regbase,
1862 info->var.bits_per_pixel,
1863 (region->dx * m) / 8, region->dy,
1864 (region->width * m) / 8, region->height,
1866 info->fix.line_length);
1869 static void cirrusfb_copyarea(struct fb_info *info,
1870 const struct fb_copyarea *area)
1872 struct fb_copyarea modded;
1874 struct cirrusfb_info *cinfo = info->par;
1875 int m = info->var.bits_per_pixel;
1877 if (info->state != FBINFO_STATE_RUNNING)
1879 if (info->flags & FBINFO_HWACCEL_DISABLED) {
1880 cfb_copyarea(info, area);
1884 vxres = info->var.xres_virtual;
1885 vyres = info->var.yres_virtual;
1886 memcpy(&modded, area, sizeof(struct fb_copyarea));
1888 if (!modded.width || !modded.height ||
1889 modded.sx >= vxres || modded.sy >= vyres ||
1890 modded.dx >= vxres || modded.dy >= vyres)
1893 if (modded.sx + modded.width > vxres)
1894 modded.width = vxres - modded.sx;
1895 if (modded.dx + modded.width > vxres)
1896 modded.width = vxres - modded.dx;
1897 if (modded.sy + modded.height > vyres)
1898 modded.height = vyres - modded.sy;
1899 if (modded.dy + modded.height > vyres)
1900 modded.height = vyres - modded.dy;
1902 cirrusfb_BitBLT(cinfo->regbase, info->var.bits_per_pixel,
1903 (area->sx * m) / 8, area->sy,
1904 (area->dx * m) / 8, area->dy,
1905 (area->width * m) / 8, area->height,
1906 info->fix.line_length);
1910 static void cirrusfb_imageblit(struct fb_info *info,
1911 const struct fb_image *image)
1913 struct cirrusfb_info *cinfo = info->par;
1915 cirrusfb_WaitBLT(cinfo->regbase);
1916 cfb_imageblit(info, image);
1919 #ifdef CONFIG_PPC_PREP
1920 #define PREP_VIDEO_BASE ((volatile unsigned long) 0xC0000000)
1921 #define PREP_IO_BASE ((volatile unsigned char *) 0x80000000)
1922 static void get_prep_addrs(unsigned long *display, unsigned long *registers)
1924 *display = PREP_VIDEO_BASE;
1925 *registers = (unsigned long) PREP_IO_BASE;
1928 #endif /* CONFIG_PPC_PREP */
1931 static int release_io_ports;
1933 /* Pulled the logic from XFree86 Cirrus driver to get the memory size,
1934 * based on the DRAM bandwidth bit and DRAM bank switching bit. This
1935 * works with 1MB, 2MB and 4MB configurations (which the Motorola boards
1937 static unsigned int __devinit cirrusfb_get_memsize(struct fb_info *info,
1938 u8 __iomem *regbase)
1941 struct cirrusfb_info *cinfo = info->par;
1943 if (cinfo->btype == BT_LAGUNA) {
1944 unsigned char SR14 = vga_rseq(regbase, CL_SEQR14);
1946 mem = ((SR14 & 7) + 1) << 20;
1948 unsigned char SRF = vga_rseq(regbase, CL_SEQRF);
1949 switch ((SRF & 0x18)) {
1956 /* 64-bit DRAM data bus width; assume 2MB.
1957 * Also indicates 2MB memory on the 5430.
1963 dev_warn(info->device, "Unknown memory size!\n");
1966 /* If DRAM bank switching is enabled, there must be
1967 * twice as much memory installed. (4MB on the 5434)
1973 /* TODO: Handling of GD5446/5480 (see XF86 sources ...) */
1977 static void get_pci_addrs(const struct pci_dev *pdev,
1978 unsigned long *display, unsigned long *registers)
1980 assert(pdev != NULL);
1981 assert(display != NULL);
1982 assert(registers != NULL);
1987 /* This is a best-guess for now */
1989 if (pci_resource_flags(pdev, 0) & IORESOURCE_IO) {
1990 *display = pci_resource_start(pdev, 1);
1991 *registers = pci_resource_start(pdev, 0);
1993 *display = pci_resource_start(pdev, 0);
1994 *registers = pci_resource_start(pdev, 1);
1997 assert(*display != 0);
2000 static void cirrusfb_pci_unmap(struct fb_info *info)
2002 struct pci_dev *pdev = to_pci_dev(info->device);
2004 iounmap(info->screen_base);
2005 #if 0 /* if system didn't claim this region, we would... */
2006 release_mem_region(0xA0000, 65535);
2008 if (release_io_ports)
2009 release_region(0x3C0, 32);
2010 pci_release_regions(pdev);
2012 #endif /* CONFIG_PCI */
2015 static void cirrusfb_zorro_unmap(struct fb_info *info)
2017 struct cirrusfb_info *cinfo = info->par;
2018 struct zorro_dev *zdev = to_zorro_dev(info->device);
2020 zorro_release_device(zdev);
2022 if (cinfo->btype == BT_PICASSO4) {
2023 cinfo->regbase -= 0x600000;
2024 iounmap((void *)cinfo->regbase);
2025 iounmap(info->screen_base);
2027 if (zorro_resource_start(zdev) > 0x01000000)
2028 iounmap(info->screen_base);
2031 #endif /* CONFIG_ZORRO */
2033 static int __devinit cirrusfb_set_fbinfo(struct fb_info *info)
2035 struct cirrusfb_info *cinfo = info->par;
2036 struct fb_var_screeninfo *var = &info->var;
2038 info->pseudo_palette = cinfo->pseudo_palette;
2039 info->flags = FBINFO_DEFAULT
2040 | FBINFO_HWACCEL_XPAN
2041 | FBINFO_HWACCEL_YPAN
2042 | FBINFO_HWACCEL_FILLRECT
2043 | FBINFO_HWACCEL_COPYAREA;
2045 info->flags |= FBINFO_HWACCEL_DISABLED;
2046 info->fbops = &cirrusfb_ops;
2047 if (cinfo->btype == BT_GD5480) {
2048 if (var->bits_per_pixel == 16)
2049 info->screen_base += 1 * MB_;
2050 if (var->bits_per_pixel == 32)
2051 info->screen_base += 2 * MB_;
2054 /* Fill fix common fields */
2055 strlcpy(info->fix.id, cirrusfb_board_info[cinfo->btype].name,
2056 sizeof(info->fix.id));
2058 /* monochrome: only 1 memory plane */
2059 /* 8 bit and above: Use whole memory area */
2060 info->fix.smem_len = info->screen_size;
2061 if (var->bits_per_pixel == 1)
2062 info->fix.smem_len /= 4;
2063 info->fix.type_aux = 0;
2064 info->fix.xpanstep = 1;
2065 info->fix.ypanstep = 1;
2066 info->fix.ywrapstep = 0;
2068 /* FIXME: map region at 0xB8000 if available, fill in here */
2069 info->fix.mmio_len = 0;
2070 info->fix.accel = FB_ACCEL_NONE;
2072 fb_alloc_cmap(&info->cmap, 256, 0);
2077 static int __devinit cirrusfb_register(struct fb_info *info)
2079 struct cirrusfb_info *cinfo = info->par;
2081 enum cirrus_board btype;
2083 btype = cinfo->btype;
2086 assert(btype != BT_NONE);
2088 /* set all the vital stuff */
2089 cirrusfb_set_fbinfo(info);
2091 dev_dbg(info->device, "(RAM start set to: 0x%p)\n", info->screen_base);
2093 err = fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 8);
2095 dev_dbg(info->device, "wrong initial video mode\n");
2097 goto err_dealloc_cmap;
2100 info->var.activate = FB_ACTIVATE_NOW;
2102 err = cirrusfb_decode_var(&info->var, &cinfo->currentmode, info);
2104 /* should never happen */
2105 dev_dbg(info->device,
2106 "choking on default var... umm, no good.\n");
2107 goto err_dealloc_cmap;
2110 err = register_framebuffer(info);
2112 dev_err(info->device,
2113 "could not register fb device; err = %d!\n", err);
2114 goto err_dealloc_cmap;
2120 fb_dealloc_cmap(&info->cmap);
2122 framebuffer_release(info);
2126 static void __devexit cirrusfb_cleanup(struct fb_info *info)
2128 struct cirrusfb_info *cinfo = info->par;
2130 switch_monitor(cinfo, 0);
2131 unregister_framebuffer(info);
2132 fb_dealloc_cmap(&info->cmap);
2133 dev_dbg(info->device, "Framebuffer unregistered\n");
2135 framebuffer_release(info);
2139 static int __devinit cirrusfb_pci_register(struct pci_dev *pdev,
2140 const struct pci_device_id *ent)
2142 struct cirrusfb_info *cinfo;
2143 struct fb_info *info;
2144 enum cirrus_board btype;
2145 unsigned long board_addr, board_size;
2148 ret = pci_enable_device(pdev);
2150 printk(KERN_ERR "cirrusfb: Cannot enable PCI device\n");
2154 info = framebuffer_alloc(sizeof(struct cirrusfb_info), &pdev->dev);
2156 printk(KERN_ERR "cirrusfb: could not allocate memory\n");
2162 cinfo->btype = btype = (enum cirrus_board) ent->driver_data;
2164 dev_dbg(info->device,
2165 " Found PCI device, base address 0 is 0x%Lx, btype set to %d\n",
2166 (unsigned long long)pdev->resource[0].start, btype);
2167 dev_dbg(info->device, " base address 1 is 0x%Lx\n",
2168 (unsigned long long)pdev->resource[1].start);
2171 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, 0x00000000);
2172 #ifdef CONFIG_PPC_PREP
2173 get_prep_addrs(&board_addr, &info->fix.mmio_start);
2175 /* PReP dies if we ioremap the IO registers, but it works w/out... */
2176 cinfo->regbase = (char __iomem *) info->fix.mmio_start;
2178 dev_dbg(info->device,
2179 "Attempt to get PCI info for Cirrus Graphics Card\n");
2180 get_pci_addrs(pdev, &board_addr, &info->fix.mmio_start);
2181 /* FIXME: this forces VGA. alternatives? */
2182 cinfo->regbase = NULL;
2185 dev_dbg(info->device, "Board address: 0x%lx, register address: 0x%lx\n",
2186 board_addr, info->fix.mmio_start);
2188 board_size = (btype == BT_GD5480) ?
2189 32 * MB_ : cirrusfb_get_memsize(info, cinfo->regbase);
2191 ret = pci_request_regions(pdev, "cirrusfb");
2193 dev_err(info->device, "cannot reserve region 0x%lx, abort\n",
2195 goto err_release_fb;
2197 #if 0 /* if the system didn't claim this region, we would... */
2198 if (!request_mem_region(0xA0000, 65535, "cirrusfb")) {
2199 dev_err(info->device, "cannot reserve region 0x%lx, abort\n",
2202 goto err_release_regions;
2205 if (request_region(0x3C0, 32, "cirrusfb"))
2206 release_io_ports = 1;
2208 info->screen_base = ioremap(board_addr, board_size);
2209 if (!info->screen_base) {
2211 goto err_release_legacy;
2214 info->fix.smem_start = board_addr;
2215 info->screen_size = board_size;
2216 cinfo->unmap = cirrusfb_pci_unmap;
2218 dev_info(info->device,
2219 "Cirrus Logic chipset on PCI bus, RAM (%lu kB) at 0x%lx\n",
2220 info->screen_size >> 10, board_addr);
2221 pci_set_drvdata(pdev, info);
2223 ret = cirrusfb_register(info);
2225 iounmap(info->screen_base);
2229 if (release_io_ports)
2230 release_region(0x3C0, 32);
2232 release_mem_region(0xA0000, 65535);
2233 err_release_regions:
2235 pci_release_regions(pdev);
2237 framebuffer_release(info);
2243 static void __devexit cirrusfb_pci_unregister(struct pci_dev *pdev)
2245 struct fb_info *info = pci_get_drvdata(pdev);
2247 cirrusfb_cleanup(info);
2250 static struct pci_driver cirrusfb_pci_driver = {
2252 .id_table = cirrusfb_pci_table,
2253 .probe = cirrusfb_pci_register,
2254 .remove = __devexit_p(cirrusfb_pci_unregister),
2257 .suspend = cirrusfb_pci_suspend,
2258 .resume = cirrusfb_pci_resume,
2262 #endif /* CONFIG_PCI */
2265 static int __devinit cirrusfb_zorro_register(struct zorro_dev *z,
2266 const struct zorro_device_id *ent)
2268 struct cirrusfb_info *cinfo;
2269 struct fb_info *info;
2270 enum cirrus_board btype;
2271 struct zorro_dev *z2 = NULL;
2272 unsigned long board_addr, board_size, size;
2275 btype = ent->driver_data;
2276 if (cirrusfb_zorro_table2[btype].id2)
2277 z2 = zorro_find_device(cirrusfb_zorro_table2[btype].id2, NULL);
2278 size = cirrusfb_zorro_table2[btype].size;
2280 info = framebuffer_alloc(sizeof(struct cirrusfb_info), &z->dev);
2282 printk(KERN_ERR "cirrusfb: could not allocate memory\n");
2287 dev_info(info->device, "%s board detected\n",
2288 cirrusfb_board_info[btype].name);
2291 cinfo->btype = btype;
2294 assert(btype != BT_NONE);
2296 board_addr = zorro_resource_start(z);
2297 board_size = zorro_resource_len(z);
2298 info->screen_size = size;
2300 if (!zorro_request_device(z, "cirrusfb")) {
2301 dev_err(info->device, "cannot reserve region 0x%lx, abort\n",
2304 goto err_release_fb;
2309 if (btype == BT_PICASSO4) {
2310 dev_info(info->device, " REG at $%lx\n", board_addr + 0x600000);
2312 /* To be precise, for the P4 this is not the */
2313 /* begin of the board, but the begin of RAM. */
2314 /* for P4, map in its address space in 2 chunks (### TEST! ) */
2315 /* (note the ugly hardcoded 16M number) */
2316 cinfo->regbase = ioremap(board_addr, 16777216);
2317 if (!cinfo->regbase)
2318 goto err_release_region;
2320 dev_dbg(info->device, "Virtual address for board set to: $%p\n",
2322 cinfo->regbase += 0x600000;
2323 info->fix.mmio_start = board_addr + 0x600000;
2325 info->fix.smem_start = board_addr + 16777216;
2326 info->screen_base = ioremap(info->fix.smem_start, 16777216);
2327 if (!info->screen_base)
2328 goto err_unmap_regbase;
2330 dev_info(info->device, " REG at $%lx\n",
2331 (unsigned long) z2->resource.start);
2333 info->fix.smem_start = board_addr;
2334 if (board_addr > 0x01000000)
2335 info->screen_base = ioremap(board_addr, board_size);
2337 info->screen_base = (caddr_t) ZTWO_VADDR(board_addr);
2338 if (!info->screen_base)
2339 goto err_release_region;
2341 /* set address for REG area of board */
2342 cinfo->regbase = (caddr_t) ZTWO_VADDR(z2->resource.start);
2343 info->fix.mmio_start = z2->resource.start;
2345 dev_dbg(info->device, "Virtual address for board set to: $%p\n",
2348 cinfo->unmap = cirrusfb_zorro_unmap;
2350 dev_info(info->device,
2351 "Cirrus Logic chipset on Zorro bus, RAM (%lu MB) at $%lx\n",
2352 board_size / MB_, board_addr);
2354 zorro_set_drvdata(z, info);
2356 ret = cirrusfb_register(info);
2358 if (btype == BT_PICASSO4) {
2359 iounmap(info->screen_base);
2360 iounmap(cinfo->regbase - 0x600000);
2361 } else if (board_addr > 0x01000000)
2362 iounmap(info->screen_base);
2367 /* Parental advisory: explicit hack */
2368 iounmap(cinfo->regbase - 0x600000);
2370 release_region(board_addr, board_size);
2372 framebuffer_release(info);
2377 void __devexit cirrusfb_zorro_unregister(struct zorro_dev *z)
2379 struct fb_info *info = zorro_get_drvdata(z);
2381 cirrusfb_cleanup(info);
2384 static struct zorro_driver cirrusfb_zorro_driver = {
2386 .id_table = cirrusfb_zorro_table,
2387 .probe = cirrusfb_zorro_register,
2388 .remove = __devexit_p(cirrusfb_zorro_unregister),
2390 #endif /* CONFIG_ZORRO */
2392 static int __init cirrusfb_init(void)
2397 char *option = NULL;
2399 if (fb_get_options("cirrusfb", &option))
2401 cirrusfb_setup(option);
2405 error |= zorro_register_driver(&cirrusfb_zorro_driver);
2408 error |= pci_register_driver(&cirrusfb_pci_driver);
2414 static int __init cirrusfb_setup(char *options)
2418 if (!options || !*options)
2421 while ((this_opt = strsep(&options, ",")) != NULL) {
2425 if (!strcmp(this_opt, "noaccel"))
2427 else if (!strncmp(this_opt, "mode:", 5))
2428 mode_option = this_opt + 5;
2430 mode_option = this_opt;
2440 MODULE_AUTHOR("Copyright 1999,2000 Jeff Garzik <jgarzik@pobox.com>");
2441 MODULE_DESCRIPTION("Accelerated FBDev driver for Cirrus Logic chips");
2442 MODULE_LICENSE("GPL");
2444 static void __exit cirrusfb_exit(void)
2447 pci_unregister_driver(&cirrusfb_pci_driver);
2450 zorro_unregister_driver(&cirrusfb_zorro_driver);
2454 module_init(cirrusfb_init);
2456 module_param(mode_option, charp, 0);
2457 MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'");
2458 module_param(noaccel, bool, 0);
2459 MODULE_PARM_DESC(noaccel, "Disable acceleration");
2462 module_exit(cirrusfb_exit);
2465 /**********************************************************************/
2466 /* about the following functions - I have used the same names for the */
2467 /* functions as Markus Wild did in his Retina driver for NetBSD as */
2468 /* they just made sense for this purpose. Apart from that, I wrote */
2469 /* these functions myself. */
2470 /**********************************************************************/
2472 /*** WGen() - write into one of the external/general registers ***/
2473 static void WGen(const struct cirrusfb_info *cinfo,
2474 int regnum, unsigned char val)
2476 unsigned long regofs = 0;
2478 if (cinfo->btype == BT_PICASSO) {
2479 /* Picasso II specific hack */
2480 /* if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D ||
2481 regnum == CL_VSSM2) */
2482 if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D)
2486 vga_w(cinfo->regbase, regofs + regnum, val);
2489 /*** RGen() - read out one of the external/general registers ***/
2490 static unsigned char RGen(const struct cirrusfb_info *cinfo, int regnum)
2492 unsigned long regofs = 0;
2494 if (cinfo->btype == BT_PICASSO) {
2495 /* Picasso II specific hack */
2496 /* if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D ||
2497 regnum == CL_VSSM2) */
2498 if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D)
2502 return vga_r(cinfo->regbase, regofs + regnum);
2505 /*** AttrOn() - turn on VideoEnable for Attribute controller ***/
2506 static void AttrOn(const struct cirrusfb_info *cinfo)
2508 assert(cinfo != NULL);
2510 if (vga_rcrt(cinfo->regbase, CL_CRT24) & 0x80) {
2511 /* if we're just in "write value" mode, write back the */
2512 /* same value as before to not modify anything */
2513 vga_w(cinfo->regbase, VGA_ATT_IW,
2514 vga_r(cinfo->regbase, VGA_ATT_R));
2516 /* turn on video bit */
2517 /* vga_w(cinfo->regbase, VGA_ATT_IW, 0x20); */
2518 vga_w(cinfo->regbase, VGA_ATT_IW, 0x33);
2520 /* dummy write on Reg0 to be on "write index" mode next time */
2521 vga_w(cinfo->regbase, VGA_ATT_IW, 0x00);
2524 /*** WHDR() - write into the Hidden DAC register ***/
2525 /* as the HDR is the only extension register that requires special treatment
2526 * (the other extension registers are accessible just like the "ordinary"
2527 * registers of their functional group) here is a specialized routine for
2530 static void WHDR(const struct cirrusfb_info *cinfo, unsigned char val)
2532 unsigned char dummy;
2534 if (cinfo->btype == BT_PICASSO) {
2535 /* Klaus' hint for correct access to HDR on some boards */
2536 /* first write 0 to pixel mask (3c6) */
2537 WGen(cinfo, VGA_PEL_MSK, 0x00);
2539 /* next read dummy from pixel address (3c8) */
2540 dummy = RGen(cinfo, VGA_PEL_IW);
2543 /* now do the usual stuff to access the HDR */
2545 dummy = RGen(cinfo, VGA_PEL_MSK);
2547 dummy = RGen(cinfo, VGA_PEL_MSK);
2549 dummy = RGen(cinfo, VGA_PEL_MSK);
2551 dummy = RGen(cinfo, VGA_PEL_MSK);
2554 WGen(cinfo, VGA_PEL_MSK, val);
2557 if (cinfo->btype == BT_PICASSO) {
2558 /* now first reset HDR access counter */
2559 dummy = RGen(cinfo, VGA_PEL_IW);
2562 /* and at the end, restore the mask value */
2563 /* ## is this mask always 0xff? */
2564 WGen(cinfo, VGA_PEL_MSK, 0xff);
2569 /*** WSFR() - write to the "special function register" (SFR) ***/
2570 static void WSFR(struct cirrusfb_info *cinfo, unsigned char val)
2573 assert(cinfo->regbase != NULL);
2575 z_writeb(val, cinfo->regbase + 0x8000);
2579 /* The Picasso has a second register for switching the monitor bit */
2580 static void WSFR2(struct cirrusfb_info *cinfo, unsigned char val)
2583 /* writing an arbitrary value to this one causes the monitor switcher */
2584 /* to flip to Amiga display */
2585 assert(cinfo->regbase != NULL);
2587 z_writeb(val, cinfo->regbase + 0x9000);
2591 /*** WClut - set CLUT entry (range: 0..63) ***/
2592 static void WClut(struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char red,
2593 unsigned char green, unsigned char blue)
2595 unsigned int data = VGA_PEL_D;
2597 /* address write mode register is not translated.. */
2598 vga_w(cinfo->regbase, VGA_PEL_IW, regnum);
2600 if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 ||
2601 cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480) {
2602 /* but DAC data register IS, at least for Picasso II */
2603 if (cinfo->btype == BT_PICASSO)
2605 vga_w(cinfo->regbase, data, red);
2606 vga_w(cinfo->regbase, data, green);
2607 vga_w(cinfo->regbase, data, blue);
2609 vga_w(cinfo->regbase, data, blue);
2610 vga_w(cinfo->regbase, data, green);
2611 vga_w(cinfo->regbase, data, red);
2616 /*** RClut - read CLUT entry (range 0..63) ***/
2617 static void RClut(struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char *red,
2618 unsigned char *green, unsigned char *blue)
2620 unsigned int data = VGA_PEL_D;
2622 vga_w(cinfo->regbase, VGA_PEL_IR, regnum);
2624 if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 ||
2625 cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480) {
2626 if (cinfo->btype == BT_PICASSO)
2628 *red = vga_r(cinfo->regbase, data);
2629 *green = vga_r(cinfo->regbase, data);
2630 *blue = vga_r(cinfo->regbase, data);
2632 *blue = vga_r(cinfo->regbase, data);
2633 *green = vga_r(cinfo->regbase, data);
2634 *red = vga_r(cinfo->regbase, data);
2639 /*******************************************************************
2642 Wait for the BitBLT engine to complete a possible earlier job
2643 *********************************************************************/
2645 /* FIXME: use interrupts instead */
2646 static void cirrusfb_WaitBLT(u8 __iomem *regbase)
2648 /* now busy-wait until we're done */
2649 while (vga_rgfx(regbase, CL_GR31) & 0x08)
2653 /*******************************************************************
2656 perform accelerated "scrolling"
2657 ********************************************************************/
2659 static void cirrusfb_BitBLT(u8 __iomem *regbase, int bits_per_pixel,
2660 u_short curx, u_short cury,
2661 u_short destx, u_short desty,
2662 u_short width, u_short height,
2663 u_short line_length)
2665 u_short nwidth, nheight;
2670 nheight = height - 1;
2673 /* if source adr < dest addr, do the Blt backwards */
2674 if (cury <= desty) {
2675 if (cury == desty) {
2676 /* if src and dest are on the same line, check x */
2683 /* standard case: forward blitting */
2684 nsrc = (cury * line_length) + curx;
2685 ndest = (desty * line_length) + destx;
2687 /* this means start addresses are at the end,
2688 * counting backwards
2690 nsrc = cury * line_length + curx +
2691 nheight * line_length + nwidth;
2692 ndest = desty * line_length + destx +
2693 nheight * line_length + nwidth;
2697 run-down of registers to be programmed:
2705 VGA_GFX_SR_VALUE / VGA_GFX_SR_ENABLE: "fill color"
2709 cirrusfb_WaitBLT(regbase);
2711 /* pitch: set to line_length */
2712 /* dest pitch low */
2713 vga_wgfx(regbase, CL_GR24, line_length & 0xff);
2715 vga_wgfx(regbase, CL_GR25, line_length >> 8);
2716 /* source pitch low */
2717 vga_wgfx(regbase, CL_GR26, line_length & 0xff);
2718 /* source pitch hi */
2719 vga_wgfx(regbase, CL_GR27, line_length >> 8);
2721 /* BLT width: actual number of pixels - 1 */
2723 vga_wgfx(regbase, CL_GR20, nwidth & 0xff);
2725 vga_wgfx(regbase, CL_GR21, nwidth >> 8);
2727 /* BLT height: actual number of lines -1 */
2728 /* BLT height low */
2729 vga_wgfx(regbase, CL_GR22, nheight & 0xff);
2731 vga_wgfx(regbase, CL_GR23, nheight >> 8);
2733 /* BLT destination */
2735 vga_wgfx(regbase, CL_GR28, (u_char) (ndest & 0xff));
2737 vga_wgfx(regbase, CL_GR29, (u_char) (ndest >> 8));
2739 vga_wgfx(regbase, CL_GR2A, (u_char) (ndest >> 16));
2743 vga_wgfx(regbase, CL_GR2C, (u_char) (nsrc & 0xff));
2745 vga_wgfx(regbase, CL_GR2D, (u_char) (nsrc >> 8));
2747 vga_wgfx(regbase, CL_GR2E, (u_char) (nsrc >> 16));
2750 vga_wgfx(regbase, CL_GR30, bltmode); /* BLT mode */
2752 /* BLT ROP: SrcCopy */
2753 vga_wgfx(regbase, CL_GR32, 0x0d); /* BLT ROP */
2755 /* and finally: GO! */
2756 vga_wgfx(regbase, CL_GR31, 0x02); /* BLT Start/status */
2759 /*******************************************************************
2762 perform accelerated rectangle fill
2763 ********************************************************************/
2765 static void cirrusfb_RectFill(u8 __iomem *regbase, int bits_per_pixel,
2766 u_short x, u_short y, u_short width, u_short height,
2767 u_char color, u_short line_length)
2769 u_short nwidth, nheight;
2774 nheight = height - 1;
2776 ndest = (y * line_length) + x;
2778 cirrusfb_WaitBLT(regbase);
2780 /* pitch: set to line_length */
2781 vga_wgfx(regbase, CL_GR24, line_length & 0xff); /* dest pitch low */
2782 vga_wgfx(regbase, CL_GR25, line_length >> 8); /* dest pitch hi */
2783 vga_wgfx(regbase, CL_GR26, line_length & 0xff); /* source pitch low */
2784 vga_wgfx(regbase, CL_GR27, line_length >> 8); /* source pitch hi */
2786 /* BLT width: actual number of pixels - 1 */
2787 vga_wgfx(regbase, CL_GR20, nwidth & 0xff); /* BLT width low */
2788 vga_wgfx(regbase, CL_GR21, nwidth >> 8); /* BLT width hi */
2790 /* BLT height: actual number of lines -1 */
2791 vga_wgfx(regbase, CL_GR22, nheight & 0xff); /* BLT height low */
2792 vga_wgfx(regbase, CL_GR23, nheight >> 8); /* BLT width hi */
2794 /* BLT destination */
2796 vga_wgfx(regbase, CL_GR28, (u_char) (ndest & 0xff));
2798 vga_wgfx(regbase, CL_GR29, (u_char) (ndest >> 8));
2800 vga_wgfx(regbase, CL_GR2A, (u_char) (ndest >> 16));
2802 /* BLT source: set to 0 (is a dummy here anyway) */
2803 vga_wgfx(regbase, CL_GR2C, 0x00); /* BLT src low */
2804 vga_wgfx(regbase, CL_GR2D, 0x00); /* BLT src mid */
2805 vga_wgfx(regbase, CL_GR2E, 0x00); /* BLT src hi */
2807 /* This is a ColorExpand Blt, using the */
2808 /* same color for foreground and background */
2809 vga_wgfx(regbase, VGA_GFX_SR_VALUE, color); /* foreground color */
2810 vga_wgfx(regbase, VGA_GFX_SR_ENABLE, color); /* background color */
2813 if (bits_per_pixel == 16) {
2814 vga_wgfx(regbase, CL_GR10, color); /* foreground color */
2815 vga_wgfx(regbase, CL_GR11, color); /* background color */
2818 } else if (bits_per_pixel == 32) {
2819 vga_wgfx(regbase, CL_GR10, color); /* foreground color */
2820 vga_wgfx(regbase, CL_GR11, color); /* background color */
2821 vga_wgfx(regbase, CL_GR12, color); /* foreground color */
2822 vga_wgfx(regbase, CL_GR13, color); /* background color */
2823 vga_wgfx(regbase, CL_GR14, 0); /* foreground color */
2824 vga_wgfx(regbase, CL_GR15, 0); /* background color */
2828 /* BLT mode: color expand, Enable 8x8 copy (faster?) */
2829 vga_wgfx(regbase, CL_GR30, op); /* BLT mode */
2831 /* BLT ROP: SrcCopy */
2832 vga_wgfx(regbase, CL_GR32, 0x0d); /* BLT ROP */
2834 /* and finally: GO! */
2835 vga_wgfx(regbase, CL_GR31, 0x02); /* BLT Start/status */
2838 /**************************************************************************
2839 * bestclock() - determine closest possible clock lower(?) than the
2840 * desired pixel clock
2841 **************************************************************************/
2842 static void bestclock(long freq, int *nom, int *den, int *div)
2847 assert(nom != NULL);
2848 assert(den != NULL);
2849 assert(div != NULL);
2860 for (n = 32; n < 128; n++) {
2863 d = (14318 * n) / freq;
2864 if ((d >= 7) && (d <= 63)) {
2871 h = ((14318 * n) / temp) >> s;
2872 h = h > freq ? h - freq : freq - h;
2881 if ((d >= 7) && (d <= 63)) {
2886 h = ((14318 * n) / d) >> s;
2887 h = h > freq ? h - freq : freq - h;
2898 /* -------------------------------------------------------------------------
2900 * debugging functions
2902 * -------------------------------------------------------------------------
2905 #ifdef CIRRUSFB_DEBUG
2908 * cirrusfb_dbg_print_regs
2909 * @base: If using newmmio, the newmmio base address, otherwise %NULL
2910 * @reg_class: type of registers to read: %CRT, or %SEQ
2913 * Dumps the given list of VGA CRTC registers. If @base is %NULL,
2914 * old-style I/O ports are queried for information, otherwise MMIO is
2915 * used at the given @base address to query the information.
2918 static void cirrusfb_dbg_print_regs(struct fb_info *info,
2920 enum cirrusfb_dbg_reg_class reg_class, ...)
2923 unsigned char val = 0;
2927 va_start(list, reg_class);
2929 name = va_arg(list, char *);
2930 while (name != NULL) {
2931 reg = va_arg(list, int);
2933 switch (reg_class) {
2935 val = vga_rcrt(regbase, (unsigned char) reg);
2938 val = vga_rseq(regbase, (unsigned char) reg);
2941 /* should never occur */
2946 dev_dbg(info->device, "%8s = 0x%02X\n", name, val);
2948 name = va_arg(list, char *);
2955 * cirrusfb_dbg_reg_dump
2956 * @base: If using newmmio, the newmmio base address, otherwise %NULL
2959 * Dumps a list of interesting VGA and CIRRUSFB registers. If @base is %NULL,
2960 * old-style I/O ports are queried for information, otherwise MMIO is
2961 * used at the given @base address to query the information.
2964 static void cirrusfb_dbg_reg_dump(struct fb_info *info, caddr_t regbase)
2966 dev_dbg(info->device, "VGA CRTC register dump:\n");
2968 cirrusfb_dbg_print_regs(info, regbase, CRT,
3018 dev_dbg(info->device, "\n");
3020 dev_dbg(info->device, "VGA SEQ register dump:\n");
3022 cirrusfb_dbg_print_regs(info, regbase, SEQ,
3051 dev_dbg(info->device, "\n");
3054 #endif /* CIRRUSFB_DEBUG */