2 * drivers/video/cirrusfb.c - driver for Cirrus Logic chipsets
4 * Copyright 1999-2001 Jeff Garzik <jgarzik@pobox.com>
6 * Contributors (thanks, all!)
9 * Overhaul for Linux 2.6
12 * Major contributions; Motorola PowerStack (PPC and PCI) support,
13 * GD54xx, 1280x1024 mode support, change MCLK based on VCLK.
16 * Excellent code review.
19 * Amiga updates and testing.
21 * Original cirrusfb author: Frank Neumann
23 * Based on retz3fb.c and cirrusfb.c:
24 * Copyright (C) 1997 Jes Sorensen
25 * Copyright (C) 1996 Frank Neumann
27 ***************************************************************
29 * Format this code with GNU indent '-kr -i8 -pcs' options.
31 * This file is subject to the terms and conditions of the GNU General Public
32 * License. See the file COPYING in the main directory of this archive
37 #define CIRRUSFB_VERSION "2.0-pre2"
39 #include <linux/module.h>
40 #include <linux/kernel.h>
41 #include <linux/errno.h>
42 #include <linux/string.h>
44 #include <linux/slab.h>
45 #include <linux/delay.h>
47 #include <linux/init.h>
48 #include <linux/selection.h>
49 #include <asm/pgtable.h>
52 #include <linux/zorro.h>
55 #include <linux/pci.h>
58 #include <asm/amigahw.h>
60 #ifdef CONFIG_PPC_PREP
61 #include <asm/machdep.h>
62 #define isPReP machine_is(prep)
67 #include "video/vga.h"
68 #include "video/cirrus.h"
70 /*****************************************************************
72 * debugging and utility macros
76 /* enable debug output? */
77 /* #define CIRRUSFB_DEBUG 1 */
79 /* disable runtime assertions? */
80 /* #define CIRRUSFB_NDEBUG */
84 #define DPRINTK(fmt, args...) \
85 printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
87 #define DPRINTK(fmt, args...)
90 /* debugging assertions */
91 #ifndef CIRRUSFB_NDEBUG
92 #define assert(expr) \
94 printk("Assertion failed! %s,%s,%s,line=%d\n", \
95 #expr, __FILE__, __FUNCTION__, __LINE__); \
101 #define MB_ (1024 * 1024)
104 #define MAX_NUM_BOARDS 7
106 /*****************************************************************
108 * chipset information
119 BT_PICASSO4, /* GD5446 */
120 BT_ALPINE, /* GD543x/4x */
122 BT_LAGUNA, /* GD546x */
126 * per-board-type information, used for enumerating and abstracting
127 * chip-specific information
128 * NOTE: MUST be in the same order as enum cirrus_board in order to
129 * use direct indexing on this array
130 * NOTE: '__initdata' cannot be used as some of this info
131 * is required at runtime. Maybe separate into an init-only and
134 static const struct cirrusfb_board_info_rec {
135 char *name; /* ASCII name of chipset */
136 long maxclock[5]; /* maximum video clock */
137 /* for 1/4bpp, 8bpp 15/16bpp, 24bpp, 32bpp - numbers from xorg code */
138 bool init_sr07 : 1; /* init SR07 during init_vgachip() */
139 bool init_sr1f : 1; /* write SR1F during init_vgachip() */
140 /* construct bit 19 of screen start address */
141 bool scrn_start_bit19 : 1;
143 /* initial SR07 value, then for each mode */
145 unsigned char sr07_1bpp;
146 unsigned char sr07_1bpp_mux;
147 unsigned char sr07_8bpp;
148 unsigned char sr07_8bpp_mux;
150 unsigned char sr1f; /* SR1F VGA initial register value */
151 } cirrusfb_board_info[] = {
156 /* the SD64/P4 have a higher max. videoclock */
157 140000, 140000, 140000, 140000, 140000,
161 .scrn_start_bit19 = true,
168 .name = "CL Piccolo",
171 90000, 90000, 90000, 90000, 90000
175 .scrn_start_bit19 = false,
182 .name = "CL Picasso",
185 90000, 90000, 90000, 90000, 90000
189 .scrn_start_bit19 = false,
196 .name = "CL Spectrum",
199 90000, 90000, 90000, 90000, 90000
203 .scrn_start_bit19 = false,
210 .name = "CL Picasso4",
212 135100, 135100, 85500, 85500, 0
216 .scrn_start_bit19 = true,
225 /* for the GD5430. GD5446 can do more... */
226 85500, 85500, 50000, 28500, 0
230 .scrn_start_bit19 = true,
233 .sr07_1bpp_mux = 0xA7,
235 .sr07_8bpp_mux = 0xA7,
241 135100, 200000, 200000, 135100, 135100
245 .scrn_start_bit19 = true,
255 135100, 135100, 135100, 135100, 135100,
259 .scrn_start_bit19 = true,
264 #define CHIP(id, btype) \
265 { PCI_VENDOR_ID_CIRRUS, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (btype) }
267 static struct pci_device_id cirrusfb_pci_table[] = {
268 CHIP(PCI_DEVICE_ID_CIRRUS_5436, BT_ALPINE),
269 CHIP(PCI_DEVICE_ID_CIRRUS_5434_8, BT_ALPINE),
270 CHIP(PCI_DEVICE_ID_CIRRUS_5434_4, BT_ALPINE),
271 CHIP(PCI_DEVICE_ID_CIRRUS_5430, BT_ALPINE), /* GD-5440 is same id */
272 CHIP(PCI_DEVICE_ID_CIRRUS_7543, BT_ALPINE),
273 CHIP(PCI_DEVICE_ID_CIRRUS_7548, BT_ALPINE),
274 CHIP(PCI_DEVICE_ID_CIRRUS_5480, BT_GD5480), /* MacPicasso likely */
275 CHIP(PCI_DEVICE_ID_CIRRUS_5446, BT_PICASSO4), /* Picasso 4 is 5446 */
276 CHIP(PCI_DEVICE_ID_CIRRUS_5462, BT_LAGUNA), /* CL Laguna */
277 CHIP(PCI_DEVICE_ID_CIRRUS_5464, BT_LAGUNA), /* CL Laguna 3D */
278 CHIP(PCI_DEVICE_ID_CIRRUS_5465, BT_LAGUNA), /* CL Laguna 3DA*/
281 MODULE_DEVICE_TABLE(pci, cirrusfb_pci_table);
283 #endif /* CONFIG_PCI */
286 static const struct zorro_device_id cirrusfb_zorro_table[] = {
288 .id = ZORRO_PROD_HELFRICH_SD64_RAM,
289 .driver_data = BT_SD64,
291 .id = ZORRO_PROD_HELFRICH_PICCOLO_RAM,
292 .driver_data = BT_PICCOLO,
294 .id = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_II_II_PLUS_RAM,
295 .driver_data = BT_PICASSO,
297 .id = ZORRO_PROD_GVP_EGS_28_24_SPECTRUM_RAM,
298 .driver_data = BT_SPECTRUM,
300 .id = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_IV_Z3,
301 .driver_data = BT_PICASSO4,
306 static const struct {
309 } cirrusfb_zorro_table2[] = {
311 .id2 = ZORRO_PROD_HELFRICH_SD64_REG,
315 .id2 = ZORRO_PROD_HELFRICH_PICCOLO_REG,
319 .id2 = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_II_II_PLUS_REG,
323 .id2 = ZORRO_PROD_GVP_EGS_28_24_SPECTRUM_REG,
331 #endif /* CONFIG_ZORRO */
333 struct cirrusfb_regs {
334 __u32 line_length; /* in BYTES! */
346 long HorizRes; /* The x resolution in pixel */
349 long HorizBlankStart;
354 long VertRes; /* the physical y resolution in scanlines */
363 #ifdef CIRRUSFB_DEBUG
364 enum cirrusfb_dbg_reg_class {
368 #endif /* CIRRUSFB_DEBUG */
370 /* info about board */
371 struct cirrusfb_info {
373 enum cirrus_board btype;
374 unsigned char SFR; /* Shadow of special function register */
376 struct cirrusfb_regs currentmode;
379 u32 pseudo_palette[16];
382 struct zorro_dev *zdev;
385 struct pci_dev *pdev;
387 void (*unmap)(struct fb_info *info);
390 static unsigned cirrusfb_def_mode = 1;
394 * Predefined Video Modes
397 static const struct {
399 struct fb_var_screeninfo var;
400 } cirrusfb_predefined[] = {
402 /* autodetect mode */
403 .name = "Autodetect",
405 /* 640x480, 31.25 kHz, 60 Hz, 25 MHz PixClock */
413 .red = { .length = 8 },
414 .green = { .length = 8 },
415 .blue = { .length = 8 },
425 .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
426 .vmode = FB_VMODE_NONINTERLACED
429 /* 800x600, 48 kHz, 76 Hz, 50 MHz PixClock */
437 .red = { .length = 8 },
438 .green = { .length = 8 },
439 .blue = { .length = 8 },
449 .vmode = FB_VMODE_NONINTERLACED
453 * Modeline from XF86Config:
454 * Mode "1024x768" 80 1024 1136 1340 1432 768 770 774 805
456 /* 1024x768, 55.8 kHz, 70 Hz, 80 MHz PixClock */
461 .xres_virtual = 1024,
464 .red = { .length = 8 },
465 .green = { .length = 8 },
466 .blue = { .length = 8 },
476 .vmode = FB_VMODE_NONINTERLACED
481 #define NUM_TOTAL_MODES ARRAY_SIZE(cirrusfb_predefined)
483 /****************************************************************************/
484 /**** BEGIN PROTOTYPES ******************************************************/
486 /*--- Interface used by the world ------------------------------------------*/
487 static int cirrusfb_init(void);
489 static int cirrusfb_setup(char *options);
492 static int cirrusfb_open(struct fb_info *info, int user);
493 static int cirrusfb_release(struct fb_info *info, int user);
494 static int cirrusfb_setcolreg(unsigned regno, unsigned red, unsigned green,
495 unsigned blue, unsigned transp,
496 struct fb_info *info);
497 static int cirrusfb_check_var(struct fb_var_screeninfo *var,
498 struct fb_info *info);
499 static int cirrusfb_set_par(struct fb_info *info);
500 static int cirrusfb_pan_display(struct fb_var_screeninfo *var,
501 struct fb_info *info);
502 static int cirrusfb_blank(int blank_mode, struct fb_info *info);
503 static void cirrusfb_fillrect(struct fb_info *info,
504 const struct fb_fillrect *region);
505 static void cirrusfb_copyarea(struct fb_info *info,
506 const struct fb_copyarea *area);
507 static void cirrusfb_imageblit(struct fb_info *info,
508 const struct fb_image *image);
510 /* function table of the above functions */
511 static struct fb_ops cirrusfb_ops = {
512 .owner = THIS_MODULE,
513 .fb_open = cirrusfb_open,
514 .fb_release = cirrusfb_release,
515 .fb_setcolreg = cirrusfb_setcolreg,
516 .fb_check_var = cirrusfb_check_var,
517 .fb_set_par = cirrusfb_set_par,
518 .fb_pan_display = cirrusfb_pan_display,
519 .fb_blank = cirrusfb_blank,
520 .fb_fillrect = cirrusfb_fillrect,
521 .fb_copyarea = cirrusfb_copyarea,
522 .fb_imageblit = cirrusfb_imageblit,
525 /*--- Hardware Specific Routines -------------------------------------------*/
526 static int cirrusfb_decode_var(const struct fb_var_screeninfo *var,
527 struct cirrusfb_regs *regs,
528 const struct fb_info *info);
529 /*--- Internal routines ----------------------------------------------------*/
530 static void init_vgachip(struct fb_info *info);
531 static void switch_monitor(struct cirrusfb_info *cinfo, int on);
532 static void WGen(const struct cirrusfb_info *cinfo,
533 int regnum, unsigned char val);
534 static unsigned char RGen(const struct cirrusfb_info *cinfo, int regnum);
535 static void AttrOn(const struct cirrusfb_info *cinfo);
536 static void WHDR(const struct cirrusfb_info *cinfo, unsigned char val);
537 static void WSFR(struct cirrusfb_info *cinfo, unsigned char val);
538 static void WSFR2(struct cirrusfb_info *cinfo, unsigned char val);
539 static void WClut(struct cirrusfb_info *cinfo, unsigned char regnum,
540 unsigned char red, unsigned char green, unsigned char blue);
542 static void RClut(struct cirrusfb_info *cinfo, unsigned char regnum,
543 unsigned char *red, unsigned char *green,
544 unsigned char *blue);
546 static void cirrusfb_WaitBLT(u8 __iomem *regbase);
547 static void cirrusfb_BitBLT(u8 __iomem *regbase, int bits_per_pixel,
548 u_short curx, u_short cury,
549 u_short destx, u_short desty,
550 u_short width, u_short height,
551 u_short line_length);
552 static void cirrusfb_RectFill(u8 __iomem *regbase, int bits_per_pixel,
553 u_short x, u_short y,
554 u_short width, u_short height,
555 u_char color, u_short line_length);
557 static void bestclock(long freq, long *best,
558 long *nom, long *den,
559 long *div, long maxfreq);
561 #ifdef CIRRUSFB_DEBUG
562 static void cirrusfb_dump(void);
563 static void cirrusfb_dbg_reg_dump(caddr_t regbase);
564 static void cirrusfb_dbg_print_regs(caddr_t regbase,
565 enum cirrusfb_dbg_reg_class reg_class, ...);
566 static void cirrusfb_dbg_print_byte(const char *name, unsigned char val);
567 #endif /* CIRRUSFB_DEBUG */
569 /*** END PROTOTYPES ********************************************************/
570 /*****************************************************************************/
571 /*** BEGIN Interface Used by the World ***************************************/
573 static int opencount;
575 /*--- Open /dev/fbx ---------------------------------------------------------*/
576 static int cirrusfb_open(struct fb_info *info, int user)
578 if (opencount++ == 0)
579 switch_monitor(info->par, 1);
583 /*--- Close /dev/fbx --------------------------------------------------------*/
584 static int cirrusfb_release(struct fb_info *info, int user)
586 if (--opencount == 0)
587 switch_monitor(info->par, 0);
591 /**** END Interface used by the World *************************************/
592 /****************************************************************************/
593 /**** BEGIN Hardware specific Routines **************************************/
595 /* Get a good MCLK value */
596 static long cirrusfb_get_mclk(long freq, int bpp, long *div)
602 /* Calculate MCLK, in case VCLK is high enough to require > 50MHz.
603 * Assume a 64-bit data path for now. The formula is:
604 * ((B * PCLK * 2)/W) * 1.2
605 * B = bytes per pixel, PCLK = pixclock, W = data width in bytes */
606 mclk = ((bpp / 8) * freq * 2) / 4;
607 mclk = (mclk * 12) / 10;
610 DPRINTK("Use MCLK of %ld kHz\n", mclk);
612 /* Calculate value for SR1F. Multiply by 2 so we can round up. */
613 mclk = ((mclk * 16) / 14318);
614 mclk = (mclk + 1) / 2;
615 DPRINTK("Set SR1F[5:0] to 0x%lx\n", mclk);
617 /* Determine if we should use MCLK instead of VCLK, and if so, what we
618 * should divide it by to get VCLK */
620 case 24751 ... 25249:
622 DPRINTK("Using VCLK = MCLK/2\n");
624 case 49501 ... 50499:
626 DPRINTK("Using VCLK = MCLK\n");
636 static int cirrusfb_check_var(struct fb_var_screeninfo *var,
637 struct fb_info *info)
639 int nom, den; /* translyting from pixels->bytes */
641 static struct { int xres, yres; } modes[] =
649 switch (var->bits_per_pixel) {
653 break; /* 8 pixel per byte, only 1/4th of mem usable */
658 nom = var->bits_per_pixel / 8;
660 break; /* 1 pixel == 1 byte */
662 printk(KERN_ERR "cirrusfb: mode %dx%dx%d rejected..."
663 "color depth not supported.\n",
664 var->xres, var->yres, var->bits_per_pixel);
665 DPRINTK("EXIT - EINVAL error\n");
669 if (var->xres * nom / den * var->yres > info->screen_size) {
670 printk(KERN_ERR "cirrusfb: mode %dx%dx%d rejected..."
671 "resolution too high to fit into video memory!\n",
672 var->xres, var->yres, var->bits_per_pixel);
673 DPRINTK("EXIT - EINVAL error\n");
677 /* use highest possible virtual resolution */
678 if (var->xres_virtual == -1 &&
679 var->yres_virtual == -1) {
681 "cirrusfb: using maximum available virtual resolution\n");
682 for (i = 0; modes[i].xres != -1; i++) {
683 int size = modes[i].xres * nom / den * modes[i].yres;
684 if (size < info->screen_size / 2)
687 if (modes[i].xres == -1) {
688 printk(KERN_ERR "cirrusfb: could not find a virtual "
689 "resolution that fits into video memory!!\n");
690 DPRINTK("EXIT - EINVAL error\n");
693 var->xres_virtual = modes[i].xres;
694 var->yres_virtual = modes[i].yres;
696 printk(KERN_INFO "cirrusfb: virtual resolution set to "
697 "maximum of %dx%d\n", var->xres_virtual,
701 if (var->xres_virtual < var->xres)
702 var->xres_virtual = var->xres;
703 if (var->yres_virtual < var->yres)
704 var->yres_virtual = var->yres;
706 if (var->xoffset < 0)
708 if (var->yoffset < 0)
711 /* truncate xoffset and yoffset to maximum if too high */
712 if (var->xoffset > var->xres_virtual - var->xres)
713 var->xoffset = var->xres_virtual - var->xres - 1;
714 if (var->yoffset > var->yres_virtual - var->yres)
715 var->yoffset = var->yres_virtual - var->yres - 1;
717 switch (var->bits_per_pixel) {
721 var->green = var->red;
722 var->blue = var->red;
728 var->green = var->red;
729 var->blue = var->red;
735 var->green.offset = -3;
736 var->blue.offset = 8;
738 var->red.offset = 10;
739 var->green.offset = 5;
740 var->blue.offset = 0;
743 var->green.length = 5;
744 var->blue.length = 5;
751 var->green.offset = 16;
752 var->blue.offset = 24;
754 var->red.offset = 16;
755 var->green.offset = 8;
756 var->blue.offset = 0;
759 var->green.length = 8;
760 var->blue.length = 8;
764 DPRINTK("Unsupported bpp size: %d\n", var->bits_per_pixel);
766 /* should never occur */
771 var->green.msb_right =
772 var->blue.msb_right =
775 var->transp.msb_right = 0;
778 if (var->vmode & FB_VMODE_DOUBLE)
780 else if (var->vmode & FB_VMODE_INTERLACED)
781 yres = (yres + 1) / 2;
784 printk(KERN_ERR "cirrusfb: ERROR: VerticalTotal >= 1280; "
785 "special treatment required! (TODO)\n");
786 DPRINTK("EXIT - EINVAL error\n");
793 static int cirrusfb_decode_var(const struct fb_var_screeninfo *var,
794 struct cirrusfb_regs *regs,
795 const struct fb_info *info)
799 int maxclockidx = var->bits_per_pixel >> 3;
800 struct cirrusfb_info *cinfo = info->par;
801 int xres, hfront, hsync, hback;
802 int yres, vfront, vsync, vback;
804 switch (var->bits_per_pixel) {
806 regs->line_length = var->xres_virtual / 8;
807 regs->visual = FB_VISUAL_MONO10;
811 regs->line_length = var->xres_virtual;
812 regs->visual = FB_VISUAL_PSEUDOCOLOR;
818 regs->line_length = var->xres_virtual * maxclockidx;
819 regs->visual = FB_VISUAL_DIRECTCOLOR;
823 DPRINTK("Unsupported bpp size: %d\n", var->bits_per_pixel);
825 /* should never occur */
829 regs->type = FB_TYPE_PACKED_PIXELS;
831 /* convert from ps to kHz */
832 freq = PICOS2KHZ(var->pixclock);
834 DPRINTK("desired pixclock: %ld kHz\n", freq);
836 maxclock = cirrusfb_board_info[cinfo->btype].maxclock[maxclockidx];
837 regs->multiplexing = 0;
839 /* If the frequency is greater than we can support, we might be able
840 * to use multiplexing for the video mode */
841 if (freq > maxclock) {
842 switch (cinfo->btype) {
845 regs->multiplexing = 1;
849 printk(KERN_ERR "cirrusfb: Frequency greater "
850 "than maxclock (%ld kHz)\n", maxclock);
851 DPRINTK("EXIT - return -EINVAL\n");
856 /* TODO: If we have a 1MB 5434, we need to put ourselves in a mode where
857 * the VCLK is double the pixel clock. */
858 switch (var->bits_per_pixel) {
861 if (regs->HorizRes <= 800)
862 /* Xbh has this type of clock for 32-bit */
868 bestclock(freq, ®s->freq, ®s->nom, ®s->den, ®s->div,
870 regs->mclk = cirrusfb_get_mclk(freq, var->bits_per_pixel,
874 hfront = var->right_margin;
875 hsync = var->hsync_len;
876 hback = var->left_margin;
879 vfront = var->lower_margin;
880 vsync = var->vsync_len;
881 vback = var->upper_margin;
883 if (var->vmode & FB_VMODE_DOUBLE) {
888 } else if (var->vmode & FB_VMODE_INTERLACED) {
889 yres = (yres + 1) / 2;
890 vfront = (vfront + 1) / 2;
891 vsync = (vsync + 1) / 2;
892 vback = (vback + 1) / 2;
894 regs->HorizRes = xres;
895 regs->HorizTotal = (xres + hfront + hsync + hback) / 8 - 5;
896 regs->HorizDispEnd = xres / 8 - 1;
897 regs->HorizBlankStart = xres / 8;
898 /* does not count with "-5" */
899 regs->HorizBlankEnd = regs->HorizTotal + 5;
900 regs->HorizSyncStart = (xres + hfront) / 8 + 1;
901 regs->HorizSyncEnd = (xres + hfront + hsync) / 8 + 1;
903 regs->VertRes = yres;
904 regs->VertTotal = yres + vfront + vsync + vback - 2;
905 regs->VertDispEnd = yres - 1;
906 regs->VertBlankStart = yres;
907 regs->VertBlankEnd = regs->VertTotal;
908 regs->VertSyncStart = yres + vfront - 1;
909 regs->VertSyncEnd = yres + vfront + vsync - 1;
911 if (regs->VertRes >= 1024) {
912 regs->VertTotal /= 2;
913 regs->VertSyncStart /= 2;
914 regs->VertSyncEnd /= 2;
915 regs->VertDispEnd /= 2;
917 if (regs->multiplexing) {
918 regs->HorizTotal /= 2;
919 regs->HorizSyncStart /= 2;
920 regs->HorizSyncEnd /= 2;
921 regs->HorizDispEnd /= 2;
927 static void cirrusfb_set_mclk(const struct cirrusfb_info *cinfo, int val,
930 assert(cinfo != NULL);
934 unsigned char old = vga_rseq(cinfo->regbase, CL_SEQR1E);
935 vga_wseq(cinfo->regbase, CL_SEQR1E, old | 0x1);
936 vga_wseq(cinfo->regbase, CL_SEQR1F, 0x40 | (val & 0x3f));
937 } else if (div == 1) {
939 unsigned char old = vga_rseq(cinfo->regbase, CL_SEQR1E);
940 vga_wseq(cinfo->regbase, CL_SEQR1E, old & ~0x1);
941 vga_wseq(cinfo->regbase, CL_SEQR1F, 0x40 | (val & 0x3f));
943 vga_wseq(cinfo->regbase, CL_SEQR1F, val & 0x3f);
947 /*************************************************************************
948 cirrusfb_set_par_foo()
950 actually writes the values for a new video mode into the hardware,
951 **************************************************************************/
952 static int cirrusfb_set_par_foo(struct fb_info *info)
954 struct cirrusfb_info *cinfo = info->par;
955 struct fb_var_screeninfo *var = &info->var;
956 struct cirrusfb_regs regs;
957 u8 __iomem *regbase = cinfo->regbase;
960 const struct cirrusfb_board_info_rec *bi;
963 DPRINTK("Requested mode: %dx%dx%d\n",
964 var->xres, var->yres, var->bits_per_pixel);
965 DPRINTK("pixclock: %d\n", var->pixclock);
969 err = cirrusfb_decode_var(var, ®s, info);
971 /* should never happen */
972 DPRINTK("mode change aborted. invalid var.\n");
976 bi = &cirrusfb_board_info[cinfo->btype];
978 /* unlock register VGA_CRTC_H_TOTAL..CRT7 */
979 vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, 0x20); /* previously: 0x00) */
981 /* if debugging is enabled, all parameters get output before writing */
982 DPRINTK("CRT0: %ld\n", regs.HorizTotal);
983 vga_wcrt(regbase, VGA_CRTC_H_TOTAL, regs.HorizTotal);
985 DPRINTK("CRT1: %ld\n", regs.HorizDispEnd);
986 vga_wcrt(regbase, VGA_CRTC_H_DISP, regs.HorizDispEnd);
988 DPRINTK("CRT2: %ld\n", regs.HorizBlankStart);
989 vga_wcrt(regbase, VGA_CRTC_H_BLANK_START, regs.HorizBlankStart);
991 /* + 128: Compatible read */
992 DPRINTK("CRT3: 128+%ld\n", regs.HorizBlankEnd % 32);
993 vga_wcrt(regbase, VGA_CRTC_H_BLANK_END,
994 128 + (regs.HorizBlankEnd % 32));
996 DPRINTK("CRT4: %ld\n", regs.HorizSyncStart);
997 vga_wcrt(regbase, VGA_CRTC_H_SYNC_START, regs.HorizSyncStart);
999 tmp = regs.HorizSyncEnd % 32;
1000 if (regs.HorizBlankEnd & 32)
1002 DPRINTK("CRT5: %d\n", tmp);
1003 vga_wcrt(regbase, VGA_CRTC_H_SYNC_END, tmp);
1005 DPRINTK("CRT6: %ld\n", regs.VertTotal & 0xff);
1006 vga_wcrt(regbase, VGA_CRTC_V_TOTAL, (regs.VertTotal & 0xff));
1008 tmp = 16; /* LineCompare bit #9 */
1009 if (regs.VertTotal & 256)
1011 if (regs.VertDispEnd & 256)
1013 if (regs.VertSyncStart & 256)
1015 if (regs.VertBlankStart & 256)
1017 if (regs.VertTotal & 512)
1019 if (regs.VertDispEnd & 512)
1021 if (regs.VertSyncStart & 512)
1023 DPRINTK("CRT7: %d\n", tmp);
1024 vga_wcrt(regbase, VGA_CRTC_OVERFLOW, tmp);
1026 tmp = 0x40; /* LineCompare bit #8 */
1027 if (regs.VertBlankStart & 512)
1029 if (var->vmode & FB_VMODE_DOUBLE)
1031 DPRINTK("CRT9: %d\n", tmp);
1032 vga_wcrt(regbase, VGA_CRTC_MAX_SCAN, tmp);
1034 DPRINTK("CRT10: %ld\n", regs.VertSyncStart & 0xff);
1035 vga_wcrt(regbase, VGA_CRTC_V_SYNC_START, regs.VertSyncStart & 0xff);
1037 DPRINTK("CRT11: 64+32+%ld\n", regs.VertSyncEnd % 16);
1038 vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, regs.VertSyncEnd % 16 + 64 + 32);
1040 DPRINTK("CRT12: %ld\n", regs.VertDispEnd & 0xff);
1041 vga_wcrt(regbase, VGA_CRTC_V_DISP_END, regs.VertDispEnd & 0xff);
1043 DPRINTK("CRT15: %ld\n", regs.VertBlankStart & 0xff);
1044 vga_wcrt(regbase, VGA_CRTC_V_BLANK_START, regs.VertBlankStart & 0xff);
1046 DPRINTK("CRT16: %ld\n", regs.VertBlankEnd & 0xff);
1047 vga_wcrt(regbase, VGA_CRTC_V_BLANK_END, regs.VertBlankEnd & 0xff);
1049 DPRINTK("CRT18: 0xff\n");
1050 vga_wcrt(regbase, VGA_CRTC_LINE_COMPARE, 0xff);
1053 if (var->vmode & FB_VMODE_INTERLACED)
1055 if (regs.HorizBlankEnd & 64)
1057 if (regs.HorizBlankEnd & 128)
1059 if (regs.VertBlankEnd & 256)
1061 if (regs.VertBlankEnd & 512)
1064 DPRINTK("CRT1a: %d\n", tmp);
1065 vga_wcrt(regbase, CL_CRT1A, tmp);
1068 /* hardware RefClock: 14.31818 MHz */
1069 /* formula: VClk = (OSC * N) / (D * (1+P)) */
1070 /* Example: VClk = (14.31818 * 91) / (23 * (1+1)) = 28.325 MHz */
1072 vga_wseq(regbase, CL_SEQRB, regs.nom);
1073 tmp = regs.den << 1;
1077 /* 6 bit denom; ONLY 5434!!! (bugged me 10 days) */
1078 if ((cinfo->btype == BT_SD64) ||
1079 (cinfo->btype == BT_ALPINE) ||
1080 (cinfo->btype == BT_GD5480))
1083 DPRINTK("CL_SEQR1B: %ld\n", (long) tmp);
1084 vga_wseq(regbase, CL_SEQR1B, tmp);
1086 if (regs.VertRes >= 1024)
1088 vga_wcrt(regbase, VGA_CRTC_MODE, 0xc7);
1090 /* mode control: VGA_CRTC_START_HI enable, ROTATE(?), 16bit
1091 * address wrap, no compat. */
1092 vga_wcrt(regbase, VGA_CRTC_MODE, 0xc3);
1094 /* HAEH? vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, 0x20);
1095 * previously: 0x00 unlock VGA_CRTC_H_TOTAL..CRT7 */
1097 /* don't know if it would hurt to also program this if no interlaced */
1098 /* mode is used, but I feel better this way.. :-) */
1099 if (var->vmode & FB_VMODE_INTERLACED)
1100 vga_wcrt(regbase, VGA_CRTC_REGS, regs.HorizTotal / 2);
1102 vga_wcrt(regbase, VGA_CRTC_REGS, 0x00); /* interlace control */
1104 vga_wseq(regbase, VGA_SEQ_CHARACTER_MAP, 0);
1106 /* adjust horizontal/vertical sync type (low/high) */
1107 /* enable display memory & CRTC I/O address for color mode */
1109 if (var->sync & FB_SYNC_HOR_HIGH_ACT)
1111 if (var->sync & FB_SYNC_VERT_HIGH_ACT)
1113 WGen(cinfo, VGA_MIS_W, tmp);
1115 /* Screen A Preset Row-Scan register */
1116 vga_wcrt(regbase, VGA_CRTC_PRESET_ROW, 0);
1117 /* text cursor on and start line */
1118 vga_wcrt(regbase, VGA_CRTC_CURSOR_START, 0);
1119 /* text cursor end line */
1120 vga_wcrt(regbase, VGA_CRTC_CURSOR_END, 31);
1122 /******************************************************
1128 /* programming for different color depths */
1129 if (var->bits_per_pixel == 1) {
1130 DPRINTK("cirrusfb: preparing for 1 bit deep display\n");
1131 vga_wgfx(regbase, VGA_GFX_MODE, 0); /* mode register */
1134 switch (cinfo->btype) {
1142 DPRINTK(" (for GD54xx)\n");
1143 vga_wseq(regbase, CL_SEQR7,
1145 bi->sr07_1bpp_mux : bi->sr07_1bpp);
1149 DPRINTK(" (for GD546x)\n");
1150 vga_wseq(regbase, CL_SEQR7,
1151 vga_rseq(regbase, CL_SEQR7) & ~0x01);
1155 printk(KERN_WARNING "cirrusfb: unknown Board\n");
1159 /* Extended Sequencer Mode */
1160 switch (cinfo->btype) {
1162 /* setting the SEQRF on SD64 is not necessary
1163 * (only during init)
1165 DPRINTK("(for SD64)\n");
1167 vga_wseq(regbase, CL_SEQR1F, 0x1a);
1172 DPRINTK("(for Piccolo/Spectrum)\n");
1173 /* ### ueberall 0x22? */
1174 /* ##vorher 1c MCLK select */
1175 vga_wseq(regbase, CL_SEQR1F, 0x22);
1176 /* evtl d0 bei 1 bit? avoid FIFO underruns..? */
1177 vga_wseq(regbase, CL_SEQRF, 0xb0);
1181 DPRINTK("(for Picasso)\n");
1182 /* ##vorher 22 MCLK select */
1183 vga_wseq(regbase, CL_SEQR1F, 0x22);
1184 /* ## vorher d0 avoid FIFO underruns..? */
1185 vga_wseq(regbase, CL_SEQRF, 0xd0);
1192 DPRINTK(" (for GD54xx)\n");
1197 printk(KERN_WARNING "cirrusfb: unknown Board\n");
1201 /* pixel mask: pass-through for first plane */
1202 WGen(cinfo, VGA_PEL_MSK, 0x01);
1203 if (regs.multiplexing)
1204 /* hidden dac reg: 1280x1024 */
1207 /* hidden dac: nothing */
1209 /* memory mode: odd/even, ext. memory */
1210 vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, 0x06);
1211 /* plane mask: only write to first plane */
1212 vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0x01);
1213 offset = var->xres_virtual / 16;
1216 /******************************************************
1222 else if (var->bits_per_pixel == 8) {
1223 DPRINTK("cirrusfb: preparing for 8 bit deep display\n");
1224 switch (cinfo->btype) {
1232 DPRINTK(" (for GD54xx)\n");
1233 vga_wseq(regbase, CL_SEQR7,
1235 bi->sr07_8bpp_mux : bi->sr07_8bpp);
1239 DPRINTK(" (for GD546x)\n");
1240 vga_wseq(regbase, CL_SEQR7,
1241 vga_rseq(regbase, CL_SEQR7) | 0x01);
1245 printk(KERN_WARNING "cirrusfb: unknown Board\n");
1249 switch (cinfo->btype) {
1252 vga_wseq(regbase, CL_SEQR1F, 0x1d);
1258 /* ### vorher 1c MCLK select */
1259 vga_wseq(regbase, CL_SEQR1F, 0x22);
1260 /* Fast Page-Mode writes */
1261 vga_wseq(regbase, CL_SEQRF, 0xb0);
1266 /* ### INCOMPLETE!! */
1267 vga_wseq(regbase, CL_SEQRF, 0xb8);
1269 /* vga_wseq(regbase, CL_SEQR1F, 0x1c); */
1273 DPRINTK(" (for GD543x)\n");
1274 cirrusfb_set_mclk(cinfo, regs.mclk, regs.divMCLK);
1275 /* We already set SRF and SR1F */
1280 DPRINTK(" (for GD54xx)\n");
1285 printk(KERN_WARNING "cirrusfb: unknown Board\n");
1289 /* mode register: 256 color mode */
1290 vga_wgfx(regbase, VGA_GFX_MODE, 64);
1291 /* pixel mask: pass-through all planes */
1292 WGen(cinfo, VGA_PEL_MSK, 0xff);
1293 if (regs.multiplexing)
1294 /* hidden dac reg: 1280x1024 */
1297 /* hidden dac: nothing */
1299 /* memory mode: chain4, ext. memory */
1300 vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, 0x0a);
1301 /* plane mask: enable writing to all 4 planes */
1302 vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0xff);
1303 offset = var->xres_virtual / 8;
1306 /******************************************************
1312 else if (var->bits_per_pixel == 16) {
1313 DPRINTK("cirrusfb: preparing for 16 bit deep display\n");
1314 switch (cinfo->btype) {
1316 /* Extended Sequencer Mode: 256c col. mode */
1317 vga_wseq(regbase, CL_SEQR7, 0xf7);
1319 vga_wseq(regbase, CL_SEQR1F, 0x1e);
1324 vga_wseq(regbase, CL_SEQR7, 0x87);
1325 /* Fast Page-Mode writes */
1326 vga_wseq(regbase, CL_SEQRF, 0xb0);
1328 vga_wseq(regbase, CL_SEQR1F, 0x22);
1332 vga_wseq(regbase, CL_SEQR7, 0x27);
1333 /* Fast Page-Mode writes */
1334 vga_wseq(regbase, CL_SEQRF, 0xb0);
1336 vga_wseq(regbase, CL_SEQR1F, 0x22);
1340 vga_wseq(regbase, CL_SEQR7, 0x27);
1341 /* vga_wseq(regbase, CL_SEQR1F, 0x1c); */
1345 DPRINTK(" (for GD543x)\n");
1346 if (regs.HorizRes >= 1024)
1347 vga_wseq(regbase, CL_SEQR7, 0xa7);
1349 vga_wseq(regbase, CL_SEQR7, 0xa3);
1350 cirrusfb_set_mclk(cinfo, regs.mclk, regs.divMCLK);
1354 DPRINTK(" (for GD5480)\n");
1355 vga_wseq(regbase, CL_SEQR7, 0x17);
1356 /* We already set SRF and SR1F */
1360 DPRINTK(" (for GD546x)\n");
1361 vga_wseq(regbase, CL_SEQR7,
1362 vga_rseq(regbase, CL_SEQR7) & ~0x01);
1366 printk(KERN_WARNING "CIRRUSFB: unknown Board\n");
1370 /* mode register: 256 color mode */
1371 vga_wgfx(regbase, VGA_GFX_MODE, 64);
1372 /* pixel mask: pass-through all planes */
1373 WGen(cinfo, VGA_PEL_MSK, 0xff);
1375 WHDR(cinfo, 0xc0); /* Copy Xbh */
1376 #elif defined(CONFIG_ZORRO)
1377 /* FIXME: CONFIG_PCI and CONFIG_ZORRO may be defined both */
1378 WHDR(cinfo, 0xa0); /* hidden dac reg: nothing special */
1380 /* memory mode: chain4, ext. memory */
1381 vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, 0x0a);
1382 /* plane mask: enable writing to all 4 planes */
1383 vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0xff);
1384 offset = var->xres_virtual / 4;
1387 /******************************************************
1393 else if (var->bits_per_pixel == 32) {
1394 DPRINTK("cirrusfb: preparing for 24/32 bit deep display\n");
1395 switch (cinfo->btype) {
1397 /* Extended Sequencer Mode: 256c col. mode */
1398 vga_wseq(regbase, CL_SEQR7, 0xf9);
1400 vga_wseq(regbase, CL_SEQR1F, 0x1e);
1405 vga_wseq(regbase, CL_SEQR7, 0x85);
1406 /* Fast Page-Mode writes */
1407 vga_wseq(regbase, CL_SEQRF, 0xb0);
1409 vga_wseq(regbase, CL_SEQR1F, 0x22);
1413 vga_wseq(regbase, CL_SEQR7, 0x25);
1414 /* Fast Page-Mode writes */
1415 vga_wseq(regbase, CL_SEQRF, 0xb0);
1417 vga_wseq(regbase, CL_SEQR1F, 0x22);
1421 vga_wseq(regbase, CL_SEQR7, 0x25);
1422 /* vga_wseq(regbase, CL_SEQR1F, 0x1c); */
1426 DPRINTK(" (for GD543x)\n");
1427 vga_wseq(regbase, CL_SEQR7, 0xa9);
1428 cirrusfb_set_mclk(cinfo, regs.mclk, regs.divMCLK);
1432 DPRINTK(" (for GD5480)\n");
1433 vga_wseq(regbase, CL_SEQR7, 0x19);
1434 /* We already set SRF and SR1F */
1438 DPRINTK(" (for GD546x)\n");
1439 vga_wseq(regbase, CL_SEQR7,
1440 vga_rseq(regbase, CL_SEQR7) & ~0x01);
1444 printk(KERN_WARNING "cirrusfb: unknown Board\n");
1448 /* mode register: 256 color mode */
1449 vga_wgfx(regbase, VGA_GFX_MODE, 64);
1450 /* pixel mask: pass-through all planes */
1451 WGen(cinfo, VGA_PEL_MSK, 0xff);
1452 /* hidden dac reg: 8-8-8 mode (24 or 32) */
1454 /* memory mode: chain4, ext. memory */
1455 vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, 0x0a);
1456 /* plane mask: enable writing to all 4 planes */
1457 vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0xff);
1458 offset = var->xres_virtual / 4;
1461 /******************************************************
1463 * unknown/unsupported bpp
1468 printk(KERN_ERR "cirrusfb: What's this?? "
1469 " requested color depth == %d.\n",
1470 var->bits_per_pixel);
1472 vga_wcrt(regbase, VGA_CRTC_OFFSET, offset & 0xff);
1475 tmp |= 0x10; /* offset overflow bit */
1477 /* screen start addr #16-18, fastpagemode cycles */
1478 vga_wcrt(regbase, CL_CRT1B, tmp);
1480 if (cinfo->btype == BT_SD64 ||
1481 cinfo->btype == BT_PICASSO4 ||
1482 cinfo->btype == BT_ALPINE ||
1483 cinfo->btype == BT_GD5480)
1484 /* screen start address bit 19 */
1485 vga_wcrt(regbase, CL_CRT1D, 0x00);
1487 /* text cursor location high */
1488 vga_wcrt(regbase, VGA_CRTC_CURSOR_HI, 0);
1489 /* text cursor location low */
1490 vga_wcrt(regbase, VGA_CRTC_CURSOR_LO, 0);
1491 /* underline row scanline = at very bottom */
1492 vga_wcrt(regbase, VGA_CRTC_UNDERLINE, 0);
1494 /* controller mode */
1495 vga_wattr(regbase, VGA_ATC_MODE, 1);
1496 /* overscan (border) color */
1497 vga_wattr(regbase, VGA_ATC_OVERSCAN, 0);
1498 /* color plane enable */
1499 vga_wattr(regbase, VGA_ATC_PLANE_ENABLE, 15);
1501 vga_wattr(regbase, CL_AR33, 0);
1503 vga_wattr(regbase, VGA_ATC_COLOR_PAGE, 0);
1505 /* [ EGS: SetOffset(); ] */
1506 /* From SetOffset(): Turn on VideoEnable bit in Attribute controller */
1509 /* set/reset register */
1510 vga_wgfx(regbase, VGA_GFX_SR_VALUE, 0);
1511 /* set/reset enable */
1512 vga_wgfx(regbase, VGA_GFX_SR_ENABLE, 0);
1514 vga_wgfx(regbase, VGA_GFX_COMPARE_VALUE, 0);
1516 vga_wgfx(regbase, VGA_GFX_DATA_ROTATE, 0);
1517 /* read map select */
1518 vga_wgfx(regbase, VGA_GFX_PLANE_READ, 0);
1519 /* miscellaneous register */
1520 vga_wgfx(regbase, VGA_GFX_MISC, 1);
1521 /* color don't care */
1522 vga_wgfx(regbase, VGA_GFX_COMPARE_MASK, 15);
1524 vga_wgfx(regbase, VGA_GFX_BIT_MASK, 255);
1526 /* graphics cursor attributes: nothing special */
1527 vga_wseq(regbase, CL_SEQR12, 0x0);
1529 /* finally, turn on everything - turn off "FullBandwidth" bit */
1530 /* also, set "DotClock%2" bit where requested */
1533 /*** FB_VMODE_CLOCK_HALVE in linux/fb.h not defined anymore ?
1534 if (var->vmode & FB_VMODE_CLOCK_HALVE)
1538 vga_wseq(regbase, VGA_SEQ_CLOCK_MODE, tmp);
1539 DPRINTK("CL_SEQR1: %d\n", tmp);
1541 cinfo->currentmode = regs;
1542 info->fix.type = regs.type;
1543 info->fix.visual = regs.visual;
1544 info->fix.line_length = regs.line_length;
1546 /* pan to requested offset */
1547 cirrusfb_pan_display(var, info);
1549 #ifdef CIRRUSFB_DEBUG
1557 /* for some reason incomprehensible to me, cirrusfb requires that you write
1558 * the registers twice for the settings to take..grr. -dte */
1559 static int cirrusfb_set_par(struct fb_info *info)
1561 cirrusfb_set_par_foo(info);
1562 return cirrusfb_set_par_foo(info);
1565 static int cirrusfb_setcolreg(unsigned regno, unsigned red, unsigned green,
1566 unsigned blue, unsigned transp,
1567 struct fb_info *info)
1569 struct cirrusfb_info *cinfo = info->par;
1574 if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
1576 red >>= (16 - info->var.red.length);
1577 green >>= (16 - info->var.green.length);
1578 blue >>= (16 - info->var.blue.length);
1582 v = (red << info->var.red.offset) |
1583 (green << info->var.green.offset) |
1584 (blue << info->var.blue.offset);
1586 cinfo->pseudo_palette[regno] = v;
1590 if (info->var.bits_per_pixel == 8)
1591 WClut(cinfo, regno, red >> 10, green >> 10, blue >> 10);
1597 /*************************************************************************
1598 cirrusfb_pan_display()
1600 performs display panning - provided hardware permits this
1601 **************************************************************************/
1602 static int cirrusfb_pan_display(struct fb_var_screeninfo *var,
1603 struct fb_info *info)
1608 unsigned char tmp = 0, tmp2 = 0, xpix;
1609 struct cirrusfb_info *cinfo = info->par;
1612 DPRINTK("virtual offset: (%d,%d)\n", var->xoffset, var->yoffset);
1614 /* no range checks for xoffset and yoffset, */
1615 /* as fb_pan_display has already done this */
1616 if (var->vmode & FB_VMODE_YWRAP)
1619 info->var.xoffset = var->xoffset;
1620 info->var.yoffset = var->yoffset;
1622 xoffset = var->xoffset * info->var.bits_per_pixel / 8;
1623 yoffset = var->yoffset;
1625 base = yoffset * cinfo->currentmode.line_length + xoffset;
1627 if (info->var.bits_per_pixel == 1) {
1628 /* base is already correct */
1629 xpix = (unsigned char) (var->xoffset % 8);
1632 xpix = (unsigned char) ((xoffset % 4) * 2);
1635 cirrusfb_WaitBLT(cinfo->regbase); /* make sure all the BLT's are done */
1637 /* lower 8 + 8 bits of screen start address */
1638 vga_wcrt(cinfo->regbase, VGA_CRTC_START_LO,
1639 (unsigned char) (base & 0xff));
1640 vga_wcrt(cinfo->regbase, VGA_CRTC_START_HI,
1641 (unsigned char) (base >> 8));
1643 /* construct bits 16, 17 and 18 of screen start address */
1651 /* 0xf2 is %11110010, exclude tmp bits */
1652 tmp2 = (vga_rcrt(cinfo->regbase, CL_CRT1B) & 0xf2) | tmp;
1653 vga_wcrt(cinfo->regbase, CL_CRT1B, tmp2);
1655 /* construct bit 19 of screen start address */
1656 if (cirrusfb_board_info[cinfo->btype].scrn_start_bit19)
1657 vga_wcrt(cinfo->regbase, CL_CRT1D, (base >> 12) & 0x80);
1659 /* write pixel panning value to AR33; this does not quite work in 8bpp
1661 * ### Piccolo..? Will this work?
1663 if (info->var.bits_per_pixel == 1)
1664 vga_wattr(cinfo->regbase, CL_AR33, xpix);
1666 cirrusfb_WaitBLT(cinfo->regbase);
1672 static int cirrusfb_blank(int blank_mode, struct fb_info *info)
1675 * Blank the screen if blank_mode != 0, else unblank. If blank == NULL
1676 * then the caller blanks by setting the CLUT (Color Look Up Table)
1677 * to all black. Return 0 if blanking succeeded, != 0 if un-/blanking
1678 * failed due to e.g. a video mode which doesn't support it.
1679 * Implements VESA suspend and powerdown modes on hardware that
1680 * supports disabling hsync/vsync:
1681 * blank_mode == 2: suspend vsync
1682 * blank_mode == 3: suspend hsync
1683 * blank_mode == 4: powerdown
1686 struct cirrusfb_info *cinfo = info->par;
1687 int current_mode = cinfo->blank_mode;
1689 DPRINTK("ENTER, blank mode = %d\n", blank_mode);
1691 if (info->state != FBINFO_STATE_RUNNING ||
1692 current_mode == blank_mode) {
1693 DPRINTK("EXIT, returning 0\n");
1698 if (current_mode == FB_BLANK_NORMAL ||
1699 current_mode == FB_BLANK_UNBLANK) {
1700 /* unblank the screen */
1701 val = vga_rseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE);
1702 /* clear "FullBandwidth" bit */
1703 vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, val & 0xdf);
1704 /* and undo VESA suspend trickery */
1705 vga_wgfx(cinfo->regbase, CL_GRE, 0x00);
1709 if (blank_mode > FB_BLANK_NORMAL) {
1710 /* blank the screen */
1711 val = vga_rseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE);
1712 /* set "FullBandwidth" bit */
1713 vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, val | 0x20);
1716 switch (blank_mode) {
1717 case FB_BLANK_UNBLANK:
1718 case FB_BLANK_NORMAL:
1720 case FB_BLANK_VSYNC_SUSPEND:
1721 vga_wgfx(cinfo->regbase, CL_GRE, 0x04);
1723 case FB_BLANK_HSYNC_SUSPEND:
1724 vga_wgfx(cinfo->regbase, CL_GRE, 0x02);
1726 case FB_BLANK_POWERDOWN:
1727 vga_wgfx(cinfo->regbase, CL_GRE, 0x06);
1730 DPRINTK("EXIT, returning 1\n");
1734 cinfo->blank_mode = blank_mode;
1735 DPRINTK("EXIT, returning 0\n");
1737 /* Let fbcon do a soft blank for us */
1738 return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
1740 /**** END Hardware specific Routines **************************************/
1741 /****************************************************************************/
1742 /**** BEGIN Internal Routines ***********************************************/
1744 static void init_vgachip(struct fb_info *info)
1746 struct cirrusfb_info *cinfo = info->par;
1747 const struct cirrusfb_board_info_rec *bi;
1751 assert(cinfo != NULL);
1753 bi = &cirrusfb_board_info[cinfo->btype];
1755 /* reset board globally */
1756 switch (cinfo->btype) {
1775 /* disable flickerfixer */
1776 vga_wcrt(cinfo->regbase, CL_CRT51, 0x00);
1778 /* from Klaus' NetBSD driver: */
1779 vga_wgfx(cinfo->regbase, CL_GR2F, 0x00);
1780 /* put blitter into 542x compat */
1781 vga_wgfx(cinfo->regbase, CL_GR33, 0x00);
1783 vga_wgfx(cinfo->regbase, CL_GR31, 0x00);
1787 /* from Klaus' NetBSD driver: */
1788 vga_wgfx(cinfo->regbase, CL_GR2F, 0x00);
1792 /* Nothing to do to reset the board. */
1796 printk(KERN_ERR "cirrusfb: Warning: Unknown board type\n");
1800 /* make sure RAM size set by this point */
1801 assert(info->screen_size > 0);
1803 /* the P4 is not fully initialized here; I rely on it having been */
1804 /* inited under AmigaOS already, which seems to work just fine */
1805 /* (Klaus advised to do it this way) */
1807 if (cinfo->btype != BT_PICASSO4) {
1808 WGen(cinfo, CL_VSSM, 0x10); /* EGS: 0x16 */
1809 WGen(cinfo, CL_POS102, 0x01);
1810 WGen(cinfo, CL_VSSM, 0x08); /* EGS: 0x0e */
1812 if (cinfo->btype != BT_SD64)
1813 WGen(cinfo, CL_VSSM2, 0x01);
1815 /* reset sequencer logic */
1816 vga_wseq(cinfo->regbase, CL_SEQR0, 0x03);
1818 /* FullBandwidth (video off) and 8/9 dot clock */
1819 vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, 0x21);
1820 /* polarity (-/-), disable access to display memory,
1821 * VGA_CRTC_START_HI base address: color
1823 WGen(cinfo, VGA_MIS_W, 0xc1);
1825 /* "magic cookie" - doesn't make any sense to me.. */
1826 /* vga_wgfx(cinfo->regbase, CL_GRA, 0xce); */
1827 /* unlock all extension registers */
1828 vga_wseq(cinfo->regbase, CL_SEQR6, 0x12);
1831 vga_wgfx(cinfo->regbase, CL_GR31, 0x04);
1833 switch (cinfo->btype) {
1835 vga_wseq(cinfo->regbase, CL_SEQRF, 0x98);
1840 vga_wseq(cinfo->regbase, CL_SEQRF, 0xb8);
1843 vga_wseq(cinfo->regbase, CL_SEQR16, 0x0f);
1844 vga_wseq(cinfo->regbase, CL_SEQRF, 0xb0);
1848 /* plane mask: nothing */
1849 vga_wseq(cinfo->regbase, VGA_SEQ_PLANE_WRITE, 0xff);
1850 /* character map select: doesn't even matter in gx mode */
1851 vga_wseq(cinfo->regbase, VGA_SEQ_CHARACTER_MAP, 0x00);
1852 /* memory mode: chain-4, no odd/even, ext. memory */
1853 vga_wseq(cinfo->regbase, VGA_SEQ_MEMORY_MODE, 0x0e);
1855 /* controller-internal base address of video memory */
1857 vga_wseq(cinfo->regbase, CL_SEQR7, bi->sr07);
1859 /* vga_wseq(cinfo->regbase, CL_SEQR8, 0x00); */
1860 /* EEPROM control: shouldn't be necessary to write to this at all.. */
1862 /* graphics cursor X position (incomplete; position gives rem. 3 bits */
1863 vga_wseq(cinfo->regbase, CL_SEQR10, 0x00);
1864 /* graphics cursor Y position (..."... ) */
1865 vga_wseq(cinfo->regbase, CL_SEQR11, 0x00);
1866 /* graphics cursor attributes */
1867 vga_wseq(cinfo->regbase, CL_SEQR12, 0x00);
1868 /* graphics cursor pattern address */
1869 vga_wseq(cinfo->regbase, CL_SEQR13, 0x00);
1871 /* writing these on a P4 might give problems.. */
1872 if (cinfo->btype != BT_PICASSO4) {
1873 /* configuration readback and ext. color */
1874 vga_wseq(cinfo->regbase, CL_SEQR17, 0x00);
1875 /* signature generator */
1876 vga_wseq(cinfo->regbase, CL_SEQR18, 0x02);
1879 /* MCLK select etc. */
1881 vga_wseq(cinfo->regbase, CL_SEQR1F, bi->sr1f);
1883 /* Screen A preset row scan: none */
1884 vga_wcrt(cinfo->regbase, VGA_CRTC_PRESET_ROW, 0x00);
1885 /* Text cursor start: disable text cursor */
1886 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_START, 0x20);
1887 /* Text cursor end: - */
1888 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_END, 0x00);
1889 /* Screen start address high: 0 */
1890 vga_wcrt(cinfo->regbase, VGA_CRTC_START_HI, 0x00);
1891 /* Screen start address low: 0 */
1892 vga_wcrt(cinfo->regbase, VGA_CRTC_START_LO, 0x00);
1893 /* text cursor location high: 0 */
1894 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_HI, 0x00);
1895 /* text cursor location low: 0 */
1896 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_LO, 0x00);
1898 /* Underline Row scanline: - */
1899 vga_wcrt(cinfo->regbase, VGA_CRTC_UNDERLINE, 0x00);
1900 /* mode control: timing enable, byte mode, no compat modes */
1901 vga_wcrt(cinfo->regbase, VGA_CRTC_MODE, 0xc3);
1902 /* Line Compare: not needed */
1903 vga_wcrt(cinfo->regbase, VGA_CRTC_LINE_COMPARE, 0x00);
1904 /* ### add 0x40 for text modes with > 30 MHz pixclock */
1905 /* ext. display controls: ext.adr. wrap */
1906 vga_wcrt(cinfo->regbase, CL_CRT1B, 0x02);
1908 /* Set/Reset registes: - */
1909 vga_wgfx(cinfo->regbase, VGA_GFX_SR_VALUE, 0x00);
1910 /* Set/Reset enable: - */
1911 vga_wgfx(cinfo->regbase, VGA_GFX_SR_ENABLE, 0x00);
1912 /* Color Compare: - */
1913 vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_VALUE, 0x00);
1914 /* Data Rotate: - */
1915 vga_wgfx(cinfo->regbase, VGA_GFX_DATA_ROTATE, 0x00);
1916 /* Read Map Select: - */
1917 vga_wgfx(cinfo->regbase, VGA_GFX_PLANE_READ, 0x00);
1918 /* Mode: conf. for 16/4/2 color mode, no odd/even, read/write mode 0 */
1919 vga_wgfx(cinfo->regbase, VGA_GFX_MODE, 0x00);
1920 /* Miscellaneous: memory map base address, graphics mode */
1921 vga_wgfx(cinfo->regbase, VGA_GFX_MISC, 0x01);
1922 /* Color Don't care: involve all planes */
1923 vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_MASK, 0x0f);
1924 /* Bit Mask: no mask at all */
1925 vga_wgfx(cinfo->regbase, VGA_GFX_BIT_MASK, 0xff);
1926 if (cinfo->btype == BT_ALPINE)
1927 /* (5434 can't have bit 3 set for bitblt) */
1928 vga_wgfx(cinfo->regbase, CL_GRB, 0x20);
1930 /* Graphics controller mode extensions: finer granularity,
1931 * 8byte data latches
1933 vga_wgfx(cinfo->regbase, CL_GRB, 0x28);
1935 vga_wgfx(cinfo->regbase, CL_GRC, 0xff); /* Color Key compare: - */
1936 vga_wgfx(cinfo->regbase, CL_GRD, 0x00); /* Color Key compare mask: - */
1937 vga_wgfx(cinfo->regbase, CL_GRE, 0x00); /* Miscellaneous control: - */
1938 /* Background color byte 1: - */
1939 /* vga_wgfx (cinfo->regbase, CL_GR10, 0x00); */
1940 /* vga_wgfx (cinfo->regbase, CL_GR11, 0x00); */
1942 /* Attribute Controller palette registers: "identity mapping" */
1943 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE0, 0x00);
1944 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE1, 0x01);
1945 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE2, 0x02);
1946 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE3, 0x03);
1947 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE4, 0x04);
1948 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE5, 0x05);
1949 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE6, 0x06);
1950 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE7, 0x07);
1951 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE8, 0x08);
1952 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE9, 0x09);
1953 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEA, 0x0a);
1954 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEB, 0x0b);
1955 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEC, 0x0c);
1956 vga_wattr(cinfo->regbase, VGA_ATC_PALETTED, 0x0d);
1957 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEE, 0x0e);
1958 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEF, 0x0f);
1960 /* Attribute Controller mode: graphics mode */
1961 vga_wattr(cinfo->regbase, VGA_ATC_MODE, 0x01);
1962 /* Overscan color reg.: reg. 0 */
1963 vga_wattr(cinfo->regbase, VGA_ATC_OVERSCAN, 0x00);
1964 /* Color Plane enable: Enable all 4 planes */
1965 vga_wattr(cinfo->regbase, VGA_ATC_PLANE_ENABLE, 0x0f);
1966 /* ### vga_wattr(cinfo->regbase, CL_AR33, 0x00); * Pixel Panning: - */
1967 /* Color Select: - */
1968 vga_wattr(cinfo->regbase, VGA_ATC_COLOR_PAGE, 0x00);
1970 WGen(cinfo, VGA_PEL_MSK, 0xff); /* Pixel mask: no mask */
1972 if (cinfo->btype != BT_ALPINE && cinfo->btype != BT_GD5480)
1973 /* polarity (-/-), enable display mem,
1974 * VGA_CRTC_START_HI i/o base = color
1976 WGen(cinfo, VGA_MIS_W, 0xc3);
1978 /* BLT Start/status: Blitter reset */
1979 vga_wgfx(cinfo->regbase, CL_GR31, 0x04);
1980 /* - " - : "end-of-reset" */
1981 vga_wgfx(cinfo->regbase, CL_GR31, 0x00);
1984 WHDR(cinfo, 0); /* Hidden DAC register: - */
1986 printk(KERN_DEBUG "cirrusfb: This board has %ld bytes of DRAM memory\n",
1992 static void switch_monitor(struct cirrusfb_info *cinfo, int on)
1994 #ifdef CONFIG_ZORRO /* only works on Zorro boards */
1995 static int IsOn = 0; /* XXX not ok for multiple boards */
1999 if (cinfo->btype == BT_PICASSO4)
2000 return; /* nothing to switch */
2001 if (cinfo->btype == BT_ALPINE)
2002 return; /* nothing to switch */
2003 if (cinfo->btype == BT_GD5480)
2004 return; /* nothing to switch */
2005 if (cinfo->btype == BT_PICASSO) {
2006 if ((on && !IsOn) || (!on && IsOn))
2013 switch (cinfo->btype) {
2015 WSFR(cinfo, cinfo->SFR | 0x21);
2018 WSFR(cinfo, cinfo->SFR | 0x28);
2023 default: /* do nothing */ break;
2026 switch (cinfo->btype) {
2028 WSFR(cinfo, cinfo->SFR & 0xde);
2031 WSFR(cinfo, cinfo->SFR & 0xd7);
2036 default: /* do nothing */ break;
2041 #endif /* CONFIG_ZORRO */
2044 /******************************************/
2045 /* Linux 2.6-style accelerated functions */
2046 /******************************************/
2048 static void cirrusfb_fillrect(struct fb_info *info,
2049 const struct fb_fillrect *region)
2051 struct fb_fillrect modded;
2053 struct cirrusfb_info *cinfo = info->par;
2054 int m = info->var.bits_per_pixel;
2055 u32 color = (info->fix.visual == FB_VISUAL_TRUECOLOR) ?
2056 cinfo->pseudo_palette[region->color] : region->color;
2058 if (info->state != FBINFO_STATE_RUNNING)
2060 if (info->flags & FBINFO_HWACCEL_DISABLED) {
2061 cfb_fillrect(info, region);
2065 vxres = info->var.xres_virtual;
2066 vyres = info->var.yres_virtual;
2068 memcpy(&modded, region, sizeof(struct fb_fillrect));
2070 if (!modded.width || !modded.height ||
2071 modded.dx >= vxres || modded.dy >= vyres)
2074 if (modded.dx + modded.width > vxres)
2075 modded.width = vxres - modded.dx;
2076 if (modded.dy + modded.height > vyres)
2077 modded.height = vyres - modded.dy;
2079 cirrusfb_RectFill(cinfo->regbase,
2080 info->var.bits_per_pixel,
2081 (region->dx * m) / 8, region->dy,
2082 (region->width * m) / 8, region->height,
2084 cinfo->currentmode.line_length);
2087 static void cirrusfb_copyarea(struct fb_info *info,
2088 const struct fb_copyarea *area)
2090 struct fb_copyarea modded;
2092 struct cirrusfb_info *cinfo = info->par;
2093 int m = info->var.bits_per_pixel;
2095 if (info->state != FBINFO_STATE_RUNNING)
2097 if (info->flags & FBINFO_HWACCEL_DISABLED) {
2098 cfb_copyarea(info, area);
2102 vxres = info->var.xres_virtual;
2103 vyres = info->var.yres_virtual;
2104 memcpy(&modded, area, sizeof(struct fb_copyarea));
2106 if (!modded.width || !modded.height ||
2107 modded.sx >= vxres || modded.sy >= vyres ||
2108 modded.dx >= vxres || modded.dy >= vyres)
2111 if (modded.sx + modded.width > vxres)
2112 modded.width = vxres - modded.sx;
2113 if (modded.dx + modded.width > vxres)
2114 modded.width = vxres - modded.dx;
2115 if (modded.sy + modded.height > vyres)
2116 modded.height = vyres - modded.sy;
2117 if (modded.dy + modded.height > vyres)
2118 modded.height = vyres - modded.dy;
2120 cirrusfb_BitBLT(cinfo->regbase, info->var.bits_per_pixel,
2121 (area->sx * m) / 8, area->sy,
2122 (area->dx * m) / 8, area->dy,
2123 (area->width * m) / 8, area->height,
2124 cinfo->currentmode.line_length);
2128 static void cirrusfb_imageblit(struct fb_info *info,
2129 const struct fb_image *image)
2131 struct cirrusfb_info *cinfo = info->par;
2133 cirrusfb_WaitBLT(cinfo->regbase);
2134 cfb_imageblit(info, image);
2137 #ifdef CONFIG_PPC_PREP
2138 #define PREP_VIDEO_BASE ((volatile unsigned long) 0xC0000000)
2139 #define PREP_IO_BASE ((volatile unsigned char *) 0x80000000)
2140 static void get_prep_addrs(unsigned long *display, unsigned long *registers)
2144 *display = PREP_VIDEO_BASE;
2145 *registers = (unsigned long) PREP_IO_BASE;
2150 #endif /* CONFIG_PPC_PREP */
2153 static int release_io_ports;
2155 /* Pulled the logic from XFree86 Cirrus driver to get the memory size,
2156 * based on the DRAM bandwidth bit and DRAM bank switching bit. This
2157 * works with 1MB, 2MB and 4MB configurations (which the Motorola boards
2159 static unsigned int cirrusfb_get_memsize(u8 __iomem *regbase)
2166 SRF = vga_rseq(regbase, CL_SEQRF);
2167 switch ((SRF & 0x18)) {
2174 /* 64-bit DRAM data bus width; assume 2MB. Also indicates 2MB memory
2181 printk(KERN_WARNING "CLgenfb: Unknown memory size!\n");
2185 /* If DRAM bank switching is enabled, there must be twice as much
2186 * memory installed. (4MB on the 5434)
2190 /* TODO: Handling of GD5446/5480 (see XF86 sources ...) */
2196 static void get_pci_addrs(const struct pci_dev *pdev,
2197 unsigned long *display, unsigned long *registers)
2199 assert(pdev != NULL);
2200 assert(display != NULL);
2201 assert(registers != NULL);
2208 /* This is a best-guess for now */
2210 if (pci_resource_flags(pdev, 0) & IORESOURCE_IO) {
2211 *display = pci_resource_start(pdev, 1);
2212 *registers = pci_resource_start(pdev, 0);
2214 *display = pci_resource_start(pdev, 0);
2215 *registers = pci_resource_start(pdev, 1);
2218 assert(*display != 0);
2223 static void cirrusfb_pci_unmap(struct fb_info *info)
2225 struct cirrusfb_info *cinfo = info->par;
2226 struct pci_dev *pdev = cinfo->pdev;
2228 iounmap(info->screen_base);
2229 #if 0 /* if system didn't claim this region, we would... */
2230 release_mem_region(0xA0000, 65535);
2232 if (release_io_ports)
2233 release_region(0x3C0, 32);
2234 pci_release_regions(pdev);
2236 #endif /* CONFIG_PCI */
2239 static void __devexit cirrusfb_zorro_unmap(struct cirrusfb_info *cinfo)
2241 zorro_release_device(cinfo->zdev);
2243 if (cinfo->btype == BT_PICASSO4) {
2244 cinfo->regbase -= 0x600000;
2245 iounmap((void *)cinfo->regbase);
2246 iounmap(info->screen_base);
2248 if (zorro_resource_start(cinfo->zdev) > 0x01000000)
2249 iounmap(info->screen_base);
2252 #endif /* CONFIG_ZORRO */
2254 static int cirrusfb_set_fbinfo(struct fb_info *info)
2256 struct cirrusfb_info *cinfo = info->par;
2257 struct fb_var_screeninfo *var = &info->var;
2259 info->pseudo_palette = cinfo->pseudo_palette;
2260 info->flags = FBINFO_DEFAULT
2261 | FBINFO_HWACCEL_XPAN
2262 | FBINFO_HWACCEL_YPAN
2263 | FBINFO_HWACCEL_FILLRECT
2264 | FBINFO_HWACCEL_COPYAREA;
2266 info->flags |= FBINFO_HWACCEL_DISABLED;
2267 info->fbops = &cirrusfb_ops;
2268 if (cinfo->btype == BT_GD5480) {
2269 if (var->bits_per_pixel == 16)
2270 info->screen_base += 1 * MB_;
2271 if (var->bits_per_pixel == 24 || var->bits_per_pixel == 32)
2272 info->screen_base += 2 * MB_;
2275 /* Fill fix common fields */
2276 strlcpy(info->fix.id, cirrusfb_board_info[cinfo->btype].name,
2277 sizeof(info->fix.id));
2279 /* monochrome: only 1 memory plane */
2280 /* 8 bit and above: Use whole memory area */
2281 info->fix.smem_len = info->screen_size;
2282 if (var->bits_per_pixel == 1)
2283 info->fix.smem_len /= 4;
2284 info->fix.type = cinfo->currentmode.type;
2285 info->fix.type_aux = 0;
2286 info->fix.visual = cinfo->currentmode.visual;
2287 info->fix.xpanstep = 1;
2288 info->fix.ypanstep = 1;
2289 info->fix.ywrapstep = 0;
2290 info->fix.line_length = cinfo->currentmode.line_length;
2292 /* FIXME: map region at 0xB8000 if available, fill in here */
2293 info->fix.mmio_len = 0;
2294 info->fix.accel = FB_ACCEL_NONE;
2296 fb_alloc_cmap(&info->cmap, 256, 0);
2301 static int cirrusfb_register(struct fb_info *info)
2303 struct cirrusfb_info *cinfo = info->par;
2305 enum cirrus_board btype;
2309 printk(KERN_INFO "cirrusfb: Driver for Cirrus Logic based "
2310 "graphic boards, v" CIRRUSFB_VERSION "\n");
2312 btype = cinfo->btype;
2315 assert(btype != BT_NONE);
2317 DPRINTK("cirrusfb: (RAM start set to: 0x%p)\n", info->screen_base);
2319 /* Make pretend we've set the var so our structures are in a "good" */
2320 /* state, even though we haven't written the mode to the hw yet... */
2321 info->var = cirrusfb_predefined[cirrusfb_def_mode].var;
2322 info->var.activate = FB_ACTIVATE_NOW;
2324 err = cirrusfb_decode_var(&info->var, &cinfo->currentmode, info);
2326 /* should never happen */
2327 DPRINTK("choking on default var... umm, no good.\n");
2328 goto err_unmap_cirrusfb;
2331 /* set all the vital stuff */
2332 cirrusfb_set_fbinfo(info);
2334 err = register_framebuffer(info);
2336 printk(KERN_ERR "cirrusfb: could not register "
2337 "fb device; err = %d!\n", err);
2338 goto err_dealloc_cmap;
2341 DPRINTK("EXIT, returning 0\n");
2345 fb_dealloc_cmap(&info->cmap);
2348 framebuffer_release(info);
2352 static void __devexit cirrusfb_cleanup(struct fb_info *info)
2354 struct cirrusfb_info *cinfo = info->par;
2357 switch_monitor(cinfo, 0);
2359 unregister_framebuffer(info);
2360 fb_dealloc_cmap(&info->cmap);
2361 printk("Framebuffer unregistered\n");
2363 framebuffer_release(info);
2369 static int cirrusfb_pci_register(struct pci_dev *pdev,
2370 const struct pci_device_id *ent)
2372 struct cirrusfb_info *cinfo;
2373 struct fb_info *info;
2374 enum cirrus_board btype;
2375 unsigned long board_addr, board_size;
2378 ret = pci_enable_device(pdev);
2380 printk(KERN_ERR "cirrusfb: Cannot enable PCI device\n");
2384 info = framebuffer_alloc(sizeof(struct cirrusfb_info), &pdev->dev);
2386 printk(KERN_ERR "cirrusfb: could not allocate memory\n");
2393 cinfo->btype = btype = (enum cirrus_board) ent->driver_data;
2395 DPRINTK(" Found PCI device, base address 0 is 0x%x, btype set to %d\n",
2396 pdev->resource[0].start, btype);
2397 DPRINTK(" base address 1 is 0x%x\n", pdev->resource[1].start);
2400 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, 0x00000000);
2401 #ifdef CONFIG_PPC_PREP
2402 get_prep_addrs(&board_addr, &info->fix.mmio_start);
2404 /* PReP dies if we ioremap the IO registers, but it works w/out... */
2405 cinfo->regbase = (char __iomem *) info->fix.mmio_start;
2407 DPRINTK("Attempt to get PCI info for Cirrus Graphics Card\n");
2408 get_pci_addrs(pdev, &board_addr, &info->fix.mmio_start);
2409 /* FIXME: this forces VGA. alternatives? */
2410 cinfo->regbase = NULL;
2413 DPRINTK("Board address: 0x%lx, register address: 0x%lx\n",
2414 board_addr, info->fix.mmio_start);
2416 board_size = (btype == BT_GD5480) ?
2417 32 * MB_ : cirrusfb_get_memsize(cinfo->regbase);
2419 ret = pci_request_regions(pdev, "cirrusfb");
2421 printk(KERN_ERR "cirrusfb: cannot reserve region 0x%lx, "
2424 goto err_release_fb;
2426 #if 0 /* if the system didn't claim this region, we would... */
2427 if (!request_mem_region(0xA0000, 65535, "cirrusfb")) {
2428 printk(KERN_ERR "cirrusfb: cannot reserve region 0x%lx, abort\n"
2432 goto err_release_regions;
2435 if (request_region(0x3C0, 32, "cirrusfb"))
2436 release_io_ports = 1;
2438 info->screen_base = ioremap(board_addr, board_size);
2439 if (!info->screen_base) {
2441 goto err_release_legacy;
2444 info->fix.smem_start = board_addr;
2445 info->screen_size = board_size;
2446 cinfo->unmap = cirrusfb_pci_unmap;
2448 printk(KERN_INFO " RAM (%lu kB) at 0xx%lx, ",
2449 info->screen_size / KB_, board_addr);
2450 printk(KERN_INFO "Cirrus Logic chipset on PCI bus\n");
2451 pci_set_drvdata(pdev, info);
2453 ret = cirrusfb_register(info);
2455 iounmap(info->screen_base);
2459 if (release_io_ports)
2460 release_region(0x3C0, 32);
2462 release_mem_region(0xA0000, 65535);
2463 err_release_regions:
2465 pci_release_regions(pdev);
2467 framebuffer_release(info);
2473 static void __devexit cirrusfb_pci_unregister(struct pci_dev *pdev)
2475 struct fb_info *info = pci_get_drvdata(pdev);
2478 cirrusfb_cleanup(info);
2483 static struct pci_driver cirrusfb_pci_driver = {
2485 .id_table = cirrusfb_pci_table,
2486 .probe = cirrusfb_pci_register,
2487 .remove = __devexit_p(cirrusfb_pci_unregister),
2490 .suspend = cirrusfb_pci_suspend,
2491 .resume = cirrusfb_pci_resume,
2495 #endif /* CONFIG_PCI */
2498 static int cirrusfb_zorro_register(struct zorro_dev *z,
2499 const struct zorro_device_id *ent)
2501 struct cirrusfb_info *cinfo;
2502 struct fb_info *info;
2503 enum cirrus_board btype;
2504 struct zorro_dev *z2 = NULL;
2505 unsigned long board_addr, board_size, size;
2508 btype = ent->driver_data;
2509 if (cirrusfb_zorro_table2[btype].id2)
2510 z2 = zorro_find_device(cirrusfb_zorro_table2[btype].id2, NULL);
2511 size = cirrusfb_zorro_table2[btype].size;
2512 printk(KERN_INFO "cirrusfb: %s board detected; ",
2513 cirrusfb_board_info[btype].name);
2515 info = framebuffer_alloc(sizeof(struct cirrusfb_info), &z->dev);
2517 printk(KERN_ERR "cirrusfb: could not allocate memory\n");
2524 cinfo->btype = btype;
2528 assert(btype != BT_NONE);
2531 board_addr = zorro_resource_start(z);
2532 board_size = zorro_resource_len(z);
2533 info->screen_size = size;
2535 if (!zorro_request_device(z, "cirrusfb")) {
2536 printk(KERN_ERR "cirrusfb: cannot reserve region 0x%lx, "
2540 goto err_release_fb;
2543 printk(" RAM (%lu MB) at $%lx, ", board_size / MB_, board_addr);
2547 if (btype == BT_PICASSO4) {
2548 printk(KERN_INFO " REG at $%lx\n", board_addr + 0x600000);
2550 /* To be precise, for the P4 this is not the */
2551 /* begin of the board, but the begin of RAM. */
2552 /* for P4, map in its address space in 2 chunks (### TEST! ) */
2553 /* (note the ugly hardcoded 16M number) */
2554 cinfo->regbase = ioremap(board_addr, 16777216);
2555 if (!cinfo->regbase)
2556 goto err_release_region;
2558 DPRINTK("cirrusfb: Virtual address for board set to: $%p\n",
2560 cinfo->regbase += 0x600000;
2561 info->fix.mmio_start = board_addr + 0x600000;
2563 info->fix.smem_start = board_addr + 16777216;
2564 info->screen_base = ioremap(info->fix.smem_start, 16777216);
2565 if (!info->screen_base)
2566 goto err_unmap_regbase;
2568 printk(KERN_INFO " REG at $%lx\n",
2569 (unsigned long) z2->resource.start);
2571 info->fix.smem_start = board_addr;
2572 if (board_addr > 0x01000000)
2573 info->screen_base = ioremap(board_addr, board_size);
2575 info->screen_base = (caddr_t) ZTWO_VADDR(board_addr);
2576 if (!info->screen_base)
2577 goto err_release_region;
2579 /* set address for REG area of board */
2580 cinfo->regbase = (caddr_t) ZTWO_VADDR(z2->resource.start);
2581 info->fix.mmio_start = z2->resource.start;
2583 DPRINTK("cirrusfb: Virtual address for board set to: $%p\n",
2586 cinfo->unmap = cirrusfb_zorro_unmap;
2588 printk(KERN_INFO "Cirrus Logic chipset on Zorro bus\n");
2589 zorro_set_drvdata(z, info);
2591 ret = cirrusfb_register(cinfo);
2593 if (btype == BT_PICASSO4) {
2594 iounmap(info->screen_base);
2595 iounmap(cinfo->regbase - 0x600000);
2596 } else if (board_addr > 0x01000000)
2597 iounmap(info->screen_base);
2602 /* Parental advisory: explicit hack */
2603 iounmap(cinfo->regbase - 0x600000);
2605 release_region(board_addr, board_size);
2607 framebuffer_release(info);
2612 void __devexit cirrusfb_zorro_unregister(struct zorro_dev *z)
2614 struct fb_info *info = zorro_get_drvdata(z);
2617 cirrusfb_cleanup(info);
2622 static struct zorro_driver cirrusfb_zorro_driver = {
2624 .id_table = cirrusfb_zorro_table,
2625 .probe = cirrusfb_zorro_register,
2626 .remove = __devexit_p(cirrusfb_zorro_unregister),
2628 #endif /* CONFIG_ZORRO */
2630 static int __init cirrusfb_init(void)
2635 char *option = NULL;
2637 if (fb_get_options("cirrusfb", &option))
2639 cirrusfb_setup(option);
2643 error |= zorro_register_driver(&cirrusfb_zorro_driver);
2646 error |= pci_register_driver(&cirrusfb_pci_driver);
2652 static int __init cirrusfb_setup(char *options) {
2653 char *this_opt, s[32];
2658 if (!options || !*options)
2661 while ((this_opt = strsep(&options, ",")) != NULL) {
2662 if (!*this_opt) continue;
2664 DPRINTK("cirrusfb_setup: option '%s'\n", this_opt);
2666 for (i = 0; i < NUM_TOTAL_MODES; i++) {
2667 sprintf(s, "mode:%s", cirrusfb_predefined[i].name);
2668 if (strcmp(this_opt, s) == 0)
2669 cirrusfb_def_mode = i;
2671 if (!strcmp(this_opt, "noaccel"))
2682 MODULE_AUTHOR("Copyright 1999,2000 Jeff Garzik <jgarzik@pobox.com>");
2683 MODULE_DESCRIPTION("Accelerated FBDev driver for Cirrus Logic chips");
2684 MODULE_LICENSE("GPL");
2686 static void __exit cirrusfb_exit(void)
2689 pci_unregister_driver(&cirrusfb_pci_driver);
2692 zorro_unregister_driver(&cirrusfb_zorro_driver);
2696 module_init(cirrusfb_init);
2699 module_exit(cirrusfb_exit);
2702 /**********************************************************************/
2703 /* about the following functions - I have used the same names for the */
2704 /* functions as Markus Wild did in his Retina driver for NetBSD as */
2705 /* they just made sense for this purpose. Apart from that, I wrote */
2706 /* these functions myself. */
2707 /**********************************************************************/
2709 /*** WGen() - write into one of the external/general registers ***/
2710 static void WGen(const struct cirrusfb_info *cinfo,
2711 int regnum, unsigned char val)
2713 unsigned long regofs = 0;
2715 if (cinfo->btype == BT_PICASSO) {
2716 /* Picasso II specific hack */
2717 /* if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D ||
2718 regnum == CL_VSSM2) */
2719 if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D)
2723 vga_w(cinfo->regbase, regofs + regnum, val);
2726 /*** RGen() - read out one of the external/general registers ***/
2727 static unsigned char RGen(const struct cirrusfb_info *cinfo, int regnum)
2729 unsigned long regofs = 0;
2731 if (cinfo->btype == BT_PICASSO) {
2732 /* Picasso II specific hack */
2733 /* if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D ||
2734 regnum == CL_VSSM2) */
2735 if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D)
2739 return vga_r(cinfo->regbase, regofs + regnum);
2742 /*** AttrOn() - turn on VideoEnable for Attribute controller ***/
2743 static void AttrOn(const struct cirrusfb_info *cinfo)
2745 assert(cinfo != NULL);
2749 if (vga_rcrt(cinfo->regbase, CL_CRT24) & 0x80) {
2750 /* if we're just in "write value" mode, write back the */
2751 /* same value as before to not modify anything */
2752 vga_w(cinfo->regbase, VGA_ATT_IW,
2753 vga_r(cinfo->regbase, VGA_ATT_R));
2755 /* turn on video bit */
2756 /* vga_w(cinfo->regbase, VGA_ATT_IW, 0x20); */
2757 vga_w(cinfo->regbase, VGA_ATT_IW, 0x33);
2759 /* dummy write on Reg0 to be on "write index" mode next time */
2760 vga_w(cinfo->regbase, VGA_ATT_IW, 0x00);
2765 /*** WHDR() - write into the Hidden DAC register ***/
2766 /* as the HDR is the only extension register that requires special treatment
2767 * (the other extension registers are accessible just like the "ordinary"
2768 * registers of their functional group) here is a specialized routine for
2771 static void WHDR(const struct cirrusfb_info *cinfo, unsigned char val)
2773 unsigned char dummy;
2775 if (cinfo->btype == BT_PICASSO) {
2776 /* Klaus' hint for correct access to HDR on some boards */
2777 /* first write 0 to pixel mask (3c6) */
2778 WGen(cinfo, VGA_PEL_MSK, 0x00);
2780 /* next read dummy from pixel address (3c8) */
2781 dummy = RGen(cinfo, VGA_PEL_IW);
2784 /* now do the usual stuff to access the HDR */
2786 dummy = RGen(cinfo, VGA_PEL_MSK);
2788 dummy = RGen(cinfo, VGA_PEL_MSK);
2790 dummy = RGen(cinfo, VGA_PEL_MSK);
2792 dummy = RGen(cinfo, VGA_PEL_MSK);
2795 WGen(cinfo, VGA_PEL_MSK, val);
2798 if (cinfo->btype == BT_PICASSO) {
2799 /* now first reset HDR access counter */
2800 dummy = RGen(cinfo, VGA_PEL_IW);
2803 /* and at the end, restore the mask value */
2804 /* ## is this mask always 0xff? */
2805 WGen(cinfo, VGA_PEL_MSK, 0xff);
2810 /*** WSFR() - write to the "special function register" (SFR) ***/
2811 static void WSFR(struct cirrusfb_info *cinfo, unsigned char val)
2814 assert(cinfo->regbase != NULL);
2816 z_writeb(val, cinfo->regbase + 0x8000);
2820 /* The Picasso has a second register for switching the monitor bit */
2821 static void WSFR2(struct cirrusfb_info *cinfo, unsigned char val)
2824 /* writing an arbitrary value to this one causes the monitor switcher */
2825 /* to flip to Amiga display */
2826 assert(cinfo->regbase != NULL);
2828 z_writeb(val, cinfo->regbase + 0x9000);
2832 /*** WClut - set CLUT entry (range: 0..63) ***/
2833 static void WClut(struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char red,
2834 unsigned char green, unsigned char blue)
2836 unsigned int data = VGA_PEL_D;
2838 /* address write mode register is not translated.. */
2839 vga_w(cinfo->regbase, VGA_PEL_IW, regnum);
2841 if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 ||
2842 cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480) {
2843 /* but DAC data register IS, at least for Picasso II */
2844 if (cinfo->btype == BT_PICASSO)
2846 vga_w(cinfo->regbase, data, red);
2847 vga_w(cinfo->regbase, data, green);
2848 vga_w(cinfo->regbase, data, blue);
2850 vga_w(cinfo->regbase, data, blue);
2851 vga_w(cinfo->regbase, data, green);
2852 vga_w(cinfo->regbase, data, red);
2857 /*** RClut - read CLUT entry (range 0..63) ***/
2858 static void RClut(struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char *red,
2859 unsigned char *green, unsigned char *blue)
2861 unsigned int data = VGA_PEL_D;
2863 vga_w(cinfo->regbase, VGA_PEL_IR, regnum);
2865 if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 ||
2866 cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480) {
2867 if (cinfo->btype == BT_PICASSO)
2869 *red = vga_r(cinfo->regbase, data);
2870 *green = vga_r(cinfo->regbase, data);
2871 *blue = vga_r(cinfo->regbase, data);
2873 *blue = vga_r(cinfo->regbase, data);
2874 *green = vga_r(cinfo->regbase, data);
2875 *red = vga_r(cinfo->regbase, data);
2880 /*******************************************************************
2883 Wait for the BitBLT engine to complete a possible earlier job
2884 *********************************************************************/
2886 /* FIXME: use interrupts instead */
2887 static void cirrusfb_WaitBLT(u8 __iomem *regbase)
2889 /* now busy-wait until we're done */
2890 while (vga_rgfx(regbase, CL_GR31) & 0x08)
2894 /*******************************************************************
2897 perform accelerated "scrolling"
2898 ********************************************************************/
2900 static void cirrusfb_BitBLT(u8 __iomem *regbase, int bits_per_pixel,
2901 u_short curx, u_short cury,
2902 u_short destx, u_short desty,
2903 u_short width, u_short height,
2904 u_short line_length)
2906 u_short nwidth, nheight;
2913 nheight = height - 1;
2916 /* if source adr < dest addr, do the Blt backwards */
2917 if (cury <= desty) {
2918 if (cury == desty) {
2919 /* if src and dest are on the same line, check x */
2926 /* standard case: forward blitting */
2927 nsrc = (cury * line_length) + curx;
2928 ndest = (desty * line_length) + destx;
2930 /* this means start addresses are at the end,
2931 * counting backwards
2933 nsrc = cury * line_length + curx +
2934 nheight * line_length + nwidth;
2935 ndest = desty * line_length + destx +
2936 nheight * line_length + nwidth;
2940 run-down of registers to be programmed:
2948 VGA_GFX_SR_VALUE / VGA_GFX_SR_ENABLE: "fill color"
2952 cirrusfb_WaitBLT(regbase);
2954 /* pitch: set to line_length */
2955 /* dest pitch low */
2956 vga_wgfx(regbase, CL_GR24, line_length & 0xff);
2958 vga_wgfx(regbase, CL_GR25, line_length >> 8);
2959 /* source pitch low */
2960 vga_wgfx(regbase, CL_GR26, line_length & 0xff);
2961 /* source pitch hi */
2962 vga_wgfx(regbase, CL_GR27, line_length >> 8);
2964 /* BLT width: actual number of pixels - 1 */
2966 vga_wgfx(regbase, CL_GR20, nwidth & 0xff);
2968 vga_wgfx(regbase, CL_GR21, nwidth >> 8);
2970 /* BLT height: actual number of lines -1 */
2971 /* BLT height low */
2972 vga_wgfx(regbase, CL_GR22, nheight & 0xff);
2974 vga_wgfx(regbase, CL_GR23, nheight >> 8);
2976 /* BLT destination */
2978 vga_wgfx(regbase, CL_GR28, (u_char) (ndest & 0xff));
2980 vga_wgfx(regbase, CL_GR29, (u_char) (ndest >> 8));
2982 vga_wgfx(regbase, CL_GR2A, (u_char) (ndest >> 16));
2986 vga_wgfx(regbase, CL_GR2C, (u_char) (nsrc & 0xff));
2988 vga_wgfx(regbase, CL_GR2D, (u_char) (nsrc >> 8));
2990 vga_wgfx(regbase, CL_GR2E, (u_char) (nsrc >> 16));
2993 vga_wgfx(regbase, CL_GR30, bltmode); /* BLT mode */
2995 /* BLT ROP: SrcCopy */
2996 vga_wgfx(regbase, CL_GR32, 0x0d); /* BLT ROP */
2998 /* and finally: GO! */
2999 vga_wgfx(regbase, CL_GR31, 0x02); /* BLT Start/status */
3004 /*******************************************************************
3007 perform accelerated rectangle fill
3008 ********************************************************************/
3010 static void cirrusfb_RectFill(u8 __iomem *regbase, int bits_per_pixel,
3011 u_short x, u_short y, u_short width, u_short height,
3012 u_char color, u_short line_length)
3014 u_short nwidth, nheight;
3021 nheight = height - 1;
3023 ndest = (y * line_length) + x;
3025 cirrusfb_WaitBLT(regbase);
3027 /* pitch: set to line_length */
3028 vga_wgfx(regbase, CL_GR24, line_length & 0xff); /* dest pitch low */
3029 vga_wgfx(regbase, CL_GR25, line_length >> 8); /* dest pitch hi */
3030 vga_wgfx(regbase, CL_GR26, line_length & 0xff); /* source pitch low */
3031 vga_wgfx(regbase, CL_GR27, line_length >> 8); /* source pitch hi */
3033 /* BLT width: actual number of pixels - 1 */
3034 vga_wgfx(regbase, CL_GR20, nwidth & 0xff); /* BLT width low */
3035 vga_wgfx(regbase, CL_GR21, nwidth >> 8); /* BLT width hi */
3037 /* BLT height: actual number of lines -1 */
3038 vga_wgfx(regbase, CL_GR22, nheight & 0xff); /* BLT height low */
3039 vga_wgfx(regbase, CL_GR23, nheight >> 8); /* BLT width hi */
3041 /* BLT destination */
3043 vga_wgfx(regbase, CL_GR28, (u_char) (ndest & 0xff));
3045 vga_wgfx(regbase, CL_GR29, (u_char) (ndest >> 8));
3047 vga_wgfx(regbase, CL_GR2A, (u_char) (ndest >> 16));
3049 /* BLT source: set to 0 (is a dummy here anyway) */
3050 vga_wgfx(regbase, CL_GR2C, 0x00); /* BLT src low */
3051 vga_wgfx(regbase, CL_GR2D, 0x00); /* BLT src mid */
3052 vga_wgfx(regbase, CL_GR2E, 0x00); /* BLT src hi */
3054 /* This is a ColorExpand Blt, using the */
3055 /* same color for foreground and background */
3056 vga_wgfx(regbase, VGA_GFX_SR_VALUE, color); /* foreground color */
3057 vga_wgfx(regbase, VGA_GFX_SR_ENABLE, color); /* background color */
3060 if (bits_per_pixel == 16) {
3061 vga_wgfx(regbase, CL_GR10, color); /* foreground color */
3062 vga_wgfx(regbase, CL_GR11, color); /* background color */
3065 } else if (bits_per_pixel == 32) {
3066 vga_wgfx(regbase, CL_GR10, color); /* foreground color */
3067 vga_wgfx(regbase, CL_GR11, color); /* background color */
3068 vga_wgfx(regbase, CL_GR12, color); /* foreground color */
3069 vga_wgfx(regbase, CL_GR13, color); /* background color */
3070 vga_wgfx(regbase, CL_GR14, 0); /* foreground color */
3071 vga_wgfx(regbase, CL_GR15, 0); /* background color */
3075 /* BLT mode: color expand, Enable 8x8 copy (faster?) */
3076 vga_wgfx(regbase, CL_GR30, op); /* BLT mode */
3078 /* BLT ROP: SrcCopy */
3079 vga_wgfx(regbase, CL_GR32, 0x0d); /* BLT ROP */
3081 /* and finally: GO! */
3082 vga_wgfx(regbase, CL_GR31, 0x02); /* BLT Start/status */
3087 /**************************************************************************
3088 * bestclock() - determine closest possible clock lower(?) than the
3089 * desired pixel clock
3090 **************************************************************************/
3091 static void bestclock(long freq, long *best, long *nom,
3092 long *den, long *div, long maxfreq)
3096 assert(best != NULL);
3097 assert(nom != NULL);
3098 assert(den != NULL);
3099 assert(div != NULL);
3100 assert(maxfreq > 0);
3117 for (n = 32; n < 128; n++) {
3118 d = (143181 * n) / f;
3119 if ((d >= 7) && (d <= 63)) {
3122 h = (14318 * n) / d;
3123 if (abs(h - freq) < abs(*best - freq)) {
3135 d = ((143181 * n) + f - 1) / f;
3136 if ((d >= 7) && (d <= 63)) {
3139 h = (14318 * n) / d;
3140 if (abs(h - freq) < abs(*best - freq)) {
3154 DPRINTK("Best possible values for given frequency:\n");
3155 DPRINTK(" best: %ld kHz nom: %ld den: %ld div: %ld\n",
3156 freq, *nom, *den, *div);
3161 /* -------------------------------------------------------------------------
3163 * debugging functions
3165 * -------------------------------------------------------------------------
3168 #ifdef CIRRUSFB_DEBUG
3171 * cirrusfb_dbg_print_byte
3172 * @name: name associated with byte value to be displayed
3173 * @val: byte value to be displayed
3176 * Display an indented string, along with a hexidecimal byte value, and
3177 * its decoded bits. Bits 7 through 0 are listed in left-to-right
3182 void cirrusfb_dbg_print_byte(const char *name, unsigned char val)
3184 DPRINTK("%8s = 0x%02X (bits 7-0: %c%c%c%c%c%c%c%c)\n",
3186 val & 0x80 ? '1' : '0',
3187 val & 0x40 ? '1' : '0',
3188 val & 0x20 ? '1' : '0',
3189 val & 0x10 ? '1' : '0',
3190 val & 0x08 ? '1' : '0',
3191 val & 0x04 ? '1' : '0',
3192 val & 0x02 ? '1' : '0',
3193 val & 0x01 ? '1' : '0');
3197 * cirrusfb_dbg_print_regs
3198 * @base: If using newmmio, the newmmio base address, otherwise %NULL
3199 * @reg_class: type of registers to read: %CRT, or %SEQ
3202 * Dumps the given list of VGA CRTC registers. If @base is %NULL,
3203 * old-style I/O ports are queried for information, otherwise MMIO is
3204 * used at the given @base address to query the information.
3208 void cirrusfb_dbg_print_regs(caddr_t regbase,
3209 enum cirrusfb_dbg_reg_class reg_class, ...)
3212 unsigned char val = 0;
3216 va_start(list, reg_class);
3218 name = va_arg(list, char *);
3219 while (name != NULL) {
3220 reg = va_arg(list, int);
3222 switch (reg_class) {
3224 val = vga_rcrt(regbase, (unsigned char) reg);
3227 val = vga_rseq(regbase, (unsigned char) reg);
3230 /* should never occur */
3235 cirrusfb_dbg_print_byte(name, val);
3237 name = va_arg(list, char *);
3250 static void cirrusfb_dump(void)
3252 cirrusfb_dbg_reg_dump(NULL);
3256 * cirrusfb_dbg_reg_dump
3257 * @base: If using newmmio, the newmmio base address, otherwise %NULL
3260 * Dumps a list of interesting VGA and CIRRUSFB registers. If @base is %NULL,
3261 * old-style I/O ports are queried for information, otherwise MMIO is
3262 * used at the given @base address to query the information.
3266 void cirrusfb_dbg_reg_dump(caddr_t regbase)
3268 DPRINTK("CIRRUSFB VGA CRTC register dump:\n");
3270 cirrusfb_dbg_print_regs(regbase, CRT,
3322 DPRINTK("CIRRUSFB VGA SEQ register dump:\n");
3324 cirrusfb_dbg_print_regs(regbase, SEQ,
3356 #endif /* CIRRUSFB_DEBUG */