2 * drivers/video/cirrusfb.c - driver for Cirrus Logic chipsets
4 * Copyright 1999-2001 Jeff Garzik <jgarzik@pobox.com>
6 * Contributors (thanks, all!)
9 * Overhaul for Linux 2.6
12 * Major contributions; Motorola PowerStack (PPC and PCI) support,
13 * GD54xx, 1280x1024 mode support, change MCLK based on VCLK.
16 * Excellent code review.
19 * Amiga updates and testing.
21 * Original cirrusfb author: Frank Neumann
23 * Based on retz3fb.c and cirrusfb.c:
24 * Copyright (C) 1997 Jes Sorensen
25 * Copyright (C) 1996 Frank Neumann
27 ***************************************************************
29 * Format this code with GNU indent '-kr -i8 -pcs' options.
31 * This file is subject to the terms and conditions of the GNU General Public
32 * License. See the file COPYING in the main directory of this archive
37 #include <linux/module.h>
38 #include <linux/kernel.h>
39 #include <linux/errno.h>
40 #include <linux/string.h>
42 #include <linux/delay.h>
44 #include <linux/init.h>
45 #include <asm/pgtable.h>
48 #include <linux/zorro.h>
51 #include <linux/pci.h>
54 #include <asm/amigahw.h>
57 #include <video/vga.h>
58 #include <video/cirrus.h>
60 /*****************************************************************
62 * debugging and utility macros
66 /* disable runtime assertions? */
67 /* #define CIRRUSFB_NDEBUG */
69 /* debugging assertions */
70 #ifndef CIRRUSFB_NDEBUG
71 #define assert(expr) \
73 printk("Assertion failed! %s,%s,%s,line=%d\n", \
74 #expr, __FILE__, __func__, __LINE__); \
80 #define MB_ (1024 * 1024)
82 /*****************************************************************
92 BT_PICCOLO, /* GD5426 */
93 BT_PICASSO, /* GD5426 or GD5428 */
94 BT_SPECTRUM, /* GD5426 or GD5428 */
95 BT_PICASSO4, /* GD5446 */
96 BT_ALPINE, /* GD543x/4x */
98 BT_LAGUNA, /* GD5462/64 */
99 BT_LAGUNAB, /* GD5465 */
103 * per-board-type information, used for enumerating and abstracting
104 * chip-specific information
105 * NOTE: MUST be in the same order as enum cirrus_board in order to
106 * use direct indexing on this array
107 * NOTE: '__initdata' cannot be used as some of this info
108 * is required at runtime. Maybe separate into an init-only and
111 static const struct cirrusfb_board_info_rec {
112 char *name; /* ASCII name of chipset */
113 long maxclock[5]; /* maximum video clock */
114 /* for 1/4bpp, 8bpp 15/16bpp, 24bpp, 32bpp - numbers from xorg code */
115 bool init_sr07 : 1; /* init SR07 during init_vgachip() */
116 bool init_sr1f : 1; /* write SR1F during init_vgachip() */
117 /* construct bit 19 of screen start address */
118 bool scrn_start_bit19 : 1;
120 /* initial SR07 value, then for each mode */
122 unsigned char sr07_1bpp;
123 unsigned char sr07_1bpp_mux;
124 unsigned char sr07_8bpp;
125 unsigned char sr07_8bpp_mux;
127 unsigned char sr1f; /* SR1F VGA initial register value */
128 } cirrusfb_board_info[] = {
133 /* the SD64/P4 have a higher max. videoclock */
134 135100, 135100, 85500, 85500, 0
138 .scrn_start_bit19 = true,
141 .sr07_1bpp_mux = 0xF6,
143 .sr07_8bpp_mux = 0xF7,
147 .name = "CL Piccolo",
150 90000, 90000, 90000, 90000, 90000
154 .scrn_start_bit19 = false,
161 .name = "CL Picasso",
164 90000, 90000, 90000, 90000, 90000
168 .scrn_start_bit19 = false,
175 .name = "CL Spectrum",
178 90000, 90000, 90000, 90000, 90000
182 .scrn_start_bit19 = false,
189 .name = "CL Picasso4",
191 135100, 135100, 85500, 85500, 0
195 .scrn_start_bit19 = true,
198 .sr07_1bpp_mux = 0xA6,
200 .sr07_8bpp_mux = 0xA7,
206 /* for the GD5430. GD5446 can do more... */
207 85500, 85500, 50000, 28500, 0
211 .scrn_start_bit19 = true,
214 .sr07_1bpp_mux = 0xA6,
216 .sr07_8bpp_mux = 0xA7,
222 135100, 200000, 200000, 135100, 135100
226 .scrn_start_bit19 = true,
235 /* taken from X11 code */
236 170000, 170000, 170000, 170000, 135100,
240 .scrn_start_bit19 = true,
243 .name = "CL Laguna AGP",
245 /* taken from X11 code */
246 170000, 250000, 170000, 170000, 135100,
250 .scrn_start_bit19 = true,
255 #define CHIP(id, btype) \
256 { PCI_VENDOR_ID_CIRRUS, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (btype) }
258 static struct pci_device_id cirrusfb_pci_table[] = {
259 CHIP(PCI_DEVICE_ID_CIRRUS_5436, BT_ALPINE),
260 CHIP(PCI_DEVICE_ID_CIRRUS_5434_8, BT_SD64),
261 CHIP(PCI_DEVICE_ID_CIRRUS_5434_4, BT_SD64),
262 CHIP(PCI_DEVICE_ID_CIRRUS_5430, BT_ALPINE), /* GD-5440 is same id */
263 CHIP(PCI_DEVICE_ID_CIRRUS_7543, BT_ALPINE),
264 CHIP(PCI_DEVICE_ID_CIRRUS_7548, BT_ALPINE),
265 CHIP(PCI_DEVICE_ID_CIRRUS_5480, BT_GD5480), /* MacPicasso likely */
266 CHIP(PCI_DEVICE_ID_CIRRUS_5446, BT_PICASSO4), /* Picasso 4 is 5446 */
267 CHIP(PCI_DEVICE_ID_CIRRUS_5462, BT_LAGUNA), /* CL Laguna */
268 CHIP(PCI_DEVICE_ID_CIRRUS_5464, BT_LAGUNA), /* CL Laguna 3D */
269 CHIP(PCI_DEVICE_ID_CIRRUS_5465, BT_LAGUNAB), /* CL Laguna 3DA*/
272 MODULE_DEVICE_TABLE(pci, cirrusfb_pci_table);
274 #endif /* CONFIG_PCI */
278 enum cirrus_board type; /* Board type */
279 u32 regoffset; /* Offset of registers in first Zorro device */
280 u32 ramsize; /* Size of video RAM in first Zorro device */
281 /* If zero, use autoprobe on RAM device */
282 u32 ramoffset; /* Offset of video RAM in first Zorro device */
283 zorro_id ramid; /* Zorro ID of RAM device */
284 zorro_id ramid2; /* Zorro ID of optional second RAM device */
287 static const struct zorrocl zcl_sd64 = {
289 .ramid = ZORRO_PROD_HELFRICH_SD64_RAM,
292 static const struct zorrocl zcl_piccolo = {
294 .ramid = ZORRO_PROD_HELFRICH_PICCOLO_RAM,
297 static const struct zorrocl zcl_picasso = {
299 .ramid = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_II_II_PLUS_RAM,
302 static const struct zorrocl zcl_spectrum = {
304 .ramid = ZORRO_PROD_GVP_EGS_28_24_SPECTRUM_RAM,
307 static const struct zorrocl zcl_picasso4_z3 = {
309 .regoffset = 0x00600000,
311 .ramoffset = 0x01000000, /* 0x02000000 for 64 MiB boards */
314 static const struct zorrocl zcl_picasso4_z2 = {
316 .regoffset = 0x10000,
317 .ramid = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_IV_Z2_RAM1,
318 .ramid2 = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_IV_Z2_RAM2,
322 static const struct zorro_device_id cirrusfb_zorro_table[] = {
324 .id = ZORRO_PROD_HELFRICH_SD64_REG,
325 .driver_data = (unsigned long)&zcl_sd64,
327 .id = ZORRO_PROD_HELFRICH_PICCOLO_REG,
328 .driver_data = (unsigned long)&zcl_piccolo,
330 .id = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_II_II_PLUS_REG,
331 .driver_data = (unsigned long)&zcl_picasso,
333 .id = ZORRO_PROD_GVP_EGS_28_24_SPECTRUM_REG,
334 .driver_data = (unsigned long)&zcl_spectrum,
336 .id = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_IV_Z3,
337 .driver_data = (unsigned long)&zcl_picasso4_z3,
339 .id = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_IV_Z2_REG,
340 .driver_data = (unsigned long)&zcl_picasso4_z2,
344 MODULE_DEVICE_TABLE(zorro, cirrusfb_zorro_table);
345 #endif /* CONFIG_ZORRO */
347 #ifdef CIRRUSFB_DEBUG
348 enum cirrusfb_dbg_reg_class {
352 #endif /* CIRRUSFB_DEBUG */
354 /* info about board */
355 struct cirrusfb_info {
357 u8 __iomem *laguna_mmio;
358 enum cirrus_board btype;
359 unsigned char SFR; /* Shadow of special function register */
364 u32 pseudo_palette[16];
366 void (*unmap)(struct fb_info *info);
370 static char *mode_option = "640x480@60";
372 /****************************************************************************/
373 /**** BEGIN PROTOTYPES ******************************************************/
375 /*--- Interface used by the world ------------------------------------------*/
376 static int cirrusfb_pan_display(struct fb_var_screeninfo *var,
377 struct fb_info *info);
379 /*--- Internal routines ----------------------------------------------------*/
380 static void init_vgachip(struct fb_info *info);
381 static void switch_monitor(struct cirrusfb_info *cinfo, int on);
382 static void WGen(const struct cirrusfb_info *cinfo,
383 int regnum, unsigned char val);
384 static unsigned char RGen(const struct cirrusfb_info *cinfo, int regnum);
385 static void AttrOn(const struct cirrusfb_info *cinfo);
386 static void WHDR(const struct cirrusfb_info *cinfo, unsigned char val);
387 static void WSFR(struct cirrusfb_info *cinfo, unsigned char val);
388 static void WSFR2(struct cirrusfb_info *cinfo, unsigned char val);
389 static void WClut(struct cirrusfb_info *cinfo, unsigned char regnum,
390 unsigned char red, unsigned char green, unsigned char blue);
392 static void RClut(struct cirrusfb_info *cinfo, unsigned char regnum,
393 unsigned char *red, unsigned char *green,
394 unsigned char *blue);
396 static void cirrusfb_WaitBLT(u8 __iomem *regbase);
397 static void cirrusfb_BitBLT(u8 __iomem *regbase, int bits_per_pixel,
398 u_short curx, u_short cury,
399 u_short destx, u_short desty,
400 u_short width, u_short height,
401 u_short line_length);
402 static void cirrusfb_RectFill(u8 __iomem *regbase, int bits_per_pixel,
403 u_short x, u_short y,
404 u_short width, u_short height,
405 u32 fg_color, u32 bg_color,
406 u_short line_length, u_char blitmode);
408 static void bestclock(long freq, int *nom, int *den, int *div);
410 #ifdef CIRRUSFB_DEBUG
411 static void cirrusfb_dbg_reg_dump(struct fb_info *info, caddr_t regbase);
412 static void cirrusfb_dbg_print_regs(struct fb_info *info,
414 enum cirrusfb_dbg_reg_class reg_class, ...);
415 #endif /* CIRRUSFB_DEBUG */
417 /*** END PROTOTYPES ********************************************************/
418 /*****************************************************************************/
419 /*** BEGIN Interface Used by the World ***************************************/
421 static inline int is_laguna(const struct cirrusfb_info *cinfo)
423 return cinfo->btype == BT_LAGUNA || cinfo->btype == BT_LAGUNAB;
426 static int opencount;
428 /*--- Open /dev/fbx ---------------------------------------------------------*/
429 static int cirrusfb_open(struct fb_info *info, int user)
431 if (opencount++ == 0)
432 switch_monitor(info->par, 1);
436 /*--- Close /dev/fbx --------------------------------------------------------*/
437 static int cirrusfb_release(struct fb_info *info, int user)
439 if (--opencount == 0)
440 switch_monitor(info->par, 0);
444 /**** END Interface used by the World *************************************/
445 /****************************************************************************/
446 /**** BEGIN Hardware specific Routines **************************************/
448 /* Check if the MCLK is not a better clock source */
449 static int cirrusfb_check_mclk(struct fb_info *info, long freq)
451 struct cirrusfb_info *cinfo = info->par;
452 long mclk = vga_rseq(cinfo->regbase, CL_SEQR1F) & 0x3f;
454 /* Read MCLK value */
455 mclk = (14318 * mclk) >> 3;
456 dev_dbg(info->device, "Read MCLK of %ld kHz\n", mclk);
458 /* Determine if we should use MCLK instead of VCLK, and if so, what we
459 * should divide it by to get VCLK
462 if (abs(freq - mclk) < 250) {
463 dev_dbg(info->device, "Using VCLK = MCLK\n");
465 } else if (abs(freq - (mclk / 2)) < 250) {
466 dev_dbg(info->device, "Using VCLK = MCLK/2\n");
473 static int cirrusfb_check_pixclock(const struct fb_var_screeninfo *var,
474 struct fb_info *info)
478 struct cirrusfb_info *cinfo = info->par;
479 unsigned maxclockidx = var->bits_per_pixel >> 3;
481 /* convert from ps to kHz */
482 freq = PICOS2KHZ(var->pixclock);
484 dev_dbg(info->device, "desired pixclock: %ld kHz\n", freq);
486 maxclock = cirrusfb_board_info[cinfo->btype].maxclock[maxclockidx];
487 cinfo->multiplexing = 0;
489 /* If the frequency is greater than we can support, we might be able
490 * to use multiplexing for the video mode */
491 if (freq > maxclock) {
492 dev_err(info->device,
493 "Frequency greater than maxclock (%ld kHz)\n",
498 * Additional constraint: 8bpp uses DAC clock doubling to allow maximum
501 if (var->bits_per_pixel == 8) {
502 switch (cinfo->btype) {
507 cinfo->multiplexing = 1;
511 cinfo->multiplexing = 1;
519 /* If we have a 1MB 5434, we need to put ourselves in a mode where
520 * the VCLK is double the pixel clock. */
521 cinfo->doubleVCLK = 0;
522 if (cinfo->btype == BT_SD64 && info->fix.smem_len <= MB_ &&
523 var->bits_per_pixel == 16) {
524 cinfo->doubleVCLK = 1;
530 static int cirrusfb_check_var(struct fb_var_screeninfo *var,
531 struct fb_info *info)
534 /* memory size in pixels */
535 unsigned pixels = info->screen_size * 8 / var->bits_per_pixel;
536 struct cirrusfb_info *cinfo = info->par;
538 switch (var->bits_per_pixel) {
542 var->green = var->red;
543 var->blue = var->red;
549 var->green = var->red;
550 var->blue = var->red;
554 var->red.offset = 11;
555 var->green.offset = 5;
556 var->blue.offset = 0;
558 var->green.length = 6;
559 var->blue.length = 5;
563 var->red.offset = 16;
564 var->green.offset = 8;
565 var->blue.offset = 0;
567 var->green.length = 8;
568 var->blue.length = 8;
572 dev_dbg(info->device,
573 "Unsupported bpp size: %d\n", var->bits_per_pixel);
577 if (var->xres_virtual < var->xres)
578 var->xres_virtual = var->xres;
579 /* use highest possible virtual resolution */
580 if (var->yres_virtual == -1) {
581 var->yres_virtual = pixels / var->xres_virtual;
583 dev_info(info->device,
584 "virtual resolution set to maximum of %dx%d\n",
585 var->xres_virtual, var->yres_virtual);
587 if (var->yres_virtual < var->yres)
588 var->yres_virtual = var->yres;
590 if (var->xres_virtual * var->yres_virtual > pixels) {
591 dev_err(info->device, "mode %dx%dx%d rejected... "
592 "virtual resolution too high to fit into video memory!\n",
593 var->xres_virtual, var->yres_virtual,
594 var->bits_per_pixel);
598 if (var->xoffset < 0)
600 if (var->yoffset < 0)
603 /* truncate xoffset and yoffset to maximum if too high */
604 if (var->xoffset > var->xres_virtual - var->xres)
605 var->xoffset = var->xres_virtual - var->xres - 1;
606 if (var->yoffset > var->yres_virtual - var->yres)
607 var->yoffset = var->yres_virtual - var->yres - 1;
610 var->green.msb_right =
611 var->blue.msb_right =
614 var->transp.msb_right = 0;
617 if (var->vmode & FB_VMODE_DOUBLE)
619 else if (var->vmode & FB_VMODE_INTERLACED)
620 yres = (yres + 1) / 2;
623 dev_err(info->device, "ERROR: VerticalTotal >= 1280; "
624 "special treatment required! (TODO)\n");
628 if (cirrusfb_check_pixclock(var, info))
631 if (!is_laguna(cinfo))
632 var->accel_flags = FB_ACCELF_TEXT;
637 static void cirrusfb_set_mclk_as_source(const struct fb_info *info, int div)
639 struct cirrusfb_info *cinfo = info->par;
640 unsigned char old1f, old1e;
642 assert(cinfo != NULL);
643 old1f = vga_rseq(cinfo->regbase, CL_SEQR1F) & ~0x40;
646 dev_dbg(info->device, "Set %s as pixclock source.\n",
647 (div == 2) ? "MCLK/2" : "MCLK");
649 old1e = vga_rseq(cinfo->regbase, CL_SEQR1E) & ~0x1;
653 vga_wseq(cinfo->regbase, CL_SEQR1E, old1e);
655 vga_wseq(cinfo->regbase, CL_SEQR1F, old1f);
658 /*************************************************************************
659 cirrusfb_set_par_foo()
661 actually writes the values for a new video mode into the hardware,
662 **************************************************************************/
663 static int cirrusfb_set_par_foo(struct fb_info *info)
665 struct cirrusfb_info *cinfo = info->par;
666 struct fb_var_screeninfo *var = &info->var;
667 u8 __iomem *regbase = cinfo->regbase;
670 const struct cirrusfb_board_info_rec *bi;
671 int hdispend, hsyncstart, hsyncend, htotal;
672 int yres, vdispend, vsyncstart, vsyncend, vtotal;
675 unsigned int control = 0, format = 0, threshold = 0;
677 dev_dbg(info->device, "Requested mode: %dx%dx%d\n",
678 var->xres, var->yres, var->bits_per_pixel);
680 switch (var->bits_per_pixel) {
682 info->fix.line_length = var->xres_virtual / 8;
683 info->fix.visual = FB_VISUAL_MONO10;
687 info->fix.line_length = var->xres_virtual;
688 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
693 info->fix.line_length = var->xres_virtual *
694 var->bits_per_pixel >> 3;
695 info->fix.visual = FB_VISUAL_TRUECOLOR;
698 info->fix.type = FB_TYPE_PACKED_PIXELS;
702 bi = &cirrusfb_board_info[cinfo->btype];
704 hsyncstart = var->xres + var->right_margin;
705 hsyncend = hsyncstart + var->hsync_len;
706 htotal = (hsyncend + var->left_margin) / 8;
707 hdispend = var->xres / 8;
708 hsyncstart = hsyncstart / 8;
709 hsyncend = hsyncend / 8;
711 vdispend = var->yres;
712 vsyncstart = vdispend + var->lower_margin;
713 vsyncend = vsyncstart + var->vsync_len;
714 vtotal = vsyncend + var->upper_margin;
716 if (var->vmode & FB_VMODE_DOUBLE) {
721 } else if (var->vmode & FB_VMODE_INTERLACED) {
722 vdispend = (vdispend + 1) / 2;
723 vsyncstart = (vsyncstart + 1) / 2;
724 vsyncend = (vsyncend + 1) / 2;
725 vtotal = (vtotal + 1) / 2;
740 if (cinfo->multiplexing) {
752 /* unlock register VGA_CRTC_H_TOTAL..CRT7 */
753 vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, 0x20); /* previously: 0x00) */
755 /* if debugging is enabled, all parameters get output before writing */
756 dev_dbg(info->device, "CRT0: %d\n", htotal);
757 vga_wcrt(regbase, VGA_CRTC_H_TOTAL, htotal);
759 dev_dbg(info->device, "CRT1: %d\n", hdispend);
760 vga_wcrt(regbase, VGA_CRTC_H_DISP, hdispend);
762 dev_dbg(info->device, "CRT2: %d\n", var->xres / 8);
763 vga_wcrt(regbase, VGA_CRTC_H_BLANK_START, var->xres / 8);
765 /* + 128: Compatible read */
766 dev_dbg(info->device, "CRT3: 128+%d\n", (htotal + 5) % 32);
767 vga_wcrt(regbase, VGA_CRTC_H_BLANK_END,
768 128 + ((htotal + 5) % 32));
770 dev_dbg(info->device, "CRT4: %d\n", hsyncstart);
771 vga_wcrt(regbase, VGA_CRTC_H_SYNC_START, hsyncstart);
774 if ((htotal + 5) & 32)
776 dev_dbg(info->device, "CRT5: %d\n", tmp);
777 vga_wcrt(regbase, VGA_CRTC_H_SYNC_END, tmp);
779 dev_dbg(info->device, "CRT6: %d\n", vtotal & 0xff);
780 vga_wcrt(regbase, VGA_CRTC_V_TOTAL, vtotal & 0xff);
782 tmp = 16; /* LineCompare bit #9 */
787 if (vsyncstart & 256)
789 if ((vdispend + 1) & 256)
795 if (vsyncstart & 512)
797 dev_dbg(info->device, "CRT7: %d\n", tmp);
798 vga_wcrt(regbase, VGA_CRTC_OVERFLOW, tmp);
800 tmp = 0x40; /* LineCompare bit #8 */
801 if ((vdispend + 1) & 512)
803 if (var->vmode & FB_VMODE_DOUBLE)
805 dev_dbg(info->device, "CRT9: %d\n", tmp);
806 vga_wcrt(regbase, VGA_CRTC_MAX_SCAN, tmp);
808 dev_dbg(info->device, "CRT10: %d\n", vsyncstart & 0xff);
809 vga_wcrt(regbase, VGA_CRTC_V_SYNC_START, vsyncstart & 0xff);
811 dev_dbg(info->device, "CRT11: 64+32+%d\n", vsyncend % 16);
812 vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, vsyncend % 16 + 64 + 32);
814 dev_dbg(info->device, "CRT12: %d\n", vdispend & 0xff);
815 vga_wcrt(regbase, VGA_CRTC_V_DISP_END, vdispend & 0xff);
817 dev_dbg(info->device, "CRT15: %d\n", (vdispend + 1) & 0xff);
818 vga_wcrt(regbase, VGA_CRTC_V_BLANK_START, (vdispend + 1) & 0xff);
820 dev_dbg(info->device, "CRT16: %d\n", vtotal & 0xff);
821 vga_wcrt(regbase, VGA_CRTC_V_BLANK_END, vtotal & 0xff);
823 dev_dbg(info->device, "CRT18: 0xff\n");
824 vga_wcrt(regbase, VGA_CRTC_LINE_COMPARE, 0xff);
827 if (var->vmode & FB_VMODE_INTERLACED)
829 if ((htotal + 5) & 64)
831 if ((htotal + 5) & 128)
838 dev_dbg(info->device, "CRT1a: %d\n", tmp);
839 vga_wcrt(regbase, CL_CRT1A, tmp);
841 freq = PICOS2KHZ(var->pixclock);
842 if (var->bits_per_pixel == 24)
843 if (cinfo->btype == BT_ALPINE || cinfo->btype == BT_SD64)
845 if (cinfo->multiplexing)
847 if (cinfo->doubleVCLK)
850 bestclock(freq, &nom, &den, &div);
852 dev_dbg(info->device, "VCLK freq: %ld kHz nom: %d den: %d div: %d\n",
853 freq, nom, den, div);
856 /* hardware RefClock: 14.31818 MHz */
857 /* formula: VClk = (OSC * N) / (D * (1+P)) */
858 /* Example: VClk = (14.31818 * 91) / (23 * (1+1)) = 28.325 MHz */
860 if (cinfo->btype == BT_ALPINE || cinfo->btype == BT_PICASSO4 ||
861 cinfo->btype == BT_SD64) {
862 /* if freq is close to mclk or mclk/2 select mclk
865 int divMCLK = cirrusfb_check_mclk(info, freq);
868 cirrusfb_set_mclk_as_source(info, divMCLK);
870 if (is_laguna(cinfo)) {
871 long pcifc = fb_readl(cinfo->laguna_mmio + 0x3fc);
872 unsigned char tile = fb_readb(cinfo->laguna_mmio + 0x407);
873 unsigned short tile_control;
875 if (cinfo->btype == BT_LAGUNAB) {
876 tile_control = fb_readw(cinfo->laguna_mmio + 0x2c4);
877 tile_control &= ~0x80;
878 fb_writew(tile_control, cinfo->laguna_mmio + 0x2c4);
881 fb_writel(pcifc | 0x10000000l, cinfo->laguna_mmio + 0x3fc);
882 fb_writeb(tile & 0x3f, cinfo->laguna_mmio + 0x407);
883 control = fb_readw(cinfo->laguna_mmio + 0x402);
884 threshold = fb_readw(cinfo->laguna_mmio + 0xea);
887 threshold &= 0xffc0 & 0x3fbf;
893 /* 6 bit denom; ONLY 5434!!! (bugged me 10 days) */
894 if ((cinfo->btype == BT_SD64) ||
895 (cinfo->btype == BT_ALPINE) ||
896 (cinfo->btype == BT_GD5480))
899 /* Laguna chipset has reversed clock registers */
900 if (is_laguna(cinfo)) {
901 vga_wseq(regbase, CL_SEQRE, tmp);
902 vga_wseq(regbase, CL_SEQR1E, nom);
904 vga_wseq(regbase, CL_SEQRE, nom);
905 vga_wseq(regbase, CL_SEQR1E, tmp);
911 vga_wcrt(regbase, VGA_CRTC_MODE, 0xc7);
913 /* mode control: VGA_CRTC_START_HI enable, ROTATE(?), 16bit
914 * address wrap, no compat. */
915 vga_wcrt(regbase, VGA_CRTC_MODE, 0xc3);
917 /* don't know if it would hurt to also program this if no interlaced */
918 /* mode is used, but I feel better this way.. :-) */
919 if (var->vmode & FB_VMODE_INTERLACED)
920 vga_wcrt(regbase, VGA_CRTC_REGS, htotal / 2);
922 vga_wcrt(regbase, VGA_CRTC_REGS, 0x00); /* interlace control */
924 /* adjust horizontal/vertical sync type (low/high), use VCLK3 */
925 /* enable display memory & CRTC I/O address for color mode */
927 if (var->sync & FB_SYNC_HOR_HIGH_ACT)
929 if (var->sync & FB_SYNC_VERT_HIGH_ACT)
931 WGen(cinfo, VGA_MIS_W, tmp);
933 /* text cursor on and start line */
934 vga_wcrt(regbase, VGA_CRTC_CURSOR_START, 0);
935 /* text cursor end line */
936 vga_wcrt(regbase, VGA_CRTC_CURSOR_END, 31);
938 /******************************************************
944 /* programming for different color depths */
945 if (var->bits_per_pixel == 1) {
946 dev_dbg(info->device, "preparing for 1 bit deep display\n");
947 vga_wgfx(regbase, VGA_GFX_MODE, 0); /* mode register */
950 switch (cinfo->btype) {
958 vga_wseq(regbase, CL_SEQR7,
959 cinfo->multiplexing ?
960 bi->sr07_1bpp_mux : bi->sr07_1bpp);
965 vga_wseq(regbase, CL_SEQR7,
966 vga_rseq(regbase, CL_SEQR7) & ~0x01);
970 dev_warn(info->device, "unknown Board\n");
974 /* Extended Sequencer Mode */
975 switch (cinfo->btype) {
979 /* evtl d0 bei 1 bit? avoid FIFO underruns..? */
980 vga_wseq(regbase, CL_SEQRF, 0xb0);
984 /* ## vorher d0 avoid FIFO underruns..? */
985 vga_wseq(regbase, CL_SEQRF, 0xd0);
998 dev_warn(info->device, "unknown Board\n");
1002 /* pixel mask: pass-through for first plane */
1003 WGen(cinfo, VGA_PEL_MSK, 0x01);
1004 if (cinfo->multiplexing)
1005 /* hidden dac reg: 1280x1024 */
1008 /* hidden dac: nothing */
1010 /* memory mode: odd/even, ext. memory */
1011 vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, 0x06);
1012 /* plane mask: only write to first plane */
1013 vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0x01);
1016 /******************************************************
1022 else if (var->bits_per_pixel == 8) {
1023 dev_dbg(info->device, "preparing for 8 bit deep display\n");
1024 switch (cinfo->btype) {
1032 vga_wseq(regbase, CL_SEQR7,
1033 cinfo->multiplexing ?
1034 bi->sr07_8bpp_mux : bi->sr07_8bpp);
1039 vga_wseq(regbase, CL_SEQR7,
1040 vga_rseq(regbase, CL_SEQR7) | 0x01);
1045 dev_warn(info->device, "unknown Board\n");
1049 switch (cinfo->btype) {
1053 /* Fast Page-Mode writes */
1054 vga_wseq(regbase, CL_SEQRF, 0xb0);
1059 /* ### INCOMPLETE!! */
1060 vga_wseq(regbase, CL_SEQRF, 0xb8);
1071 dev_warn(info->device, "unknown board\n");
1075 /* mode register: 256 color mode */
1076 vga_wgfx(regbase, VGA_GFX_MODE, 64);
1077 if (cinfo->multiplexing)
1078 /* hidden dac reg: 1280x1024 */
1081 /* hidden dac: nothing */
1085 /******************************************************
1091 else if (var->bits_per_pixel == 16) {
1092 dev_dbg(info->device, "preparing for 16 bit deep display\n");
1093 switch (cinfo->btype) {
1096 vga_wseq(regbase, CL_SEQR7, 0x87);
1097 /* Fast Page-Mode writes */
1098 vga_wseq(regbase, CL_SEQRF, 0xb0);
1102 vga_wseq(regbase, CL_SEQR7, 0x27);
1103 /* Fast Page-Mode writes */
1104 vga_wseq(regbase, CL_SEQRF, 0xb0);
1110 /* Extended Sequencer Mode: 256c col. mode */
1111 vga_wseq(regbase, CL_SEQR7,
1112 cinfo->doubleVCLK ? 0xa3 : 0xa7);
1116 vga_wseq(regbase, CL_SEQR7, 0x17);
1117 /* We already set SRF and SR1F */
1122 vga_wseq(regbase, CL_SEQR7,
1123 vga_rseq(regbase, CL_SEQR7) & ~0x01);
1130 dev_warn(info->device, "unknown Board\n");
1134 /* mode register: 256 color mode */
1135 vga_wgfx(regbase, VGA_GFX_MODE, 64);
1137 WHDR(cinfo, cinfo->doubleVCLK ? 0xe1 : 0xc1);
1138 #elif defined(CONFIG_ZORRO)
1139 /* FIXME: CONFIG_PCI and CONFIG_ZORRO may be defined both */
1140 WHDR(cinfo, 0xa0); /* hidden dac reg: nothing special */
1144 /******************************************************
1150 else if (var->bits_per_pixel == 24) {
1151 dev_dbg(info->device, "preparing for 24 bit deep display\n");
1152 switch (cinfo->btype) {
1155 vga_wseq(regbase, CL_SEQR7, 0x85);
1156 /* Fast Page-Mode writes */
1157 vga_wseq(regbase, CL_SEQRF, 0xb0);
1161 vga_wseq(regbase, CL_SEQR7, 0x25);
1162 /* Fast Page-Mode writes */
1163 vga_wseq(regbase, CL_SEQRF, 0xb0);
1169 /* Extended Sequencer Mode: 256c col. mode */
1170 vga_wseq(regbase, CL_SEQR7, 0xa5);
1174 vga_wseq(regbase, CL_SEQR7, 0x15);
1175 /* We already set SRF and SR1F */
1180 vga_wseq(regbase, CL_SEQR7,
1181 vga_rseq(regbase, CL_SEQR7) & ~0x01);
1188 dev_warn(info->device, "unknown Board\n");
1192 /* mode register: 256 color mode */
1193 vga_wgfx(regbase, VGA_GFX_MODE, 64);
1194 /* hidden dac reg: 8-8-8 mode (24 or 32) */
1198 /******************************************************
1200 * unknown/unsupported bpp
1205 dev_err(info->device,
1206 "What's this? requested color depth == %d.\n",
1207 var->bits_per_pixel);
1209 pitch = info->fix.line_length >> 3;
1210 vga_wcrt(regbase, VGA_CRTC_OFFSET, pitch & 0xff);
1213 tmp |= 0x10; /* offset overflow bit */
1215 /* screen start addr #16-18, fastpagemode cycles */
1216 vga_wcrt(regbase, CL_CRT1B, tmp);
1218 /* screen start address bit 19 */
1219 if (cirrusfb_board_info[cinfo->btype].scrn_start_bit19)
1220 vga_wcrt(regbase, CL_CRT1D, (pitch >> 9) & 1);
1222 if (is_laguna(cinfo)) {
1224 if ((htotal + 5) & 256)
1228 if (hsyncstart & 256)
1232 if (vdispend & 1024)
1234 if (vsyncstart & 1024)
1237 vga_wcrt(regbase, CL_CRT1E, tmp);
1238 dev_dbg(info->device, "CRT1e: %d\n", tmp);
1242 vga_wattr(regbase, CL_AR33, 0);
1244 /* [ EGS: SetOffset(); ] */
1245 /* From SetOffset(): Turn on VideoEnable bit in Attribute controller */
1248 if (is_laguna(cinfo)) {
1250 fb_writew(control | 0x1000, cinfo->laguna_mmio + 0x402);
1251 fb_writew(format, cinfo->laguna_mmio + 0xc0);
1252 fb_writew(threshold, cinfo->laguna_mmio + 0xea);
1254 /* finally, turn on everything - turn off "FullBandwidth" bit */
1255 /* also, set "DotClock%2" bit where requested */
1258 /*** FB_VMODE_CLOCK_HALVE in linux/fb.h not defined anymore ?
1259 if (var->vmode & FB_VMODE_CLOCK_HALVE)
1263 vga_wseq(regbase, VGA_SEQ_CLOCK_MODE, tmp);
1264 dev_dbg(info->device, "CL_SEQR1: %d\n", tmp);
1266 #ifdef CIRRUSFB_DEBUG
1267 cirrusfb_dbg_reg_dump(info, NULL);
1273 /* for some reason incomprehensible to me, cirrusfb requires that you write
1274 * the registers twice for the settings to take..grr. -dte */
1275 static int cirrusfb_set_par(struct fb_info *info)
1277 cirrusfb_set_par_foo(info);
1278 return cirrusfb_set_par_foo(info);
1281 static int cirrusfb_setcolreg(unsigned regno, unsigned red, unsigned green,
1282 unsigned blue, unsigned transp,
1283 struct fb_info *info)
1285 struct cirrusfb_info *cinfo = info->par;
1290 if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
1292 red >>= (16 - info->var.red.length);
1293 green >>= (16 - info->var.green.length);
1294 blue >>= (16 - info->var.blue.length);
1298 v = (red << info->var.red.offset) |
1299 (green << info->var.green.offset) |
1300 (blue << info->var.blue.offset);
1302 cinfo->pseudo_palette[regno] = v;
1306 if (info->var.bits_per_pixel == 8)
1307 WClut(cinfo, regno, red >> 10, green >> 10, blue >> 10);
1313 /*************************************************************************
1314 cirrusfb_pan_display()
1316 performs display panning - provided hardware permits this
1317 **************************************************************************/
1318 static int cirrusfb_pan_display(struct fb_var_screeninfo *var,
1319 struct fb_info *info)
1323 unsigned char tmp, xpix;
1324 struct cirrusfb_info *cinfo = info->par;
1326 /* no range checks for xoffset and yoffset, */
1327 /* as fb_pan_display has already done this */
1328 if (var->vmode & FB_VMODE_YWRAP)
1331 xoffset = var->xoffset * info->var.bits_per_pixel / 8;
1333 base = var->yoffset * info->fix.line_length + xoffset;
1335 if (info->var.bits_per_pixel == 1) {
1336 /* base is already correct */
1337 xpix = (unsigned char) (var->xoffset % 8);
1340 xpix = (unsigned char) ((xoffset % 4) * 2);
1343 if (!is_laguna(cinfo))
1344 cirrusfb_WaitBLT(cinfo->regbase);
1346 /* lower 8 + 8 bits of screen start address */
1347 vga_wcrt(cinfo->regbase, VGA_CRTC_START_LO, base & 0xff);
1348 vga_wcrt(cinfo->regbase, VGA_CRTC_START_HI, (base >> 8) & 0xff);
1350 /* 0xf2 is %11110010, exclude tmp bits */
1351 tmp = vga_rcrt(cinfo->regbase, CL_CRT1B) & 0xf2;
1352 /* construct bits 16, 17 and 18 of screen start address */
1360 vga_wcrt(cinfo->regbase, CL_CRT1B, tmp);
1362 /* construct bit 19 of screen start address */
1363 if (cirrusfb_board_info[cinfo->btype].scrn_start_bit19) {
1364 tmp = vga_rcrt(cinfo->regbase, CL_CRT1D);
1365 if (is_laguna(cinfo))
1366 tmp = (tmp & ~0x18) | ((base >> 16) & 0x18);
1368 tmp = (tmp & ~0x80) | ((base >> 12) & 0x80);
1369 vga_wcrt(cinfo->regbase, CL_CRT1D, tmp);
1372 /* write pixel panning value to AR33; this does not quite work in 8bpp
1374 * ### Piccolo..? Will this work?
1376 if (info->var.bits_per_pixel == 1)
1377 vga_wattr(cinfo->regbase, CL_AR33, xpix);
1382 static int cirrusfb_blank(int blank_mode, struct fb_info *info)
1385 * Blank the screen if blank_mode != 0, else unblank. If blank == NULL
1386 * then the caller blanks by setting the CLUT (Color Look Up Table)
1387 * to all black. Return 0 if blanking succeeded, != 0 if un-/blanking
1388 * failed due to e.g. a video mode which doesn't support it.
1389 * Implements VESA suspend and powerdown modes on hardware that
1390 * supports disabling hsync/vsync:
1391 * blank_mode == 2: suspend vsync
1392 * blank_mode == 3: suspend hsync
1393 * blank_mode == 4: powerdown
1396 struct cirrusfb_info *cinfo = info->par;
1397 int current_mode = cinfo->blank_mode;
1399 dev_dbg(info->device, "ENTER, blank mode = %d\n", blank_mode);
1401 if (info->state != FBINFO_STATE_RUNNING ||
1402 current_mode == blank_mode) {
1403 dev_dbg(info->device, "EXIT, returning 0\n");
1408 if (current_mode == FB_BLANK_NORMAL ||
1409 current_mode == FB_BLANK_UNBLANK)
1410 /* clear "FullBandwidth" bit */
1413 /* set "FullBandwidth" bit */
1416 val |= vga_rseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE) & 0xdf;
1417 vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, val);
1419 switch (blank_mode) {
1420 case FB_BLANK_UNBLANK:
1421 case FB_BLANK_NORMAL:
1424 case FB_BLANK_VSYNC_SUSPEND:
1427 case FB_BLANK_HSYNC_SUSPEND:
1430 case FB_BLANK_POWERDOWN:
1434 dev_dbg(info->device, "EXIT, returning 1\n");
1438 vga_wgfx(cinfo->regbase, CL_GRE, val);
1440 cinfo->blank_mode = blank_mode;
1441 dev_dbg(info->device, "EXIT, returning 0\n");
1443 /* Let fbcon do a soft blank for us */
1444 return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
1447 /**** END Hardware specific Routines **************************************/
1448 /****************************************************************************/
1449 /**** BEGIN Internal Routines ***********************************************/
1451 static void init_vgachip(struct fb_info *info)
1453 struct cirrusfb_info *cinfo = info->par;
1454 const struct cirrusfb_board_info_rec *bi;
1456 assert(cinfo != NULL);
1458 bi = &cirrusfb_board_info[cinfo->btype];
1460 /* reset board globally */
1461 switch (cinfo->btype) {
1480 /* disable flickerfixer */
1481 vga_wcrt(cinfo->regbase, CL_CRT51, 0x00);
1484 vga_wgfx(cinfo->regbase, CL_GR31, 0x00);
1485 case BT_GD5480: /* fall through */
1486 /* from Klaus' NetBSD driver: */
1487 vga_wgfx(cinfo->regbase, CL_GR2F, 0x00);
1488 case BT_ALPINE: /* fall through */
1489 /* put blitter into 542x compat */
1490 vga_wgfx(cinfo->regbase, CL_GR33, 0x00);
1495 /* Nothing to do to reset the board. */
1499 dev_err(info->device, "Warning: Unknown board type\n");
1503 /* make sure RAM size set by this point */
1504 assert(info->screen_size > 0);
1506 /* the P4 is not fully initialized here; I rely on it having been */
1507 /* inited under AmigaOS already, which seems to work just fine */
1508 /* (Klaus advised to do it this way) */
1510 if (cinfo->btype != BT_PICASSO4) {
1511 WGen(cinfo, CL_VSSM, 0x10); /* EGS: 0x16 */
1512 WGen(cinfo, CL_POS102, 0x01);
1513 WGen(cinfo, CL_VSSM, 0x08); /* EGS: 0x0e */
1515 if (cinfo->btype != BT_SD64)
1516 WGen(cinfo, CL_VSSM2, 0x01);
1518 /* reset sequencer logic */
1519 vga_wseq(cinfo->regbase, VGA_SEQ_RESET, 0x03);
1521 /* FullBandwidth (video off) and 8/9 dot clock */
1522 vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, 0x21);
1524 /* "magic cookie" - doesn't make any sense to me.. */
1525 /* vga_wgfx(cinfo->regbase, CL_GRA, 0xce); */
1526 /* unlock all extension registers */
1527 vga_wseq(cinfo->regbase, CL_SEQR6, 0x12);
1529 switch (cinfo->btype) {
1531 vga_wseq(cinfo->regbase, CL_SEQRF, 0x98);
1539 vga_wseq(cinfo->regbase, CL_SEQRF, 0xb8);
1543 vga_wseq(cinfo->regbase, CL_SEQR16, 0x0f);
1544 vga_wseq(cinfo->regbase, CL_SEQRF, 0xb0);
1548 /* plane mask: nothing */
1549 vga_wseq(cinfo->regbase, VGA_SEQ_PLANE_WRITE, 0xff);
1550 /* character map select: doesn't even matter in gx mode */
1551 vga_wseq(cinfo->regbase, VGA_SEQ_CHARACTER_MAP, 0x00);
1552 /* memory mode: chain4, ext. memory */
1553 vga_wseq(cinfo->regbase, VGA_SEQ_MEMORY_MODE, 0x0a);
1555 /* controller-internal base address of video memory */
1557 vga_wseq(cinfo->regbase, CL_SEQR7, bi->sr07);
1559 /* vga_wseq(cinfo->regbase, CL_SEQR8, 0x00); */
1560 /* EEPROM control: shouldn't be necessary to write to this at all.. */
1562 /* graphics cursor X position (incomplete; position gives rem. 3 bits */
1563 vga_wseq(cinfo->regbase, CL_SEQR10, 0x00);
1564 /* graphics cursor Y position (..."... ) */
1565 vga_wseq(cinfo->regbase, CL_SEQR11, 0x00);
1566 /* graphics cursor attributes */
1567 vga_wseq(cinfo->regbase, CL_SEQR12, 0x00);
1568 /* graphics cursor pattern address */
1569 vga_wseq(cinfo->regbase, CL_SEQR13, 0x00);
1571 /* writing these on a P4 might give problems.. */
1572 if (cinfo->btype != BT_PICASSO4) {
1573 /* configuration readback and ext. color */
1574 vga_wseq(cinfo->regbase, CL_SEQR17, 0x00);
1575 /* signature generator */
1576 vga_wseq(cinfo->regbase, CL_SEQR18, 0x02);
1579 /* Screen A preset row scan: none */
1580 vga_wcrt(cinfo->regbase, VGA_CRTC_PRESET_ROW, 0x00);
1581 /* Text cursor start: disable text cursor */
1582 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_START, 0x20);
1583 /* Text cursor end: - */
1584 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_END, 0x00);
1585 /* text cursor location high: 0 */
1586 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_HI, 0x00);
1587 /* text cursor location low: 0 */
1588 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_LO, 0x00);
1590 /* Underline Row scanline: - */
1591 vga_wcrt(cinfo->regbase, VGA_CRTC_UNDERLINE, 0x00);
1592 /* ### add 0x40 for text modes with > 30 MHz pixclock */
1593 /* ext. display controls: ext.adr. wrap */
1594 vga_wcrt(cinfo->regbase, CL_CRT1B, 0x02);
1596 /* Set/Reset registers: - */
1597 vga_wgfx(cinfo->regbase, VGA_GFX_SR_VALUE, 0x00);
1598 /* Set/Reset enable: - */
1599 vga_wgfx(cinfo->regbase, VGA_GFX_SR_ENABLE, 0x00);
1600 /* Color Compare: - */
1601 vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_VALUE, 0x00);
1602 /* Data Rotate: - */
1603 vga_wgfx(cinfo->regbase, VGA_GFX_DATA_ROTATE, 0x00);
1604 /* Read Map Select: - */
1605 vga_wgfx(cinfo->regbase, VGA_GFX_PLANE_READ, 0x00);
1606 /* Mode: conf. for 16/4/2 color mode, no odd/even, read/write mode 0 */
1607 vga_wgfx(cinfo->regbase, VGA_GFX_MODE, 0x00);
1608 /* Miscellaneous: memory map base address, graphics mode */
1609 vga_wgfx(cinfo->regbase, VGA_GFX_MISC, 0x01);
1610 /* Color Don't care: involve all planes */
1611 vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_MASK, 0x0f);
1612 /* Bit Mask: no mask at all */
1613 vga_wgfx(cinfo->regbase, VGA_GFX_BIT_MASK, 0xff);
1615 if (cinfo->btype == BT_ALPINE || cinfo->btype == BT_SD64 ||
1617 /* (5434 can't have bit 3 set for bitblt) */
1618 vga_wgfx(cinfo->regbase, CL_GRB, 0x20);
1620 /* Graphics controller mode extensions: finer granularity,
1621 * 8byte data latches
1623 vga_wgfx(cinfo->regbase, CL_GRB, 0x28);
1625 vga_wgfx(cinfo->regbase, CL_GRC, 0xff); /* Color Key compare: - */
1626 vga_wgfx(cinfo->regbase, CL_GRD, 0x00); /* Color Key compare mask: - */
1627 vga_wgfx(cinfo->regbase, CL_GRE, 0x00); /* Miscellaneous control: - */
1628 /* Background color byte 1: - */
1629 /* vga_wgfx (cinfo->regbase, CL_GR10, 0x00); */
1630 /* vga_wgfx (cinfo->regbase, CL_GR11, 0x00); */
1632 /* Attribute Controller palette registers: "identity mapping" */
1633 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE0, 0x00);
1634 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE1, 0x01);
1635 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE2, 0x02);
1636 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE3, 0x03);
1637 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE4, 0x04);
1638 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE5, 0x05);
1639 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE6, 0x06);
1640 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE7, 0x07);
1641 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE8, 0x08);
1642 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE9, 0x09);
1643 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEA, 0x0a);
1644 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEB, 0x0b);
1645 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEC, 0x0c);
1646 vga_wattr(cinfo->regbase, VGA_ATC_PALETTED, 0x0d);
1647 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEE, 0x0e);
1648 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEF, 0x0f);
1650 /* Attribute Controller mode: graphics mode */
1651 vga_wattr(cinfo->regbase, VGA_ATC_MODE, 0x01);
1652 /* Overscan color reg.: reg. 0 */
1653 vga_wattr(cinfo->regbase, VGA_ATC_OVERSCAN, 0x00);
1654 /* Color Plane enable: Enable all 4 planes */
1655 vga_wattr(cinfo->regbase, VGA_ATC_PLANE_ENABLE, 0x0f);
1656 /* Color Select: - */
1657 vga_wattr(cinfo->regbase, VGA_ATC_COLOR_PAGE, 0x00);
1659 WGen(cinfo, VGA_PEL_MSK, 0xff); /* Pixel mask: no mask */
1661 /* BLT Start/status: Blitter reset */
1662 vga_wgfx(cinfo->regbase, CL_GR31, 0x04);
1663 /* - " - : "end-of-reset" */
1664 vga_wgfx(cinfo->regbase, CL_GR31, 0x00);
1667 WHDR(cinfo, 0); /* Hidden DAC register: - */
1671 static void switch_monitor(struct cirrusfb_info *cinfo, int on)
1673 #ifdef CONFIG_ZORRO /* only works on Zorro boards */
1674 static int IsOn = 0; /* XXX not ok for multiple boards */
1676 if (cinfo->btype == BT_PICASSO4)
1677 return; /* nothing to switch */
1678 if (cinfo->btype == BT_ALPINE)
1679 return; /* nothing to switch */
1680 if (cinfo->btype == BT_GD5480)
1681 return; /* nothing to switch */
1682 if (cinfo->btype == BT_PICASSO) {
1683 if ((on && !IsOn) || (!on && IsOn))
1688 switch (cinfo->btype) {
1690 WSFR(cinfo, cinfo->SFR | 0x21);
1693 WSFR(cinfo, cinfo->SFR | 0x28);
1698 default: /* do nothing */ break;
1701 switch (cinfo->btype) {
1703 WSFR(cinfo, cinfo->SFR & 0xde);
1706 WSFR(cinfo, cinfo->SFR & 0xd7);
1711 default: /* do nothing */
1715 #endif /* CONFIG_ZORRO */
1718 /******************************************/
1719 /* Linux 2.6-style accelerated functions */
1720 /******************************************/
1722 static int cirrusfb_sync(struct fb_info *info)
1724 struct cirrusfb_info *cinfo = info->par;
1726 if (!is_laguna(cinfo)) {
1727 while (vga_rgfx(cinfo->regbase, CL_GR31) & 0x03)
1733 static void cirrusfb_fillrect(struct fb_info *info,
1734 const struct fb_fillrect *region)
1736 struct fb_fillrect modded;
1738 struct cirrusfb_info *cinfo = info->par;
1739 int m = info->var.bits_per_pixel;
1740 u32 color = (info->fix.visual == FB_VISUAL_TRUECOLOR) ?
1741 cinfo->pseudo_palette[region->color] : region->color;
1743 if (info->state != FBINFO_STATE_RUNNING)
1745 if (info->flags & FBINFO_HWACCEL_DISABLED) {
1746 cfb_fillrect(info, region);
1750 vxres = info->var.xres_virtual;
1751 vyres = info->var.yres_virtual;
1753 memcpy(&modded, region, sizeof(struct fb_fillrect));
1755 if (!modded.width || !modded.height ||
1756 modded.dx >= vxres || modded.dy >= vyres)
1759 if (modded.dx + modded.width > vxres)
1760 modded.width = vxres - modded.dx;
1761 if (modded.dy + modded.height > vyres)
1762 modded.height = vyres - modded.dy;
1764 cirrusfb_RectFill(cinfo->regbase,
1765 info->var.bits_per_pixel,
1766 (region->dx * m) / 8, region->dy,
1767 (region->width * m) / 8, region->height,
1769 info->fix.line_length, 0x40);
1772 static void cirrusfb_copyarea(struct fb_info *info,
1773 const struct fb_copyarea *area)
1775 struct fb_copyarea modded;
1777 struct cirrusfb_info *cinfo = info->par;
1778 int m = info->var.bits_per_pixel;
1780 if (info->state != FBINFO_STATE_RUNNING)
1782 if (info->flags & FBINFO_HWACCEL_DISABLED) {
1783 cfb_copyarea(info, area);
1787 vxres = info->var.xres_virtual;
1788 vyres = info->var.yres_virtual;
1789 memcpy(&modded, area, sizeof(struct fb_copyarea));
1791 if (!modded.width || !modded.height ||
1792 modded.sx >= vxres || modded.sy >= vyres ||
1793 modded.dx >= vxres || modded.dy >= vyres)
1796 if (modded.sx + modded.width > vxres)
1797 modded.width = vxres - modded.sx;
1798 if (modded.dx + modded.width > vxres)
1799 modded.width = vxres - modded.dx;
1800 if (modded.sy + modded.height > vyres)
1801 modded.height = vyres - modded.sy;
1802 if (modded.dy + modded.height > vyres)
1803 modded.height = vyres - modded.dy;
1805 cirrusfb_BitBLT(cinfo->regbase, info->var.bits_per_pixel,
1806 (area->sx * m) / 8, area->sy,
1807 (area->dx * m) / 8, area->dy,
1808 (area->width * m) / 8, area->height,
1809 info->fix.line_length);
1813 static void cirrusfb_imageblit(struct fb_info *info,
1814 const struct fb_image *image)
1816 struct cirrusfb_info *cinfo = info->par;
1817 unsigned char op = (info->var.bits_per_pixel == 24) ? 0xc : 0x4;
1819 if (info->state != FBINFO_STATE_RUNNING)
1821 /* Alpine/SD64 does not work at 24bpp ??? */
1822 if (info->flags & FBINFO_HWACCEL_DISABLED || image->depth != 1)
1823 cfb_imageblit(info, image);
1824 else if ((cinfo->btype == BT_ALPINE || cinfo->btype == BT_SD64) &&
1826 cfb_imageblit(info, image);
1828 unsigned size = ((image->width + 7) >> 3) * image->height;
1829 int m = info->var.bits_per_pixel;
1832 if (info->var.bits_per_pixel == 8) {
1833 fg = image->fg_color;
1834 bg = image->bg_color;
1836 fg = ((u32 *)(info->pseudo_palette))[image->fg_color];
1837 bg = ((u32 *)(info->pseudo_palette))[image->bg_color];
1839 if (info->var.bits_per_pixel == 24) {
1840 /* clear background first */
1841 cirrusfb_RectFill(cinfo->regbase,
1842 info->var.bits_per_pixel,
1843 (image->dx * m) / 8, image->dy,
1844 (image->width * m) / 8,
1847 info->fix.line_length, 0x40);
1849 cirrusfb_RectFill(cinfo->regbase,
1850 info->var.bits_per_pixel,
1851 (image->dx * m) / 8, image->dy,
1852 (image->width * m) / 8, image->height,
1854 info->fix.line_length, op);
1855 memcpy(info->screen_base, image->data, size);
1860 static int release_io_ports;
1862 /* Pulled the logic from XFree86 Cirrus driver to get the memory size,
1863 * based on the DRAM bandwidth bit and DRAM bank switching bit. This
1864 * works with 1MB, 2MB and 4MB configurations (which the Motorola boards
1866 static unsigned int cirrusfb_get_memsize(struct fb_info *info,
1867 u8 __iomem *regbase)
1870 struct cirrusfb_info *cinfo = info->par;
1872 if (is_laguna(cinfo)) {
1873 unsigned char SR14 = vga_rseq(regbase, CL_SEQR14);
1875 mem = ((SR14 & 7) + 1) << 20;
1877 unsigned char SRF = vga_rseq(regbase, CL_SEQRF);
1878 switch ((SRF & 0x18)) {
1885 /* 64-bit DRAM data bus width; assume 2MB.
1886 * Also indicates 2MB memory on the 5430.
1892 dev_warn(info->device, "Unknown memory size!\n");
1895 /* If DRAM bank switching is enabled, there must be
1896 * twice as much memory installed. (4MB on the 5434)
1898 if (cinfo->btype != BT_ALPINE && (SRF & 0x80) != 0)
1902 /* TODO: Handling of GD5446/5480 (see XF86 sources ...) */
1906 static void get_pci_addrs(const struct pci_dev *pdev,
1907 unsigned long *display, unsigned long *registers)
1909 assert(pdev != NULL);
1910 assert(display != NULL);
1911 assert(registers != NULL);
1916 /* This is a best-guess for now */
1918 if (pci_resource_flags(pdev, 0) & IORESOURCE_IO) {
1919 *display = pci_resource_start(pdev, 1);
1920 *registers = pci_resource_start(pdev, 0);
1922 *display = pci_resource_start(pdev, 0);
1923 *registers = pci_resource_start(pdev, 1);
1926 assert(*display != 0);
1929 static void cirrusfb_pci_unmap(struct fb_info *info)
1931 struct pci_dev *pdev = to_pci_dev(info->device);
1932 struct cirrusfb_info *cinfo = info->par;
1934 if (cinfo->laguna_mmio == NULL)
1935 iounmap(cinfo->laguna_mmio);
1936 iounmap(info->screen_base);
1937 #if 0 /* if system didn't claim this region, we would... */
1938 release_mem_region(0xA0000, 65535);
1940 if (release_io_ports)
1941 release_region(0x3C0, 32);
1942 pci_release_regions(pdev);
1944 #endif /* CONFIG_PCI */
1947 static void cirrusfb_zorro_unmap(struct fb_info *info)
1949 struct cirrusfb_info *cinfo = info->par;
1950 struct zorro_dev *zdev = to_zorro_dev(info->device);
1952 if (info->fix.smem_start > 16 * MB_)
1953 iounmap(info->screen_base);
1954 if (info->fix.mmio_start > 16 * MB_)
1955 iounmap(cinfo->regbase);
1957 zorro_release_device(zdev);
1959 #endif /* CONFIG_ZORRO */
1961 /* function table of the above functions */
1962 static struct fb_ops cirrusfb_ops = {
1963 .owner = THIS_MODULE,
1964 .fb_open = cirrusfb_open,
1965 .fb_release = cirrusfb_release,
1966 .fb_setcolreg = cirrusfb_setcolreg,
1967 .fb_check_var = cirrusfb_check_var,
1968 .fb_set_par = cirrusfb_set_par,
1969 .fb_pan_display = cirrusfb_pan_display,
1970 .fb_blank = cirrusfb_blank,
1971 .fb_fillrect = cirrusfb_fillrect,
1972 .fb_copyarea = cirrusfb_copyarea,
1973 .fb_sync = cirrusfb_sync,
1974 .fb_imageblit = cirrusfb_imageblit,
1977 static int cirrusfb_set_fbinfo(struct fb_info *info)
1979 struct cirrusfb_info *cinfo = info->par;
1980 struct fb_var_screeninfo *var = &info->var;
1982 info->pseudo_palette = cinfo->pseudo_palette;
1983 info->flags = FBINFO_DEFAULT
1984 | FBINFO_HWACCEL_XPAN
1985 | FBINFO_HWACCEL_YPAN
1986 | FBINFO_HWACCEL_FILLRECT
1987 | FBINFO_HWACCEL_IMAGEBLIT
1988 | FBINFO_HWACCEL_COPYAREA;
1989 if (noaccel || is_laguna(cinfo)) {
1990 info->flags |= FBINFO_HWACCEL_DISABLED;
1991 info->fix.accel = FB_ACCEL_NONE;
1993 info->fix.accel = FB_ACCEL_CIRRUS_ALPINE;
1995 info->fbops = &cirrusfb_ops;
1997 if (cinfo->btype == BT_GD5480) {
1998 if (var->bits_per_pixel == 16)
1999 info->screen_base += 1 * MB_;
2000 if (var->bits_per_pixel == 32)
2001 info->screen_base += 2 * MB_;
2004 /* Fill fix common fields */
2005 strlcpy(info->fix.id, cirrusfb_board_info[cinfo->btype].name,
2006 sizeof(info->fix.id));
2008 /* monochrome: only 1 memory plane */
2009 /* 8 bit and above: Use whole memory area */
2010 info->fix.smem_len = info->screen_size;
2011 if (var->bits_per_pixel == 1)
2012 info->fix.smem_len /= 4;
2013 info->fix.type_aux = 0;
2014 info->fix.xpanstep = 1;
2015 info->fix.ypanstep = 1;
2016 info->fix.ywrapstep = 0;
2018 /* FIXME: map region at 0xB8000 if available, fill in here */
2019 info->fix.mmio_len = 0;
2021 fb_alloc_cmap(&info->cmap, 256, 0);
2026 static int cirrusfb_register(struct fb_info *info)
2028 struct cirrusfb_info *cinfo = info->par;
2032 assert(cinfo->btype != BT_NONE);
2034 /* set all the vital stuff */
2035 cirrusfb_set_fbinfo(info);
2037 dev_dbg(info->device, "(RAM start set to: 0x%p)\n", info->screen_base);
2039 err = fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 8);
2041 dev_dbg(info->device, "wrong initial video mode\n");
2043 goto err_dealloc_cmap;
2046 info->var.activate = FB_ACTIVATE_NOW;
2048 err = cirrusfb_check_var(&info->var, info);
2050 /* should never happen */
2051 dev_dbg(info->device,
2052 "choking on default var... umm, no good.\n");
2053 goto err_dealloc_cmap;
2056 err = register_framebuffer(info);
2058 dev_err(info->device,
2059 "could not register fb device; err = %d!\n", err);
2060 goto err_dealloc_cmap;
2066 fb_dealloc_cmap(&info->cmap);
2070 static void cirrusfb_cleanup(struct fb_info *info)
2072 struct cirrusfb_info *cinfo = info->par;
2074 switch_monitor(cinfo, 0);
2075 unregister_framebuffer(info);
2076 fb_dealloc_cmap(&info->cmap);
2077 dev_dbg(info->device, "Framebuffer unregistered\n");
2079 framebuffer_release(info);
2083 static int cirrusfb_pci_register(struct pci_dev *pdev,
2084 const struct pci_device_id *ent)
2086 struct cirrusfb_info *cinfo;
2087 struct fb_info *info;
2088 unsigned long board_addr, board_size;
2091 ret = pci_enable_device(pdev);
2093 printk(KERN_ERR "cirrusfb: Cannot enable PCI device\n");
2097 info = framebuffer_alloc(sizeof(struct cirrusfb_info), &pdev->dev);
2099 printk(KERN_ERR "cirrusfb: could not allocate memory\n");
2105 cinfo->btype = (enum cirrus_board) ent->driver_data;
2107 dev_dbg(info->device,
2108 " Found PCI device, base address 0 is 0x%Lx, btype set to %d\n",
2109 (unsigned long long)pdev->resource[0].start, cinfo->btype);
2110 dev_dbg(info->device, " base address 1 is 0x%Lx\n",
2111 (unsigned long long)pdev->resource[1].start);
2113 dev_dbg(info->device,
2114 "Attempt to get PCI info for Cirrus Graphics Card\n");
2115 get_pci_addrs(pdev, &board_addr, &info->fix.mmio_start);
2116 /* FIXME: this forces VGA. alternatives? */
2117 cinfo->regbase = NULL;
2118 cinfo->laguna_mmio = ioremap(info->fix.mmio_start, 0x1000);
2120 dev_dbg(info->device, "Board address: 0x%lx, register address: 0x%lx\n",
2121 board_addr, info->fix.mmio_start);
2123 board_size = (cinfo->btype == BT_GD5480) ?
2124 32 * MB_ : cirrusfb_get_memsize(info, cinfo->regbase);
2126 ret = pci_request_regions(pdev, "cirrusfb");
2128 dev_err(info->device, "cannot reserve region 0x%lx, abort\n",
2130 goto err_release_fb;
2132 #if 0 /* if the system didn't claim this region, we would... */
2133 if (!request_mem_region(0xA0000, 65535, "cirrusfb")) {
2134 dev_err(info->device, "cannot reserve region 0x%lx, abort\n",
2137 goto err_release_regions;
2140 if (request_region(0x3C0, 32, "cirrusfb"))
2141 release_io_ports = 1;
2143 info->screen_base = ioremap(board_addr, board_size);
2144 if (!info->screen_base) {
2146 goto err_release_legacy;
2149 info->fix.smem_start = board_addr;
2150 info->screen_size = board_size;
2151 cinfo->unmap = cirrusfb_pci_unmap;
2153 dev_info(info->device,
2154 "Cirrus Logic chipset on PCI bus, RAM (%lu kB) at 0x%lx\n",
2155 info->screen_size >> 10, board_addr);
2156 pci_set_drvdata(pdev, info);
2158 ret = cirrusfb_register(info);
2162 pci_set_drvdata(pdev, NULL);
2163 iounmap(info->screen_base);
2165 if (release_io_ports)
2166 release_region(0x3C0, 32);
2168 release_mem_region(0xA0000, 65535);
2169 err_release_regions:
2171 pci_release_regions(pdev);
2173 if (cinfo->laguna_mmio != NULL)
2174 iounmap(cinfo->laguna_mmio);
2175 framebuffer_release(info);
2180 static void cirrusfb_pci_unregister(struct pci_dev *pdev)
2182 struct fb_info *info = pci_get_drvdata(pdev);
2184 cirrusfb_cleanup(info);
2187 static struct pci_driver cirrusfb_pci_driver = {
2189 .id_table = cirrusfb_pci_table,
2190 .probe = cirrusfb_pci_register,
2191 .remove = cirrusfb_pci_unregister,
2194 .suspend = cirrusfb_pci_suspend,
2195 .resume = cirrusfb_pci_resume,
2199 #endif /* CONFIG_PCI */
2202 static int cirrusfb_zorro_register(struct zorro_dev *z,
2203 const struct zorro_device_id *ent)
2205 struct fb_info *info;
2207 const struct zorrocl *zcl;
2208 enum cirrus_board btype;
2209 unsigned long regbase, ramsize, rambase;
2210 struct cirrusfb_info *cinfo;
2212 info = framebuffer_alloc(sizeof(struct cirrusfb_info), &z->dev);
2214 printk(KERN_ERR "cirrusfb: could not allocate memory\n");
2218 zcl = (const struct zorrocl *)ent->driver_data;
2220 regbase = zorro_resource_start(z) + zcl->regoffset;
2221 ramsize = zcl->ramsize;
2223 rambase = zorro_resource_start(z) + zcl->ramoffset;
2224 if (zorro_resource_len(z) == 64 * MB_) {
2225 /* Quirk for 64 MiB Picasso IV */
2226 rambase += zcl->ramoffset;
2229 struct zorro_dev *ram = zorro_find_device(zcl->ramid, NULL);
2230 if (!ram || !zorro_resource_len(ram)) {
2231 dev_err(info->device, "No video RAM found\n");
2233 goto err_release_fb;
2235 rambase = zorro_resource_start(ram);
2236 ramsize = zorro_resource_len(ram);
2238 (ram = zorro_find_device(zcl->ramid2, NULL))) {
2239 if (zorro_resource_start(ram) != rambase + ramsize) {
2240 dev_warn(info->device,
2241 "Skipping non-contiguous RAM at %pR\n",
2244 ramsize += zorro_resource_len(ram);
2249 dev_info(info->device,
2250 "%s board detected, REG at 0x%lx, %lu MiB RAM at 0x%lx\n",
2251 cirrusfb_board_info[btype].name, regbase, ramsize / MB_,
2254 if (!zorro_request_device(z, "cirrusfb")) {
2255 dev_err(info->device, "Cannot reserve %pR\n", &z->resource);
2257 goto err_release_fb;
2261 cinfo->btype = btype;
2263 info->fix.mmio_start = regbase;
2264 cinfo->regbase = regbase > 16 * MB_ ? ioremap(regbase, 64 * 1024)
2265 : (caddr_t)ZTWO_VADDR(regbase);
2266 if (!cinfo->regbase) {
2267 dev_err(info->device, "Cannot map registers\n");
2269 goto err_release_dev;
2272 info->fix.smem_start = rambase;
2273 info->screen_size = ramsize;
2274 info->screen_base = rambase > 16 * MB_ ? ioremap(rambase, ramsize)
2275 : (caddr_t)ZTWO_VADDR(rambase);
2276 if (!info->screen_base) {
2277 dev_err(info->device, "Cannot map video RAM\n");
2282 cinfo->unmap = cirrusfb_zorro_unmap;
2284 dev_info(info->device,
2285 "Cirrus Logic chipset on Zorro bus, RAM (%lu MiB) at 0x%lx\n",
2286 ramsize / MB_, rambase);
2288 /* MCLK select etc. */
2289 if (cirrusfb_board_info[btype].init_sr1f)
2290 vga_wseq(cinfo->regbase, CL_SEQR1F,
2291 cirrusfb_board_info[btype].sr1f);
2293 error = cirrusfb_register(info);
2295 dev_err(info->device, "Failed to register device, error %d\n",
2300 zorro_set_drvdata(z, info);
2304 if (rambase > 16 * MB_)
2305 iounmap(info->screen_base);
2308 if (regbase > 16 * MB_)
2309 iounmap(cinfo->regbase);
2311 zorro_release_device(z);
2313 framebuffer_release(info);
2317 void cirrusfb_zorro_unregister(struct zorro_dev *z)
2319 struct fb_info *info = zorro_get_drvdata(z);
2321 cirrusfb_cleanup(info);
2322 zorro_set_drvdata(z, NULL);
2325 static struct zorro_driver cirrusfb_zorro_driver = {
2327 .id_table = cirrusfb_zorro_table,
2328 .probe = cirrusfb_zorro_register,
2329 .remove = cirrusfb_zorro_unregister,
2331 #endif /* CONFIG_ZORRO */
2334 static int __init cirrusfb_setup(char *options)
2338 if (!options || !*options)
2341 while ((this_opt = strsep(&options, ",")) != NULL) {
2345 if (!strcmp(this_opt, "noaccel"))
2347 else if (!strncmp(this_opt, "mode:", 5))
2348 mode_option = this_opt + 5;
2350 mode_option = this_opt;
2360 MODULE_AUTHOR("Copyright 1999,2000 Jeff Garzik <jgarzik@pobox.com>");
2361 MODULE_DESCRIPTION("Accelerated FBDev driver for Cirrus Logic chips");
2362 MODULE_LICENSE("GPL");
2364 static int __init cirrusfb_init(void)
2369 char *option = NULL;
2371 if (fb_get_options("cirrusfb", &option))
2373 cirrusfb_setup(option);
2377 error |= zorro_register_driver(&cirrusfb_zorro_driver);
2380 error |= pci_register_driver(&cirrusfb_pci_driver);
2385 static void __exit cirrusfb_exit(void)
2388 pci_unregister_driver(&cirrusfb_pci_driver);
2391 zorro_unregister_driver(&cirrusfb_zorro_driver);
2395 module_init(cirrusfb_init);
2397 module_param(mode_option, charp, 0);
2398 MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'");
2399 module_param(noaccel, bool, 0);
2400 MODULE_PARM_DESC(noaccel, "Disable acceleration");
2403 module_exit(cirrusfb_exit);
2406 /**********************************************************************/
2407 /* about the following functions - I have used the same names for the */
2408 /* functions as Markus Wild did in his Retina driver for NetBSD as */
2409 /* they just made sense for this purpose. Apart from that, I wrote */
2410 /* these functions myself. */
2411 /**********************************************************************/
2413 /*** WGen() - write into one of the external/general registers ***/
2414 static void WGen(const struct cirrusfb_info *cinfo,
2415 int regnum, unsigned char val)
2417 unsigned long regofs = 0;
2419 if (cinfo->btype == BT_PICASSO) {
2420 /* Picasso II specific hack */
2421 /* if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D ||
2422 regnum == CL_VSSM2) */
2423 if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D)
2427 vga_w(cinfo->regbase, regofs + regnum, val);
2430 /*** RGen() - read out one of the external/general registers ***/
2431 static unsigned char RGen(const struct cirrusfb_info *cinfo, int regnum)
2433 unsigned long regofs = 0;
2435 if (cinfo->btype == BT_PICASSO) {
2436 /* Picasso II specific hack */
2437 /* if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D ||
2438 regnum == CL_VSSM2) */
2439 if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D)
2443 return vga_r(cinfo->regbase, regofs + regnum);
2446 /*** AttrOn() - turn on VideoEnable for Attribute controller ***/
2447 static void AttrOn(const struct cirrusfb_info *cinfo)
2449 assert(cinfo != NULL);
2451 if (vga_rcrt(cinfo->regbase, CL_CRT24) & 0x80) {
2452 /* if we're just in "write value" mode, write back the */
2453 /* same value as before to not modify anything */
2454 vga_w(cinfo->regbase, VGA_ATT_IW,
2455 vga_r(cinfo->regbase, VGA_ATT_R));
2457 /* turn on video bit */
2458 /* vga_w(cinfo->regbase, VGA_ATT_IW, 0x20); */
2459 vga_w(cinfo->regbase, VGA_ATT_IW, 0x33);
2461 /* dummy write on Reg0 to be on "write index" mode next time */
2462 vga_w(cinfo->regbase, VGA_ATT_IW, 0x00);
2465 /*** WHDR() - write into the Hidden DAC register ***/
2466 /* as the HDR is the only extension register that requires special treatment
2467 * (the other extension registers are accessible just like the "ordinary"
2468 * registers of their functional group) here is a specialized routine for
2471 static void WHDR(const struct cirrusfb_info *cinfo, unsigned char val)
2473 unsigned char dummy;
2475 if (is_laguna(cinfo))
2477 if (cinfo->btype == BT_PICASSO) {
2478 /* Klaus' hint for correct access to HDR on some boards */
2479 /* first write 0 to pixel mask (3c6) */
2480 WGen(cinfo, VGA_PEL_MSK, 0x00);
2482 /* next read dummy from pixel address (3c8) */
2483 dummy = RGen(cinfo, VGA_PEL_IW);
2486 /* now do the usual stuff to access the HDR */
2488 dummy = RGen(cinfo, VGA_PEL_MSK);
2490 dummy = RGen(cinfo, VGA_PEL_MSK);
2492 dummy = RGen(cinfo, VGA_PEL_MSK);
2494 dummy = RGen(cinfo, VGA_PEL_MSK);
2497 WGen(cinfo, VGA_PEL_MSK, val);
2500 if (cinfo->btype == BT_PICASSO) {
2501 /* now first reset HDR access counter */
2502 dummy = RGen(cinfo, VGA_PEL_IW);
2505 /* and at the end, restore the mask value */
2506 /* ## is this mask always 0xff? */
2507 WGen(cinfo, VGA_PEL_MSK, 0xff);
2512 /*** WSFR() - write to the "special function register" (SFR) ***/
2513 static void WSFR(struct cirrusfb_info *cinfo, unsigned char val)
2516 assert(cinfo->regbase != NULL);
2518 z_writeb(val, cinfo->regbase + 0x8000);
2522 /* The Picasso has a second register for switching the monitor bit */
2523 static void WSFR2(struct cirrusfb_info *cinfo, unsigned char val)
2526 /* writing an arbitrary value to this one causes the monitor switcher */
2527 /* to flip to Amiga display */
2528 assert(cinfo->regbase != NULL);
2530 z_writeb(val, cinfo->regbase + 0x9000);
2534 /*** WClut - set CLUT entry (range: 0..63) ***/
2535 static void WClut(struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char red,
2536 unsigned char green, unsigned char blue)
2538 unsigned int data = VGA_PEL_D;
2540 /* address write mode register is not translated.. */
2541 vga_w(cinfo->regbase, VGA_PEL_IW, regnum);
2543 if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 ||
2544 cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480 ||
2545 cinfo->btype == BT_SD64 || is_laguna(cinfo)) {
2546 /* but DAC data register IS, at least for Picasso II */
2547 if (cinfo->btype == BT_PICASSO)
2549 vga_w(cinfo->regbase, data, red);
2550 vga_w(cinfo->regbase, data, green);
2551 vga_w(cinfo->regbase, data, blue);
2553 vga_w(cinfo->regbase, data, blue);
2554 vga_w(cinfo->regbase, data, green);
2555 vga_w(cinfo->regbase, data, red);
2560 /*** RClut - read CLUT entry (range 0..63) ***/
2561 static void RClut(struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char *red,
2562 unsigned char *green, unsigned char *blue)
2564 unsigned int data = VGA_PEL_D;
2566 vga_w(cinfo->regbase, VGA_PEL_IR, regnum);
2568 if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 ||
2569 cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480) {
2570 if (cinfo->btype == BT_PICASSO)
2572 *red = vga_r(cinfo->regbase, data);
2573 *green = vga_r(cinfo->regbase, data);
2574 *blue = vga_r(cinfo->regbase, data);
2576 *blue = vga_r(cinfo->regbase, data);
2577 *green = vga_r(cinfo->regbase, data);
2578 *red = vga_r(cinfo->regbase, data);
2583 /*******************************************************************
2586 Wait for the BitBLT engine to complete a possible earlier job
2587 *********************************************************************/
2589 /* FIXME: use interrupts instead */
2590 static void cirrusfb_WaitBLT(u8 __iomem *regbase)
2592 while (vga_rgfx(regbase, CL_GR31) & 0x08)
2596 /*******************************************************************
2599 perform accelerated "scrolling"
2600 ********************************************************************/
2602 static void cirrusfb_set_blitter(u8 __iomem *regbase,
2603 u_short nwidth, u_short nheight,
2604 u_long nsrc, u_long ndest,
2605 u_short bltmode, u_short line_length)
2608 /* pitch: set to line_length */
2609 /* dest pitch low */
2610 vga_wgfx(regbase, CL_GR24, line_length & 0xff);
2612 vga_wgfx(regbase, CL_GR25, line_length >> 8);
2613 /* source pitch low */
2614 vga_wgfx(regbase, CL_GR26, line_length & 0xff);
2615 /* source pitch hi */
2616 vga_wgfx(regbase, CL_GR27, line_length >> 8);
2618 /* BLT width: actual number of pixels - 1 */
2620 vga_wgfx(regbase, CL_GR20, nwidth & 0xff);
2622 vga_wgfx(regbase, CL_GR21, nwidth >> 8);
2624 /* BLT height: actual number of lines -1 */
2625 /* BLT height low */
2626 vga_wgfx(regbase, CL_GR22, nheight & 0xff);
2628 vga_wgfx(regbase, CL_GR23, nheight >> 8);
2630 /* BLT destination */
2632 vga_wgfx(regbase, CL_GR28, (u_char) (ndest & 0xff));
2634 vga_wgfx(regbase, CL_GR29, (u_char) (ndest >> 8));
2636 vga_wgfx(regbase, CL_GR2A, (u_char) (ndest >> 16));
2640 vga_wgfx(regbase, CL_GR2C, (u_char) (nsrc & 0xff));
2642 vga_wgfx(regbase, CL_GR2D, (u_char) (nsrc >> 8));
2644 vga_wgfx(regbase, CL_GR2E, (u_char) (nsrc >> 16));
2647 vga_wgfx(regbase, CL_GR30, bltmode); /* BLT mode */
2649 /* BLT ROP: SrcCopy */
2650 vga_wgfx(regbase, CL_GR32, 0x0d); /* BLT ROP */
2652 /* and finally: GO! */
2653 vga_wgfx(regbase, CL_GR31, 0x02); /* BLT Start/status */
2656 /*******************************************************************
2659 perform accelerated "scrolling"
2660 ********************************************************************/
2662 static void cirrusfb_BitBLT(u8 __iomem *regbase, int bits_per_pixel,
2663 u_short curx, u_short cury,
2664 u_short destx, u_short desty,
2665 u_short width, u_short height,
2666 u_short line_length)
2668 u_short nwidth = width - 1;
2669 u_short nheight = height - 1;
2674 /* if source adr < dest addr, do the Blt backwards */
2675 if (cury <= desty) {
2676 if (cury == desty) {
2677 /* if src and dest are on the same line, check x */
2683 /* standard case: forward blitting */
2684 nsrc = (cury * line_length) + curx;
2685 ndest = (desty * line_length) + destx;
2687 /* this means start addresses are at the end,
2688 * counting backwards
2690 nsrc += nheight * line_length + nwidth;
2691 ndest += nheight * line_length + nwidth;
2694 cirrusfb_WaitBLT(regbase);
2696 cirrusfb_set_blitter(regbase, nwidth, nheight,
2697 nsrc, ndest, bltmode, line_length);
2700 /*******************************************************************
2703 perform accelerated rectangle fill
2704 ********************************************************************/
2706 static void cirrusfb_RectFill(u8 __iomem *regbase, int bits_per_pixel,
2707 u_short x, u_short y, u_short width, u_short height,
2708 u32 fg_color, u32 bg_color, u_short line_length,
2711 u_long ndest = (y * line_length) + x;
2714 cirrusfb_WaitBLT(regbase);
2716 /* This is a ColorExpand Blt, using the */
2717 /* same color for foreground and background */
2718 vga_wgfx(regbase, VGA_GFX_SR_VALUE, bg_color);
2719 vga_wgfx(regbase, VGA_GFX_SR_ENABLE, fg_color);
2722 if (bits_per_pixel >= 16) {
2723 vga_wgfx(regbase, CL_GR10, bg_color >> 8);
2724 vga_wgfx(regbase, CL_GR11, fg_color >> 8);
2727 if (bits_per_pixel >= 24) {
2728 vga_wgfx(regbase, CL_GR12, bg_color >> 16);
2729 vga_wgfx(regbase, CL_GR13, fg_color >> 16);
2732 if (bits_per_pixel == 32) {
2733 vga_wgfx(regbase, CL_GR14, bg_color >> 24);
2734 vga_wgfx(regbase, CL_GR15, fg_color >> 24);
2737 cirrusfb_set_blitter(regbase, width - 1, height - 1,
2738 0, ndest, op | blitmode, line_length);
2741 /**************************************************************************
2742 * bestclock() - determine closest possible clock lower(?) than the
2743 * desired pixel clock
2744 **************************************************************************/
2745 static void bestclock(long freq, int *nom, int *den, int *div)
2750 assert(nom != NULL);
2751 assert(den != NULL);
2752 assert(div != NULL);
2763 for (n = 32; n < 128; n++) {
2766 d = (14318 * n) / freq;
2767 if ((d >= 7) && (d <= 63)) {
2774 h = ((14318 * n) / temp) >> s;
2775 h = h > freq ? h - freq : freq - h;
2784 if ((d >= 7) && (d <= 63)) {
2789 h = ((14318 * n) / d) >> s;
2790 h = h > freq ? h - freq : freq - h;
2801 /* -------------------------------------------------------------------------
2803 * debugging functions
2805 * -------------------------------------------------------------------------
2808 #ifdef CIRRUSFB_DEBUG
2811 * cirrusfb_dbg_print_regs
2812 * @base: If using newmmio, the newmmio base address, otherwise %NULL
2813 * @reg_class: type of registers to read: %CRT, or %SEQ
2816 * Dumps the given list of VGA CRTC registers. If @base is %NULL,
2817 * old-style I/O ports are queried for information, otherwise MMIO is
2818 * used at the given @base address to query the information.
2821 static void cirrusfb_dbg_print_regs(struct fb_info *info,
2823 enum cirrusfb_dbg_reg_class reg_class, ...)
2826 unsigned char val = 0;
2830 va_start(list, reg_class);
2832 name = va_arg(list, char *);
2833 while (name != NULL) {
2834 reg = va_arg(list, int);
2836 switch (reg_class) {
2838 val = vga_rcrt(regbase, (unsigned char) reg);
2841 val = vga_rseq(regbase, (unsigned char) reg);
2844 /* should never occur */
2849 dev_dbg(info->device, "%8s = 0x%02X\n", name, val);
2851 name = va_arg(list, char *);
2858 * cirrusfb_dbg_reg_dump
2859 * @base: If using newmmio, the newmmio base address, otherwise %NULL
2862 * Dumps a list of interesting VGA and CIRRUSFB registers. If @base is %NULL,
2863 * old-style I/O ports are queried for information, otherwise MMIO is
2864 * used at the given @base address to query the information.
2867 static void cirrusfb_dbg_reg_dump(struct fb_info *info, caddr_t regbase)
2869 dev_dbg(info->device, "VGA CRTC register dump:\n");
2871 cirrusfb_dbg_print_regs(info, regbase, CRT,
2921 dev_dbg(info->device, "\n");
2923 dev_dbg(info->device, "VGA SEQ register dump:\n");
2925 cirrusfb_dbg_print_regs(info, regbase, SEQ,
2954 dev_dbg(info->device, "\n");
2957 #endif /* CIRRUSFB_DEBUG */