2 * drivers/video/cirrusfb.c - driver for Cirrus Logic chipsets
4 * Copyright 1999-2001 Jeff Garzik <jgarzik@pobox.com>
6 * Contributors (thanks, all!)
9 * Overhaul for Linux 2.6
12 * Major contributions; Motorola PowerStack (PPC and PCI) support,
13 * GD54xx, 1280x1024 mode support, change MCLK based on VCLK.
16 * Excellent code review.
19 * Amiga updates and testing.
21 * Original cirrusfb author: Frank Neumann
23 * Based on retz3fb.c and cirrusfb.c:
24 * Copyright (C) 1997 Jes Sorensen
25 * Copyright (C) 1996 Frank Neumann
27 ***************************************************************
29 * Format this code with GNU indent '-kr -i8 -pcs' options.
31 * This file is subject to the terms and conditions of the GNU General Public
32 * License. See the file COPYING in the main directory of this archive
37 #include <linux/module.h>
38 #include <linux/kernel.h>
39 #include <linux/errno.h>
40 #include <linux/string.h>
42 #include <linux/slab.h>
43 #include <linux/delay.h>
45 #include <linux/init.h>
46 #include <asm/pgtable.h>
49 #include <linux/zorro.h>
52 #include <linux/pci.h>
55 #include <asm/amigahw.h>
57 #ifdef CONFIG_PPC_PREP
58 #include <asm/machdep.h>
59 #define isPReP machine_is(prep)
64 #include <video/vga.h>
65 #include <video/cirrus.h>
67 /*****************************************************************
69 * debugging and utility macros
73 /* disable runtime assertions? */
74 /* #define CIRRUSFB_NDEBUG */
76 /* debugging assertions */
77 #ifndef CIRRUSFB_NDEBUG
78 #define assert(expr) \
80 printk("Assertion failed! %s,%s,%s,line=%d\n", \
81 #expr, __FILE__, __func__, __LINE__); \
87 #define MB_ (1024 * 1024)
89 /*****************************************************************
102 BT_PICASSO4, /* GD5446 */
103 BT_ALPINE, /* GD543x/4x */
105 BT_LAGUNA, /* GD5462/64 */
106 BT_LAGUNAB, /* GD5465 */
110 * per-board-type information, used for enumerating and abstracting
111 * chip-specific information
112 * NOTE: MUST be in the same order as enum cirrus_board in order to
113 * use direct indexing on this array
114 * NOTE: '__initdata' cannot be used as some of this info
115 * is required at runtime. Maybe separate into an init-only and
118 static const struct cirrusfb_board_info_rec {
119 char *name; /* ASCII name of chipset */
120 long maxclock[5]; /* maximum video clock */
121 /* for 1/4bpp, 8bpp 15/16bpp, 24bpp, 32bpp - numbers from xorg code */
122 bool init_sr07 : 1; /* init SR07 during init_vgachip() */
123 bool init_sr1f : 1; /* write SR1F during init_vgachip() */
124 /* construct bit 19 of screen start address */
125 bool scrn_start_bit19 : 1;
127 /* initial SR07 value, then for each mode */
129 unsigned char sr07_1bpp;
130 unsigned char sr07_1bpp_mux;
131 unsigned char sr07_8bpp;
132 unsigned char sr07_8bpp_mux;
134 unsigned char sr1f; /* SR1F VGA initial register value */
135 } cirrusfb_board_info[] = {
140 /* the SD64/P4 have a higher max. videoclock */
141 135100, 135100, 85500, 85500, 0
145 .scrn_start_bit19 = true,
152 .name = "CL Piccolo",
155 90000, 90000, 90000, 90000, 90000
159 .scrn_start_bit19 = false,
166 .name = "CL Picasso",
169 90000, 90000, 90000, 90000, 90000
173 .scrn_start_bit19 = false,
180 .name = "CL Spectrum",
183 90000, 90000, 90000, 90000, 90000
187 .scrn_start_bit19 = false,
194 .name = "CL Picasso4",
196 135100, 135100, 85500, 85500, 0
200 .scrn_start_bit19 = true,
209 /* for the GD5430. GD5446 can do more... */
210 85500, 85500, 50000, 28500, 0
214 .scrn_start_bit19 = true,
217 .sr07_1bpp_mux = 0xA7,
219 .sr07_8bpp_mux = 0xA7,
225 135100, 200000, 200000, 135100, 135100
229 .scrn_start_bit19 = true,
238 /* taken from X11 code */
239 170000, 170000, 170000, 170000, 135100,
243 .scrn_start_bit19 = true,
246 .name = "CL Laguna AGP",
248 /* taken from X11 code */
249 170000, 250000, 170000, 170000, 135100,
253 .scrn_start_bit19 = true,
258 #define CHIP(id, btype) \
259 { PCI_VENDOR_ID_CIRRUS, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (btype) }
261 static struct pci_device_id cirrusfb_pci_table[] = {
262 CHIP(PCI_DEVICE_ID_CIRRUS_5436, BT_ALPINE),
263 CHIP(PCI_DEVICE_ID_CIRRUS_5434_8, BT_ALPINE),
264 CHIP(PCI_DEVICE_ID_CIRRUS_5434_4, BT_ALPINE),
265 CHIP(PCI_DEVICE_ID_CIRRUS_5430, BT_ALPINE), /* GD-5440 is same id */
266 CHIP(PCI_DEVICE_ID_CIRRUS_7543, BT_ALPINE),
267 CHIP(PCI_DEVICE_ID_CIRRUS_7548, BT_ALPINE),
268 CHIP(PCI_DEVICE_ID_CIRRUS_5480, BT_GD5480), /* MacPicasso likely */
269 CHIP(PCI_DEVICE_ID_CIRRUS_5446, BT_PICASSO4), /* Picasso 4 is 5446 */
270 CHIP(PCI_DEVICE_ID_CIRRUS_5462, BT_LAGUNA), /* CL Laguna */
271 CHIP(PCI_DEVICE_ID_CIRRUS_5464, BT_LAGUNA), /* CL Laguna 3D */
272 CHIP(PCI_DEVICE_ID_CIRRUS_5465, BT_LAGUNAB), /* CL Laguna 3DA*/
275 MODULE_DEVICE_TABLE(pci, cirrusfb_pci_table);
277 #endif /* CONFIG_PCI */
280 static const struct zorro_device_id cirrusfb_zorro_table[] = {
282 .id = ZORRO_PROD_HELFRICH_SD64_RAM,
283 .driver_data = BT_SD64,
285 .id = ZORRO_PROD_HELFRICH_PICCOLO_RAM,
286 .driver_data = BT_PICCOLO,
288 .id = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_II_II_PLUS_RAM,
289 .driver_data = BT_PICASSO,
291 .id = ZORRO_PROD_GVP_EGS_28_24_SPECTRUM_RAM,
292 .driver_data = BT_SPECTRUM,
294 .id = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_IV_Z3,
295 .driver_data = BT_PICASSO4,
300 static const struct {
303 } cirrusfb_zorro_table2[] = {
305 .id2 = ZORRO_PROD_HELFRICH_SD64_REG,
309 .id2 = ZORRO_PROD_HELFRICH_PICCOLO_REG,
313 .id2 = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_II_II_PLUS_REG,
317 .id2 = ZORRO_PROD_GVP_EGS_28_24_SPECTRUM_REG,
325 #endif /* CONFIG_ZORRO */
327 #ifdef CIRRUSFB_DEBUG
328 enum cirrusfb_dbg_reg_class {
332 #endif /* CIRRUSFB_DEBUG */
334 /* info about board */
335 struct cirrusfb_info {
337 u8 __iomem *laguna_mmio;
338 enum cirrus_board btype;
339 unsigned char SFR; /* Shadow of special function register */
343 u32 pseudo_palette[16];
345 void (*unmap)(struct fb_info *info);
348 static int noaccel __devinitdata;
349 static char *mode_option __devinitdata = "640x480@60";
351 /****************************************************************************/
352 /**** BEGIN PROTOTYPES ******************************************************/
354 /*--- Interface used by the world ------------------------------------------*/
355 static int cirrusfb_pan_display(struct fb_var_screeninfo *var,
356 struct fb_info *info);
358 /*--- Internal routines ----------------------------------------------------*/
359 static void init_vgachip(struct fb_info *info);
360 static void switch_monitor(struct cirrusfb_info *cinfo, int on);
361 static void WGen(const struct cirrusfb_info *cinfo,
362 int regnum, unsigned char val);
363 static unsigned char RGen(const struct cirrusfb_info *cinfo, int regnum);
364 static void AttrOn(const struct cirrusfb_info *cinfo);
365 static void WHDR(const struct cirrusfb_info *cinfo, unsigned char val);
366 static void WSFR(struct cirrusfb_info *cinfo, unsigned char val);
367 static void WSFR2(struct cirrusfb_info *cinfo, unsigned char val);
368 static void WClut(struct cirrusfb_info *cinfo, unsigned char regnum,
369 unsigned char red, unsigned char green, unsigned char blue);
371 static void RClut(struct cirrusfb_info *cinfo, unsigned char regnum,
372 unsigned char *red, unsigned char *green,
373 unsigned char *blue);
375 static void cirrusfb_WaitBLT(u8 __iomem *regbase);
376 static void cirrusfb_BitBLT(u8 __iomem *regbase, int bits_per_pixel,
377 u_short curx, u_short cury,
378 u_short destx, u_short desty,
379 u_short width, u_short height,
380 u_short line_length);
381 static void cirrusfb_RectFill(u8 __iomem *regbase, int bits_per_pixel,
382 u_short x, u_short y,
383 u_short width, u_short height,
384 u_char color, u_short line_length);
386 static void bestclock(long freq, int *nom, int *den, int *div);
388 #ifdef CIRRUSFB_DEBUG
389 static void cirrusfb_dbg_reg_dump(struct fb_info *info, caddr_t regbase);
390 static void cirrusfb_dbg_print_regs(struct fb_info *info,
392 enum cirrusfb_dbg_reg_class reg_class, ...);
393 #endif /* CIRRUSFB_DEBUG */
395 /*** END PROTOTYPES ********************************************************/
396 /*****************************************************************************/
397 /*** BEGIN Interface Used by the World ***************************************/
399 static inline int is_laguna(const struct cirrusfb_info *cinfo)
401 return cinfo->btype == BT_LAGUNA || cinfo->btype == BT_LAGUNAB;
404 static int opencount;
406 /*--- Open /dev/fbx ---------------------------------------------------------*/
407 static int cirrusfb_open(struct fb_info *info, int user)
409 if (opencount++ == 0)
410 switch_monitor(info->par, 1);
414 /*--- Close /dev/fbx --------------------------------------------------------*/
415 static int cirrusfb_release(struct fb_info *info, int user)
417 if (--opencount == 0)
418 switch_monitor(info->par, 0);
422 /**** END Interface used by the World *************************************/
423 /****************************************************************************/
424 /**** BEGIN Hardware specific Routines **************************************/
426 /* Check if the MCLK is not a better clock source */
427 static int cirrusfb_check_mclk(struct fb_info *info, long freq)
429 struct cirrusfb_info *cinfo = info->par;
430 long mclk = vga_rseq(cinfo->regbase, CL_SEQR1F) & 0x3f;
432 /* Read MCLK value */
433 mclk = (14318 * mclk) >> 3;
434 dev_dbg(info->device, "Read MCLK of %ld kHz\n", mclk);
436 /* Determine if we should use MCLK instead of VCLK, and if so, what we
437 * should divide it by to get VCLK
440 if (abs(freq - mclk) < 250) {
441 dev_dbg(info->device, "Using VCLK = MCLK\n");
443 } else if (abs(freq - (mclk / 2)) < 250) {
444 dev_dbg(info->device, "Using VCLK = MCLK/2\n");
451 static int cirrusfb_check_pixclock(const struct fb_var_screeninfo *var,
452 struct fb_info *info)
456 struct cirrusfb_info *cinfo = info->par;
457 unsigned maxclockidx = var->bits_per_pixel >> 3;
459 /* convert from ps to kHz */
460 freq = PICOS2KHZ(var->pixclock);
462 dev_dbg(info->device, "desired pixclock: %ld kHz\n", freq);
464 maxclock = cirrusfb_board_info[cinfo->btype].maxclock[maxclockidx];
465 cinfo->multiplexing = 0;
467 /* If the frequency is greater than we can support, we might be able
468 * to use multiplexing for the video mode */
469 if (freq > maxclock) {
470 switch (cinfo->btype) {
473 cinfo->multiplexing = 1;
477 dev_err(info->device,
478 "Frequency greater than maxclock (%ld kHz)\n",
484 /* TODO: If we have a 1MB 5434, we need to put ourselves in a mode where
485 * the VCLK is double the pixel clock. */
486 switch (var->bits_per_pixel) {
489 if (var->xres <= 800)
490 /* Xbh has this type of clock for 32-bit */
498 static int cirrusfb_check_var(struct fb_var_screeninfo *var,
499 struct fb_info *info)
502 /* memory size in pixels */
503 unsigned pixels = info->screen_size * 8 / var->bits_per_pixel;
505 switch (var->bits_per_pixel) {
509 var->green = var->red;
510 var->blue = var->red;
516 var->green = var->red;
517 var->blue = var->red;
523 var->green.offset = -3;
524 var->blue.offset = 8;
526 var->red.offset = 11;
527 var->green.offset = 5;
528 var->blue.offset = 0;
531 var->green.length = 6;
532 var->blue.length = 5;
538 var->green.offset = 16;
539 var->blue.offset = 24;
541 var->red.offset = 16;
542 var->green.offset = 8;
543 var->blue.offset = 0;
546 var->green.length = 8;
547 var->blue.length = 8;
551 dev_dbg(info->device,
552 "Unsupported bpp size: %d\n", var->bits_per_pixel);
554 /* should never occur */
558 if (var->xres_virtual < var->xres)
559 var->xres_virtual = var->xres;
560 /* use highest possible virtual resolution */
561 if (var->yres_virtual == -1) {
562 var->yres_virtual = pixels / var->xres_virtual;
564 dev_info(info->device,
565 "virtual resolution set to maximum of %dx%d\n",
566 var->xres_virtual, var->yres_virtual);
568 if (var->yres_virtual < var->yres)
569 var->yres_virtual = var->yres;
571 if (var->xres_virtual * var->yres_virtual > pixels) {
572 dev_err(info->device, "mode %dx%dx%d rejected... "
573 "virtual resolution too high to fit into video memory!\n",
574 var->xres_virtual, var->yres_virtual,
575 var->bits_per_pixel);
579 if (var->xoffset < 0)
581 if (var->yoffset < 0)
584 /* truncate xoffset and yoffset to maximum if too high */
585 if (var->xoffset > var->xres_virtual - var->xres)
586 var->xoffset = var->xres_virtual - var->xres - 1;
587 if (var->yoffset > var->yres_virtual - var->yres)
588 var->yoffset = var->yres_virtual - var->yres - 1;
591 var->green.msb_right =
592 var->blue.msb_right =
595 var->transp.msb_right = 0;
598 if (var->vmode & FB_VMODE_DOUBLE)
600 else if (var->vmode & FB_VMODE_INTERLACED)
601 yres = (yres + 1) / 2;
604 dev_err(info->device, "ERROR: VerticalTotal >= 1280; "
605 "special treatment required! (TODO)\n");
609 if (cirrusfb_check_pixclock(var, info))
615 static void cirrusfb_set_mclk_as_source(const struct fb_info *info, int div)
617 struct cirrusfb_info *cinfo = info->par;
618 unsigned char old1f, old1e;
620 assert(cinfo != NULL);
621 old1f = vga_rseq(cinfo->regbase, CL_SEQR1F) & ~0x40;
624 dev_dbg(info->device, "Set %s as pixclock source.\n",
625 (div == 2) ? "MCLK/2" : "MCLK");
627 old1e = vga_rseq(cinfo->regbase, CL_SEQR1E) & ~0x1;
631 vga_wseq(cinfo->regbase, CL_SEQR1E, old1e);
633 vga_wseq(cinfo->regbase, CL_SEQR1F, old1f);
636 /*************************************************************************
637 cirrusfb_set_par_foo()
639 actually writes the values for a new video mode into the hardware,
640 **************************************************************************/
641 static int cirrusfb_set_par_foo(struct fb_info *info)
643 struct cirrusfb_info *cinfo = info->par;
644 struct fb_var_screeninfo *var = &info->var;
645 u8 __iomem *regbase = cinfo->regbase;
648 const struct cirrusfb_board_info_rec *bi;
649 int hdispend, hsyncstart, hsyncend, htotal;
650 int yres, vdispend, vsyncstart, vsyncend, vtotal;
653 unsigned int control = 0, format = 0, threshold = 0;
655 dev_dbg(info->device, "Requested mode: %dx%dx%d\n",
656 var->xres, var->yres, var->bits_per_pixel);
658 switch (var->bits_per_pixel) {
660 info->fix.line_length = var->xres_virtual / 8;
661 info->fix.visual = FB_VISUAL_MONO10;
665 info->fix.line_length = var->xres_virtual;
666 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
671 info->fix.line_length = var->xres_virtual *
672 var->bits_per_pixel >> 3;
673 info->fix.visual = FB_VISUAL_TRUECOLOR;
676 info->fix.type = FB_TYPE_PACKED_PIXELS;
680 bi = &cirrusfb_board_info[cinfo->btype];
682 hsyncstart = var->xres + var->right_margin;
683 hsyncend = hsyncstart + var->hsync_len;
684 htotal = (hsyncend + var->left_margin) / 8 - 5;
685 hdispend = var->xres / 8 - 1;
686 hsyncstart = hsyncstart / 8 + 1;
687 hsyncend = hsyncend / 8 + 1;
690 vsyncstart = yres + var->lower_margin;
691 vsyncend = vsyncstart + var->vsync_len;
692 vtotal = vsyncend + var->upper_margin;
695 if (var->vmode & FB_VMODE_DOUBLE) {
700 } else if (var->vmode & FB_VMODE_INTERLACED) {
701 yres = (yres + 1) / 2;
702 vsyncstart = (vsyncstart + 1) / 2;
703 vsyncend = (vsyncend + 1) / 2;
704 vtotal = (vtotal + 1) / 2;
717 if (cinfo->multiplexing) {
723 /* unlock register VGA_CRTC_H_TOTAL..CRT7 */
724 vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, 0x20); /* previously: 0x00) */
726 /* if debugging is enabled, all parameters get output before writing */
727 dev_dbg(info->device, "CRT0: %d\n", htotal);
728 vga_wcrt(regbase, VGA_CRTC_H_TOTAL, htotal);
730 dev_dbg(info->device, "CRT1: %d\n", hdispend);
731 vga_wcrt(regbase, VGA_CRTC_H_DISP, hdispend);
733 dev_dbg(info->device, "CRT2: %d\n", var->xres / 8);
734 vga_wcrt(regbase, VGA_CRTC_H_BLANK_START, var->xres / 8);
736 /* + 128: Compatible read */
737 dev_dbg(info->device, "CRT3: 128+%d\n", (htotal + 5) % 32);
738 vga_wcrt(regbase, VGA_CRTC_H_BLANK_END,
739 128 + ((htotal + 5) % 32));
741 dev_dbg(info->device, "CRT4: %d\n", hsyncstart);
742 vga_wcrt(regbase, VGA_CRTC_H_SYNC_START, hsyncstart);
745 if ((htotal + 5) & 32)
747 dev_dbg(info->device, "CRT5: %d\n", tmp);
748 vga_wcrt(regbase, VGA_CRTC_H_SYNC_END, tmp);
750 dev_dbg(info->device, "CRT6: %d\n", vtotal & 0xff);
751 vga_wcrt(regbase, VGA_CRTC_V_TOTAL, vtotal & 0xff);
753 tmp = 16; /* LineCompare bit #9 */
758 if (vsyncstart & 256)
760 if ((vdispend + 1) & 256)
766 if (vsyncstart & 512)
768 dev_dbg(info->device, "CRT7: %d\n", tmp);
769 vga_wcrt(regbase, VGA_CRTC_OVERFLOW, tmp);
771 tmp = 0x40; /* LineCompare bit #8 */
772 if ((vdispend + 1) & 512)
774 if (var->vmode & FB_VMODE_DOUBLE)
776 dev_dbg(info->device, "CRT9: %d\n", tmp);
777 vga_wcrt(regbase, VGA_CRTC_MAX_SCAN, tmp);
779 dev_dbg(info->device, "CRT10: %d\n", vsyncstart & 0xff);
780 vga_wcrt(regbase, VGA_CRTC_V_SYNC_START, vsyncstart & 0xff);
782 dev_dbg(info->device, "CRT11: 64+32+%d\n", vsyncend % 16);
783 vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, vsyncend % 16 + 64 + 32);
785 dev_dbg(info->device, "CRT12: %d\n", vdispend & 0xff);
786 vga_wcrt(regbase, VGA_CRTC_V_DISP_END, vdispend & 0xff);
788 dev_dbg(info->device, "CRT15: %d\n", (vdispend + 1) & 0xff);
789 vga_wcrt(regbase, VGA_CRTC_V_BLANK_START, (vdispend + 1) & 0xff);
791 dev_dbg(info->device, "CRT16: %d\n", vtotal & 0xff);
792 vga_wcrt(regbase, VGA_CRTC_V_BLANK_END, vtotal & 0xff);
794 dev_dbg(info->device, "CRT18: 0xff\n");
795 vga_wcrt(regbase, VGA_CRTC_LINE_COMPARE, 0xff);
798 if (var->vmode & FB_VMODE_INTERLACED)
800 if ((htotal + 5) & 64)
802 if ((htotal + 5) & 128)
809 dev_dbg(info->device, "CRT1a: %d\n", tmp);
810 vga_wcrt(regbase, CL_CRT1A, tmp);
812 freq = PICOS2KHZ(var->pixclock);
813 bestclock(freq, &nom, &den, &div);
815 dev_dbg(info->device, "VCLK freq: %ld kHz nom: %d den: %d div: %d\n",
816 freq, nom, den, div);
819 /* hardware RefClock: 14.31818 MHz */
820 /* formula: VClk = (OSC * N) / (D * (1+P)) */
821 /* Example: VClk = (14.31818 * 91) / (23 * (1+1)) = 28.325 MHz */
823 if (cinfo->btype == BT_ALPINE) {
824 /* if freq is close to mclk or mclk/2 select mclk
827 int divMCLK = cirrusfb_check_mclk(info, freq);
830 cirrusfb_set_mclk_as_source(info, divMCLK);
833 if (is_laguna(cinfo)) {
834 long pcifc = fb_readl(cinfo->laguna_mmio + 0x3fc);
835 unsigned char tile = fb_readb(cinfo->laguna_mmio + 0x407);
836 unsigned short tile_control;
838 if (cinfo->btype == BT_LAGUNAB) {
839 tile_control = fb_readw(cinfo->laguna_mmio + 0x2c4);
840 tile_control &= ~0x80;
841 fb_writew(tile_control, cinfo->laguna_mmio + 0x2c4);
844 fb_writel(pcifc | 0x10000000l, cinfo->laguna_mmio + 0x3fc);
845 fb_writeb(tile & 0x3f, cinfo->laguna_mmio + 0x407);
846 control = fb_readw(cinfo->laguna_mmio + 0x402);
847 threshold = fb_readw(cinfo->laguna_mmio + 0xea);
850 threshold &= 0xffe0 & 0x3fbf;
856 /* 6 bit denom; ONLY 5434!!! (bugged me 10 days) */
857 if ((cinfo->btype == BT_SD64) ||
858 (cinfo->btype == BT_ALPINE) ||
859 (cinfo->btype == BT_GD5480))
862 dev_dbg(info->device, "CL_SEQR1B: %d\n", (int) tmp);
863 /* Laguna chipset has reversed clock registers */
864 if (is_laguna(cinfo)) {
865 vga_wseq(regbase, CL_SEQRE, tmp);
866 vga_wseq(regbase, CL_SEQR1E, nom);
868 vga_wseq(regbase, CL_SEQRB, nom);
869 vga_wseq(regbase, CL_SEQR1B, tmp);
875 vga_wcrt(regbase, VGA_CRTC_MODE, 0xc7);
877 /* mode control: VGA_CRTC_START_HI enable, ROTATE(?), 16bit
878 * address wrap, no compat. */
879 vga_wcrt(regbase, VGA_CRTC_MODE, 0xc3);
881 /* don't know if it would hurt to also program this if no interlaced */
882 /* mode is used, but I feel better this way.. :-) */
883 if (var->vmode & FB_VMODE_INTERLACED)
884 vga_wcrt(regbase, VGA_CRTC_REGS, htotal / 2);
886 vga_wcrt(regbase, VGA_CRTC_REGS, 0x00); /* interlace control */
888 /* adjust horizontal/vertical sync type (low/high) */
889 /* enable display memory & CRTC I/O address for color mode */
891 if (var->sync & FB_SYNC_HOR_HIGH_ACT)
893 if (var->sync & FB_SYNC_VERT_HIGH_ACT)
895 if (is_laguna(cinfo))
897 WGen(cinfo, VGA_MIS_W, tmp);
899 /* text cursor on and start line */
900 vga_wcrt(regbase, VGA_CRTC_CURSOR_START, 0);
901 /* text cursor end line */
902 vga_wcrt(regbase, VGA_CRTC_CURSOR_END, 31);
904 /******************************************************
910 /* programming for different color depths */
911 if (var->bits_per_pixel == 1) {
912 dev_dbg(info->device, "preparing for 1 bit deep display\n");
913 vga_wgfx(regbase, VGA_GFX_MODE, 0); /* mode register */
916 switch (cinfo->btype) {
924 vga_wseq(regbase, CL_SEQR7,
925 cinfo->multiplexing ?
926 bi->sr07_1bpp_mux : bi->sr07_1bpp);
931 vga_wseq(regbase, CL_SEQR7,
932 vga_rseq(regbase, CL_SEQR7) & ~0x01);
936 dev_warn(info->device, "unknown Board\n");
940 /* Extended Sequencer Mode */
941 switch (cinfo->btype) {
943 /* setting the SEQRF on SD64 is not necessary
947 vga_wseq(regbase, CL_SEQR1F, 0x1a);
952 /* ### ueberall 0x22? */
953 /* ##vorher 1c MCLK select */
954 vga_wseq(regbase, CL_SEQR1F, 0x22);
955 /* evtl d0 bei 1 bit? avoid FIFO underruns..? */
956 vga_wseq(regbase, CL_SEQRF, 0xb0);
960 /* ##vorher 22 MCLK select */
961 vga_wseq(regbase, CL_SEQR1F, 0x22);
962 /* ## vorher d0 avoid FIFO underruns..? */
963 vga_wseq(regbase, CL_SEQRF, 0xd0);
975 dev_warn(info->device, "unknown Board\n");
979 /* pixel mask: pass-through for first plane */
980 WGen(cinfo, VGA_PEL_MSK, 0x01);
981 if (cinfo->multiplexing)
982 /* hidden dac reg: 1280x1024 */
985 /* hidden dac: nothing */
987 /* memory mode: odd/even, ext. memory */
988 vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, 0x06);
989 /* plane mask: only write to first plane */
990 vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0x01);
993 /******************************************************
999 else if (var->bits_per_pixel == 8) {
1000 dev_dbg(info->device, "preparing for 8 bit deep display\n");
1001 switch (cinfo->btype) {
1009 vga_wseq(regbase, CL_SEQR7,
1010 cinfo->multiplexing ?
1011 bi->sr07_8bpp_mux : bi->sr07_8bpp);
1016 vga_wseq(regbase, CL_SEQR7,
1017 vga_rseq(regbase, CL_SEQR7) | 0x01);
1022 dev_warn(info->device, "unknown Board\n");
1026 switch (cinfo->btype) {
1029 vga_wseq(regbase, CL_SEQR1F, 0x1d);
1035 /* ### vorher 1c MCLK select */
1036 vga_wseq(regbase, CL_SEQR1F, 0x22);
1037 /* Fast Page-Mode writes */
1038 vga_wseq(regbase, CL_SEQRF, 0xb0);
1043 /* ### INCOMPLETE!! */
1044 vga_wseq(regbase, CL_SEQRF, 0xb8);
1046 /* vga_wseq(regbase, CL_SEQR1F, 0x1c); */
1050 /* We already set SRF and SR1F */
1060 dev_warn(info->device, "unknown board\n");
1064 /* mode register: 256 color mode */
1065 vga_wgfx(regbase, VGA_GFX_MODE, 64);
1066 if (cinfo->multiplexing)
1067 /* hidden dac reg: 1280x1024 */
1070 /* hidden dac: nothing */
1074 /******************************************************
1080 else if (var->bits_per_pixel == 16) {
1081 dev_dbg(info->device, "preparing for 16 bit deep display\n");
1082 switch (cinfo->btype) {
1084 /* Extended Sequencer Mode: 256c col. mode */
1085 vga_wseq(regbase, CL_SEQR7, 0xf7);
1087 vga_wseq(regbase, CL_SEQR1F, 0x1e);
1092 vga_wseq(regbase, CL_SEQR7, 0x87);
1093 /* Fast Page-Mode writes */
1094 vga_wseq(regbase, CL_SEQRF, 0xb0);
1096 vga_wseq(regbase, CL_SEQR1F, 0x22);
1100 vga_wseq(regbase, CL_SEQR7, 0x27);
1101 /* Fast Page-Mode writes */
1102 vga_wseq(regbase, CL_SEQRF, 0xb0);
1104 vga_wseq(regbase, CL_SEQR1F, 0x22);
1108 vga_wseq(regbase, CL_SEQR7, 0x27);
1109 /* vga_wseq(regbase, CL_SEQR1F, 0x1c); */
1113 vga_wseq(regbase, CL_SEQR7, 0xa7);
1117 vga_wseq(regbase, CL_SEQR7, 0x17);
1118 /* We already set SRF and SR1F */
1123 vga_wseq(regbase, CL_SEQR7,
1124 vga_rseq(regbase, CL_SEQR7) & ~0x01);
1131 dev_warn(info->device, "unknown Board\n");
1135 /* mode register: 256 color mode */
1136 vga_wgfx(regbase, VGA_GFX_MODE, 64);
1138 WHDR(cinfo, 0xc1); /* Copy Xbh */
1139 #elif defined(CONFIG_ZORRO)
1140 /* FIXME: CONFIG_PCI and CONFIG_ZORRO may be defined both */
1141 WHDR(cinfo, 0xa0); /* hidden dac reg: nothing special */
1145 /******************************************************
1151 else if (var->bits_per_pixel == 32) {
1152 dev_dbg(info->device, "preparing for 32 bit deep display\n");
1153 switch (cinfo->btype) {
1155 /* Extended Sequencer Mode: 256c col. mode */
1156 vga_wseq(regbase, CL_SEQR7, 0xf9);
1158 vga_wseq(regbase, CL_SEQR1F, 0x1e);
1163 vga_wseq(regbase, CL_SEQR7, 0x85);
1164 /* Fast Page-Mode writes */
1165 vga_wseq(regbase, CL_SEQRF, 0xb0);
1167 vga_wseq(regbase, CL_SEQR1F, 0x22);
1171 vga_wseq(regbase, CL_SEQR7, 0x25);
1172 /* Fast Page-Mode writes */
1173 vga_wseq(regbase, CL_SEQRF, 0xb0);
1175 vga_wseq(regbase, CL_SEQR1F, 0x22);
1179 vga_wseq(regbase, CL_SEQR7, 0x25);
1180 /* vga_wseq(regbase, CL_SEQR1F, 0x1c); */
1184 vga_wseq(regbase, CL_SEQR7, 0xa9);
1188 vga_wseq(regbase, CL_SEQR7, 0x19);
1189 /* We already set SRF and SR1F */
1194 vga_wseq(regbase, CL_SEQR7,
1195 vga_rseq(regbase, CL_SEQR7) & ~0x01);
1202 dev_warn(info->device, "unknown Board\n");
1206 /* mode register: 256 color mode */
1207 vga_wgfx(regbase, VGA_GFX_MODE, 64);
1208 /* hidden dac reg: 8-8-8 mode (24 or 32) */
1212 /******************************************************
1214 * unknown/unsupported bpp
1219 dev_err(info->device,
1220 "What's this? requested color depth == %d.\n",
1221 var->bits_per_pixel);
1223 pitch = info->fix.line_length >> 3;
1224 vga_wcrt(regbase, VGA_CRTC_OFFSET, pitch & 0xff);
1227 tmp |= 0x10; /* offset overflow bit */
1229 /* screen start addr #16-18, fastpagemode cycles */
1230 vga_wcrt(regbase, CL_CRT1B, tmp);
1232 /* screen start address bit 19 */
1233 if (cirrusfb_board_info[cinfo->btype].scrn_start_bit19)
1234 vga_wcrt(regbase, CL_CRT1D, (pitch >> 9) & 1);
1236 if (is_laguna(cinfo)) {
1238 if ((htotal + 5) & 256)
1242 if (hsyncstart & 256)
1246 if (vdispend & 1024)
1248 if (vsyncstart & 1024)
1251 vga_wcrt(regbase, CL_CRT1E, tmp);
1252 dev_dbg(info->device, "CRT1e: %d\n", tmp);
1256 vga_wattr(regbase, CL_AR33, 0);
1258 /* [ EGS: SetOffset(); ] */
1259 /* From SetOffset(): Turn on VideoEnable bit in Attribute controller */
1262 if (is_laguna(cinfo)) {
1264 fb_writew(control | 0x1000, cinfo->laguna_mmio + 0x402);
1265 fb_writew(format, cinfo->laguna_mmio + 0xc0);
1266 fb_writew(threshold, cinfo->laguna_mmio + 0xea);
1268 /* finally, turn on everything - turn off "FullBandwidth" bit */
1269 /* also, set "DotClock%2" bit where requested */
1272 /*** FB_VMODE_CLOCK_HALVE in linux/fb.h not defined anymore ?
1273 if (var->vmode & FB_VMODE_CLOCK_HALVE)
1277 vga_wseq(regbase, VGA_SEQ_CLOCK_MODE, tmp);
1278 dev_dbg(info->device, "CL_SEQR1: %d\n", tmp);
1280 #ifdef CIRRUSFB_DEBUG
1281 cirrusfb_dbg_reg_dump(info, NULL);
1287 /* for some reason incomprehensible to me, cirrusfb requires that you write
1288 * the registers twice for the settings to take..grr. -dte */
1289 static int cirrusfb_set_par(struct fb_info *info)
1291 cirrusfb_set_par_foo(info);
1292 return cirrusfb_set_par_foo(info);
1295 static int cirrusfb_setcolreg(unsigned regno, unsigned red, unsigned green,
1296 unsigned blue, unsigned transp,
1297 struct fb_info *info)
1299 struct cirrusfb_info *cinfo = info->par;
1304 if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
1306 red >>= (16 - info->var.red.length);
1307 green >>= (16 - info->var.green.length);
1308 blue >>= (16 - info->var.blue.length);
1312 v = (red << info->var.red.offset) |
1313 (green << info->var.green.offset) |
1314 (blue << info->var.blue.offset);
1316 cinfo->pseudo_palette[regno] = v;
1320 if (info->var.bits_per_pixel == 8)
1321 WClut(cinfo, regno, red >> 10, green >> 10, blue >> 10);
1327 /*************************************************************************
1328 cirrusfb_pan_display()
1330 performs display panning - provided hardware permits this
1331 **************************************************************************/
1332 static int cirrusfb_pan_display(struct fb_var_screeninfo *var,
1333 struct fb_info *info)
1337 unsigned char tmp, xpix;
1338 struct cirrusfb_info *cinfo = info->par;
1340 dev_dbg(info->device,
1341 "virtual offset: (%d,%d)\n", var->xoffset, var->yoffset);
1343 /* no range checks for xoffset and yoffset, */
1344 /* as fb_pan_display has already done this */
1345 if (var->vmode & FB_VMODE_YWRAP)
1348 xoffset = var->xoffset * info->var.bits_per_pixel / 8;
1350 base = var->yoffset * info->fix.line_length + xoffset;
1352 if (info->var.bits_per_pixel == 1) {
1353 /* base is already correct */
1354 xpix = (unsigned char) (var->xoffset % 8);
1357 xpix = (unsigned char) ((xoffset % 4) * 2);
1360 if (!is_laguna(cinfo))
1361 cirrusfb_WaitBLT(cinfo->regbase);
1363 /* lower 8 + 8 bits of screen start address */
1364 vga_wcrt(cinfo->regbase, VGA_CRTC_START_LO, base & 0xff);
1365 vga_wcrt(cinfo->regbase, VGA_CRTC_START_HI, (base >> 8) & 0xff);
1367 /* 0xf2 is %11110010, exclude tmp bits */
1368 tmp = vga_rcrt(cinfo->regbase, CL_CRT1B) & 0xf2;
1369 /* construct bits 16, 17 and 18 of screen start address */
1377 vga_wcrt(cinfo->regbase, CL_CRT1B, tmp);
1379 /* construct bit 19 of screen start address */
1380 if (cirrusfb_board_info[cinfo->btype].scrn_start_bit19) {
1381 tmp = vga_rcrt(cinfo->regbase, CL_CRT1D);
1382 if (is_laguna(cinfo))
1383 tmp = (tmp & ~0x18) | ((base >> 16) & 0x18);
1385 tmp = (tmp & ~0x80) | ((base >> 12) & 0x80);
1386 vga_wcrt(cinfo->regbase, CL_CRT1D, tmp);
1389 /* write pixel panning value to AR33; this does not quite work in 8bpp
1391 * ### Piccolo..? Will this work?
1393 if (info->var.bits_per_pixel == 1)
1394 vga_wattr(cinfo->regbase, CL_AR33, xpix);
1396 if (!is_laguna(cinfo))
1397 cirrusfb_WaitBLT(cinfo->regbase);
1402 static int cirrusfb_blank(int blank_mode, struct fb_info *info)
1405 * Blank the screen if blank_mode != 0, else unblank. If blank == NULL
1406 * then the caller blanks by setting the CLUT (Color Look Up Table)
1407 * to all black. Return 0 if blanking succeeded, != 0 if un-/blanking
1408 * failed due to e.g. a video mode which doesn't support it.
1409 * Implements VESA suspend and powerdown modes on hardware that
1410 * supports disabling hsync/vsync:
1411 * blank_mode == 2: suspend vsync
1412 * blank_mode == 3: suspend hsync
1413 * blank_mode == 4: powerdown
1416 struct cirrusfb_info *cinfo = info->par;
1417 int current_mode = cinfo->blank_mode;
1419 dev_dbg(info->device, "ENTER, blank mode = %d\n", blank_mode);
1421 if (info->state != FBINFO_STATE_RUNNING ||
1422 current_mode == blank_mode) {
1423 dev_dbg(info->device, "EXIT, returning 0\n");
1428 if (current_mode == FB_BLANK_NORMAL ||
1429 current_mode == FB_BLANK_UNBLANK)
1430 /* clear "FullBandwidth" bit */
1433 /* set "FullBandwidth" bit */
1436 val |= vga_rseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE) & 0xdf;
1437 vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, val);
1439 switch (blank_mode) {
1440 case FB_BLANK_UNBLANK:
1441 case FB_BLANK_NORMAL:
1444 case FB_BLANK_VSYNC_SUSPEND:
1447 case FB_BLANK_HSYNC_SUSPEND:
1450 case FB_BLANK_POWERDOWN:
1454 dev_dbg(info->device, "EXIT, returning 1\n");
1458 vga_wgfx(cinfo->regbase, CL_GRE, val);
1460 cinfo->blank_mode = blank_mode;
1461 dev_dbg(info->device, "EXIT, returning 0\n");
1463 /* Let fbcon do a soft blank for us */
1464 return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
1467 /**** END Hardware specific Routines **************************************/
1468 /****************************************************************************/
1469 /**** BEGIN Internal Routines ***********************************************/
1471 static void init_vgachip(struct fb_info *info)
1473 struct cirrusfb_info *cinfo = info->par;
1474 const struct cirrusfb_board_info_rec *bi;
1476 assert(cinfo != NULL);
1478 bi = &cirrusfb_board_info[cinfo->btype];
1480 /* reset board globally */
1481 switch (cinfo->btype) {
1500 /* disable flickerfixer */
1501 vga_wcrt(cinfo->regbase, CL_CRT51, 0x00);
1503 /* from Klaus' NetBSD driver: */
1504 vga_wgfx(cinfo->regbase, CL_GR2F, 0x00);
1505 /* put blitter into 542x compat */
1506 vga_wgfx(cinfo->regbase, CL_GR33, 0x00);
1508 vga_wgfx(cinfo->regbase, CL_GR31, 0x00);
1512 /* from Klaus' NetBSD driver: */
1513 vga_wgfx(cinfo->regbase, CL_GR2F, 0x00);
1519 /* Nothing to do to reset the board. */
1523 dev_err(info->device, "Warning: Unknown board type\n");
1527 /* make sure RAM size set by this point */
1528 assert(info->screen_size > 0);
1530 /* the P4 is not fully initialized here; I rely on it having been */
1531 /* inited under AmigaOS already, which seems to work just fine */
1532 /* (Klaus advised to do it this way) */
1534 if (cinfo->btype != BT_PICASSO4) {
1535 WGen(cinfo, CL_VSSM, 0x10); /* EGS: 0x16 */
1536 WGen(cinfo, CL_POS102, 0x01);
1537 WGen(cinfo, CL_VSSM, 0x08); /* EGS: 0x0e */
1539 if (cinfo->btype != BT_SD64)
1540 WGen(cinfo, CL_VSSM2, 0x01);
1542 /* reset sequencer logic */
1543 vga_wseq(cinfo->regbase, VGA_SEQ_RESET, 0x03);
1545 /* FullBandwidth (video off) and 8/9 dot clock */
1546 vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, 0x21);
1548 /* "magic cookie" - doesn't make any sense to me.. */
1549 /* vga_wgfx(cinfo->regbase, CL_GRA, 0xce); */
1550 /* unlock all extension registers */
1551 vga_wseq(cinfo->regbase, CL_SEQR6, 0x12);
1554 vga_wgfx(cinfo->regbase, CL_GR31, 0x04);
1556 switch (cinfo->btype) {
1558 vga_wseq(cinfo->regbase, CL_SEQRF, 0x98);
1565 vga_wseq(cinfo->regbase, CL_SEQRF, 0xb8);
1568 vga_wseq(cinfo->regbase, CL_SEQR16, 0x0f);
1569 vga_wseq(cinfo->regbase, CL_SEQRF, 0xb0);
1573 /* plane mask: nothing */
1574 vga_wseq(cinfo->regbase, VGA_SEQ_PLANE_WRITE, 0xff);
1575 /* character map select: doesn't even matter in gx mode */
1576 vga_wseq(cinfo->regbase, VGA_SEQ_CHARACTER_MAP, 0x00);
1577 /* memory mode: chain4, ext. memory */
1578 vga_wseq(cinfo->regbase, VGA_SEQ_MEMORY_MODE, 0x0a);
1580 /* controller-internal base address of video memory */
1582 vga_wseq(cinfo->regbase, CL_SEQR7, bi->sr07);
1584 /* vga_wseq(cinfo->regbase, CL_SEQR8, 0x00); */
1585 /* EEPROM control: shouldn't be necessary to write to this at all.. */
1587 /* graphics cursor X position (incomplete; position gives rem. 3 bits */
1588 vga_wseq(cinfo->regbase, CL_SEQR10, 0x00);
1589 /* graphics cursor Y position (..."... ) */
1590 vga_wseq(cinfo->regbase, CL_SEQR11, 0x00);
1591 /* graphics cursor attributes */
1592 vga_wseq(cinfo->regbase, CL_SEQR12, 0x00);
1593 /* graphics cursor pattern address */
1594 vga_wseq(cinfo->regbase, CL_SEQR13, 0x00);
1596 /* writing these on a P4 might give problems.. */
1597 if (cinfo->btype != BT_PICASSO4) {
1598 /* configuration readback and ext. color */
1599 vga_wseq(cinfo->regbase, CL_SEQR17, 0x00);
1600 /* signature generator */
1601 vga_wseq(cinfo->regbase, CL_SEQR18, 0x02);
1604 /* MCLK select etc. */
1606 vga_wseq(cinfo->regbase, CL_SEQR1F, bi->sr1f);
1608 /* Screen A preset row scan: none */
1609 vga_wcrt(cinfo->regbase, VGA_CRTC_PRESET_ROW, 0x00);
1610 /* Text cursor start: disable text cursor */
1611 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_START, 0x20);
1612 /* Text cursor end: - */
1613 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_END, 0x00);
1614 /* text cursor location high: 0 */
1615 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_HI, 0x00);
1616 /* text cursor location low: 0 */
1617 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_LO, 0x00);
1619 /* Underline Row scanline: - */
1620 vga_wcrt(cinfo->regbase, VGA_CRTC_UNDERLINE, 0x00);
1621 /* ### add 0x40 for text modes with > 30 MHz pixclock */
1622 /* ext. display controls: ext.adr. wrap */
1623 vga_wcrt(cinfo->regbase, CL_CRT1B, 0x02);
1625 /* Set/Reset registes: - */
1626 vga_wgfx(cinfo->regbase, VGA_GFX_SR_VALUE, 0x00);
1627 /* Set/Reset enable: - */
1628 vga_wgfx(cinfo->regbase, VGA_GFX_SR_ENABLE, 0x00);
1629 /* Color Compare: - */
1630 vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_VALUE, 0x00);
1631 /* Data Rotate: - */
1632 vga_wgfx(cinfo->regbase, VGA_GFX_DATA_ROTATE, 0x00);
1633 /* Read Map Select: - */
1634 vga_wgfx(cinfo->regbase, VGA_GFX_PLANE_READ, 0x00);
1635 /* Mode: conf. for 16/4/2 color mode, no odd/even, read/write mode 0 */
1636 vga_wgfx(cinfo->regbase, VGA_GFX_MODE, 0x00);
1637 /* Miscellaneous: memory map base address, graphics mode */
1638 vga_wgfx(cinfo->regbase, VGA_GFX_MISC, 0x01);
1639 /* Color Don't care: involve all planes */
1640 vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_MASK, 0x0f);
1641 /* Bit Mask: no mask at all */
1642 vga_wgfx(cinfo->regbase, VGA_GFX_BIT_MASK, 0xff);
1644 if (cinfo->btype == BT_ALPINE || is_laguna(cinfo))
1645 /* (5434 can't have bit 3 set for bitblt) */
1646 vga_wgfx(cinfo->regbase, CL_GRB, 0x20);
1648 /* Graphics controller mode extensions: finer granularity,
1649 * 8byte data latches
1651 vga_wgfx(cinfo->regbase, CL_GRB, 0x28);
1653 vga_wgfx(cinfo->regbase, CL_GRC, 0xff); /* Color Key compare: - */
1654 vga_wgfx(cinfo->regbase, CL_GRD, 0x00); /* Color Key compare mask: - */
1655 vga_wgfx(cinfo->regbase, CL_GRE, 0x00); /* Miscellaneous control: - */
1656 /* Background color byte 1: - */
1657 /* vga_wgfx (cinfo->regbase, CL_GR10, 0x00); */
1658 /* vga_wgfx (cinfo->regbase, CL_GR11, 0x00); */
1660 /* Attribute Controller palette registers: "identity mapping" */
1661 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE0, 0x00);
1662 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE1, 0x01);
1663 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE2, 0x02);
1664 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE3, 0x03);
1665 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE4, 0x04);
1666 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE5, 0x05);
1667 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE6, 0x06);
1668 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE7, 0x07);
1669 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE8, 0x08);
1670 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE9, 0x09);
1671 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEA, 0x0a);
1672 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEB, 0x0b);
1673 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEC, 0x0c);
1674 vga_wattr(cinfo->regbase, VGA_ATC_PALETTED, 0x0d);
1675 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEE, 0x0e);
1676 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEF, 0x0f);
1678 /* Attribute Controller mode: graphics mode */
1679 vga_wattr(cinfo->regbase, VGA_ATC_MODE, 0x01);
1680 /* Overscan color reg.: reg. 0 */
1681 vga_wattr(cinfo->regbase, VGA_ATC_OVERSCAN, 0x00);
1682 /* Color Plane enable: Enable all 4 planes */
1683 vga_wattr(cinfo->regbase, VGA_ATC_PLANE_ENABLE, 0x0f);
1684 /* Color Select: - */
1685 vga_wattr(cinfo->regbase, VGA_ATC_COLOR_PAGE, 0x00);
1687 WGen(cinfo, VGA_PEL_MSK, 0xff); /* Pixel mask: no mask */
1689 /* BLT Start/status: Blitter reset */
1690 vga_wgfx(cinfo->regbase, CL_GR31, 0x04);
1691 /* - " - : "end-of-reset" */
1692 vga_wgfx(cinfo->regbase, CL_GR31, 0x00);
1695 WHDR(cinfo, 0); /* Hidden DAC register: - */
1699 static void switch_monitor(struct cirrusfb_info *cinfo, int on)
1701 #ifdef CONFIG_ZORRO /* only works on Zorro boards */
1702 static int IsOn = 0; /* XXX not ok for multiple boards */
1704 if (cinfo->btype == BT_PICASSO4)
1705 return; /* nothing to switch */
1706 if (cinfo->btype == BT_ALPINE)
1707 return; /* nothing to switch */
1708 if (cinfo->btype == BT_GD5480)
1709 return; /* nothing to switch */
1710 if (cinfo->btype == BT_PICASSO) {
1711 if ((on && !IsOn) || (!on && IsOn))
1716 switch (cinfo->btype) {
1718 WSFR(cinfo, cinfo->SFR | 0x21);
1721 WSFR(cinfo, cinfo->SFR | 0x28);
1726 default: /* do nothing */ break;
1729 switch (cinfo->btype) {
1731 WSFR(cinfo, cinfo->SFR & 0xde);
1734 WSFR(cinfo, cinfo->SFR & 0xd7);
1739 default: /* do nothing */
1743 #endif /* CONFIG_ZORRO */
1746 /******************************************/
1747 /* Linux 2.6-style accelerated functions */
1748 /******************************************/
1750 static void cirrusfb_fillrect(struct fb_info *info,
1751 const struct fb_fillrect *region)
1753 struct fb_fillrect modded;
1755 struct cirrusfb_info *cinfo = info->par;
1756 int m = info->var.bits_per_pixel;
1757 u32 color = (info->fix.visual == FB_VISUAL_TRUECOLOR) ?
1758 cinfo->pseudo_palette[region->color] : region->color;
1760 if (info->state != FBINFO_STATE_RUNNING)
1762 if (info->flags & FBINFO_HWACCEL_DISABLED) {
1763 cfb_fillrect(info, region);
1767 vxres = info->var.xres_virtual;
1768 vyres = info->var.yres_virtual;
1770 memcpy(&modded, region, sizeof(struct fb_fillrect));
1772 if (!modded.width || !modded.height ||
1773 modded.dx >= vxres || modded.dy >= vyres)
1776 if (modded.dx + modded.width > vxres)
1777 modded.width = vxres - modded.dx;
1778 if (modded.dy + modded.height > vyres)
1779 modded.height = vyres - modded.dy;
1781 cirrusfb_RectFill(cinfo->regbase,
1782 info->var.bits_per_pixel,
1783 (region->dx * m) / 8, region->dy,
1784 (region->width * m) / 8, region->height,
1786 info->fix.line_length);
1789 static void cirrusfb_copyarea(struct fb_info *info,
1790 const struct fb_copyarea *area)
1792 struct fb_copyarea modded;
1794 struct cirrusfb_info *cinfo = info->par;
1795 int m = info->var.bits_per_pixel;
1797 if (info->state != FBINFO_STATE_RUNNING)
1799 if (info->flags & FBINFO_HWACCEL_DISABLED) {
1800 cfb_copyarea(info, area);
1804 vxres = info->var.xres_virtual;
1805 vyres = info->var.yres_virtual;
1806 memcpy(&modded, area, sizeof(struct fb_copyarea));
1808 if (!modded.width || !modded.height ||
1809 modded.sx >= vxres || modded.sy >= vyres ||
1810 modded.dx >= vxres || modded.dy >= vyres)
1813 if (modded.sx + modded.width > vxres)
1814 modded.width = vxres - modded.sx;
1815 if (modded.dx + modded.width > vxres)
1816 modded.width = vxres - modded.dx;
1817 if (modded.sy + modded.height > vyres)
1818 modded.height = vyres - modded.sy;
1819 if (modded.dy + modded.height > vyres)
1820 modded.height = vyres - modded.dy;
1822 cirrusfb_BitBLT(cinfo->regbase, info->var.bits_per_pixel,
1823 (area->sx * m) / 8, area->sy,
1824 (area->dx * m) / 8, area->dy,
1825 (area->width * m) / 8, area->height,
1826 info->fix.line_length);
1830 static void cirrusfb_imageblit(struct fb_info *info,
1831 const struct fb_image *image)
1833 struct cirrusfb_info *cinfo = info->par;
1835 if (!is_laguna(cinfo))
1836 cirrusfb_WaitBLT(cinfo->regbase);
1837 cfb_imageblit(info, image);
1840 #ifdef CONFIG_PPC_PREP
1841 #define PREP_VIDEO_BASE ((volatile unsigned long) 0xC0000000)
1842 #define PREP_IO_BASE ((volatile unsigned char *) 0x80000000)
1843 static void get_prep_addrs(unsigned long *display, unsigned long *registers)
1845 *display = PREP_VIDEO_BASE;
1846 *registers = (unsigned long) PREP_IO_BASE;
1849 #endif /* CONFIG_PPC_PREP */
1852 static int release_io_ports;
1854 /* Pulled the logic from XFree86 Cirrus driver to get the memory size,
1855 * based on the DRAM bandwidth bit and DRAM bank switching bit. This
1856 * works with 1MB, 2MB and 4MB configurations (which the Motorola boards
1858 static unsigned int __devinit cirrusfb_get_memsize(struct fb_info *info,
1859 u8 __iomem *regbase)
1862 struct cirrusfb_info *cinfo = info->par;
1864 if (is_laguna(cinfo)) {
1865 unsigned char SR14 = vga_rseq(regbase, CL_SEQR14);
1867 mem = ((SR14 & 7) + 1) << 20;
1869 unsigned char SRF = vga_rseq(regbase, CL_SEQRF);
1870 switch ((SRF & 0x18)) {
1877 /* 64-bit DRAM data bus width; assume 2MB.
1878 * Also indicates 2MB memory on the 5430.
1884 dev_warn(info->device, "Unknown memory size!\n");
1887 /* If DRAM bank switching is enabled, there must be
1888 * twice as much memory installed. (4MB on the 5434)
1894 /* TODO: Handling of GD5446/5480 (see XF86 sources ...) */
1898 static void get_pci_addrs(const struct pci_dev *pdev,
1899 unsigned long *display, unsigned long *registers)
1901 assert(pdev != NULL);
1902 assert(display != NULL);
1903 assert(registers != NULL);
1908 /* This is a best-guess for now */
1910 if (pci_resource_flags(pdev, 0) & IORESOURCE_IO) {
1911 *display = pci_resource_start(pdev, 1);
1912 *registers = pci_resource_start(pdev, 0);
1914 *display = pci_resource_start(pdev, 0);
1915 *registers = pci_resource_start(pdev, 1);
1918 assert(*display != 0);
1921 static void cirrusfb_pci_unmap(struct fb_info *info)
1923 struct pci_dev *pdev = to_pci_dev(info->device);
1924 struct cirrusfb_info *cinfo = info->par;
1926 if (cinfo->laguna_mmio == NULL)
1927 iounmap(cinfo->laguna_mmio);
1928 iounmap(info->screen_base);
1929 #if 0 /* if system didn't claim this region, we would... */
1930 release_mem_region(0xA0000, 65535);
1932 if (release_io_ports)
1933 release_region(0x3C0, 32);
1934 pci_release_regions(pdev);
1936 #endif /* CONFIG_PCI */
1939 static void cirrusfb_zorro_unmap(struct fb_info *info)
1941 struct cirrusfb_info *cinfo = info->par;
1942 struct zorro_dev *zdev = to_zorro_dev(info->device);
1944 zorro_release_device(zdev);
1946 if (cinfo->btype == BT_PICASSO4) {
1947 cinfo->regbase -= 0x600000;
1948 iounmap((void *)cinfo->regbase);
1949 iounmap(info->screen_base);
1951 if (zorro_resource_start(zdev) > 0x01000000)
1952 iounmap(info->screen_base);
1955 #endif /* CONFIG_ZORRO */
1957 /* function table of the above functions */
1958 static struct fb_ops cirrusfb_ops = {
1959 .owner = THIS_MODULE,
1960 .fb_open = cirrusfb_open,
1961 .fb_release = cirrusfb_release,
1962 .fb_setcolreg = cirrusfb_setcolreg,
1963 .fb_check_var = cirrusfb_check_var,
1964 .fb_set_par = cirrusfb_set_par,
1965 .fb_pan_display = cirrusfb_pan_display,
1966 .fb_blank = cirrusfb_blank,
1967 .fb_fillrect = cirrusfb_fillrect,
1968 .fb_copyarea = cirrusfb_copyarea,
1969 .fb_imageblit = cirrusfb_imageblit,
1972 static int __devinit cirrusfb_set_fbinfo(struct fb_info *info)
1974 struct cirrusfb_info *cinfo = info->par;
1975 struct fb_var_screeninfo *var = &info->var;
1977 info->pseudo_palette = cinfo->pseudo_palette;
1978 info->flags = FBINFO_DEFAULT
1979 | FBINFO_HWACCEL_XPAN
1980 | FBINFO_HWACCEL_YPAN
1981 | FBINFO_HWACCEL_FILLRECT
1982 | FBINFO_HWACCEL_COPYAREA;
1983 if (noaccel || is_laguna(cinfo))
1984 info->flags |= FBINFO_HWACCEL_DISABLED;
1985 info->fbops = &cirrusfb_ops;
1986 if (cinfo->btype == BT_GD5480) {
1987 if (var->bits_per_pixel == 16)
1988 info->screen_base += 1 * MB_;
1989 if (var->bits_per_pixel == 32)
1990 info->screen_base += 2 * MB_;
1993 /* Fill fix common fields */
1994 strlcpy(info->fix.id, cirrusfb_board_info[cinfo->btype].name,
1995 sizeof(info->fix.id));
1997 /* monochrome: only 1 memory plane */
1998 /* 8 bit and above: Use whole memory area */
1999 info->fix.smem_len = info->screen_size;
2000 if (var->bits_per_pixel == 1)
2001 info->fix.smem_len /= 4;
2002 info->fix.type_aux = 0;
2003 info->fix.xpanstep = 1;
2004 info->fix.ypanstep = 1;
2005 info->fix.ywrapstep = 0;
2007 /* FIXME: map region at 0xB8000 if available, fill in here */
2008 info->fix.mmio_len = 0;
2009 info->fix.accel = FB_ACCEL_NONE;
2011 fb_alloc_cmap(&info->cmap, 256, 0);
2016 static int __devinit cirrusfb_register(struct fb_info *info)
2018 struct cirrusfb_info *cinfo = info->par;
2022 assert(cinfo->btype != BT_NONE);
2024 /* set all the vital stuff */
2025 cirrusfb_set_fbinfo(info);
2027 dev_dbg(info->device, "(RAM start set to: 0x%p)\n", info->screen_base);
2029 err = fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 8);
2031 dev_dbg(info->device, "wrong initial video mode\n");
2033 goto err_dealloc_cmap;
2036 info->var.activate = FB_ACTIVATE_NOW;
2038 err = cirrusfb_check_var(&info->var, info);
2040 /* should never happen */
2041 dev_dbg(info->device,
2042 "choking on default var... umm, no good.\n");
2043 goto err_dealloc_cmap;
2046 err = register_framebuffer(info);
2048 dev_err(info->device,
2049 "could not register fb device; err = %d!\n", err);
2050 goto err_dealloc_cmap;
2056 fb_dealloc_cmap(&info->cmap);
2058 framebuffer_release(info);
2062 static void __devexit cirrusfb_cleanup(struct fb_info *info)
2064 struct cirrusfb_info *cinfo = info->par;
2066 switch_monitor(cinfo, 0);
2067 unregister_framebuffer(info);
2068 fb_dealloc_cmap(&info->cmap);
2069 dev_dbg(info->device, "Framebuffer unregistered\n");
2071 framebuffer_release(info);
2075 static int __devinit cirrusfb_pci_register(struct pci_dev *pdev,
2076 const struct pci_device_id *ent)
2078 struct cirrusfb_info *cinfo;
2079 struct fb_info *info;
2080 unsigned long board_addr, board_size;
2083 ret = pci_enable_device(pdev);
2085 printk(KERN_ERR "cirrusfb: Cannot enable PCI device\n");
2089 info = framebuffer_alloc(sizeof(struct cirrusfb_info), &pdev->dev);
2091 printk(KERN_ERR "cirrusfb: could not allocate memory\n");
2097 cinfo->btype = (enum cirrus_board) ent->driver_data;
2099 dev_dbg(info->device,
2100 " Found PCI device, base address 0 is 0x%Lx, btype set to %d\n",
2101 (unsigned long long)pdev->resource[0].start, cinfo->btype);
2102 dev_dbg(info->device, " base address 1 is 0x%Lx\n",
2103 (unsigned long long)pdev->resource[1].start);
2106 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, 0x00000000);
2107 #ifdef CONFIG_PPC_PREP
2108 get_prep_addrs(&board_addr, &info->fix.mmio_start);
2110 /* PReP dies if we ioremap the IO registers, but it works w/out... */
2111 cinfo->regbase = (char __iomem *) info->fix.mmio_start;
2113 dev_dbg(info->device,
2114 "Attempt to get PCI info for Cirrus Graphics Card\n");
2115 get_pci_addrs(pdev, &board_addr, &info->fix.mmio_start);
2116 /* FIXME: this forces VGA. alternatives? */
2117 cinfo->regbase = NULL;
2118 cinfo->laguna_mmio = ioremap(info->fix.mmio_start, 0x1000);
2121 dev_dbg(info->device, "Board address: 0x%lx, register address: 0x%lx\n",
2122 board_addr, info->fix.mmio_start);
2124 board_size = (cinfo->btype == BT_GD5480) ?
2125 32 * MB_ : cirrusfb_get_memsize(info, cinfo->regbase);
2127 ret = pci_request_regions(pdev, "cirrusfb");
2129 dev_err(info->device, "cannot reserve region 0x%lx, abort\n",
2131 goto err_release_fb;
2133 #if 0 /* if the system didn't claim this region, we would... */
2134 if (!request_mem_region(0xA0000, 65535, "cirrusfb")) {
2135 dev_err(info->device, "cannot reserve region 0x%lx, abort\n",
2138 goto err_release_regions;
2141 if (request_region(0x3C0, 32, "cirrusfb"))
2142 release_io_ports = 1;
2144 info->screen_base = ioremap(board_addr, board_size);
2145 if (!info->screen_base) {
2147 goto err_release_legacy;
2150 info->fix.smem_start = board_addr;
2151 info->screen_size = board_size;
2152 cinfo->unmap = cirrusfb_pci_unmap;
2154 dev_info(info->device,
2155 "Cirrus Logic chipset on PCI bus, RAM (%lu kB) at 0x%lx\n",
2156 info->screen_size >> 10, board_addr);
2157 pci_set_drvdata(pdev, info);
2159 ret = cirrusfb_register(info);
2163 pci_set_drvdata(pdev, NULL);
2164 iounmap(info->screen_base);
2166 if (release_io_ports)
2167 release_region(0x3C0, 32);
2169 release_mem_region(0xA0000, 65535);
2170 err_release_regions:
2172 pci_release_regions(pdev);
2174 if (cinfo->laguna_mmio != NULL)
2175 iounmap(cinfo->laguna_mmio);
2176 framebuffer_release(info);
2181 static void __devexit cirrusfb_pci_unregister(struct pci_dev *pdev)
2183 struct fb_info *info = pci_get_drvdata(pdev);
2185 cirrusfb_cleanup(info);
2188 static struct pci_driver cirrusfb_pci_driver = {
2190 .id_table = cirrusfb_pci_table,
2191 .probe = cirrusfb_pci_register,
2192 .remove = __devexit_p(cirrusfb_pci_unregister),
2195 .suspend = cirrusfb_pci_suspend,
2196 .resume = cirrusfb_pci_resume,
2200 #endif /* CONFIG_PCI */
2203 static int __devinit cirrusfb_zorro_register(struct zorro_dev *z,
2204 const struct zorro_device_id *ent)
2206 struct cirrusfb_info *cinfo;
2207 struct fb_info *info;
2208 enum cirrus_board btype;
2209 struct zorro_dev *z2 = NULL;
2210 unsigned long board_addr, board_size, size;
2213 btype = ent->driver_data;
2214 if (cirrusfb_zorro_table2[btype].id2)
2215 z2 = zorro_find_device(cirrusfb_zorro_table2[btype].id2, NULL);
2216 size = cirrusfb_zorro_table2[btype].size;
2218 info = framebuffer_alloc(sizeof(struct cirrusfb_info), &z->dev);
2220 printk(KERN_ERR "cirrusfb: could not allocate memory\n");
2225 dev_info(info->device, "%s board detected\n",
2226 cirrusfb_board_info[btype].name);
2229 cinfo->btype = btype;
2232 assert(btype != BT_NONE);
2234 board_addr = zorro_resource_start(z);
2235 board_size = zorro_resource_len(z);
2236 info->screen_size = size;
2238 if (!zorro_request_device(z, "cirrusfb")) {
2239 dev_err(info->device, "cannot reserve region 0x%lx, abort\n",
2242 goto err_release_fb;
2247 if (btype == BT_PICASSO4) {
2248 dev_info(info->device, " REG at $%lx\n", board_addr + 0x600000);
2250 /* To be precise, for the P4 this is not the */
2251 /* begin of the board, but the begin of RAM. */
2252 /* for P4, map in its address space in 2 chunks (### TEST! ) */
2253 /* (note the ugly hardcoded 16M number) */
2254 cinfo->regbase = ioremap(board_addr, 16777216);
2255 if (!cinfo->regbase)
2256 goto err_release_region;
2258 dev_dbg(info->device, "Virtual address for board set to: $%p\n",
2260 cinfo->regbase += 0x600000;
2261 info->fix.mmio_start = board_addr + 0x600000;
2263 info->fix.smem_start = board_addr + 16777216;
2264 info->screen_base = ioremap(info->fix.smem_start, 16777216);
2265 if (!info->screen_base)
2266 goto err_unmap_regbase;
2268 dev_info(info->device, " REG at $%lx\n",
2269 (unsigned long) z2->resource.start);
2271 info->fix.smem_start = board_addr;
2272 if (board_addr > 0x01000000)
2273 info->screen_base = ioremap(board_addr, board_size);
2275 info->screen_base = (caddr_t) ZTWO_VADDR(board_addr);
2276 if (!info->screen_base)
2277 goto err_release_region;
2279 /* set address for REG area of board */
2280 cinfo->regbase = (caddr_t) ZTWO_VADDR(z2->resource.start);
2281 info->fix.mmio_start = z2->resource.start;
2283 dev_dbg(info->device, "Virtual address for board set to: $%p\n",
2286 cinfo->unmap = cirrusfb_zorro_unmap;
2288 dev_info(info->device,
2289 "Cirrus Logic chipset on Zorro bus, RAM (%lu MB) at $%lx\n",
2290 board_size / MB_, board_addr);
2292 zorro_set_drvdata(z, info);
2294 ret = cirrusfb_register(info);
2296 if (btype == BT_PICASSO4) {
2297 iounmap(info->screen_base);
2298 iounmap(cinfo->regbase - 0x600000);
2299 } else if (board_addr > 0x01000000)
2300 iounmap(info->screen_base);
2305 /* Parental advisory: explicit hack */
2306 iounmap(cinfo->regbase - 0x600000);
2308 release_region(board_addr, board_size);
2310 framebuffer_release(info);
2315 void __devexit cirrusfb_zorro_unregister(struct zorro_dev *z)
2317 struct fb_info *info = zorro_get_drvdata(z);
2319 cirrusfb_cleanup(info);
2322 static struct zorro_driver cirrusfb_zorro_driver = {
2324 .id_table = cirrusfb_zorro_table,
2325 .probe = cirrusfb_zorro_register,
2326 .remove = __devexit_p(cirrusfb_zorro_unregister),
2328 #endif /* CONFIG_ZORRO */
2331 static int __init cirrusfb_setup(char *options)
2335 if (!options || !*options)
2338 while ((this_opt = strsep(&options, ",")) != NULL) {
2342 if (!strcmp(this_opt, "noaccel"))
2344 else if (!strncmp(this_opt, "mode:", 5))
2345 mode_option = this_opt + 5;
2347 mode_option = this_opt;
2357 MODULE_AUTHOR("Copyright 1999,2000 Jeff Garzik <jgarzik@pobox.com>");
2358 MODULE_DESCRIPTION("Accelerated FBDev driver for Cirrus Logic chips");
2359 MODULE_LICENSE("GPL");
2361 static int __init cirrusfb_init(void)
2366 char *option = NULL;
2368 if (fb_get_options("cirrusfb", &option))
2370 cirrusfb_setup(option);
2374 error |= zorro_register_driver(&cirrusfb_zorro_driver);
2377 error |= pci_register_driver(&cirrusfb_pci_driver);
2382 static void __exit cirrusfb_exit(void)
2385 pci_unregister_driver(&cirrusfb_pci_driver);
2388 zorro_unregister_driver(&cirrusfb_zorro_driver);
2392 module_init(cirrusfb_init);
2394 module_param(mode_option, charp, 0);
2395 MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'");
2396 module_param(noaccel, bool, 0);
2397 MODULE_PARM_DESC(noaccel, "Disable acceleration");
2400 module_exit(cirrusfb_exit);
2403 /**********************************************************************/
2404 /* about the following functions - I have used the same names for the */
2405 /* functions as Markus Wild did in his Retina driver for NetBSD as */
2406 /* they just made sense for this purpose. Apart from that, I wrote */
2407 /* these functions myself. */
2408 /**********************************************************************/
2410 /*** WGen() - write into one of the external/general registers ***/
2411 static void WGen(const struct cirrusfb_info *cinfo,
2412 int regnum, unsigned char val)
2414 unsigned long regofs = 0;
2416 if (cinfo->btype == BT_PICASSO) {
2417 /* Picasso II specific hack */
2418 /* if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D ||
2419 regnum == CL_VSSM2) */
2420 if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D)
2424 vga_w(cinfo->regbase, regofs + regnum, val);
2427 /*** RGen() - read out one of the external/general registers ***/
2428 static unsigned char RGen(const struct cirrusfb_info *cinfo, int regnum)
2430 unsigned long regofs = 0;
2432 if (cinfo->btype == BT_PICASSO) {
2433 /* Picasso II specific hack */
2434 /* if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D ||
2435 regnum == CL_VSSM2) */
2436 if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D)
2440 return vga_r(cinfo->regbase, regofs + regnum);
2443 /*** AttrOn() - turn on VideoEnable for Attribute controller ***/
2444 static void AttrOn(const struct cirrusfb_info *cinfo)
2446 assert(cinfo != NULL);
2448 if (vga_rcrt(cinfo->regbase, CL_CRT24) & 0x80) {
2449 /* if we're just in "write value" mode, write back the */
2450 /* same value as before to not modify anything */
2451 vga_w(cinfo->regbase, VGA_ATT_IW,
2452 vga_r(cinfo->regbase, VGA_ATT_R));
2454 /* turn on video bit */
2455 /* vga_w(cinfo->regbase, VGA_ATT_IW, 0x20); */
2456 vga_w(cinfo->regbase, VGA_ATT_IW, 0x33);
2458 /* dummy write on Reg0 to be on "write index" mode next time */
2459 vga_w(cinfo->regbase, VGA_ATT_IW, 0x00);
2462 /*** WHDR() - write into the Hidden DAC register ***/
2463 /* as the HDR is the only extension register that requires special treatment
2464 * (the other extension registers are accessible just like the "ordinary"
2465 * registers of their functional group) here is a specialized routine for
2468 static void WHDR(const struct cirrusfb_info *cinfo, unsigned char val)
2470 unsigned char dummy;
2472 if (is_laguna(cinfo))
2474 if (cinfo->btype == BT_PICASSO) {
2475 /* Klaus' hint for correct access to HDR on some boards */
2476 /* first write 0 to pixel mask (3c6) */
2477 WGen(cinfo, VGA_PEL_MSK, 0x00);
2479 /* next read dummy from pixel address (3c8) */
2480 dummy = RGen(cinfo, VGA_PEL_IW);
2483 /* now do the usual stuff to access the HDR */
2485 dummy = RGen(cinfo, VGA_PEL_MSK);
2487 dummy = RGen(cinfo, VGA_PEL_MSK);
2489 dummy = RGen(cinfo, VGA_PEL_MSK);
2491 dummy = RGen(cinfo, VGA_PEL_MSK);
2494 WGen(cinfo, VGA_PEL_MSK, val);
2497 if (cinfo->btype == BT_PICASSO) {
2498 /* now first reset HDR access counter */
2499 dummy = RGen(cinfo, VGA_PEL_IW);
2502 /* and at the end, restore the mask value */
2503 /* ## is this mask always 0xff? */
2504 WGen(cinfo, VGA_PEL_MSK, 0xff);
2509 /*** WSFR() - write to the "special function register" (SFR) ***/
2510 static void WSFR(struct cirrusfb_info *cinfo, unsigned char val)
2513 assert(cinfo->regbase != NULL);
2515 z_writeb(val, cinfo->regbase + 0x8000);
2519 /* The Picasso has a second register for switching the monitor bit */
2520 static void WSFR2(struct cirrusfb_info *cinfo, unsigned char val)
2523 /* writing an arbitrary value to this one causes the monitor switcher */
2524 /* to flip to Amiga display */
2525 assert(cinfo->regbase != NULL);
2527 z_writeb(val, cinfo->regbase + 0x9000);
2531 /*** WClut - set CLUT entry (range: 0..63) ***/
2532 static void WClut(struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char red,
2533 unsigned char green, unsigned char blue)
2535 unsigned int data = VGA_PEL_D;
2537 /* address write mode register is not translated.. */
2538 vga_w(cinfo->regbase, VGA_PEL_IW, regnum);
2540 if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 ||
2541 cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480 ||
2543 /* but DAC data register IS, at least for Picasso II */
2544 if (cinfo->btype == BT_PICASSO)
2546 vga_w(cinfo->regbase, data, red);
2547 vga_w(cinfo->regbase, data, green);
2548 vga_w(cinfo->regbase, data, blue);
2550 vga_w(cinfo->regbase, data, blue);
2551 vga_w(cinfo->regbase, data, green);
2552 vga_w(cinfo->regbase, data, red);
2557 /*** RClut - read CLUT entry (range 0..63) ***/
2558 static void RClut(struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char *red,
2559 unsigned char *green, unsigned char *blue)
2561 unsigned int data = VGA_PEL_D;
2563 vga_w(cinfo->regbase, VGA_PEL_IR, regnum);
2565 if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 ||
2566 cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480) {
2567 if (cinfo->btype == BT_PICASSO)
2569 *red = vga_r(cinfo->regbase, data);
2570 *green = vga_r(cinfo->regbase, data);
2571 *blue = vga_r(cinfo->regbase, data);
2573 *blue = vga_r(cinfo->regbase, data);
2574 *green = vga_r(cinfo->regbase, data);
2575 *red = vga_r(cinfo->regbase, data);
2580 /*******************************************************************
2583 Wait for the BitBLT engine to complete a possible earlier job
2584 *********************************************************************/
2586 /* FIXME: use interrupts instead */
2587 static void cirrusfb_WaitBLT(u8 __iomem *regbase)
2589 /* now busy-wait until we're done */
2590 while (vga_rgfx(regbase, CL_GR31) & 0x08)
2594 /*******************************************************************
2597 perform accelerated "scrolling"
2598 ********************************************************************/
2600 static void cirrusfb_BitBLT(u8 __iomem *regbase, int bits_per_pixel,
2601 u_short curx, u_short cury,
2602 u_short destx, u_short desty,
2603 u_short width, u_short height,
2604 u_short line_length)
2606 u_short nwidth, nheight;
2611 nheight = height - 1;
2614 /* if source adr < dest addr, do the Blt backwards */
2615 if (cury <= desty) {
2616 if (cury == desty) {
2617 /* if src and dest are on the same line, check x */
2624 /* standard case: forward blitting */
2625 nsrc = (cury * line_length) + curx;
2626 ndest = (desty * line_length) + destx;
2628 /* this means start addresses are at the end,
2629 * counting backwards
2631 nsrc = cury * line_length + curx +
2632 nheight * line_length + nwidth;
2633 ndest = desty * line_length + destx +
2634 nheight * line_length + nwidth;
2638 run-down of registers to be programmed:
2646 VGA_GFX_SR_VALUE / VGA_GFX_SR_ENABLE: "fill color"
2650 cirrusfb_WaitBLT(regbase);
2652 /* pitch: set to line_length */
2653 /* dest pitch low */
2654 vga_wgfx(regbase, CL_GR24, line_length & 0xff);
2656 vga_wgfx(regbase, CL_GR25, line_length >> 8);
2657 /* source pitch low */
2658 vga_wgfx(regbase, CL_GR26, line_length & 0xff);
2659 /* source pitch hi */
2660 vga_wgfx(regbase, CL_GR27, line_length >> 8);
2662 /* BLT width: actual number of pixels - 1 */
2664 vga_wgfx(regbase, CL_GR20, nwidth & 0xff);
2666 vga_wgfx(regbase, CL_GR21, nwidth >> 8);
2668 /* BLT height: actual number of lines -1 */
2669 /* BLT height low */
2670 vga_wgfx(regbase, CL_GR22, nheight & 0xff);
2672 vga_wgfx(regbase, CL_GR23, nheight >> 8);
2674 /* BLT destination */
2676 vga_wgfx(regbase, CL_GR28, (u_char) (ndest & 0xff));
2678 vga_wgfx(regbase, CL_GR29, (u_char) (ndest >> 8));
2680 vga_wgfx(regbase, CL_GR2A, (u_char) (ndest >> 16));
2684 vga_wgfx(regbase, CL_GR2C, (u_char) (nsrc & 0xff));
2686 vga_wgfx(regbase, CL_GR2D, (u_char) (nsrc >> 8));
2688 vga_wgfx(regbase, CL_GR2E, (u_char) (nsrc >> 16));
2691 vga_wgfx(regbase, CL_GR30, bltmode); /* BLT mode */
2693 /* BLT ROP: SrcCopy */
2694 vga_wgfx(regbase, CL_GR32, 0x0d); /* BLT ROP */
2696 /* and finally: GO! */
2697 vga_wgfx(regbase, CL_GR31, 0x02); /* BLT Start/status */
2700 /*******************************************************************
2703 perform accelerated rectangle fill
2704 ********************************************************************/
2706 static void cirrusfb_RectFill(u8 __iomem *regbase, int bits_per_pixel,
2707 u_short x, u_short y, u_short width, u_short height,
2708 u_char color, u_short line_length)
2710 u_short nwidth, nheight;
2715 nheight = height - 1;
2717 ndest = (y * line_length) + x;
2719 cirrusfb_WaitBLT(regbase);
2721 /* pitch: set to line_length */
2722 vga_wgfx(regbase, CL_GR24, line_length & 0xff); /* dest pitch low */
2723 vga_wgfx(regbase, CL_GR25, line_length >> 8); /* dest pitch hi */
2724 vga_wgfx(regbase, CL_GR26, line_length & 0xff); /* source pitch low */
2725 vga_wgfx(regbase, CL_GR27, line_length >> 8); /* source pitch hi */
2727 /* BLT width: actual number of pixels - 1 */
2728 vga_wgfx(regbase, CL_GR20, nwidth & 0xff); /* BLT width low */
2729 vga_wgfx(regbase, CL_GR21, nwidth >> 8); /* BLT width hi */
2731 /* BLT height: actual number of lines -1 */
2732 vga_wgfx(regbase, CL_GR22, nheight & 0xff); /* BLT height low */
2733 vga_wgfx(regbase, CL_GR23, nheight >> 8); /* BLT width hi */
2735 /* BLT destination */
2737 vga_wgfx(regbase, CL_GR28, (u_char) (ndest & 0xff));
2739 vga_wgfx(regbase, CL_GR29, (u_char) (ndest >> 8));
2741 vga_wgfx(regbase, CL_GR2A, (u_char) (ndest >> 16));
2743 /* BLT source: set to 0 (is a dummy here anyway) */
2744 vga_wgfx(regbase, CL_GR2C, 0x00); /* BLT src low */
2745 vga_wgfx(regbase, CL_GR2D, 0x00); /* BLT src mid */
2746 vga_wgfx(regbase, CL_GR2E, 0x00); /* BLT src hi */
2748 /* This is a ColorExpand Blt, using the */
2749 /* same color for foreground and background */
2750 vga_wgfx(regbase, VGA_GFX_SR_VALUE, color); /* foreground color */
2751 vga_wgfx(regbase, VGA_GFX_SR_ENABLE, color); /* background color */
2754 if (bits_per_pixel == 16) {
2755 vga_wgfx(regbase, CL_GR10, color); /* foreground color */
2756 vga_wgfx(regbase, CL_GR11, color); /* background color */
2759 } else if (bits_per_pixel == 32) {
2760 vga_wgfx(regbase, CL_GR10, color); /* foreground color */
2761 vga_wgfx(regbase, CL_GR11, color); /* background color */
2762 vga_wgfx(regbase, CL_GR12, color); /* foreground color */
2763 vga_wgfx(regbase, CL_GR13, color); /* background color */
2764 vga_wgfx(regbase, CL_GR14, 0); /* foreground color */
2765 vga_wgfx(regbase, CL_GR15, 0); /* background color */
2769 /* BLT mode: color expand, Enable 8x8 copy (faster?) */
2770 vga_wgfx(regbase, CL_GR30, op); /* BLT mode */
2772 /* BLT ROP: SrcCopy */
2773 vga_wgfx(regbase, CL_GR32, 0x0d); /* BLT ROP */
2775 /* and finally: GO! */
2776 vga_wgfx(regbase, CL_GR31, 0x02); /* BLT Start/status */
2779 /**************************************************************************
2780 * bestclock() - determine closest possible clock lower(?) than the
2781 * desired pixel clock
2782 **************************************************************************/
2783 static void bestclock(long freq, int *nom, int *den, int *div)
2788 assert(nom != NULL);
2789 assert(den != NULL);
2790 assert(div != NULL);
2801 for (n = 32; n < 128; n++) {
2804 d = (14318 * n) / freq;
2805 if ((d >= 7) && (d <= 63)) {
2812 h = ((14318 * n) / temp) >> s;
2813 h = h > freq ? h - freq : freq - h;
2822 if ((d >= 7) && (d <= 63)) {
2827 h = ((14318 * n) / d) >> s;
2828 h = h > freq ? h - freq : freq - h;
2839 /* -------------------------------------------------------------------------
2841 * debugging functions
2843 * -------------------------------------------------------------------------
2846 #ifdef CIRRUSFB_DEBUG
2849 * cirrusfb_dbg_print_regs
2850 * @base: If using newmmio, the newmmio base address, otherwise %NULL
2851 * @reg_class: type of registers to read: %CRT, or %SEQ
2854 * Dumps the given list of VGA CRTC registers. If @base is %NULL,
2855 * old-style I/O ports are queried for information, otherwise MMIO is
2856 * used at the given @base address to query the information.
2859 static void cirrusfb_dbg_print_regs(struct fb_info *info,
2861 enum cirrusfb_dbg_reg_class reg_class, ...)
2864 unsigned char val = 0;
2868 va_start(list, reg_class);
2870 name = va_arg(list, char *);
2871 while (name != NULL) {
2872 reg = va_arg(list, int);
2874 switch (reg_class) {
2876 val = vga_rcrt(regbase, (unsigned char) reg);
2879 val = vga_rseq(regbase, (unsigned char) reg);
2882 /* should never occur */
2887 dev_dbg(info->device, "%8s = 0x%02X\n", name, val);
2889 name = va_arg(list, char *);
2896 * cirrusfb_dbg_reg_dump
2897 * @base: If using newmmio, the newmmio base address, otherwise %NULL
2900 * Dumps a list of interesting VGA and CIRRUSFB registers. If @base is %NULL,
2901 * old-style I/O ports are queried for information, otherwise MMIO is
2902 * used at the given @base address to query the information.
2905 static void cirrusfb_dbg_reg_dump(struct fb_info *info, caddr_t regbase)
2907 dev_dbg(info->device, "VGA CRTC register dump:\n");
2909 cirrusfb_dbg_print_regs(info, regbase, CRT,
2959 dev_dbg(info->device, "\n");
2961 dev_dbg(info->device, "VGA SEQ register dump:\n");
2963 cirrusfb_dbg_print_regs(info, regbase, SEQ,
2992 dev_dbg(info->device, "\n");
2995 #endif /* CIRRUSFB_DEBUG */