2 * drivers/video/cirrusfb.c - driver for Cirrus Logic chipsets
4 * Copyright 1999-2001 Jeff Garzik <jgarzik@pobox.com>
6 * Contributors (thanks, all!)
9 * Overhaul for Linux 2.6
12 * Major contributions; Motorola PowerStack (PPC and PCI) support,
13 * GD54xx, 1280x1024 mode support, change MCLK based on VCLK.
16 * Excellent code review.
19 * Amiga updates and testing.
21 * Original cirrusfb author: Frank Neumann
23 * Based on retz3fb.c and cirrusfb.c:
24 * Copyright (C) 1997 Jes Sorensen
25 * Copyright (C) 1996 Frank Neumann
27 ***************************************************************
29 * Format this code with GNU indent '-kr -i8 -pcs' options.
31 * This file is subject to the terms and conditions of the GNU General Public
32 * License. See the file COPYING in the main directory of this archive
37 #include <linux/module.h>
38 #include <linux/kernel.h>
39 #include <linux/errno.h>
40 #include <linux/string.h>
42 #include <linux/delay.h>
44 #include <linux/init.h>
45 #include <asm/pgtable.h>
48 #include <linux/zorro.h>
51 #include <linux/pci.h>
54 #include <asm/amigahw.h>
56 #ifdef CONFIG_PPC_PREP
57 #include <asm/machdep.h>
58 #define isPReP machine_is(prep)
63 #include <video/vga.h>
64 #include <video/cirrus.h>
66 /*****************************************************************
68 * debugging and utility macros
72 /* disable runtime assertions? */
73 /* #define CIRRUSFB_NDEBUG */
75 /* debugging assertions */
76 #ifndef CIRRUSFB_NDEBUG
77 #define assert(expr) \
79 printk("Assertion failed! %s,%s,%s,line=%d\n", \
80 #expr, __FILE__, __func__, __LINE__); \
86 #define MB_ (1024 * 1024)
88 /*****************************************************************
98 BT_PICCOLO, /* GD5426 */
99 BT_PICASSO, /* GD5426 or GD5428 */
100 BT_SPECTRUM, /* GD5426 or GD5428 */
101 BT_PICASSO4, /* GD5446 */
102 BT_ALPINE, /* GD543x/4x */
104 BT_LAGUNA, /* GD5462/64 */
105 BT_LAGUNAB, /* GD5465 */
109 * per-board-type information, used for enumerating and abstracting
110 * chip-specific information
111 * NOTE: MUST be in the same order as enum cirrus_board in order to
112 * use direct indexing on this array
113 * NOTE: '__initdata' cannot be used as some of this info
114 * is required at runtime. Maybe separate into an init-only and
117 static const struct cirrusfb_board_info_rec {
118 char *name; /* ASCII name of chipset */
119 long maxclock[5]; /* maximum video clock */
120 /* for 1/4bpp, 8bpp 15/16bpp, 24bpp, 32bpp - numbers from xorg code */
121 bool init_sr07 : 1; /* init SR07 during init_vgachip() */
122 bool init_sr1f : 1; /* write SR1F during init_vgachip() */
123 /* construct bit 19 of screen start address */
124 bool scrn_start_bit19 : 1;
126 /* initial SR07 value, then for each mode */
128 unsigned char sr07_1bpp;
129 unsigned char sr07_1bpp_mux;
130 unsigned char sr07_8bpp;
131 unsigned char sr07_8bpp_mux;
133 unsigned char sr1f; /* SR1F VGA initial register value */
134 } cirrusfb_board_info[] = {
139 /* the SD64/P4 have a higher max. videoclock */
140 135100, 135100, 85500, 85500, 0
144 .scrn_start_bit19 = true,
147 .sr07_1bpp_mux = 0xF6,
149 .sr07_8bpp_mux = 0xF7,
153 .name = "CL Piccolo",
156 90000, 90000, 90000, 90000, 90000
160 .scrn_start_bit19 = false,
167 .name = "CL Picasso",
170 90000, 90000, 90000, 90000, 90000
174 .scrn_start_bit19 = false,
181 .name = "CL Spectrum",
184 90000, 90000, 90000, 90000, 90000
188 .scrn_start_bit19 = false,
195 .name = "CL Picasso4",
197 135100, 135100, 85500, 85500, 0
201 .scrn_start_bit19 = true,
204 .sr07_1bpp_mux = 0xA6,
206 .sr07_8bpp_mux = 0xA7,
212 /* for the GD5430. GD5446 can do more... */
213 85500, 85500, 50000, 28500, 0
217 .scrn_start_bit19 = true,
220 .sr07_1bpp_mux = 0xA6,
222 .sr07_8bpp_mux = 0xA7,
228 135100, 200000, 200000, 135100, 135100
232 .scrn_start_bit19 = true,
241 /* taken from X11 code */
242 170000, 170000, 170000, 170000, 135100,
246 .scrn_start_bit19 = true,
249 .name = "CL Laguna AGP",
251 /* taken from X11 code */
252 170000, 250000, 170000, 170000, 135100,
256 .scrn_start_bit19 = true,
261 #define CHIP(id, btype) \
262 { PCI_VENDOR_ID_CIRRUS, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (btype) }
264 static struct pci_device_id cirrusfb_pci_table[] = {
265 CHIP(PCI_DEVICE_ID_CIRRUS_5436, BT_ALPINE),
266 CHIP(PCI_DEVICE_ID_CIRRUS_5434_8, BT_SD64),
267 CHIP(PCI_DEVICE_ID_CIRRUS_5434_4, BT_SD64),
268 CHIP(PCI_DEVICE_ID_CIRRUS_5430, BT_ALPINE), /* GD-5440 is same id */
269 CHIP(PCI_DEVICE_ID_CIRRUS_7543, BT_ALPINE),
270 CHIP(PCI_DEVICE_ID_CIRRUS_7548, BT_ALPINE),
271 CHIP(PCI_DEVICE_ID_CIRRUS_5480, BT_GD5480), /* MacPicasso likely */
272 CHIP(PCI_DEVICE_ID_CIRRUS_5446, BT_PICASSO4), /* Picasso 4 is 5446 */
273 CHIP(PCI_DEVICE_ID_CIRRUS_5462, BT_LAGUNA), /* CL Laguna */
274 CHIP(PCI_DEVICE_ID_CIRRUS_5464, BT_LAGUNA), /* CL Laguna 3D */
275 CHIP(PCI_DEVICE_ID_CIRRUS_5465, BT_LAGUNAB), /* CL Laguna 3DA*/
278 MODULE_DEVICE_TABLE(pci, cirrusfb_pci_table);
280 #endif /* CONFIG_PCI */
283 static const struct zorro_device_id cirrusfb_zorro_table[] = {
285 .id = ZORRO_PROD_HELFRICH_SD64_RAM,
286 .driver_data = BT_SD64,
288 .id = ZORRO_PROD_HELFRICH_PICCOLO_RAM,
289 .driver_data = BT_PICCOLO,
291 .id = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_II_II_PLUS_RAM,
292 .driver_data = BT_PICASSO,
294 .id = ZORRO_PROD_GVP_EGS_28_24_SPECTRUM_RAM,
295 .driver_data = BT_SPECTRUM,
297 .id = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_IV_Z3,
298 .driver_data = BT_PICASSO4,
303 static const struct {
306 } cirrusfb_zorro_table2[] = {
308 .id2 = ZORRO_PROD_HELFRICH_SD64_REG,
312 .id2 = ZORRO_PROD_HELFRICH_PICCOLO_REG,
316 .id2 = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_II_II_PLUS_REG,
320 .id2 = ZORRO_PROD_GVP_EGS_28_24_SPECTRUM_REG,
328 #endif /* CONFIG_ZORRO */
330 #ifdef CIRRUSFB_DEBUG
331 enum cirrusfb_dbg_reg_class {
335 #endif /* CIRRUSFB_DEBUG */
337 /* info about board */
338 struct cirrusfb_info {
340 u8 __iomem *laguna_mmio;
341 enum cirrus_board btype;
342 unsigned char SFR; /* Shadow of special function register */
347 u32 pseudo_palette[16];
349 void (*unmap)(struct fb_info *info);
352 static int noaccel __devinitdata;
353 static char *mode_option __devinitdata = "640x480@60";
355 /****************************************************************************/
356 /**** BEGIN PROTOTYPES ******************************************************/
358 /*--- Interface used by the world ------------------------------------------*/
359 static int cirrusfb_pan_display(struct fb_var_screeninfo *var,
360 struct fb_info *info);
362 /*--- Internal routines ----------------------------------------------------*/
363 static void init_vgachip(struct fb_info *info);
364 static void switch_monitor(struct cirrusfb_info *cinfo, int on);
365 static void WGen(const struct cirrusfb_info *cinfo,
366 int regnum, unsigned char val);
367 static unsigned char RGen(const struct cirrusfb_info *cinfo, int regnum);
368 static void AttrOn(const struct cirrusfb_info *cinfo);
369 static void WHDR(const struct cirrusfb_info *cinfo, unsigned char val);
370 static void WSFR(struct cirrusfb_info *cinfo, unsigned char val);
371 static void WSFR2(struct cirrusfb_info *cinfo, unsigned char val);
372 static void WClut(struct cirrusfb_info *cinfo, unsigned char regnum,
373 unsigned char red, unsigned char green, unsigned char blue);
375 static void RClut(struct cirrusfb_info *cinfo, unsigned char regnum,
376 unsigned char *red, unsigned char *green,
377 unsigned char *blue);
379 static void cirrusfb_WaitBLT(u8 __iomem *regbase);
380 static void cirrusfb_BitBLT(u8 __iomem *regbase, int bits_per_pixel,
381 u_short curx, u_short cury,
382 u_short destx, u_short desty,
383 u_short width, u_short height,
384 u_short line_length);
385 static void cirrusfb_RectFill(u8 __iomem *regbase, int bits_per_pixel,
386 u_short x, u_short y,
387 u_short width, u_short height,
388 u32 fg_color, u32 bg_color,
389 u_short line_length, u_char blitmode);
391 static void bestclock(long freq, int *nom, int *den, int *div);
393 #ifdef CIRRUSFB_DEBUG
394 static void cirrusfb_dbg_reg_dump(struct fb_info *info, caddr_t regbase);
395 static void cirrusfb_dbg_print_regs(struct fb_info *info,
397 enum cirrusfb_dbg_reg_class reg_class, ...);
398 #endif /* CIRRUSFB_DEBUG */
400 /*** END PROTOTYPES ********************************************************/
401 /*****************************************************************************/
402 /*** BEGIN Interface Used by the World ***************************************/
404 static inline int is_laguna(const struct cirrusfb_info *cinfo)
406 return cinfo->btype == BT_LAGUNA || cinfo->btype == BT_LAGUNAB;
409 static int opencount;
411 /*--- Open /dev/fbx ---------------------------------------------------------*/
412 static int cirrusfb_open(struct fb_info *info, int user)
414 if (opencount++ == 0)
415 switch_monitor(info->par, 1);
419 /*--- Close /dev/fbx --------------------------------------------------------*/
420 static int cirrusfb_release(struct fb_info *info, int user)
422 if (--opencount == 0)
423 switch_monitor(info->par, 0);
427 /**** END Interface used by the World *************************************/
428 /****************************************************************************/
429 /**** BEGIN Hardware specific Routines **************************************/
431 /* Check if the MCLK is not a better clock source */
432 static int cirrusfb_check_mclk(struct fb_info *info, long freq)
434 struct cirrusfb_info *cinfo = info->par;
435 long mclk = vga_rseq(cinfo->regbase, CL_SEQR1F) & 0x3f;
437 /* Read MCLK value */
438 mclk = (14318 * mclk) >> 3;
439 dev_dbg(info->device, "Read MCLK of %ld kHz\n", mclk);
441 /* Determine if we should use MCLK instead of VCLK, and if so, what we
442 * should divide it by to get VCLK
445 if (abs(freq - mclk) < 250) {
446 dev_dbg(info->device, "Using VCLK = MCLK\n");
448 } else if (abs(freq - (mclk / 2)) < 250) {
449 dev_dbg(info->device, "Using VCLK = MCLK/2\n");
456 static int cirrusfb_check_pixclock(const struct fb_var_screeninfo *var,
457 struct fb_info *info)
461 struct cirrusfb_info *cinfo = info->par;
462 unsigned maxclockidx = var->bits_per_pixel >> 3;
464 /* convert from ps to kHz */
465 freq = PICOS2KHZ(var->pixclock);
467 dev_dbg(info->device, "desired pixclock: %ld kHz\n", freq);
469 maxclock = cirrusfb_board_info[cinfo->btype].maxclock[maxclockidx];
470 cinfo->multiplexing = 0;
472 /* If the frequency is greater than we can support, we might be able
473 * to use multiplexing for the video mode */
474 if (freq > maxclock) {
475 dev_err(info->device,
476 "Frequency greater than maxclock (%ld kHz)\n",
481 * Additional constraint: 8bpp uses DAC clock doubling to allow maximum
484 if (var->bits_per_pixel == 8) {
485 switch (cinfo->btype) {
490 cinfo->multiplexing = 1;
494 cinfo->multiplexing = 1;
502 /* If we have a 1MB 5434, we need to put ourselves in a mode where
503 * the VCLK is double the pixel clock. */
504 cinfo->doubleVCLK = 0;
505 if (cinfo->btype == BT_SD64 && info->fix.smem_len <= MB_ &&
506 var->bits_per_pixel == 16) {
507 cinfo->doubleVCLK = 1;
513 static int cirrusfb_check_var(struct fb_var_screeninfo *var,
514 struct fb_info *info)
517 /* memory size in pixels */
518 unsigned pixels = info->screen_size * 8 / var->bits_per_pixel;
519 struct cirrusfb_info *cinfo = info->par;
521 switch (var->bits_per_pixel) {
525 var->green = var->red;
526 var->blue = var->red;
532 var->green = var->red;
533 var->blue = var->red;
539 var->green.offset = -3;
540 var->blue.offset = 8;
542 var->red.offset = 11;
543 var->green.offset = 5;
544 var->blue.offset = 0;
547 var->green.length = 6;
548 var->blue.length = 5;
554 var->green.offset = 8;
555 var->blue.offset = 16;
557 var->red.offset = 16;
558 var->green.offset = 8;
559 var->blue.offset = 0;
562 var->green.length = 8;
563 var->blue.length = 8;
567 dev_dbg(info->device,
568 "Unsupported bpp size: %d\n", var->bits_per_pixel);
572 if (var->xres_virtual < var->xres)
573 var->xres_virtual = var->xres;
574 /* use highest possible virtual resolution */
575 if (var->yres_virtual == -1) {
576 var->yres_virtual = pixels / var->xres_virtual;
578 dev_info(info->device,
579 "virtual resolution set to maximum of %dx%d\n",
580 var->xres_virtual, var->yres_virtual);
582 if (var->yres_virtual < var->yres)
583 var->yres_virtual = var->yres;
585 if (var->xres_virtual * var->yres_virtual > pixels) {
586 dev_err(info->device, "mode %dx%dx%d rejected... "
587 "virtual resolution too high to fit into video memory!\n",
588 var->xres_virtual, var->yres_virtual,
589 var->bits_per_pixel);
593 if (var->xoffset < 0)
595 if (var->yoffset < 0)
598 /* truncate xoffset and yoffset to maximum if too high */
599 if (var->xoffset > var->xres_virtual - var->xres)
600 var->xoffset = var->xres_virtual - var->xres - 1;
601 if (var->yoffset > var->yres_virtual - var->yres)
602 var->yoffset = var->yres_virtual - var->yres - 1;
605 var->green.msb_right =
606 var->blue.msb_right =
609 var->transp.msb_right = 0;
612 if (var->vmode & FB_VMODE_DOUBLE)
614 else if (var->vmode & FB_VMODE_INTERLACED)
615 yres = (yres + 1) / 2;
618 dev_err(info->device, "ERROR: VerticalTotal >= 1280; "
619 "special treatment required! (TODO)\n");
623 if (cirrusfb_check_pixclock(var, info))
626 if (!is_laguna(cinfo))
627 var->accel_flags = FB_ACCELF_TEXT;
632 static void cirrusfb_set_mclk_as_source(const struct fb_info *info, int div)
634 struct cirrusfb_info *cinfo = info->par;
635 unsigned char old1f, old1e;
637 assert(cinfo != NULL);
638 old1f = vga_rseq(cinfo->regbase, CL_SEQR1F) & ~0x40;
641 dev_dbg(info->device, "Set %s as pixclock source.\n",
642 (div == 2) ? "MCLK/2" : "MCLK");
644 old1e = vga_rseq(cinfo->regbase, CL_SEQR1E) & ~0x1;
648 vga_wseq(cinfo->regbase, CL_SEQR1E, old1e);
650 vga_wseq(cinfo->regbase, CL_SEQR1F, old1f);
653 /*************************************************************************
654 cirrusfb_set_par_foo()
656 actually writes the values for a new video mode into the hardware,
657 **************************************************************************/
658 static int cirrusfb_set_par_foo(struct fb_info *info)
660 struct cirrusfb_info *cinfo = info->par;
661 struct fb_var_screeninfo *var = &info->var;
662 u8 __iomem *regbase = cinfo->regbase;
665 const struct cirrusfb_board_info_rec *bi;
666 int hdispend, hsyncstart, hsyncend, htotal;
667 int yres, vdispend, vsyncstart, vsyncend, vtotal;
670 unsigned int control = 0, format = 0, threshold = 0;
672 dev_dbg(info->device, "Requested mode: %dx%dx%d\n",
673 var->xres, var->yres, var->bits_per_pixel);
675 switch (var->bits_per_pixel) {
677 info->fix.line_length = var->xres_virtual / 8;
678 info->fix.visual = FB_VISUAL_MONO10;
682 info->fix.line_length = var->xres_virtual;
683 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
688 info->fix.line_length = var->xres_virtual *
689 var->bits_per_pixel >> 3;
690 info->fix.visual = FB_VISUAL_TRUECOLOR;
693 info->fix.type = FB_TYPE_PACKED_PIXELS;
697 bi = &cirrusfb_board_info[cinfo->btype];
699 hsyncstart = var->xres + var->right_margin;
700 hsyncend = hsyncstart + var->hsync_len;
701 htotal = (hsyncend + var->left_margin) / 8;
702 hdispend = var->xres / 8;
703 hsyncstart = hsyncstart / 8;
704 hsyncend = hsyncend / 8;
706 vdispend = var->yres;
707 vsyncstart = vdispend + var->lower_margin;
708 vsyncend = vsyncstart + var->vsync_len;
709 vtotal = vsyncend + var->upper_margin;
711 if (var->vmode & FB_VMODE_DOUBLE) {
716 } else if (var->vmode & FB_VMODE_INTERLACED) {
717 vdispend = (vdispend + 1) / 2;
718 vsyncstart = (vsyncstart + 1) / 2;
719 vsyncend = (vsyncend + 1) / 2;
720 vtotal = (vtotal + 1) / 2;
735 if (cinfo->multiplexing) {
747 /* unlock register VGA_CRTC_H_TOTAL..CRT7 */
748 vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, 0x20); /* previously: 0x00) */
750 /* if debugging is enabled, all parameters get output before writing */
751 dev_dbg(info->device, "CRT0: %d\n", htotal);
752 vga_wcrt(regbase, VGA_CRTC_H_TOTAL, htotal);
754 dev_dbg(info->device, "CRT1: %d\n", hdispend);
755 vga_wcrt(regbase, VGA_CRTC_H_DISP, hdispend);
757 dev_dbg(info->device, "CRT2: %d\n", var->xres / 8);
758 vga_wcrt(regbase, VGA_CRTC_H_BLANK_START, var->xres / 8);
760 /* + 128: Compatible read */
761 dev_dbg(info->device, "CRT3: 128+%d\n", (htotal + 5) % 32);
762 vga_wcrt(regbase, VGA_CRTC_H_BLANK_END,
763 128 + ((htotal + 5) % 32));
765 dev_dbg(info->device, "CRT4: %d\n", hsyncstart);
766 vga_wcrt(regbase, VGA_CRTC_H_SYNC_START, hsyncstart);
769 if ((htotal + 5) & 32)
771 dev_dbg(info->device, "CRT5: %d\n", tmp);
772 vga_wcrt(regbase, VGA_CRTC_H_SYNC_END, tmp);
774 dev_dbg(info->device, "CRT6: %d\n", vtotal & 0xff);
775 vga_wcrt(regbase, VGA_CRTC_V_TOTAL, vtotal & 0xff);
777 tmp = 16; /* LineCompare bit #9 */
782 if (vsyncstart & 256)
784 if ((vdispend + 1) & 256)
790 if (vsyncstart & 512)
792 dev_dbg(info->device, "CRT7: %d\n", tmp);
793 vga_wcrt(regbase, VGA_CRTC_OVERFLOW, tmp);
795 tmp = 0x40; /* LineCompare bit #8 */
796 if ((vdispend + 1) & 512)
798 if (var->vmode & FB_VMODE_DOUBLE)
800 dev_dbg(info->device, "CRT9: %d\n", tmp);
801 vga_wcrt(regbase, VGA_CRTC_MAX_SCAN, tmp);
803 dev_dbg(info->device, "CRT10: %d\n", vsyncstart & 0xff);
804 vga_wcrt(regbase, VGA_CRTC_V_SYNC_START, vsyncstart & 0xff);
806 dev_dbg(info->device, "CRT11: 64+32+%d\n", vsyncend % 16);
807 vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, vsyncend % 16 + 64 + 32);
809 dev_dbg(info->device, "CRT12: %d\n", vdispend & 0xff);
810 vga_wcrt(regbase, VGA_CRTC_V_DISP_END, vdispend & 0xff);
812 dev_dbg(info->device, "CRT15: %d\n", (vdispend + 1) & 0xff);
813 vga_wcrt(regbase, VGA_CRTC_V_BLANK_START, (vdispend + 1) & 0xff);
815 dev_dbg(info->device, "CRT16: %d\n", vtotal & 0xff);
816 vga_wcrt(regbase, VGA_CRTC_V_BLANK_END, vtotal & 0xff);
818 dev_dbg(info->device, "CRT18: 0xff\n");
819 vga_wcrt(regbase, VGA_CRTC_LINE_COMPARE, 0xff);
822 if (var->vmode & FB_VMODE_INTERLACED)
824 if ((htotal + 5) & 64)
826 if ((htotal + 5) & 128)
833 dev_dbg(info->device, "CRT1a: %d\n", tmp);
834 vga_wcrt(regbase, CL_CRT1A, tmp);
836 freq = PICOS2KHZ(var->pixclock);
837 if (var->bits_per_pixel == 24)
838 if (cinfo->btype == BT_ALPINE || cinfo->btype == BT_SD64)
840 if (cinfo->multiplexing)
842 if (cinfo->doubleVCLK)
845 bestclock(freq, &nom, &den, &div);
847 dev_dbg(info->device, "VCLK freq: %ld kHz nom: %d den: %d div: %d\n",
848 freq, nom, den, div);
851 /* hardware RefClock: 14.31818 MHz */
852 /* formula: VClk = (OSC * N) / (D * (1+P)) */
853 /* Example: VClk = (14.31818 * 91) / (23 * (1+1)) = 28.325 MHz */
855 if (cinfo->btype == BT_ALPINE || cinfo->btype == BT_PICASSO4 ||
856 cinfo->btype == BT_SD64) {
857 /* if freq is close to mclk or mclk/2 select mclk
860 int divMCLK = cirrusfb_check_mclk(info, freq);
863 cirrusfb_set_mclk_as_source(info, divMCLK);
865 if (is_laguna(cinfo)) {
866 long pcifc = fb_readl(cinfo->laguna_mmio + 0x3fc);
867 unsigned char tile = fb_readb(cinfo->laguna_mmio + 0x407);
868 unsigned short tile_control;
870 if (cinfo->btype == BT_LAGUNAB) {
871 tile_control = fb_readw(cinfo->laguna_mmio + 0x2c4);
872 tile_control &= ~0x80;
873 fb_writew(tile_control, cinfo->laguna_mmio + 0x2c4);
876 fb_writel(pcifc | 0x10000000l, cinfo->laguna_mmio + 0x3fc);
877 fb_writeb(tile & 0x3f, cinfo->laguna_mmio + 0x407);
878 control = fb_readw(cinfo->laguna_mmio + 0x402);
879 threshold = fb_readw(cinfo->laguna_mmio + 0xea);
882 threshold &= 0xffc0 & 0x3fbf;
888 /* 6 bit denom; ONLY 5434!!! (bugged me 10 days) */
889 if ((cinfo->btype == BT_SD64) ||
890 (cinfo->btype == BT_ALPINE) ||
891 (cinfo->btype == BT_GD5480))
894 /* Laguna chipset has reversed clock registers */
895 if (is_laguna(cinfo)) {
896 vga_wseq(regbase, CL_SEQRE, tmp);
897 vga_wseq(regbase, CL_SEQR1E, nom);
899 vga_wseq(regbase, CL_SEQRE, nom);
900 vga_wseq(regbase, CL_SEQR1E, tmp);
906 vga_wcrt(regbase, VGA_CRTC_MODE, 0xc7);
908 /* mode control: VGA_CRTC_START_HI enable, ROTATE(?), 16bit
909 * address wrap, no compat. */
910 vga_wcrt(regbase, VGA_CRTC_MODE, 0xc3);
912 /* don't know if it would hurt to also program this if no interlaced */
913 /* mode is used, but I feel better this way.. :-) */
914 if (var->vmode & FB_VMODE_INTERLACED)
915 vga_wcrt(regbase, VGA_CRTC_REGS, htotal / 2);
917 vga_wcrt(regbase, VGA_CRTC_REGS, 0x00); /* interlace control */
919 /* adjust horizontal/vertical sync type (low/high), use VCLK3 */
920 /* enable display memory & CRTC I/O address for color mode */
922 if (var->sync & FB_SYNC_HOR_HIGH_ACT)
924 if (var->sync & FB_SYNC_VERT_HIGH_ACT)
926 WGen(cinfo, VGA_MIS_W, tmp);
928 /* text cursor on and start line */
929 vga_wcrt(regbase, VGA_CRTC_CURSOR_START, 0);
930 /* text cursor end line */
931 vga_wcrt(regbase, VGA_CRTC_CURSOR_END, 31);
933 /******************************************************
939 /* programming for different color depths */
940 if (var->bits_per_pixel == 1) {
941 dev_dbg(info->device, "preparing for 1 bit deep display\n");
942 vga_wgfx(regbase, VGA_GFX_MODE, 0); /* mode register */
945 switch (cinfo->btype) {
953 vga_wseq(regbase, CL_SEQR7,
954 cinfo->multiplexing ?
955 bi->sr07_1bpp_mux : bi->sr07_1bpp);
960 vga_wseq(regbase, CL_SEQR7,
961 vga_rseq(regbase, CL_SEQR7) & ~0x01);
965 dev_warn(info->device, "unknown Board\n");
969 /* Extended Sequencer Mode */
970 switch (cinfo->btype) {
974 /* evtl d0 bei 1 bit? avoid FIFO underruns..? */
975 vga_wseq(regbase, CL_SEQRF, 0xb0);
979 /* ## vorher d0 avoid FIFO underruns..? */
980 vga_wseq(regbase, CL_SEQRF, 0xd0);
993 dev_warn(info->device, "unknown Board\n");
997 /* pixel mask: pass-through for first plane */
998 WGen(cinfo, VGA_PEL_MSK, 0x01);
999 if (cinfo->multiplexing)
1000 /* hidden dac reg: 1280x1024 */
1003 /* hidden dac: nothing */
1005 /* memory mode: odd/even, ext. memory */
1006 vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, 0x06);
1007 /* plane mask: only write to first plane */
1008 vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0x01);
1011 /******************************************************
1017 else if (var->bits_per_pixel == 8) {
1018 dev_dbg(info->device, "preparing for 8 bit deep display\n");
1019 switch (cinfo->btype) {
1027 vga_wseq(regbase, CL_SEQR7,
1028 cinfo->multiplexing ?
1029 bi->sr07_8bpp_mux : bi->sr07_8bpp);
1034 vga_wseq(regbase, CL_SEQR7,
1035 vga_rseq(regbase, CL_SEQR7) | 0x01);
1040 dev_warn(info->device, "unknown Board\n");
1044 switch (cinfo->btype) {
1048 /* Fast Page-Mode writes */
1049 vga_wseq(regbase, CL_SEQRF, 0xb0);
1054 /* ### INCOMPLETE!! */
1055 vga_wseq(regbase, CL_SEQRF, 0xb8);
1066 dev_warn(info->device, "unknown board\n");
1070 /* mode register: 256 color mode */
1071 vga_wgfx(regbase, VGA_GFX_MODE, 64);
1072 if (cinfo->multiplexing)
1073 /* hidden dac reg: 1280x1024 */
1076 /* hidden dac: nothing */
1080 /******************************************************
1086 else if (var->bits_per_pixel == 16) {
1087 dev_dbg(info->device, "preparing for 16 bit deep display\n");
1088 switch (cinfo->btype) {
1091 vga_wseq(regbase, CL_SEQR7, 0x87);
1092 /* Fast Page-Mode writes */
1093 vga_wseq(regbase, CL_SEQRF, 0xb0);
1097 vga_wseq(regbase, CL_SEQR7, 0x27);
1098 /* Fast Page-Mode writes */
1099 vga_wseq(regbase, CL_SEQRF, 0xb0);
1105 /* Extended Sequencer Mode: 256c col. mode */
1106 vga_wseq(regbase, CL_SEQR7,
1107 cinfo->doubleVCLK ? 0xa3 : 0xa7);
1111 vga_wseq(regbase, CL_SEQR7, 0x17);
1112 /* We already set SRF and SR1F */
1117 vga_wseq(regbase, CL_SEQR7,
1118 vga_rseq(regbase, CL_SEQR7) & ~0x01);
1125 dev_warn(info->device, "unknown Board\n");
1129 /* mode register: 256 color mode */
1130 vga_wgfx(regbase, VGA_GFX_MODE, 64);
1132 WHDR(cinfo, cinfo->doubleVCLK ? 0xe1 : 0xc1);
1133 #elif defined(CONFIG_ZORRO)
1134 /* FIXME: CONFIG_PCI and CONFIG_ZORRO may be defined both */
1135 WHDR(cinfo, 0xa0); /* hidden dac reg: nothing special */
1139 /******************************************************
1145 else if (var->bits_per_pixel == 24) {
1146 dev_dbg(info->device, "preparing for 24 bit deep display\n");
1147 switch (cinfo->btype) {
1150 vga_wseq(regbase, CL_SEQR7, 0x85);
1151 /* Fast Page-Mode writes */
1152 vga_wseq(regbase, CL_SEQRF, 0xb0);
1156 vga_wseq(regbase, CL_SEQR7, 0x25);
1157 /* Fast Page-Mode writes */
1158 vga_wseq(regbase, CL_SEQRF, 0xb0);
1164 /* Extended Sequencer Mode: 256c col. mode */
1165 vga_wseq(regbase, CL_SEQR7, 0xa5);
1169 vga_wseq(regbase, CL_SEQR7, 0x15);
1170 /* We already set SRF and SR1F */
1175 vga_wseq(regbase, CL_SEQR7,
1176 vga_rseq(regbase, CL_SEQR7) & ~0x01);
1183 dev_warn(info->device, "unknown Board\n");
1187 /* mode register: 256 color mode */
1188 vga_wgfx(regbase, VGA_GFX_MODE, 64);
1189 /* hidden dac reg: 8-8-8 mode (24 or 32) */
1193 /******************************************************
1195 * unknown/unsupported bpp
1200 dev_err(info->device,
1201 "What's this? requested color depth == %d.\n",
1202 var->bits_per_pixel);
1204 pitch = info->fix.line_length >> 3;
1205 vga_wcrt(regbase, VGA_CRTC_OFFSET, pitch & 0xff);
1208 tmp |= 0x10; /* offset overflow bit */
1210 /* screen start addr #16-18, fastpagemode cycles */
1211 vga_wcrt(regbase, CL_CRT1B, tmp);
1213 /* screen start address bit 19 */
1214 if (cirrusfb_board_info[cinfo->btype].scrn_start_bit19)
1215 vga_wcrt(regbase, CL_CRT1D, (pitch >> 9) & 1);
1217 if (is_laguna(cinfo)) {
1219 if ((htotal + 5) & 256)
1223 if (hsyncstart & 256)
1227 if (vdispend & 1024)
1229 if (vsyncstart & 1024)
1232 vga_wcrt(regbase, CL_CRT1E, tmp);
1233 dev_dbg(info->device, "CRT1e: %d\n", tmp);
1237 vga_wattr(regbase, CL_AR33, 0);
1239 /* [ EGS: SetOffset(); ] */
1240 /* From SetOffset(): Turn on VideoEnable bit in Attribute controller */
1243 if (is_laguna(cinfo)) {
1245 fb_writew(control | 0x1000, cinfo->laguna_mmio + 0x402);
1246 fb_writew(format, cinfo->laguna_mmio + 0xc0);
1247 fb_writew(threshold, cinfo->laguna_mmio + 0xea);
1249 /* finally, turn on everything - turn off "FullBandwidth" bit */
1250 /* also, set "DotClock%2" bit where requested */
1253 /*** FB_VMODE_CLOCK_HALVE in linux/fb.h not defined anymore ?
1254 if (var->vmode & FB_VMODE_CLOCK_HALVE)
1258 vga_wseq(regbase, VGA_SEQ_CLOCK_MODE, tmp);
1259 dev_dbg(info->device, "CL_SEQR1: %d\n", tmp);
1261 #ifdef CIRRUSFB_DEBUG
1262 cirrusfb_dbg_reg_dump(info, NULL);
1268 /* for some reason incomprehensible to me, cirrusfb requires that you write
1269 * the registers twice for the settings to take..grr. -dte */
1270 static int cirrusfb_set_par(struct fb_info *info)
1272 cirrusfb_set_par_foo(info);
1273 return cirrusfb_set_par_foo(info);
1276 static int cirrusfb_setcolreg(unsigned regno, unsigned red, unsigned green,
1277 unsigned blue, unsigned transp,
1278 struct fb_info *info)
1280 struct cirrusfb_info *cinfo = info->par;
1285 if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
1287 red >>= (16 - info->var.red.length);
1288 green >>= (16 - info->var.green.length);
1289 blue >>= (16 - info->var.blue.length);
1293 v = (red << info->var.red.offset) |
1294 (green << info->var.green.offset) |
1295 (blue << info->var.blue.offset);
1297 cinfo->pseudo_palette[regno] = v;
1301 if (info->var.bits_per_pixel == 8)
1302 WClut(cinfo, regno, red >> 10, green >> 10, blue >> 10);
1308 /*************************************************************************
1309 cirrusfb_pan_display()
1311 performs display panning - provided hardware permits this
1312 **************************************************************************/
1313 static int cirrusfb_pan_display(struct fb_var_screeninfo *var,
1314 struct fb_info *info)
1318 unsigned char tmp, xpix;
1319 struct cirrusfb_info *cinfo = info->par;
1321 /* no range checks for xoffset and yoffset, */
1322 /* as fb_pan_display has already done this */
1323 if (var->vmode & FB_VMODE_YWRAP)
1326 xoffset = var->xoffset * info->var.bits_per_pixel / 8;
1328 base = var->yoffset * info->fix.line_length + xoffset;
1330 if (info->var.bits_per_pixel == 1) {
1331 /* base is already correct */
1332 xpix = (unsigned char) (var->xoffset % 8);
1335 xpix = (unsigned char) ((xoffset % 4) * 2);
1338 if (!is_laguna(cinfo))
1339 cirrusfb_WaitBLT(cinfo->regbase);
1341 /* lower 8 + 8 bits of screen start address */
1342 vga_wcrt(cinfo->regbase, VGA_CRTC_START_LO, base & 0xff);
1343 vga_wcrt(cinfo->regbase, VGA_CRTC_START_HI, (base >> 8) & 0xff);
1345 /* 0xf2 is %11110010, exclude tmp bits */
1346 tmp = vga_rcrt(cinfo->regbase, CL_CRT1B) & 0xf2;
1347 /* construct bits 16, 17 and 18 of screen start address */
1355 vga_wcrt(cinfo->regbase, CL_CRT1B, tmp);
1357 /* construct bit 19 of screen start address */
1358 if (cirrusfb_board_info[cinfo->btype].scrn_start_bit19) {
1359 tmp = vga_rcrt(cinfo->regbase, CL_CRT1D);
1360 if (is_laguna(cinfo))
1361 tmp = (tmp & ~0x18) | ((base >> 16) & 0x18);
1363 tmp = (tmp & ~0x80) | ((base >> 12) & 0x80);
1364 vga_wcrt(cinfo->regbase, CL_CRT1D, tmp);
1367 /* write pixel panning value to AR33; this does not quite work in 8bpp
1369 * ### Piccolo..? Will this work?
1371 if (info->var.bits_per_pixel == 1)
1372 vga_wattr(cinfo->regbase, CL_AR33, xpix);
1377 static int cirrusfb_blank(int blank_mode, struct fb_info *info)
1380 * Blank the screen if blank_mode != 0, else unblank. If blank == NULL
1381 * then the caller blanks by setting the CLUT (Color Look Up Table)
1382 * to all black. Return 0 if blanking succeeded, != 0 if un-/blanking
1383 * failed due to e.g. a video mode which doesn't support it.
1384 * Implements VESA suspend and powerdown modes on hardware that
1385 * supports disabling hsync/vsync:
1386 * blank_mode == 2: suspend vsync
1387 * blank_mode == 3: suspend hsync
1388 * blank_mode == 4: powerdown
1391 struct cirrusfb_info *cinfo = info->par;
1392 int current_mode = cinfo->blank_mode;
1394 dev_dbg(info->device, "ENTER, blank mode = %d\n", blank_mode);
1396 if (info->state != FBINFO_STATE_RUNNING ||
1397 current_mode == blank_mode) {
1398 dev_dbg(info->device, "EXIT, returning 0\n");
1403 if (current_mode == FB_BLANK_NORMAL ||
1404 current_mode == FB_BLANK_UNBLANK)
1405 /* clear "FullBandwidth" bit */
1408 /* set "FullBandwidth" bit */
1411 val |= vga_rseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE) & 0xdf;
1412 vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, val);
1414 switch (blank_mode) {
1415 case FB_BLANK_UNBLANK:
1416 case FB_BLANK_NORMAL:
1419 case FB_BLANK_VSYNC_SUSPEND:
1422 case FB_BLANK_HSYNC_SUSPEND:
1425 case FB_BLANK_POWERDOWN:
1429 dev_dbg(info->device, "EXIT, returning 1\n");
1433 vga_wgfx(cinfo->regbase, CL_GRE, val);
1435 cinfo->blank_mode = blank_mode;
1436 dev_dbg(info->device, "EXIT, returning 0\n");
1438 /* Let fbcon do a soft blank for us */
1439 return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
1442 /**** END Hardware specific Routines **************************************/
1443 /****************************************************************************/
1444 /**** BEGIN Internal Routines ***********************************************/
1446 static void init_vgachip(struct fb_info *info)
1448 struct cirrusfb_info *cinfo = info->par;
1449 const struct cirrusfb_board_info_rec *bi;
1451 assert(cinfo != NULL);
1453 bi = &cirrusfb_board_info[cinfo->btype];
1455 /* reset board globally */
1456 switch (cinfo->btype) {
1475 /* disable flickerfixer */
1476 vga_wcrt(cinfo->regbase, CL_CRT51, 0x00);
1479 vga_wgfx(cinfo->regbase, CL_GR31, 0x00);
1480 case BT_GD5480: /* fall through */
1481 /* from Klaus' NetBSD driver: */
1482 vga_wgfx(cinfo->regbase, CL_GR2F, 0x00);
1483 case BT_ALPINE: /* fall through */
1484 /* put blitter into 542x compat */
1485 vga_wgfx(cinfo->regbase, CL_GR33, 0x00);
1490 /* Nothing to do to reset the board. */
1494 dev_err(info->device, "Warning: Unknown board type\n");
1498 /* make sure RAM size set by this point */
1499 assert(info->screen_size > 0);
1501 /* the P4 is not fully initialized here; I rely on it having been */
1502 /* inited under AmigaOS already, which seems to work just fine */
1503 /* (Klaus advised to do it this way) */
1505 if (cinfo->btype != BT_PICASSO4) {
1506 WGen(cinfo, CL_VSSM, 0x10); /* EGS: 0x16 */
1507 WGen(cinfo, CL_POS102, 0x01);
1508 WGen(cinfo, CL_VSSM, 0x08); /* EGS: 0x0e */
1510 if (cinfo->btype != BT_SD64)
1511 WGen(cinfo, CL_VSSM2, 0x01);
1513 /* reset sequencer logic */
1514 vga_wseq(cinfo->regbase, VGA_SEQ_RESET, 0x03);
1516 /* FullBandwidth (video off) and 8/9 dot clock */
1517 vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, 0x21);
1519 /* "magic cookie" - doesn't make any sense to me.. */
1520 /* vga_wgfx(cinfo->regbase, CL_GRA, 0xce); */
1521 /* unlock all extension registers */
1522 vga_wseq(cinfo->regbase, CL_SEQR6, 0x12);
1524 switch (cinfo->btype) {
1526 vga_wseq(cinfo->regbase, CL_SEQRF, 0x98);
1534 vga_wseq(cinfo->regbase, CL_SEQRF, 0xb8);
1538 vga_wseq(cinfo->regbase, CL_SEQR16, 0x0f);
1539 vga_wseq(cinfo->regbase, CL_SEQRF, 0xb0);
1543 /* plane mask: nothing */
1544 vga_wseq(cinfo->regbase, VGA_SEQ_PLANE_WRITE, 0xff);
1545 /* character map select: doesn't even matter in gx mode */
1546 vga_wseq(cinfo->regbase, VGA_SEQ_CHARACTER_MAP, 0x00);
1547 /* memory mode: chain4, ext. memory */
1548 vga_wseq(cinfo->regbase, VGA_SEQ_MEMORY_MODE, 0x0a);
1550 /* controller-internal base address of video memory */
1552 vga_wseq(cinfo->regbase, CL_SEQR7, bi->sr07);
1554 /* vga_wseq(cinfo->regbase, CL_SEQR8, 0x00); */
1555 /* EEPROM control: shouldn't be necessary to write to this at all.. */
1557 /* graphics cursor X position (incomplete; position gives rem. 3 bits */
1558 vga_wseq(cinfo->regbase, CL_SEQR10, 0x00);
1559 /* graphics cursor Y position (..."... ) */
1560 vga_wseq(cinfo->regbase, CL_SEQR11, 0x00);
1561 /* graphics cursor attributes */
1562 vga_wseq(cinfo->regbase, CL_SEQR12, 0x00);
1563 /* graphics cursor pattern address */
1564 vga_wseq(cinfo->regbase, CL_SEQR13, 0x00);
1566 /* writing these on a P4 might give problems.. */
1567 if (cinfo->btype != BT_PICASSO4) {
1568 /* configuration readback and ext. color */
1569 vga_wseq(cinfo->regbase, CL_SEQR17, 0x00);
1570 /* signature generator */
1571 vga_wseq(cinfo->regbase, CL_SEQR18, 0x02);
1574 /* Screen A preset row scan: none */
1575 vga_wcrt(cinfo->regbase, VGA_CRTC_PRESET_ROW, 0x00);
1576 /* Text cursor start: disable text cursor */
1577 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_START, 0x20);
1578 /* Text cursor end: - */
1579 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_END, 0x00);
1580 /* text cursor location high: 0 */
1581 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_HI, 0x00);
1582 /* text cursor location low: 0 */
1583 vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_LO, 0x00);
1585 /* Underline Row scanline: - */
1586 vga_wcrt(cinfo->regbase, VGA_CRTC_UNDERLINE, 0x00);
1587 /* ### add 0x40 for text modes with > 30 MHz pixclock */
1588 /* ext. display controls: ext.adr. wrap */
1589 vga_wcrt(cinfo->regbase, CL_CRT1B, 0x02);
1591 /* Set/Reset registes: - */
1592 vga_wgfx(cinfo->regbase, VGA_GFX_SR_VALUE, 0x00);
1593 /* Set/Reset enable: - */
1594 vga_wgfx(cinfo->regbase, VGA_GFX_SR_ENABLE, 0x00);
1595 /* Color Compare: - */
1596 vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_VALUE, 0x00);
1597 /* Data Rotate: - */
1598 vga_wgfx(cinfo->regbase, VGA_GFX_DATA_ROTATE, 0x00);
1599 /* Read Map Select: - */
1600 vga_wgfx(cinfo->regbase, VGA_GFX_PLANE_READ, 0x00);
1601 /* Mode: conf. for 16/4/2 color mode, no odd/even, read/write mode 0 */
1602 vga_wgfx(cinfo->regbase, VGA_GFX_MODE, 0x00);
1603 /* Miscellaneous: memory map base address, graphics mode */
1604 vga_wgfx(cinfo->regbase, VGA_GFX_MISC, 0x01);
1605 /* Color Don't care: involve all planes */
1606 vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_MASK, 0x0f);
1607 /* Bit Mask: no mask at all */
1608 vga_wgfx(cinfo->regbase, VGA_GFX_BIT_MASK, 0xff);
1610 if (cinfo->btype == BT_ALPINE || cinfo->btype == BT_SD64 ||
1612 /* (5434 can't have bit 3 set for bitblt) */
1613 vga_wgfx(cinfo->regbase, CL_GRB, 0x20);
1615 /* Graphics controller mode extensions: finer granularity,
1616 * 8byte data latches
1618 vga_wgfx(cinfo->regbase, CL_GRB, 0x28);
1620 vga_wgfx(cinfo->regbase, CL_GRC, 0xff); /* Color Key compare: - */
1621 vga_wgfx(cinfo->regbase, CL_GRD, 0x00); /* Color Key compare mask: - */
1622 vga_wgfx(cinfo->regbase, CL_GRE, 0x00); /* Miscellaneous control: - */
1623 /* Background color byte 1: - */
1624 /* vga_wgfx (cinfo->regbase, CL_GR10, 0x00); */
1625 /* vga_wgfx (cinfo->regbase, CL_GR11, 0x00); */
1627 /* Attribute Controller palette registers: "identity mapping" */
1628 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE0, 0x00);
1629 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE1, 0x01);
1630 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE2, 0x02);
1631 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE3, 0x03);
1632 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE4, 0x04);
1633 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE5, 0x05);
1634 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE6, 0x06);
1635 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE7, 0x07);
1636 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE8, 0x08);
1637 vga_wattr(cinfo->regbase, VGA_ATC_PALETTE9, 0x09);
1638 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEA, 0x0a);
1639 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEB, 0x0b);
1640 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEC, 0x0c);
1641 vga_wattr(cinfo->regbase, VGA_ATC_PALETTED, 0x0d);
1642 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEE, 0x0e);
1643 vga_wattr(cinfo->regbase, VGA_ATC_PALETTEF, 0x0f);
1645 /* Attribute Controller mode: graphics mode */
1646 vga_wattr(cinfo->regbase, VGA_ATC_MODE, 0x01);
1647 /* Overscan color reg.: reg. 0 */
1648 vga_wattr(cinfo->regbase, VGA_ATC_OVERSCAN, 0x00);
1649 /* Color Plane enable: Enable all 4 planes */
1650 vga_wattr(cinfo->regbase, VGA_ATC_PLANE_ENABLE, 0x0f);
1651 /* Color Select: - */
1652 vga_wattr(cinfo->regbase, VGA_ATC_COLOR_PAGE, 0x00);
1654 WGen(cinfo, VGA_PEL_MSK, 0xff); /* Pixel mask: no mask */
1656 /* BLT Start/status: Blitter reset */
1657 vga_wgfx(cinfo->regbase, CL_GR31, 0x04);
1658 /* - " - : "end-of-reset" */
1659 vga_wgfx(cinfo->regbase, CL_GR31, 0x00);
1662 WHDR(cinfo, 0); /* Hidden DAC register: - */
1666 static void switch_monitor(struct cirrusfb_info *cinfo, int on)
1668 #ifdef CONFIG_ZORRO /* only works on Zorro boards */
1669 static int IsOn = 0; /* XXX not ok for multiple boards */
1671 if (cinfo->btype == BT_PICASSO4)
1672 return; /* nothing to switch */
1673 if (cinfo->btype == BT_ALPINE)
1674 return; /* nothing to switch */
1675 if (cinfo->btype == BT_GD5480)
1676 return; /* nothing to switch */
1677 if (cinfo->btype == BT_PICASSO) {
1678 if ((on && !IsOn) || (!on && IsOn))
1683 switch (cinfo->btype) {
1685 WSFR(cinfo, cinfo->SFR | 0x21);
1688 WSFR(cinfo, cinfo->SFR | 0x28);
1693 default: /* do nothing */ break;
1696 switch (cinfo->btype) {
1698 WSFR(cinfo, cinfo->SFR & 0xde);
1701 WSFR(cinfo, cinfo->SFR & 0xd7);
1706 default: /* do nothing */
1710 #endif /* CONFIG_ZORRO */
1713 /******************************************/
1714 /* Linux 2.6-style accelerated functions */
1715 /******************************************/
1717 static int cirrusfb_sync(struct fb_info *info)
1719 struct cirrusfb_info *cinfo = info->par;
1721 if (!is_laguna(cinfo)) {
1722 while (vga_rgfx(cinfo->regbase, CL_GR31) & 0x03)
1728 static void cirrusfb_fillrect(struct fb_info *info,
1729 const struct fb_fillrect *region)
1731 struct fb_fillrect modded;
1733 struct cirrusfb_info *cinfo = info->par;
1734 int m = info->var.bits_per_pixel;
1735 u32 color = (info->fix.visual == FB_VISUAL_TRUECOLOR) ?
1736 cinfo->pseudo_palette[region->color] : region->color;
1738 if (info->state != FBINFO_STATE_RUNNING)
1740 if (info->flags & FBINFO_HWACCEL_DISABLED) {
1741 cfb_fillrect(info, region);
1745 vxres = info->var.xres_virtual;
1746 vyres = info->var.yres_virtual;
1748 memcpy(&modded, region, sizeof(struct fb_fillrect));
1750 if (!modded.width || !modded.height ||
1751 modded.dx >= vxres || modded.dy >= vyres)
1754 if (modded.dx + modded.width > vxres)
1755 modded.width = vxres - modded.dx;
1756 if (modded.dy + modded.height > vyres)
1757 modded.height = vyres - modded.dy;
1759 cirrusfb_RectFill(cinfo->regbase,
1760 info->var.bits_per_pixel,
1761 (region->dx * m) / 8, region->dy,
1762 (region->width * m) / 8, region->height,
1764 info->fix.line_length, 0x40);
1767 static void cirrusfb_copyarea(struct fb_info *info,
1768 const struct fb_copyarea *area)
1770 struct fb_copyarea modded;
1772 struct cirrusfb_info *cinfo = info->par;
1773 int m = info->var.bits_per_pixel;
1775 if (info->state != FBINFO_STATE_RUNNING)
1777 if (info->flags & FBINFO_HWACCEL_DISABLED) {
1778 cfb_copyarea(info, area);
1782 vxres = info->var.xres_virtual;
1783 vyres = info->var.yres_virtual;
1784 memcpy(&modded, area, sizeof(struct fb_copyarea));
1786 if (!modded.width || !modded.height ||
1787 modded.sx >= vxres || modded.sy >= vyres ||
1788 modded.dx >= vxres || modded.dy >= vyres)
1791 if (modded.sx + modded.width > vxres)
1792 modded.width = vxres - modded.sx;
1793 if (modded.dx + modded.width > vxres)
1794 modded.width = vxres - modded.dx;
1795 if (modded.sy + modded.height > vyres)
1796 modded.height = vyres - modded.sy;
1797 if (modded.dy + modded.height > vyres)
1798 modded.height = vyres - modded.dy;
1800 cirrusfb_BitBLT(cinfo->regbase, info->var.bits_per_pixel,
1801 (area->sx * m) / 8, area->sy,
1802 (area->dx * m) / 8, area->dy,
1803 (area->width * m) / 8, area->height,
1804 info->fix.line_length);
1808 static void cirrusfb_imageblit(struct fb_info *info,
1809 const struct fb_image *image)
1811 struct cirrusfb_info *cinfo = info->par;
1812 unsigned char op = (info->var.bits_per_pixel == 24) ? 0xc : 0x4;
1814 if (info->state != FBINFO_STATE_RUNNING)
1816 /* Alpine/SD64 does not work at 24bpp ??? */
1817 if (info->flags & FBINFO_HWACCEL_DISABLED || image->depth != 1)
1818 cfb_imageblit(info, image);
1819 else if ((cinfo->btype == BT_ALPINE || cinfo->btype == BT_SD64) &&
1821 cfb_imageblit(info, image);
1823 unsigned size = ((image->width + 7) >> 3) * image->height;
1824 int m = info->var.bits_per_pixel;
1827 if (info->var.bits_per_pixel == 8) {
1828 fg = image->fg_color;
1829 bg = image->bg_color;
1831 fg = ((u32 *)(info->pseudo_palette))[image->fg_color];
1832 bg = ((u32 *)(info->pseudo_palette))[image->bg_color];
1834 if (info->var.bits_per_pixel == 24) {
1835 /* clear background first */
1836 cirrusfb_RectFill(cinfo->regbase,
1837 info->var.bits_per_pixel,
1838 (image->dx * m) / 8, image->dy,
1839 (image->width * m) / 8,
1842 info->fix.line_length, 0x40);
1844 cirrusfb_RectFill(cinfo->regbase,
1845 info->var.bits_per_pixel,
1846 (image->dx * m) / 8, image->dy,
1847 (image->width * m) / 8, image->height,
1849 info->fix.line_length, op);
1850 memcpy(info->screen_base, image->data, size);
1854 #ifdef CONFIG_PPC_PREP
1855 #define PREP_VIDEO_BASE ((volatile unsigned long) 0xC0000000)
1856 #define PREP_IO_BASE ((volatile unsigned char *) 0x80000000)
1857 static void get_prep_addrs(unsigned long *display, unsigned long *registers)
1859 *display = PREP_VIDEO_BASE;
1860 *registers = (unsigned long) PREP_IO_BASE;
1863 #endif /* CONFIG_PPC_PREP */
1866 static int release_io_ports;
1868 /* Pulled the logic from XFree86 Cirrus driver to get the memory size,
1869 * based on the DRAM bandwidth bit and DRAM bank switching bit. This
1870 * works with 1MB, 2MB and 4MB configurations (which the Motorola boards
1872 static unsigned int __devinit cirrusfb_get_memsize(struct fb_info *info,
1873 u8 __iomem *regbase)
1876 struct cirrusfb_info *cinfo = info->par;
1878 if (is_laguna(cinfo)) {
1879 unsigned char SR14 = vga_rseq(regbase, CL_SEQR14);
1881 mem = ((SR14 & 7) + 1) << 20;
1883 unsigned char SRF = vga_rseq(regbase, CL_SEQRF);
1884 switch ((SRF & 0x18)) {
1891 /* 64-bit DRAM data bus width; assume 2MB.
1892 * Also indicates 2MB memory on the 5430.
1898 dev_warn(info->device, "Unknown memory size!\n");
1901 /* If DRAM bank switching is enabled, there must be
1902 * twice as much memory installed. (4MB on the 5434)
1904 if (cinfo->btype != BT_ALPINE && (SRF & 0x80) != 0)
1908 /* TODO: Handling of GD5446/5480 (see XF86 sources ...) */
1912 static void get_pci_addrs(const struct pci_dev *pdev,
1913 unsigned long *display, unsigned long *registers)
1915 assert(pdev != NULL);
1916 assert(display != NULL);
1917 assert(registers != NULL);
1922 /* This is a best-guess for now */
1924 if (pci_resource_flags(pdev, 0) & IORESOURCE_IO) {
1925 *display = pci_resource_start(pdev, 1);
1926 *registers = pci_resource_start(pdev, 0);
1928 *display = pci_resource_start(pdev, 0);
1929 *registers = pci_resource_start(pdev, 1);
1932 assert(*display != 0);
1935 static void cirrusfb_pci_unmap(struct fb_info *info)
1937 struct pci_dev *pdev = to_pci_dev(info->device);
1938 struct cirrusfb_info *cinfo = info->par;
1940 if (cinfo->laguna_mmio == NULL)
1941 iounmap(cinfo->laguna_mmio);
1942 iounmap(info->screen_base);
1943 #if 0 /* if system didn't claim this region, we would... */
1944 release_mem_region(0xA0000, 65535);
1946 if (release_io_ports)
1947 release_region(0x3C0, 32);
1948 pci_release_regions(pdev);
1950 #endif /* CONFIG_PCI */
1953 static void cirrusfb_zorro_unmap(struct fb_info *info)
1955 struct cirrusfb_info *cinfo = info->par;
1956 struct zorro_dev *zdev = to_zorro_dev(info->device);
1958 zorro_release_device(zdev);
1960 if (cinfo->btype == BT_PICASSO4) {
1961 cinfo->regbase -= 0x600000;
1962 iounmap((void *)cinfo->regbase);
1963 iounmap(info->screen_base);
1965 if (zorro_resource_start(zdev) > 0x01000000)
1966 iounmap(info->screen_base);
1969 #endif /* CONFIG_ZORRO */
1971 /* function table of the above functions */
1972 static struct fb_ops cirrusfb_ops = {
1973 .owner = THIS_MODULE,
1974 .fb_open = cirrusfb_open,
1975 .fb_release = cirrusfb_release,
1976 .fb_setcolreg = cirrusfb_setcolreg,
1977 .fb_check_var = cirrusfb_check_var,
1978 .fb_set_par = cirrusfb_set_par,
1979 .fb_pan_display = cirrusfb_pan_display,
1980 .fb_blank = cirrusfb_blank,
1981 .fb_fillrect = cirrusfb_fillrect,
1982 .fb_copyarea = cirrusfb_copyarea,
1983 .fb_sync = cirrusfb_sync,
1984 .fb_imageblit = cirrusfb_imageblit,
1987 static int __devinit cirrusfb_set_fbinfo(struct fb_info *info)
1989 struct cirrusfb_info *cinfo = info->par;
1990 struct fb_var_screeninfo *var = &info->var;
1992 info->pseudo_palette = cinfo->pseudo_palette;
1993 info->flags = FBINFO_DEFAULT
1994 | FBINFO_HWACCEL_XPAN
1995 | FBINFO_HWACCEL_YPAN
1996 | FBINFO_HWACCEL_FILLRECT
1997 | FBINFO_HWACCEL_IMAGEBLIT
1998 | FBINFO_HWACCEL_COPYAREA;
1999 if (noaccel || is_laguna(cinfo)) {
2000 info->flags |= FBINFO_HWACCEL_DISABLED;
2001 info->fix.accel = FB_ACCEL_NONE;
2003 info->fix.accel = FB_ACCEL_CIRRUS_ALPINE;
2005 info->fbops = &cirrusfb_ops;
2007 if (cinfo->btype == BT_GD5480) {
2008 if (var->bits_per_pixel == 16)
2009 info->screen_base += 1 * MB_;
2010 if (var->bits_per_pixel == 32)
2011 info->screen_base += 2 * MB_;
2014 /* Fill fix common fields */
2015 strlcpy(info->fix.id, cirrusfb_board_info[cinfo->btype].name,
2016 sizeof(info->fix.id));
2018 /* monochrome: only 1 memory plane */
2019 /* 8 bit and above: Use whole memory area */
2020 info->fix.smem_len = info->screen_size;
2021 if (var->bits_per_pixel == 1)
2022 info->fix.smem_len /= 4;
2023 info->fix.type_aux = 0;
2024 info->fix.xpanstep = 1;
2025 info->fix.ypanstep = 1;
2026 info->fix.ywrapstep = 0;
2028 /* FIXME: map region at 0xB8000 if available, fill in here */
2029 info->fix.mmio_len = 0;
2031 fb_alloc_cmap(&info->cmap, 256, 0);
2036 static int __devinit cirrusfb_register(struct fb_info *info)
2038 struct cirrusfb_info *cinfo = info->par;
2042 assert(cinfo->btype != BT_NONE);
2044 /* set all the vital stuff */
2045 cirrusfb_set_fbinfo(info);
2047 dev_dbg(info->device, "(RAM start set to: 0x%p)\n", info->screen_base);
2049 err = fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 8);
2051 dev_dbg(info->device, "wrong initial video mode\n");
2053 goto err_dealloc_cmap;
2056 info->var.activate = FB_ACTIVATE_NOW;
2058 err = cirrusfb_check_var(&info->var, info);
2060 /* should never happen */
2061 dev_dbg(info->device,
2062 "choking on default var... umm, no good.\n");
2063 goto err_dealloc_cmap;
2066 err = register_framebuffer(info);
2068 dev_err(info->device,
2069 "could not register fb device; err = %d!\n", err);
2070 goto err_dealloc_cmap;
2076 fb_dealloc_cmap(&info->cmap);
2080 static void __devexit cirrusfb_cleanup(struct fb_info *info)
2082 struct cirrusfb_info *cinfo = info->par;
2084 switch_monitor(cinfo, 0);
2085 unregister_framebuffer(info);
2086 fb_dealloc_cmap(&info->cmap);
2087 dev_dbg(info->device, "Framebuffer unregistered\n");
2089 framebuffer_release(info);
2093 static int __devinit cirrusfb_pci_register(struct pci_dev *pdev,
2094 const struct pci_device_id *ent)
2096 struct cirrusfb_info *cinfo;
2097 struct fb_info *info;
2098 unsigned long board_addr, board_size;
2101 ret = pci_enable_device(pdev);
2103 printk(KERN_ERR "cirrusfb: Cannot enable PCI device\n");
2107 info = framebuffer_alloc(sizeof(struct cirrusfb_info), &pdev->dev);
2109 printk(KERN_ERR "cirrusfb: could not allocate memory\n");
2115 cinfo->btype = (enum cirrus_board) ent->driver_data;
2117 dev_dbg(info->device,
2118 " Found PCI device, base address 0 is 0x%Lx, btype set to %d\n",
2119 (unsigned long long)pdev->resource[0].start, cinfo->btype);
2120 dev_dbg(info->device, " base address 1 is 0x%Lx\n",
2121 (unsigned long long)pdev->resource[1].start);
2124 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, 0x00000000);
2125 #ifdef CONFIG_PPC_PREP
2126 get_prep_addrs(&board_addr, &info->fix.mmio_start);
2128 /* PReP dies if we ioremap the IO registers, but it works w/out... */
2129 cinfo->regbase = (char __iomem *) info->fix.mmio_start;
2131 dev_dbg(info->device,
2132 "Attempt to get PCI info for Cirrus Graphics Card\n");
2133 get_pci_addrs(pdev, &board_addr, &info->fix.mmio_start);
2134 /* FIXME: this forces VGA. alternatives? */
2135 cinfo->regbase = NULL;
2136 cinfo->laguna_mmio = ioremap(info->fix.mmio_start, 0x1000);
2139 dev_dbg(info->device, "Board address: 0x%lx, register address: 0x%lx\n",
2140 board_addr, info->fix.mmio_start);
2142 board_size = (cinfo->btype == BT_GD5480) ?
2143 32 * MB_ : cirrusfb_get_memsize(info, cinfo->regbase);
2145 ret = pci_request_regions(pdev, "cirrusfb");
2147 dev_err(info->device, "cannot reserve region 0x%lx, abort\n",
2149 goto err_release_fb;
2151 #if 0 /* if the system didn't claim this region, we would... */
2152 if (!request_mem_region(0xA0000, 65535, "cirrusfb")) {
2153 dev_err(info->device, "cannot reserve region 0x%lx, abort\n",
2156 goto err_release_regions;
2159 if (request_region(0x3C0, 32, "cirrusfb"))
2160 release_io_ports = 1;
2162 info->screen_base = ioremap(board_addr, board_size);
2163 if (!info->screen_base) {
2165 goto err_release_legacy;
2168 info->fix.smem_start = board_addr;
2169 info->screen_size = board_size;
2170 cinfo->unmap = cirrusfb_pci_unmap;
2172 dev_info(info->device,
2173 "Cirrus Logic chipset on PCI bus, RAM (%lu kB) at 0x%lx\n",
2174 info->screen_size >> 10, board_addr);
2175 pci_set_drvdata(pdev, info);
2177 ret = cirrusfb_register(info);
2181 pci_set_drvdata(pdev, NULL);
2182 iounmap(info->screen_base);
2184 if (release_io_ports)
2185 release_region(0x3C0, 32);
2187 release_mem_region(0xA0000, 65535);
2188 err_release_regions:
2190 pci_release_regions(pdev);
2192 if (cinfo->laguna_mmio != NULL)
2193 iounmap(cinfo->laguna_mmio);
2194 framebuffer_release(info);
2199 static void __devexit cirrusfb_pci_unregister(struct pci_dev *pdev)
2201 struct fb_info *info = pci_get_drvdata(pdev);
2203 cirrusfb_cleanup(info);
2206 static struct pci_driver cirrusfb_pci_driver = {
2208 .id_table = cirrusfb_pci_table,
2209 .probe = cirrusfb_pci_register,
2210 .remove = __devexit_p(cirrusfb_pci_unregister),
2213 .suspend = cirrusfb_pci_suspend,
2214 .resume = cirrusfb_pci_resume,
2218 #endif /* CONFIG_PCI */
2221 static int __devinit cirrusfb_zorro_register(struct zorro_dev *z,
2222 const struct zorro_device_id *ent)
2224 struct cirrusfb_info *cinfo;
2225 struct fb_info *info;
2226 enum cirrus_board btype;
2227 struct zorro_dev *z2 = NULL;
2228 unsigned long board_addr, board_size, size;
2231 btype = ent->driver_data;
2232 if (cirrusfb_zorro_table2[btype].id2)
2233 z2 = zorro_find_device(cirrusfb_zorro_table2[btype].id2, NULL);
2234 size = cirrusfb_zorro_table2[btype].size;
2236 info = framebuffer_alloc(sizeof(struct cirrusfb_info), &z->dev);
2238 printk(KERN_ERR "cirrusfb: could not allocate memory\n");
2243 dev_info(info->device, "%s board detected\n",
2244 cirrusfb_board_info[btype].name);
2247 cinfo->btype = btype;
2250 assert(btype != BT_NONE);
2252 board_addr = zorro_resource_start(z);
2253 board_size = zorro_resource_len(z);
2254 info->screen_size = size;
2256 if (!zorro_request_device(z, "cirrusfb")) {
2257 dev_err(info->device, "cannot reserve region 0x%lx, abort\n",
2260 goto err_release_fb;
2265 if (btype == BT_PICASSO4) {
2266 dev_info(info->device, " REG at $%lx\n", board_addr + 0x600000);
2268 /* To be precise, for the P4 this is not the */
2269 /* begin of the board, but the begin of RAM. */
2270 /* for P4, map in its address space in 2 chunks (### TEST! ) */
2271 /* (note the ugly hardcoded 16M number) */
2272 cinfo->regbase = ioremap(board_addr, 16777216);
2273 if (!cinfo->regbase)
2274 goto err_release_region;
2276 dev_dbg(info->device, "Virtual address for board set to: $%p\n",
2278 cinfo->regbase += 0x600000;
2279 info->fix.mmio_start = board_addr + 0x600000;
2281 info->fix.smem_start = board_addr + 16777216;
2282 info->screen_base = ioremap(info->fix.smem_start, 16777216);
2283 if (!info->screen_base)
2284 goto err_unmap_regbase;
2286 dev_info(info->device, " REG at $%lx\n",
2287 (unsigned long) z2->resource.start);
2289 info->fix.smem_start = board_addr;
2290 if (board_addr > 0x01000000)
2291 info->screen_base = ioremap(board_addr, board_size);
2293 info->screen_base = (caddr_t) ZTWO_VADDR(board_addr);
2294 if (!info->screen_base)
2295 goto err_release_region;
2297 /* set address for REG area of board */
2298 cinfo->regbase = (caddr_t) ZTWO_VADDR(z2->resource.start);
2299 info->fix.mmio_start = z2->resource.start;
2301 dev_dbg(info->device, "Virtual address for board set to: $%p\n",
2304 cinfo->unmap = cirrusfb_zorro_unmap;
2306 dev_info(info->device,
2307 "Cirrus Logic chipset on Zorro bus, RAM (%lu MB) at $%lx\n",
2308 board_size / MB_, board_addr);
2310 zorro_set_drvdata(z, info);
2312 /* MCLK select etc. */
2313 if (cirrusfb_board_info[btype].init_sr1f)
2314 vga_wseq(cinfo->regbase, CL_SEQR1F,
2315 cirrusfb_board_info[btype].sr1f);
2317 ret = cirrusfb_register(info);
2321 if (btype == BT_PICASSO4 || board_addr > 0x01000000)
2322 iounmap(info->screen_base);
2325 if (btype == BT_PICASSO4)
2326 iounmap(cinfo->regbase - 0x600000);
2328 release_region(board_addr, board_size);
2330 framebuffer_release(info);
2335 void __devexit cirrusfb_zorro_unregister(struct zorro_dev *z)
2337 struct fb_info *info = zorro_get_drvdata(z);
2339 cirrusfb_cleanup(info);
2342 static struct zorro_driver cirrusfb_zorro_driver = {
2344 .id_table = cirrusfb_zorro_table,
2345 .probe = cirrusfb_zorro_register,
2346 .remove = __devexit_p(cirrusfb_zorro_unregister),
2348 #endif /* CONFIG_ZORRO */
2351 static int __init cirrusfb_setup(char *options)
2355 if (!options || !*options)
2358 while ((this_opt = strsep(&options, ",")) != NULL) {
2362 if (!strcmp(this_opt, "noaccel"))
2364 else if (!strncmp(this_opt, "mode:", 5))
2365 mode_option = this_opt + 5;
2367 mode_option = this_opt;
2377 MODULE_AUTHOR("Copyright 1999,2000 Jeff Garzik <jgarzik@pobox.com>");
2378 MODULE_DESCRIPTION("Accelerated FBDev driver for Cirrus Logic chips");
2379 MODULE_LICENSE("GPL");
2381 static int __init cirrusfb_init(void)
2386 char *option = NULL;
2388 if (fb_get_options("cirrusfb", &option))
2390 cirrusfb_setup(option);
2394 error |= zorro_register_driver(&cirrusfb_zorro_driver);
2397 error |= pci_register_driver(&cirrusfb_pci_driver);
2402 static void __exit cirrusfb_exit(void)
2405 pci_unregister_driver(&cirrusfb_pci_driver);
2408 zorro_unregister_driver(&cirrusfb_zorro_driver);
2412 module_init(cirrusfb_init);
2414 module_param(mode_option, charp, 0);
2415 MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'");
2416 module_param(noaccel, bool, 0);
2417 MODULE_PARM_DESC(noaccel, "Disable acceleration");
2420 module_exit(cirrusfb_exit);
2423 /**********************************************************************/
2424 /* about the following functions - I have used the same names for the */
2425 /* functions as Markus Wild did in his Retina driver for NetBSD as */
2426 /* they just made sense for this purpose. Apart from that, I wrote */
2427 /* these functions myself. */
2428 /**********************************************************************/
2430 /*** WGen() - write into one of the external/general registers ***/
2431 static void WGen(const struct cirrusfb_info *cinfo,
2432 int regnum, unsigned char val)
2434 unsigned long regofs = 0;
2436 if (cinfo->btype == BT_PICASSO) {
2437 /* Picasso II specific hack */
2438 /* if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D ||
2439 regnum == CL_VSSM2) */
2440 if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D)
2444 vga_w(cinfo->regbase, regofs + regnum, val);
2447 /*** RGen() - read out one of the external/general registers ***/
2448 static unsigned char RGen(const struct cirrusfb_info *cinfo, int regnum)
2450 unsigned long regofs = 0;
2452 if (cinfo->btype == BT_PICASSO) {
2453 /* Picasso II specific hack */
2454 /* if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D ||
2455 regnum == CL_VSSM2) */
2456 if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D)
2460 return vga_r(cinfo->regbase, regofs + regnum);
2463 /*** AttrOn() - turn on VideoEnable for Attribute controller ***/
2464 static void AttrOn(const struct cirrusfb_info *cinfo)
2466 assert(cinfo != NULL);
2468 if (vga_rcrt(cinfo->regbase, CL_CRT24) & 0x80) {
2469 /* if we're just in "write value" mode, write back the */
2470 /* same value as before to not modify anything */
2471 vga_w(cinfo->regbase, VGA_ATT_IW,
2472 vga_r(cinfo->regbase, VGA_ATT_R));
2474 /* turn on video bit */
2475 /* vga_w(cinfo->regbase, VGA_ATT_IW, 0x20); */
2476 vga_w(cinfo->regbase, VGA_ATT_IW, 0x33);
2478 /* dummy write on Reg0 to be on "write index" mode next time */
2479 vga_w(cinfo->regbase, VGA_ATT_IW, 0x00);
2482 /*** WHDR() - write into the Hidden DAC register ***/
2483 /* as the HDR is the only extension register that requires special treatment
2484 * (the other extension registers are accessible just like the "ordinary"
2485 * registers of their functional group) here is a specialized routine for
2488 static void WHDR(const struct cirrusfb_info *cinfo, unsigned char val)
2490 unsigned char dummy;
2492 if (is_laguna(cinfo))
2494 if (cinfo->btype == BT_PICASSO) {
2495 /* Klaus' hint for correct access to HDR on some boards */
2496 /* first write 0 to pixel mask (3c6) */
2497 WGen(cinfo, VGA_PEL_MSK, 0x00);
2499 /* next read dummy from pixel address (3c8) */
2500 dummy = RGen(cinfo, VGA_PEL_IW);
2503 /* now do the usual stuff to access the HDR */
2505 dummy = RGen(cinfo, VGA_PEL_MSK);
2507 dummy = RGen(cinfo, VGA_PEL_MSK);
2509 dummy = RGen(cinfo, VGA_PEL_MSK);
2511 dummy = RGen(cinfo, VGA_PEL_MSK);
2514 WGen(cinfo, VGA_PEL_MSK, val);
2517 if (cinfo->btype == BT_PICASSO) {
2518 /* now first reset HDR access counter */
2519 dummy = RGen(cinfo, VGA_PEL_IW);
2522 /* and at the end, restore the mask value */
2523 /* ## is this mask always 0xff? */
2524 WGen(cinfo, VGA_PEL_MSK, 0xff);
2529 /*** WSFR() - write to the "special function register" (SFR) ***/
2530 static void WSFR(struct cirrusfb_info *cinfo, unsigned char val)
2533 assert(cinfo->regbase != NULL);
2535 z_writeb(val, cinfo->regbase + 0x8000);
2539 /* The Picasso has a second register for switching the monitor bit */
2540 static void WSFR2(struct cirrusfb_info *cinfo, unsigned char val)
2543 /* writing an arbitrary value to this one causes the monitor switcher */
2544 /* to flip to Amiga display */
2545 assert(cinfo->regbase != NULL);
2547 z_writeb(val, cinfo->regbase + 0x9000);
2551 /*** WClut - set CLUT entry (range: 0..63) ***/
2552 static void WClut(struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char red,
2553 unsigned char green, unsigned char blue)
2555 unsigned int data = VGA_PEL_D;
2557 /* address write mode register is not translated.. */
2558 vga_w(cinfo->regbase, VGA_PEL_IW, regnum);
2560 if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 ||
2561 cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480 ||
2562 cinfo->btype == BT_SD64 || is_laguna(cinfo)) {
2563 /* but DAC data register IS, at least for Picasso II */
2564 if (cinfo->btype == BT_PICASSO)
2566 vga_w(cinfo->regbase, data, red);
2567 vga_w(cinfo->regbase, data, green);
2568 vga_w(cinfo->regbase, data, blue);
2570 vga_w(cinfo->regbase, data, blue);
2571 vga_w(cinfo->regbase, data, green);
2572 vga_w(cinfo->regbase, data, red);
2577 /*** RClut - read CLUT entry (range 0..63) ***/
2578 static void RClut(struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char *red,
2579 unsigned char *green, unsigned char *blue)
2581 unsigned int data = VGA_PEL_D;
2583 vga_w(cinfo->regbase, VGA_PEL_IR, regnum);
2585 if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 ||
2586 cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480) {
2587 if (cinfo->btype == BT_PICASSO)
2589 *red = vga_r(cinfo->regbase, data);
2590 *green = vga_r(cinfo->regbase, data);
2591 *blue = vga_r(cinfo->regbase, data);
2593 *blue = vga_r(cinfo->regbase, data);
2594 *green = vga_r(cinfo->regbase, data);
2595 *red = vga_r(cinfo->regbase, data);
2600 /*******************************************************************
2603 Wait for the BitBLT engine to complete a possible earlier job
2604 *********************************************************************/
2606 /* FIXME: use interrupts instead */
2607 static void cirrusfb_WaitBLT(u8 __iomem *regbase)
2609 while (vga_rgfx(regbase, CL_GR31) & 0x08)
2613 /*******************************************************************
2616 perform accelerated "scrolling"
2617 ********************************************************************/
2619 static void cirrusfb_set_blitter(u8 __iomem *regbase,
2620 u_short nwidth, u_short nheight,
2621 u_long nsrc, u_long ndest,
2622 u_short bltmode, u_short line_length)
2625 /* pitch: set to line_length */
2626 /* dest pitch low */
2627 vga_wgfx(regbase, CL_GR24, line_length & 0xff);
2629 vga_wgfx(regbase, CL_GR25, line_length >> 8);
2630 /* source pitch low */
2631 vga_wgfx(regbase, CL_GR26, line_length & 0xff);
2632 /* source pitch hi */
2633 vga_wgfx(regbase, CL_GR27, line_length >> 8);
2635 /* BLT width: actual number of pixels - 1 */
2637 vga_wgfx(regbase, CL_GR20, nwidth & 0xff);
2639 vga_wgfx(regbase, CL_GR21, nwidth >> 8);
2641 /* BLT height: actual number of lines -1 */
2642 /* BLT height low */
2643 vga_wgfx(regbase, CL_GR22, nheight & 0xff);
2645 vga_wgfx(regbase, CL_GR23, nheight >> 8);
2647 /* BLT destination */
2649 vga_wgfx(regbase, CL_GR28, (u_char) (ndest & 0xff));
2651 vga_wgfx(regbase, CL_GR29, (u_char) (ndest >> 8));
2653 vga_wgfx(regbase, CL_GR2A, (u_char) (ndest >> 16));
2657 vga_wgfx(regbase, CL_GR2C, (u_char) (nsrc & 0xff));
2659 vga_wgfx(regbase, CL_GR2D, (u_char) (nsrc >> 8));
2661 vga_wgfx(regbase, CL_GR2E, (u_char) (nsrc >> 16));
2664 vga_wgfx(regbase, CL_GR30, bltmode); /* BLT mode */
2666 /* BLT ROP: SrcCopy */
2667 vga_wgfx(regbase, CL_GR32, 0x0d); /* BLT ROP */
2669 /* and finally: GO! */
2670 vga_wgfx(regbase, CL_GR31, 0x02); /* BLT Start/status */
2673 /*******************************************************************
2676 perform accelerated "scrolling"
2677 ********************************************************************/
2679 static void cirrusfb_BitBLT(u8 __iomem *regbase, int bits_per_pixel,
2680 u_short curx, u_short cury,
2681 u_short destx, u_short desty,
2682 u_short width, u_short height,
2683 u_short line_length)
2685 u_short nwidth = width - 1;
2686 u_short nheight = height - 1;
2691 /* if source adr < dest addr, do the Blt backwards */
2692 if (cury <= desty) {
2693 if (cury == desty) {
2694 /* if src and dest are on the same line, check x */
2700 /* standard case: forward blitting */
2701 nsrc = (cury * line_length) + curx;
2702 ndest = (desty * line_length) + destx;
2704 /* this means start addresses are at the end,
2705 * counting backwards
2707 nsrc += nheight * line_length + nwidth;
2708 ndest += nheight * line_length + nwidth;
2711 cirrusfb_WaitBLT(regbase);
2713 cirrusfb_set_blitter(regbase, nwidth, nheight,
2714 nsrc, ndest, bltmode, line_length);
2717 /*******************************************************************
2720 perform accelerated rectangle fill
2721 ********************************************************************/
2723 static void cirrusfb_RectFill(u8 __iomem *regbase, int bits_per_pixel,
2724 u_short x, u_short y, u_short width, u_short height,
2725 u32 fg_color, u32 bg_color, u_short line_length,
2728 u_long ndest = (y * line_length) + x;
2731 cirrusfb_WaitBLT(regbase);
2733 /* This is a ColorExpand Blt, using the */
2734 /* same color for foreground and background */
2735 vga_wgfx(regbase, VGA_GFX_SR_VALUE, bg_color);
2736 vga_wgfx(regbase, VGA_GFX_SR_ENABLE, fg_color);
2739 if (bits_per_pixel >= 16) {
2740 vga_wgfx(regbase, CL_GR10, bg_color >> 8);
2741 vga_wgfx(regbase, CL_GR11, fg_color >> 8);
2744 if (bits_per_pixel >= 24) {
2745 vga_wgfx(regbase, CL_GR12, bg_color >> 16);
2746 vga_wgfx(regbase, CL_GR13, fg_color >> 16);
2749 if (bits_per_pixel == 32) {
2750 vga_wgfx(regbase, CL_GR14, bg_color >> 24);
2751 vga_wgfx(regbase, CL_GR15, fg_color >> 24);
2754 cirrusfb_set_blitter(regbase, width - 1, height - 1,
2755 0, ndest, op | blitmode, line_length);
2758 /**************************************************************************
2759 * bestclock() - determine closest possible clock lower(?) than the
2760 * desired pixel clock
2761 **************************************************************************/
2762 static void bestclock(long freq, int *nom, int *den, int *div)
2767 assert(nom != NULL);
2768 assert(den != NULL);
2769 assert(div != NULL);
2780 for (n = 32; n < 128; n++) {
2783 d = (14318 * n) / freq;
2784 if ((d >= 7) && (d <= 63)) {
2791 h = ((14318 * n) / temp) >> s;
2792 h = h > freq ? h - freq : freq - h;
2801 if ((d >= 7) && (d <= 63)) {
2806 h = ((14318 * n) / d) >> s;
2807 h = h > freq ? h - freq : freq - h;
2818 /* -------------------------------------------------------------------------
2820 * debugging functions
2822 * -------------------------------------------------------------------------
2825 #ifdef CIRRUSFB_DEBUG
2828 * cirrusfb_dbg_print_regs
2829 * @base: If using newmmio, the newmmio base address, otherwise %NULL
2830 * @reg_class: type of registers to read: %CRT, or %SEQ
2833 * Dumps the given list of VGA CRTC registers. If @base is %NULL,
2834 * old-style I/O ports are queried for information, otherwise MMIO is
2835 * used at the given @base address to query the information.
2838 static void cirrusfb_dbg_print_regs(struct fb_info *info,
2840 enum cirrusfb_dbg_reg_class reg_class, ...)
2843 unsigned char val = 0;
2847 va_start(list, reg_class);
2849 name = va_arg(list, char *);
2850 while (name != NULL) {
2851 reg = va_arg(list, int);
2853 switch (reg_class) {
2855 val = vga_rcrt(regbase, (unsigned char) reg);
2858 val = vga_rseq(regbase, (unsigned char) reg);
2861 /* should never occur */
2866 dev_dbg(info->device, "%8s = 0x%02X\n", name, val);
2868 name = va_arg(list, char *);
2875 * cirrusfb_dbg_reg_dump
2876 * @base: If using newmmio, the newmmio base address, otherwise %NULL
2879 * Dumps a list of interesting VGA and CIRRUSFB registers. If @base is %NULL,
2880 * old-style I/O ports are queried for information, otherwise MMIO is
2881 * used at the given @base address to query the information.
2884 static void cirrusfb_dbg_reg_dump(struct fb_info *info, caddr_t regbase)
2886 dev_dbg(info->device, "VGA CRTC register dump:\n");
2888 cirrusfb_dbg_print_regs(info, regbase, CRT,
2938 dev_dbg(info->device, "\n");
2940 dev_dbg(info->device, "VGA SEQ register dump:\n");
2942 cirrusfb_dbg_print_regs(info, regbase, SEQ,
2971 dev_dbg(info->device, "\n");
2974 #endif /* CIRRUSFB_DEBUG */