drivers/video/display/screen/lcd_b101ew05.c

   1
   2 #include <linux/delay.h>
   3 #include <linux/rk_fb.h>
   4 #include <mach/gpio.h>
   5 #include <mach/iomux.h>
   6 #include <mach/board.h>
   7 #if defined(CONFIG_RK_HDMI)
   8 #include "../../rockchip/hdmi/rk_hdmi.h"
   9 #endif
  10
  11
  12 #if  defined(CONFIG_RK610_LVDS) || defined(CONFIG_RK616_VIF)
  13 #include "../transmitter/rk610_lcd.h"
  14 #endif
  15
  16
  17 /* Base */
  18 #if  defined(CONFIG_RK610_LVDS) || defined(CONFIG_RK616_VIF)
  19 #define OUT_TYPE                SCREEN_LVDS
  20 #define LVDS_FORMAT             LVDS_8BIT_2
  21 #else
  22 #define OUT_TYPE            SCREEN_RGB
  23 #endif
  24
  25 #define OUT_FACE            OUT_D888_P666
  26
  27
  28 #define OUT_CLK           71000000
  29 #define LCDC_ACLK         300000000           //29 lcdc axi DMA ÆµÂÊ
  30
  31 /* Timing */
  32 #define H_PW                    10
  33 #define H_BP                    100
  34 #define H_VD                    1280
  35 #define H_FP                    18
  36
  37 #define V_PW                    2
  38 #define V_BP                    8
  39 #define V_VD                    800
  40 #define V_FP                    6
  41
  42 #define LCD_WIDTH               216
  43 #define LCD_HEIGHT              135
  44 /* Other */
  45 #if defined(CONFIG_RK610_LVDS) || defined(CONFIG_RK616_VIF)
  46 #define DCLK_POL        1
  47 #else
  48 #define DCLK_POL        0
  49 #endif
  50 #define DEN_POL         0
  51 #define VSYNC_POL       0
  52 #define HSYNC_POL       0
  53
  54 #define SWAP_RB         0
  55 #define SWAP_RG         0
  56 #define SWAP_GB         0
  57
  58 int dsp_lut[256] ={
  59                 0x00000000, 0x00010101, 0x00020202, 0x00030303, 0x00040404, 0x00050505, 0x00060606, 0x00070707,
  60                 0x00080808, 0x00090909, 0x000a0a0a, 0x000b0b0b, 0x000c0c0c, 0x000d0d0d, 0x000e0e0e, 0x000f0f0f,
  61                 0x00101010, 0x00111111, 0x00121212, 0x00131313, 0x00141414, 0x00151515, 0x00161616, 0x00171717,
  62                 0x00181818, 0x00191919, 0x001a1a1a, 0x001b1b1b, 0x001c1c1c, 0x001d1d1d, 0x001e1e1e, 0x001f1f1f,
  63                 0x00202020, 0x00212121, 0x00222222, 0x00232323, 0x00242424, 0x00252525, 0x00262626, 0x00272727,
  64                 0x00282828, 0x00292929, 0x002a2a2a, 0x002b2b2b, 0x002c2c2c, 0x002d2d2d, 0x002e2e2e, 0x002f2f2f,
  65                 0x00303030, 0x00313131, 0x00323232, 0x00333333, 0x00343434, 0x00353535, 0x00363636, 0x00373737,
  66                 0x00383838, 0x00393939, 0x003a3a3a, 0x003b3b3b, 0x003c3c3c, 0x003d3d3d, 0x003e3e3e, 0x003f3f3f,
  67                 0x00404040, 0x00414141, 0x00424242, 0x00434343, 0x00444444, 0x00454545, 0x00464646, 0x00474747,
  68                 0x00484848, 0x00494949, 0x004a4a4a, 0x004b4b4b, 0x004c4c4c, 0x004d4d4d, 0x004e4e4e, 0x004f4f4f,
  69                 0x00505050, 0x00515151, 0x00525252, 0x00535353, 0x00545454, 0x00555555, 0x00565656, 0x00575757,
  70                 0x00585858, 0x00595959, 0x005a5a5a, 0x005b5b5b, 0x005c5c5c, 0x005d5d5d, 0x005e5e5e, 0x005f5f5f,
  71                 0x00606060, 0x00616161, 0x00626262, 0x00636363, 0x00646464, 0x00656565, 0x00666666, 0x00676767,
  72                 0x00686868, 0x00696969, 0x006a6a6a, 0x006b6b6b, 0x006c6c6c, 0x006d6d6d, 0x006e6e6e, 0x006f6f6f,
  73                 0x00707070, 0x00717171, 0x00727272, 0x00737373, 0x00747474, 0x00757575, 0x00767676, 0x00777777,
  74                 0x00787878, 0x00797979, 0x007a7a7a, 0x007b7b7b, 0x007c7c7c, 0x007d7d7d, 0x007e7e7e, 0x007f7f7f,
  75                 0x00808080, 0x00818181, 0x00828282, 0x00838383, 0x00848484, 0x00858585, 0x00868686, 0x00878787,
  76                 0x00888888, 0x00898989, 0x008a8a8a, 0x008b8b8b, 0x008c8c8c, 0x008d8d8d, 0x008e8e8e, 0x008f8f8f,
  77                 0x00909090, 0x00919191, 0x00929292, 0x00939393, 0x00949494, 0x00959595, 0x00969696, 0x00979797,
  78                 0x00989898, 0x00999999, 0x009a9a9a, 0x009b9b9b, 0x009c9c9c, 0x009d9d9d, 0x009e9e9e, 0x009f9f9f,
  79                 0x00a0a0a0, 0x00a1a1a1, 0x00a2a2a2, 0x00a3a3a3, 0x00a4a4a4, 0x00a5a5a5, 0x00a6a6a6, 0x00a7a7a7,
  80                 0x00a8a8a8, 0x00a9a9a9, 0x00aaaaaa, 0x00ababab, 0x00acacac, 0x00adadad, 0x00aeaeae, 0x00afafaf,
  81                 0x00b0b0b0, 0x00b1b1b1, 0x00b2b2b2, 0x00b3b3b3, 0x00b4b4b4, 0x00b5b5b5, 0x00b6b6b6, 0x00b7b7b7,
  82                 0x00b8b8b8, 0x00b9b9b9, 0x00bababa, 0x00bbbbbb, 0x00bcbcbc, 0x00bdbdbd, 0x00bebebe, 0x00bfbfbf,
  83                 0x00c0c0c0, 0x00c1c1c1, 0x00c2c2c2, 0x00c3c3c3, 0x00c4c4c4, 0x00c5c5c5, 0x00c6c6c6, 0x00c7c7c7,
  84                 0x00c8c8c8, 0x00c9c9c9, 0x00cacaca, 0x00cbcbcb, 0x00cccccc, 0x00cdcdcd, 0x00cecece, 0x00cfcfcf,
  85                 0x00d0d0d0, 0x00d1d1d1, 0x00d2d2d2, 0x00d3d3d3, 0x00d4d4d4, 0x00d5d5d5, 0x00d6d6d6, 0x00d7d7d7,
  86                 0x00d8d8d8, 0x00d9d9d9, 0x00dadada, 0x00dbdbdb, 0x00dcdcdc, 0x00dddddd, 0x00dedede, 0x00dfdfdf,
  87                 0x00e0e0e0, 0x00e1e1e1, 0x00e2e2e2, 0x00e3e3e3, 0x00e4e4e4, 0x00e5e5e5, 0x00e6e6e6, 0x00e7e7e7,
  88                 0x00e8e8e8, 0x00e9e9e9, 0x00eaeaea, 0x00ebebeb, 0x00ececec, 0x00ededed, 0x00eeeeee, 0x00efefef,
  89                 0x00f0f0f0, 0x00f1f1f1, 0x00f2f2f2, 0x00f3f3f3, 0x00f4f4f4, 0x00f5f5f5, 0x00f6f6f6, 0x00f7f7f7,
  90                 0x00f8f8f8, 0x00f9f9f9, 0x00fafafa, 0x00fbfbfb, 0x00fcfcfc, 0x00fdfdfd, 0x00fefefe, 0x00ffffff,
  91 };
  92
  93 #if  defined(CONFIG_ONE_LCDC_DUAL_OUTPUT_INF)&& ( defined(CONFIG_RK610_LVDS) || defined(CONFIG_RK616_VIF))
  94
  95 /* scaler Timing    */
  96 //1920*1080*60
  97
  98 #define S_OUT_CLK               SCALE_RATE(148500000,74250000) //m=16 n=9 no=4
  99 #define S_H_PW                  48
 100 #define S_H_BP                  98
 101 #define S_H_VD                  1280
 102 #define S_H_FP                  59
 103
 104 #define S_V_PW                  6
 105 #define S_V_BP                  25
 106 #define S_V_VD                  800
 107 #define S_V_FP                  2
 108
 109 #define S_H_ST                  495
 110 #define S_V_ST                  2
 111
 112 #define S_PLL_CFG_VAL           0x01842016
 113 #define S_FRAC                  0xc16c2d
 114 #define S_SCL_VST               0x25
 115 #define S_SCL_HST               0x4ba
 116 #define S_VIF_VST               0x1
 117 #define S_VIF_HST               0xca
 118
 119 //1920*1080*50
 120 #define S1_OUT_CLK              SCALE_RATE(148500000,57375000)  //m=17 n=11 no=4
 121 #define S1_H_PW                 10
 122 #define S1_H_BP                 10
 123 #define S1_H_VD                 1280
 124 #define S1_H_FP                 77
 125
 126 #define S1_V_PW                 10
 127 #define S1_V_BP                 10
 128 #define S1_V_VD                 800
 129 #define S1_V_FP                 13
 130
 131 #define S1_H_ST                 459
 132 #define S1_V_ST                 13
 133
 134 #define S1_PLL_CFG_VAL          0x01c42016
 135 #define S1_FRAC                 0x1f9ad4
 136 #define S1_SCL_VST              0x25
 137 #define S1_SCL_HST              0x5ab
 138 #define S1_VIF_VST              0x1
 139 #define S1_VIF_HST              0xca
 140
 141
 142 //1280*720*60
 143 #define S2_OUT_CLK              SCALE_RATE(74250000,74250000)  //m=32 n=9 no=4
 144 #define S2_H_PW                 48
 145 #define S2_H_BP                 98
 146 #define S2_H_VD                 1280
 147 #define S2_H_FP                 59
 148
 149 #define S2_V_PW                 6
 150 #define S2_V_BP                 25
 151 #define S2_V_VD                 800
 152 #define S2_V_FP                 2
 153
 154 #define S2_H_ST                 495
 155 #define S2_V_ST                 5
 156
 157
 158 //bellow are for jettaB
 159 #define S2_PLL_CFG_VAL          0x01822016
 160 #define S2_FRAC                 0xc16c2d
 161 #define S2_SCL_VST              0x19
 162 #define S2_SCL_HST              0x483
 163 #define S2_VIF_VST              0x1
 164 #define S2_VIF_HST              0xcf
 165
 166
 167 //1280*720*50
 168
 169 #define S3_OUT_CLK              SCALE_RATE(74250000,67500000)   // m=34 n=11 no=4
 170 #define S3_H_PW                 48
 171 #define S3_H_BP                 233
 172 #define S3_H_VD                 1280
 173 #define S3_H_FP                 59
 174
 175 #define S3_V_PW                 6
 176 #define S3_V_BP                 25
 177 #define S3_V_VD                 800
 178 #define S3_V_FP                 2
 179
 180 #define S3_H_ST                 540
 181 #define S3_V_ST                 3
 182
 183 #define S3_PLL_CFG_VAL          0x01c22016
 184 #define S3_FRAC                 0x1f9ad4
 185 #define S3_SCL_VST              0x19
 186 #define S3_SCL_HST              0x569
 187 #define S3_VIF_VST              0x1
 188 #define S3_VIF_HST              0xcf
 189
 190
 191 //720*576*50
 192 #define S4_OUT_CLK              SCALE_RATE(27000000,70312500)  //m=75 n=4 no=8
 193 #define S4_H_PW                 48
 194 #define S4_H_BP                 233
 195 #define S4_H_VD                 1280
 196 #define S4_H_FP                 59
 197
 198 #define S4_V_PW                 9
 199 #define S4_V_BP                 57
 200 #define S4_V_VD                 800
 201 #define S4_V_FP                 2
 202
 203 #define S4_H_ST                 90
 204 #define S4_V_ST                 2
 205
 206 #define S4_PLL_CFG_VAL          0x01412016
 207 #define S4_FRAC                 0xa23d09
 208 #define S4_SCL_VST              0x2d
 209 #define S4_SCL_HST              0x33d
 210 #define S4_VIF_VST              0x1
 211 #define S4_VIF_HST              0xc1
 212
 213
 214 //720*480*60
 215 #define S5_OUT_CLK              SCALE_RATE(27000000,75000000)  //m=100 n=9 no=4
 216 #define S5_H_PW                 48
 217 #define S5_H_BP                 86
 218 #define S5_H_VD                 1280
 219 #define S5_H_FP                 16
 220
 221 #define S5_V_PW                 9
 222 #define S5_V_BP                 35
 223 #define S5_V_VD                 800
 224 #define S5_V_FP                 30
 225
 226 #define S5_H_ST                 476
 227 #define S5_V_ST                 12
 228
 229 #define S5_PLL_CFG_VAL          0x01c11013
 230 #define S5_FRAC                 0x25325e
 231 #define S5_SCL_VST              0x26
 232 #define S5_SCL_HST              0x2ae
 233 #define S5_VIF_VST              0x1
 234 #define S5_VIF_HST              0xc1
 235
 236
 237 #define S_DCLK_POL       1
 238
 239
 240 static int set_scaler_info(struct rk29fb_screen *screen, u8 hdmi_resolution)
 241 {
 242         screen->s_clk_inv = S_DCLK_POL;
 243         screen->s_den_inv = 0;
 244         screen->s_hv_sync_inv = 0;
 245         switch(hdmi_resolution)
 246         {
 247         case HDMI_1920x1080p_60Hz:
 248                 /* Scaler Timing    */
 249                 screen->hdmi_resolution = hdmi_resolution;
 250                 screen->s_pixclock = S_OUT_CLK;
 251                 screen->s_hsync_len = S_H_PW;
 252                 screen->s_left_margin = S_H_BP;
 253                 screen->s_right_margin = S_H_FP;
 254                 screen->s_hsync_len = S_H_PW;
 255                 screen->s_upper_margin = S_V_BP;
 256                 screen->s_lower_margin = S_V_FP;
 257                 screen->s_vsync_len = S_V_PW;
 258                 screen->s_hsync_st = S_H_ST;
 259                 screen->s_vsync_st = S_V_ST;
 260
 261                 //bellow are for JettaB
 262                 screen->pll_cfg_val = S_PLL_CFG_VAL;
 263                 screen->frac        = S_FRAC;
 264                 screen->scl_vst     = S_SCL_VST;
 265                 screen->scl_hst     = S_SCL_HST;
 266                 screen->vif_vst     = S_VIF_VST;
 267                 screen->vif_hst     = S_VIF_HST;
 268                 break;
 269         case HDMI_1920x1080p_50Hz:
 270                 /* Scaler Timing    */
 271                 screen->hdmi_resolution = hdmi_resolution;
 272                 screen->s_pixclock = S1_OUT_CLK;
 273                 screen->s_hsync_len = S1_H_PW;
 274                 screen->s_left_margin = S1_H_BP;
 275                 screen->s_right_margin = S1_H_FP;
 276                 screen->s_hsync_len = S1_H_PW;
 277                 screen->s_upper_margin = S1_V_BP;
 278                 screen->s_lower_margin = S1_V_FP;
 279                 screen->s_vsync_len = S1_V_PW;
 280                 screen->s_hsync_st = S1_H_ST;
 281                 screen->s_vsync_st = S1_V_ST;
 282
 283                 screen->pll_cfg_val = S1_PLL_CFG_VAL;
 284                 screen->frac        = S1_FRAC;
 285                 screen->scl_vst     = S1_SCL_VST;
 286                 screen->scl_hst     = S1_SCL_HST;
 287                 screen->vif_vst     = S1_VIF_VST;
 288                 screen->vif_hst     = S1_VIF_HST;
 289                 break;
 290         case HDMI_1280x720p_60Hz:
 291                 /* Scaler Timing    */
 292                 screen->hdmi_resolution = hdmi_resolution;
 293                 screen->s_pixclock = S2_OUT_CLK;
 294                 screen->s_hsync_len = S2_H_PW;
 295                 screen->s_left_margin = S2_H_BP;
 296                 screen->s_right_margin = S2_H_FP;
 297                 screen->s_hsync_len = S2_H_PW;
 298                 screen->s_upper_margin = S2_V_BP;
 299                 screen->s_lower_margin = S2_V_FP;
 300                 screen->s_vsync_len = S2_V_PW;
 301                 screen->s_hsync_st = S2_H_ST;
 302                 screen->s_vsync_st = S2_V_ST;
 303
 304                 screen->pll_cfg_val = S2_PLL_CFG_VAL;
 305                 screen->frac        = S2_FRAC;
 306                 screen->scl_vst     = S2_SCL_VST;
 307                 screen->scl_hst     = S2_SCL_HST;
 308                 screen->vif_vst     = S2_VIF_VST;
 309                 screen->vif_hst     = S2_VIF_HST;
 310                 break;
 311         case HDMI_1280x720p_50Hz:
 312                 /* Scaler Timing    */
 313                 screen->hdmi_resolution = hdmi_resolution;
 314                 screen->s_pixclock = S3_OUT_CLK;
 315                 screen->s_hsync_len = S3_H_PW;
 316                 screen->s_left_margin = S3_H_BP;
 317                 screen->s_right_margin = S3_H_FP;
 318                 screen->s_hsync_len = S3_H_PW;
 319                 screen->s_upper_margin = S3_V_BP;
 320                 screen->s_lower_margin = S3_V_FP;
 321                 screen->s_vsync_len = S3_V_PW;
 322                 screen->s_hsync_st = S3_H_ST;
 323                 screen->s_vsync_st = S3_V_ST;
 324
 325                 screen->pll_cfg_val = S3_PLL_CFG_VAL;
 326                 screen->frac        = S3_FRAC;
 327                 screen->scl_vst     = S3_SCL_VST;
 328                 screen->scl_hst     = S3_SCL_HST;
 329                 screen->vif_vst     = S3_VIF_VST;
 330                 screen->vif_hst     = S3_VIF_HST;
 331                 break;
 332         case HDMI_720x576p_50Hz_4_3:
 333         case HDMI_720x576p_50Hz_16_9:
 334                 /* Scaler Timing    */
 335                 screen->hdmi_resolution = hdmi_resolution;
 336                 screen->s_pixclock = S4_OUT_CLK;
 337                 screen->s_hsync_len = S4_H_PW;
 338                 screen->s_left_margin = S4_H_BP;
 339                 screen->s_right_margin = S4_H_FP;
 340                 screen->s_hsync_len = S4_H_PW;
 341                 screen->s_upper_margin = S4_V_BP;
 342                 screen->s_lower_margin = S4_V_FP;
 343                 screen->s_vsync_len = S4_V_PW;
 344                 screen->s_hsync_st = S4_H_ST;
 345                 screen->s_vsync_st = S4_V_ST;
 346
 347                 screen->pll_cfg_val = S4_PLL_CFG_VAL;
 348                 screen->frac        = S4_FRAC;
 349                 screen->scl_vst     = S4_SCL_VST;
 350                 screen->scl_hst     = S4_SCL_HST;
 351                 screen->vif_vst     = S4_VIF_VST;
 352                 screen->vif_hst     = S4_VIF_HST;
 353                 break;
 354
 355         case HDMI_720x480p_60Hz_16_9:
 356         case HDMI_720x480p_60Hz_4_3:
 357                 /* Scaler Timing    */
 358                 screen->hdmi_resolution = hdmi_resolution;
 359                 screen->s_pixclock = S5_OUT_CLK;
 360                 screen->s_hsync_len = S5_H_PW;
 361                 screen->s_left_margin = S5_H_BP;
 362                 screen->s_right_margin = S5_H_FP;
 363                 screen->s_hsync_len = S5_H_PW;
 364                 screen->s_upper_margin = S5_V_BP;
 365                 screen->s_lower_margin = S5_V_FP;
 366                 screen->s_vsync_len = S5_V_PW;
 367                 screen->s_hsync_st = S5_H_ST;
 368                 screen->s_vsync_st = S5_V_ST;
 369
 370                 screen->pll_cfg_val = S5_PLL_CFG_VAL;
 371                 screen->frac        = S5_FRAC;
 372                 screen->scl_vst     = S5_SCL_VST;
 373                 screen->scl_hst     = S5_SCL_HST;
 374                 screen->vif_vst     = S5_VIF_VST;
 375                 screen->vif_hst     = S5_VIF_HST;
 376                 break;
 377         default :
 378                 printk("%s lcd not support dual display at this hdmi resolution %d \n",__func__,hdmi_resolution);
 379                 return -1;
 380                 break;
 381         }
 382
 383         return 0;
 384 }
 385 #else
 386 #define set_scaler_info  NULL
 387 #endif
 388
 389 void set_lcd_info(struct rk29fb_screen *screen, struct rk29lcd_info *lcd_info )
 390 {
 391         /* screen type & face */
 392         screen->face = OUT_FACE;
 393         screen->type = OUT_TYPE;
 394 #if defined(CONFIG_RK610_LVDS)|| defined(CONFIG_RK616_VIF)
 395         screen->hw_format = LVDS_FORMAT;
 396 #endif
 397
 398         /* Screen size */
 399         screen->x_res = H_VD;
 400         screen->y_res = V_VD;
 401
 402         screen->width = LCD_WIDTH;
 403         screen->height = LCD_HEIGHT;
 404
 405     /* Timing */
 406         screen->lcdc_aclk = LCDC_ACLK;
 407         screen->pixclock = OUT_CLK;
 408         screen->left_margin = H_BP;
 409         screen->right_margin = H_FP;
 410         screen->hsync_len = H_PW;
 411         screen->upper_margin = V_BP;
 412         screen->lower_margin = V_FP;
 413         screen->vsync_len = V_PW;
 414
 415         /* Pin polarity */
 416         screen->pin_hsync = HSYNC_POL;
 417         screen->pin_vsync = VSYNC_POL;
 418         screen->pin_den = DEN_POL;
 419         screen->pin_dclk = DCLK_POL;
 420
 421         /* Swap rule */
 422         screen->swap_rb = SWAP_RB;
 423         screen->swap_rg = SWAP_RG;
 424         screen->swap_gb = SWAP_GB;
 425         screen->swap_delta = 0;
 426         screen->swap_dumy = 0;
 427
 428         /* Operation function*/
 429         screen->init = NULL;
 430         screen->standby = NULL;
 431         screen->dsp_lut = dsp_lut;
 432         screen->sscreen_get = set_scaler_info;
 433 #if defined(CONFIG_RK610_LVDS) || defined(CONFIG_RK616_VIF)
 434         screen->sscreen_set = rk610_lcd_scaler_set_param;
 435 #endif
 436 }
 437
 438 size_t get_fb_size(void)
 439 {
 440         size_t size = 0;
 441         #if defined(CONFIG_THREE_FB_BUFFER)
 442                 size = ((H_VD)*(V_VD)<<2)* 3; //three buffer
 443         #else
 444                 size = ((H_VD)*(V_VD)<<2)<<1; //two buffer
 445         #endif
 446         return ALIGN(size,SZ_1M);
 447 }