2 * Header file for Samsung DP (Display Port) interface driver.
4 * Copyright (C) 2012 Samsung Electronics Co., Ltd.
5 * Author: Jingoo Han <jg1.han@samsung.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
13 #ifndef _EXYNOS_DP_CORE_H
14 #define _EXYNOS_DP_CORE_H
24 enum link_training_state lt_state;
27 struct exynos_dp_device {
31 void __iomem *reg_base;
32 void __iomem *phy_addr;
33 unsigned int enable_mask;
35 struct video_info *video_info;
36 struct link_train link_train;
40 void exynos_dp_enable_video_mute(struct exynos_dp_device *dp, bool enable);
41 void exynos_dp_stop_video(struct exynos_dp_device *dp);
42 void exynos_dp_lane_swap(struct exynos_dp_device *dp, bool enable);
43 void exynos_dp_init_analog_param(struct exynos_dp_device *dp);
44 void exynos_dp_init_interrupt(struct exynos_dp_device *dp);
45 void exynos_dp_reset(struct exynos_dp_device *dp);
46 void exynos_dp_swreset(struct exynos_dp_device *dp);
47 void exynos_dp_config_interrupt(struct exynos_dp_device *dp);
48 enum pll_status exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp);
49 void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable);
50 void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
51 enum analog_power_block block,
53 void exynos_dp_init_analog_func(struct exynos_dp_device *dp);
54 void exynos_dp_init_hpd(struct exynos_dp_device *dp);
55 void exynos_dp_reset_aux(struct exynos_dp_device *dp);
56 void exynos_dp_init_aux(struct exynos_dp_device *dp);
57 int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp);
58 void exynos_dp_enable_sw_function(struct exynos_dp_device *dp);
59 int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp);
60 int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
61 unsigned int reg_addr,
63 int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
64 unsigned int reg_addr,
66 int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
67 unsigned int reg_addr,
69 unsigned char data[]);
70 int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
71 unsigned int reg_addr,
73 unsigned char data[]);
74 int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
75 unsigned int device_addr,
76 unsigned int reg_addr);
77 int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
78 unsigned int device_addr,
79 unsigned int reg_addr,
81 int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
82 unsigned int device_addr,
83 unsigned int reg_addr,
85 unsigned char edid[]);
86 void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype);
87 void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype);
88 void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count);
89 void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count);
90 void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable);
91 void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
92 enum pattern_set pattern);
93 void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level);
94 void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level);
95 void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level);
96 void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level);
97 void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
99 void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
101 void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
103 void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
105 u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp);
106 u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp);
107 u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp);
108 u32 exynos_dp_get_lane3_link_training(struct exynos_dp_device *dp);
109 void exynos_dp_reset_macro(struct exynos_dp_device *dp);
110 void exynos_dp_init_video(struct exynos_dp_device *dp);
112 void exynos_dp_set_video_color_format(struct exynos_dp_device *dp,
117 int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp);
118 void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
119 enum clock_recovery_m_value_type type,
122 void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type);
123 void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable);
124 void exynos_dp_start_video(struct exynos_dp_device *dp);
125 int exynos_dp_is_video_stream_on(struct exynos_dp_device *dp);
126 void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp,
127 struct video_info *video_info);
128 void exynos_dp_enable_scrambling(struct exynos_dp_device *dp);
129 void exynos_dp_disable_scrambling(struct exynos_dp_device *dp);
131 /* I2C EDID Chip ID, Slave Address */
132 #define I2C_EDID_DEVICE_ADDR 0x50
133 #define I2C_E_EDID_DEVICE_ADDR 0x30
135 #define EDID_BLOCK_LENGTH 0x80
136 #define EDID_HEADER_PATTERN 0x00
137 #define EDID_EXTENSION_FLAG 0x7e
138 #define EDID_CHECKSUM 0x7f
140 /* Definition for DPCD Register */
141 #define DPCD_ADDR_DPCD_REV 0x0000
142 #define DPCD_ADDR_MAX_LINK_RATE 0x0001
143 #define DPCD_ADDR_MAX_LANE_COUNT 0x0002
144 #define DPCD_ADDR_LINK_BW_SET 0x0100
145 #define DPCD_ADDR_LANE_COUNT_SET 0x0101
146 #define DPCD_ADDR_TRAINING_PATTERN_SET 0x0102
147 #define DPCD_ADDR_TRAINING_LANE0_SET 0x0103
148 #define DPCD_ADDR_LANE0_1_STATUS 0x0202
149 #define DPCD_ADDR_LANE_ALIGN_STATUS_UPDATED 0x0204
150 #define DPCD_ADDR_ADJUST_REQUEST_LANE0_1 0x0206
151 #define DPCD_ADDR_ADJUST_REQUEST_LANE2_3 0x0207
152 #define DPCD_ADDR_TEST_REQUEST 0x0218
153 #define DPCD_ADDR_TEST_RESPONSE 0x0260
154 #define DPCD_ADDR_TEST_EDID_CHECKSUM 0x0261
155 #define DPCD_ADDR_SINK_POWER_STATE 0x0600
157 /* DPCD_ADDR_MAX_LANE_COUNT */
158 #define DPCD_ENHANCED_FRAME_CAP(x) (((x) >> 7) & 0x1)
159 #define DPCD_MAX_LANE_COUNT(x) ((x) & 0x1f)
161 /* DPCD_ADDR_LANE_COUNT_SET */
162 #define DPCD_ENHANCED_FRAME_EN (0x1 << 7)
163 #define DPCD_LANE_COUNT_SET(x) ((x) & 0x1f)
165 /* DPCD_ADDR_TRAINING_PATTERN_SET */
166 #define DPCD_SCRAMBLING_DISABLED (0x1 << 5)
167 #define DPCD_SCRAMBLING_ENABLED (0x0 << 5)
168 #define DPCD_TRAINING_PATTERN_2 (0x2 << 0)
169 #define DPCD_TRAINING_PATTERN_1 (0x1 << 0)
170 #define DPCD_TRAINING_PATTERN_DISABLED (0x0 << 0)
172 /* DPCD_ADDR_TRAINING_LANE0_SET */
173 #define DPCD_MAX_PRE_EMPHASIS_REACHED (0x1 << 5)
174 #define DPCD_PRE_EMPHASIS_SET(x) (((x) & 0x3) << 3)
175 #define DPCD_PRE_EMPHASIS_GET(x) (((x) >> 3) & 0x3)
176 #define DPCD_PRE_EMPHASIS_PATTERN2_LEVEL0 (0x0 << 3)
177 #define DPCD_MAX_SWING_REACHED (0x1 << 2)
178 #define DPCD_VOLTAGE_SWING_SET(x) (((x) & 0x3) << 0)
179 #define DPCD_VOLTAGE_SWING_GET(x) (((x) >> 0) & 0x3)
180 #define DPCD_VOLTAGE_SWING_PATTERN1_LEVEL0 (0x0 << 0)
182 /* DPCD_ADDR_LANE0_1_STATUS */
183 #define DPCD_LANE_SYMBOL_LOCKED (0x1 << 2)
184 #define DPCD_LANE_CHANNEL_EQ_DONE (0x1 << 1)
185 #define DPCD_LANE_CR_DONE (0x1 << 0)
186 #define DPCD_CHANNEL_EQ_BITS (DPCD_LANE_CR_DONE| \
187 DPCD_LANE_CHANNEL_EQ_DONE|\
188 DPCD_LANE_SYMBOL_LOCKED)
190 /* DPCD_ADDR_LANE_ALIGN__STATUS_UPDATED */
191 #define DPCD_LINK_STATUS_UPDATED (0x1 << 7)
192 #define DPCD_DOWNSTREAM_PORT_STATUS_CHANGED (0x1 << 6)
193 #define DPCD_INTERLANE_ALIGN_DONE (0x1 << 0)
195 /* DPCD_ADDR_TEST_REQUEST */
196 #define DPCD_TEST_EDID_READ (0x1 << 2)
198 /* DPCD_ADDR_TEST_RESPONSE */
199 #define DPCD_TEST_EDID_CHECKSUM_WRITE (0x1 << 2)
201 /* DPCD_ADDR_SINK_POWER_STATE */
202 #define DPCD_SET_POWER_STATE_D0 (0x1 << 0)
203 #define DPCD_SET_POWER_STATE_D4 (0x2 << 0)
205 #endif /* _EXYNOS_DP_CORE_H */