2 * Samsung DP (Display port) register interface driver.
4 * Copyright (C) 2012 Samsung Electronics Co., Ltd.
5 * Author: Jingoo Han <jg1.han@samsung.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
13 #include <linux/device.h>
15 #include <linux/delay.h>
17 #include <video/exynos_dp.h>
19 #include "exynos_dp_core.h"
20 #include "exynos_dp_reg.h"
22 #define COMMON_INT_MASK_1 0
23 #define COMMON_INT_MASK_2 0
24 #define COMMON_INT_MASK_3 0
25 #define COMMON_INT_MASK_4 (HOTPLUG_CHG | HPD_LOST | PLUG)
26 #define INT_STA_MASK INT_HPD
28 void exynos_dp_enable_video_mute(struct exynos_dp_device *dp, bool enable)
33 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
34 reg |= HDCP_VIDEO_MUTE;
35 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
37 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
38 reg &= ~HDCP_VIDEO_MUTE;
39 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
43 void exynos_dp_stop_video(struct exynos_dp_device *dp)
47 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
49 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
52 void exynos_dp_lane_swap(struct exynos_dp_device *dp, bool enable)
57 reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 |
58 LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3;
60 reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 |
61 LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
63 writel(reg, dp->reg_base + EXYNOS_DP_LANE_MAP);
66 void exynos_dp_init_analog_param(struct exynos_dp_device *dp)
70 reg = TX_TERMINAL_CTRL_50_OHM;
71 writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_1);
73 reg = SEL_24M | TX_DVDD_BIT_1_0625V;
74 writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_2);
76 reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO;
77 writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_3);
79 reg = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM |
80 TX_CUR1_2X | TX_CUR_16_MA;
81 writel(reg, dp->reg_base + EXYNOS_DP_PLL_FILTER_CTL_1);
83 reg = CH3_AMP_400_MV | CH2_AMP_400_MV |
84 CH1_AMP_400_MV | CH0_AMP_400_MV;
85 writel(reg, dp->reg_base + EXYNOS_DP_TX_AMP_TUNING_CTL);
88 void exynos_dp_init_interrupt(struct exynos_dp_device *dp)
90 /* Set interrupt pin assertion polarity as high */
91 writel(INT_POL, dp->reg_base + EXYNOS_DP_INT_CTL);
93 /* Clear pending regisers */
94 writel(0xff, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
95 writel(0x4f, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_2);
96 writel(0xe0, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_3);
97 writel(0xe7, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
98 writel(0x63, dp->reg_base + EXYNOS_DP_INT_STA);
100 /* 0:mask,1: unmask */
101 writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_1);
102 writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_2);
103 writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_3);
104 writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_4);
105 writel(0x00, dp->reg_base + EXYNOS_DP_INT_STA_MASK);
108 void exynos_dp_reset(struct exynos_dp_device *dp)
112 exynos_dp_stop_video(dp);
113 exynos_dp_enable_video_mute(dp, 0);
115 reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
116 AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
117 HDCP_FUNC_EN_N | SW_FUNC_EN_N;
118 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
120 reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N |
121 SERDES_FIFO_FUNC_EN_N |
122 LS_CLK_DOMAIN_FUNC_EN_N;
123 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
125 usleep_range(20, 30);
127 exynos_dp_lane_swap(dp, 0);
129 writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
130 writel(0x40, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
131 writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
132 writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
134 writel(0x0, dp->reg_base + EXYNOS_DP_PKT_SEND_CTL);
135 writel(0x0, dp->reg_base + EXYNOS_DP_HDCP_CTL);
137 writel(0x5e, dp->reg_base + EXYNOS_DP_HPD_DEGLITCH_L);
138 writel(0x1a, dp->reg_base + EXYNOS_DP_HPD_DEGLITCH_H);
140 writel(0x10, dp->reg_base + EXYNOS_DP_LINK_DEBUG_CTL);
142 writel(0x0, dp->reg_base + EXYNOS_DP_PHY_TEST);
144 writel(0x0, dp->reg_base + EXYNOS_DP_VIDEO_FIFO_THRD);
145 writel(0x20, dp->reg_base + EXYNOS_DP_AUDIO_MARGIN);
147 writel(0x4, dp->reg_base + EXYNOS_DP_M_VID_GEN_FILTER_TH);
148 writel(0x2, dp->reg_base + EXYNOS_DP_M_AUD_GEN_FILTER_TH);
150 writel(0x00000101, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
153 void exynos_dp_swreset(struct exynos_dp_device *dp)
155 writel(RESET_DP_TX, dp->reg_base + EXYNOS_DP_TX_SW_RESET);
158 void exynos_dp_config_interrupt(struct exynos_dp_device *dp)
162 /* 0: mask, 1: unmask */
163 reg = COMMON_INT_MASK_1;
164 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_1);
166 reg = COMMON_INT_MASK_2;
167 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_2);
169 reg = COMMON_INT_MASK_3;
170 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_3);
172 reg = COMMON_INT_MASK_4;
173 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_4);
176 writel(reg, dp->reg_base + EXYNOS_DP_INT_STA_MASK);
179 enum pll_status exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp)
183 reg = readl(dp->reg_base + EXYNOS_DP_DEBUG_CTL);
190 void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable)
195 reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL);
197 writel(reg, dp->reg_base + EXYNOS_DP_PLL_CTL);
199 reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL);
201 writel(reg, dp->reg_base + EXYNOS_DP_PLL_CTL);
205 void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
206 enum analog_power_block block,
214 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
216 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
218 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
220 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
225 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
227 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
229 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
231 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
236 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
238 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
240 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
242 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
247 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
249 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
251 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
253 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
258 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
260 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
262 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
264 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
269 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
271 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
273 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
275 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
280 reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD |
282 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
284 writel(0x00, dp->reg_base + EXYNOS_DP_PHY_PD);
292 void exynos_dp_init_analog_func(struct exynos_dp_device *dp)
295 int timeout_loop = 0;
297 exynos_dp_set_analog_power_down(dp, POWER_ALL, 0);
300 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
302 reg = readl(dp->reg_base + EXYNOS_DP_DEBUG_CTL);
303 reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL);
304 writel(reg, dp->reg_base + EXYNOS_DP_DEBUG_CTL);
307 if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
308 exynos_dp_set_pll_power_down(dp, 0);
310 while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
312 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
313 dev_err(dp->dev, "failed to get pll lock status\n");
316 usleep_range(10, 20);
320 /* Enable Serdes FIFO function and Link symbol clock domain module */
321 reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
322 reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N
324 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
327 void exynos_dp_clear_hotplug_interrupts(struct exynos_dp_device *dp)
331 reg = HOTPLUG_CHG | HPD_LOST | PLUG;
332 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
335 writel(reg, dp->reg_base + EXYNOS_DP_INT_STA);
338 void exynos_dp_init_hpd(struct exynos_dp_device *dp)
342 exynos_dp_clear_hotplug_interrupts(dp);
344 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
345 reg &= ~(F_HPD | HPD_CTRL);
346 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
349 enum dp_irq_type exynos_dp_get_irq_type(struct exynos_dp_device *dp)
353 /* Parse hotplug interrupt status register */
354 reg = readl(dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
357 return DP_IRQ_TYPE_HP_CABLE_IN;
360 return DP_IRQ_TYPE_HP_CABLE_OUT;
362 if (reg & HOTPLUG_CHG)
363 return DP_IRQ_TYPE_HP_CHANGE;
365 return DP_IRQ_TYPE_UNKNOWN;
368 void exynos_dp_reset_aux(struct exynos_dp_device *dp)
372 /* Disable AUX channel module */
373 reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
374 reg |= AUX_FUNC_EN_N;
375 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
378 void exynos_dp_init_aux(struct exynos_dp_device *dp)
382 /* Clear inerrupts related to AUX channel */
383 reg = RPLY_RECEIV | AUX_ERR;
384 writel(reg, dp->reg_base + EXYNOS_DP_INT_STA);
386 exynos_dp_reset_aux(dp);
388 /* Disable AUX transaction H/W retry */
389 reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0)|
390 AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
391 writel(reg, dp->reg_base + EXYNOS_DP_AUX_HW_RETRY_CTL) ;
393 /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
394 reg = DEFER_CTRL_EN | DEFER_COUNT(1);
395 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_DEFER_CTL);
397 /* Enable AUX channel module */
398 reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
399 reg &= ~AUX_FUNC_EN_N;
400 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
403 int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp)
407 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
408 if (reg & HPD_STATUS)
414 void exynos_dp_enable_sw_function(struct exynos_dp_device *dp)
418 reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1);
419 reg &= ~SW_FUNC_EN_N;
420 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
423 int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp)
427 int timeout_loop = 0;
429 /* Enable AUX CH operation */
430 reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
432 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
434 /* Is AUX CH command reply received? */
435 reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
436 while (!(reg & RPLY_RECEIV)) {
438 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
439 dev_err(dp->dev, "AUX CH command reply failed!\n");
442 reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
443 usleep_range(10, 11);
446 /* Clear interrupt source for AUX CH command reply */
447 writel(RPLY_RECEIV, dp->reg_base + EXYNOS_DP_INT_STA);
449 /* Clear interrupt source for AUX CH access error */
450 reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
452 writel(AUX_ERR, dp->reg_base + EXYNOS_DP_INT_STA);
456 /* Check AUX CH error access status */
457 reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_STA);
458 if ((reg & AUX_STATUS_MASK) != 0) {
459 dev_err(dp->dev, "AUX CH error happens: %d\n\n",
460 reg & AUX_STATUS_MASK);
467 int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
468 unsigned int reg_addr,
475 for (i = 0; i < 3; i++) {
476 /* Clear AUX CH data buffer */
478 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
480 /* Select DPCD device address */
481 reg = AUX_ADDR_7_0(reg_addr);
482 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
483 reg = AUX_ADDR_15_8(reg_addr);
484 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
485 reg = AUX_ADDR_19_16(reg_addr);
486 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
488 /* Write data buffer */
489 reg = (unsigned int)data;
490 writel(reg, dp->reg_base + EXYNOS_DP_BUF_DATA_0);
493 * Set DisplayPort transaction and write 1 byte
494 * If bit 3 is 1, DisplayPort transaction.
495 * If Bit 3 is 0, I2C transaction.
497 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
498 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
500 /* Start AUX transaction */
501 retval = exynos_dp_start_aux_transaction(dp);
505 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
512 int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
513 unsigned int reg_addr,
520 for (i = 0; i < 3; i++) {
521 /* Clear AUX CH data buffer */
523 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
525 /* Select DPCD device address */
526 reg = AUX_ADDR_7_0(reg_addr);
527 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
528 reg = AUX_ADDR_15_8(reg_addr);
529 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
530 reg = AUX_ADDR_19_16(reg_addr);
531 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
534 * Set DisplayPort transaction and read 1 byte
535 * If bit 3 is 1, DisplayPort transaction.
536 * If Bit 3 is 0, I2C transaction.
538 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
539 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
541 /* Start AUX transaction */
542 retval = exynos_dp_start_aux_transaction(dp);
546 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
550 /* Read data buffer */
551 reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0);
552 *data = (unsigned char)(reg & 0xff);
557 int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
558 unsigned int reg_addr,
560 unsigned char data[])
563 unsigned int start_offset;
564 unsigned int cur_data_count;
565 unsigned int cur_data_idx;
569 /* Clear AUX CH data buffer */
571 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
574 while (start_offset < count) {
575 /* Buffer size of AUX CH is 16 * 4bytes */
576 if ((count - start_offset) > 16)
579 cur_data_count = count - start_offset;
581 for (i = 0; i < 3; i++) {
582 /* Select DPCD device address */
583 reg = AUX_ADDR_7_0(reg_addr + start_offset);
584 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
585 reg = AUX_ADDR_15_8(reg_addr + start_offset);
586 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
587 reg = AUX_ADDR_19_16(reg_addr + start_offset);
588 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
590 for (cur_data_idx = 0; cur_data_idx < cur_data_count;
592 reg = data[start_offset + cur_data_idx];
593 writel(reg, dp->reg_base + EXYNOS_DP_BUF_DATA_0
598 * Set DisplayPort transaction and write
599 * If bit 3 is 1, DisplayPort transaction.
600 * If Bit 3 is 0, I2C transaction.
602 reg = AUX_LENGTH(cur_data_count) |
603 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
604 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
606 /* Start AUX transaction */
607 retval = exynos_dp_start_aux_transaction(dp);
611 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
615 start_offset += cur_data_count;
621 int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
622 unsigned int reg_addr,
624 unsigned char data[])
627 unsigned int start_offset;
628 unsigned int cur_data_count;
629 unsigned int cur_data_idx;
633 /* Clear AUX CH data buffer */
635 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
638 while (start_offset < count) {
639 /* Buffer size of AUX CH is 16 * 4bytes */
640 if ((count - start_offset) > 16)
643 cur_data_count = count - start_offset;
645 /* AUX CH Request Transaction process */
646 for (i = 0; i < 3; i++) {
647 /* Select DPCD device address */
648 reg = AUX_ADDR_7_0(reg_addr + start_offset);
649 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
650 reg = AUX_ADDR_15_8(reg_addr + start_offset);
651 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
652 reg = AUX_ADDR_19_16(reg_addr + start_offset);
653 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
656 * Set DisplayPort transaction and read
657 * If bit 3 is 1, DisplayPort transaction.
658 * If Bit 3 is 0, I2C transaction.
660 reg = AUX_LENGTH(cur_data_count) |
661 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
662 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
664 /* Start AUX transaction */
665 retval = exynos_dp_start_aux_transaction(dp);
669 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
673 for (cur_data_idx = 0; cur_data_idx < cur_data_count;
675 reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0
677 data[start_offset + cur_data_idx] =
681 start_offset += cur_data_count;
687 int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
688 unsigned int device_addr,
689 unsigned int reg_addr)
694 /* Set EDID device address */
696 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
697 writel(0x0, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
698 writel(0x0, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
700 /* Set offset from base address of EDID device */
701 writel(reg_addr, dp->reg_base + EXYNOS_DP_BUF_DATA_0);
704 * Set I2C transaction and write address
705 * If bit 3 is 1, DisplayPort transaction.
706 * If Bit 3 is 0, I2C transaction.
708 reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
710 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
712 /* Start AUX transaction */
713 retval = exynos_dp_start_aux_transaction(dp);
715 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
720 int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
721 unsigned int device_addr,
722 unsigned int reg_addr,
729 for (i = 0; i < 3; i++) {
730 /* Clear AUX CH data buffer */
732 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
734 /* Select EDID device */
735 retval = exynos_dp_select_i2c_device(dp, device_addr, reg_addr);
740 * Set I2C transaction and read data
741 * If bit 3 is 1, DisplayPort transaction.
742 * If Bit 3 is 0, I2C transaction.
744 reg = AUX_TX_COMM_I2C_TRANSACTION |
746 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
748 /* Start AUX transaction */
749 retval = exynos_dp_start_aux_transaction(dp);
753 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
759 *data = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0);
764 int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
765 unsigned int device_addr,
766 unsigned int reg_addr,
768 unsigned char edid[])
772 unsigned int cur_data_idx;
773 unsigned int defer = 0;
776 for (i = 0; i < count; i += 16) {
777 for (j = 0; j < 3; j++) {
778 /* Clear AUX CH data buffer */
780 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
782 /* Set normal AUX CH command */
783 reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
785 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
788 * If Rx sends defer, Tx sends only reads
789 * request without sending address
792 retval = exynos_dp_select_i2c_device(dp,
793 device_addr, reg_addr + i);
799 * Set I2C transaction and write data
800 * If bit 3 is 1, DisplayPort transaction.
801 * If Bit 3 is 0, I2C transaction.
803 reg = AUX_LENGTH(16) |
804 AUX_TX_COMM_I2C_TRANSACTION |
806 writel(reg, dp->reg_base +
807 EXYNOS_DP_AUX_CH_CTL_1);
809 /* Start AUX transaction */
810 retval = exynos_dp_start_aux_transaction(dp);
815 "%s: Aux Transaction fail!\n",
818 /* Check if Rx sends defer */
819 reg = readl(dp->reg_base + EXYNOS_DP_AUX_RX_COMM);
820 if (reg == AUX_RX_COMM_AUX_DEFER ||
821 reg == AUX_RX_COMM_I2C_DEFER) {
822 dev_err(dp->dev, "Defer: %d\n\n", reg);
827 for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
828 reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0
830 edid[i + cur_data_idx] = (unsigned char)reg;
837 void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype)
842 if ((bwtype == LINK_RATE_2_70GBPS) || (bwtype == LINK_RATE_1_62GBPS))
843 writel(reg, dp->reg_base + EXYNOS_DP_LINK_BW_SET);
846 void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype)
850 reg = readl(dp->reg_base + EXYNOS_DP_LINK_BW_SET);
854 void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count)
859 writel(reg, dp->reg_base + EXYNOS_DP_LANE_COUNT_SET);
862 void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count)
866 reg = readl(dp->reg_base + EXYNOS_DP_LANE_COUNT_SET);
870 void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable)
875 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
877 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
879 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
881 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
885 void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
886 enum pattern_set pattern)
892 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7;
893 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
896 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2;
897 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
900 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1;
901 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
904 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2;
905 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
908 reg = SCRAMBLING_ENABLE |
909 LINK_QUAL_PATTERN_SET_DISABLE |
910 SW_TRAINING_PATTERN_SET_NORMAL;
911 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
918 void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level)
922 reg = readl(dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
923 reg &= ~PRE_EMPHASIS_SET_MASK;
924 reg |= level << PRE_EMPHASIS_SET_SHIFT;
925 writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
928 void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level)
932 reg = readl(dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
933 reg &= ~PRE_EMPHASIS_SET_MASK;
934 reg |= level << PRE_EMPHASIS_SET_SHIFT;
935 writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
938 void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level)
942 reg = readl(dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
943 reg &= ~PRE_EMPHASIS_SET_MASK;
944 reg |= level << PRE_EMPHASIS_SET_SHIFT;
945 writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
948 void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level)
952 reg = readl(dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
953 reg &= ~PRE_EMPHASIS_SET_MASK;
954 reg |= level << PRE_EMPHASIS_SET_SHIFT;
955 writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
958 void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
964 writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
967 void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
973 writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
976 void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
982 writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
985 void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
991 writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
994 u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp)
998 reg = readl(dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
1002 u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp)
1006 reg = readl(dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
1010 u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp)
1014 reg = readl(dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
1018 u32 exynos_dp_get_lane3_link_training(struct exynos_dp_device *dp)
1022 reg = readl(dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
1026 void exynos_dp_reset_macro(struct exynos_dp_device *dp)
1030 reg = readl(dp->reg_base + EXYNOS_DP_PHY_TEST);
1032 writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST);
1034 /* 10 us is the minimum reset time. */
1035 usleep_range(10, 20);
1038 writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST);
1041 void exynos_dp_init_video(struct exynos_dp_device *dp)
1045 reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
1046 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
1049 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
1051 reg = CHA_CRI(4) | CHA_CTRL;
1052 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
1055 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
1057 reg = VID_HRES_TH(2) | VID_VRES_TH(0);
1058 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_8);
1061 void exynos_dp_set_video_color_format(struct exynos_dp_device *dp,
1069 /* Configure the input color depth, color space, dynamic range */
1070 reg = (dynamic_range << IN_D_RANGE_SHIFT) |
1071 (color_depth << IN_BPC_SHIFT) |
1072 (color_space << IN_COLOR_F_SHIFT);
1073 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_2);
1075 /* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
1076 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_3);
1077 reg &= ~IN_YC_COEFFI_MASK;
1079 reg |= IN_YC_COEFFI_ITU709;
1081 reg |= IN_YC_COEFFI_ITU601;
1082 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_3);
1085 int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp)
1089 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1);
1090 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
1092 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1);
1094 if (!(reg & DET_STA)) {
1095 dev_dbg(dp->dev, "Input stream clock not detected.\n");
1099 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_2);
1100 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
1102 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_2);
1103 dev_dbg(dp->dev, "wait SYS_CTL_2.\n");
1105 if (reg & CHA_STA) {
1106 dev_dbg(dp->dev, "Input stream clk is changing\n");
1113 void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
1114 enum clock_recovery_m_value_type type,
1120 if (type == REGISTER_M) {
1121 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
1123 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
1124 reg = m_value & 0xff;
1125 writel(reg, dp->reg_base + EXYNOS_DP_M_VID_0);
1126 reg = (m_value >> 8) & 0xff;
1127 writel(reg, dp->reg_base + EXYNOS_DP_M_VID_1);
1128 reg = (m_value >> 16) & 0xff;
1129 writel(reg, dp->reg_base + EXYNOS_DP_M_VID_2);
1131 reg = n_value & 0xff;
1132 writel(reg, dp->reg_base + EXYNOS_DP_N_VID_0);
1133 reg = (n_value >> 8) & 0xff;
1134 writel(reg, dp->reg_base + EXYNOS_DP_N_VID_1);
1135 reg = (n_value >> 16) & 0xff;
1136 writel(reg, dp->reg_base + EXYNOS_DP_N_VID_2);
1138 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
1140 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
1142 writel(0x00, dp->reg_base + EXYNOS_DP_N_VID_0);
1143 writel(0x80, dp->reg_base + EXYNOS_DP_N_VID_1);
1144 writel(0x00, dp->reg_base + EXYNOS_DP_N_VID_2);
1148 void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type)
1152 if (type == VIDEO_TIMING_FROM_CAPTURE) {
1153 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1155 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1157 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1159 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1163 void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable)
1168 reg = readl(dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
1169 reg &= ~VIDEO_MODE_MASK;
1170 reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE;
1171 writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
1173 reg = readl(dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
1174 reg &= ~VIDEO_MODE_MASK;
1175 reg |= VIDEO_MODE_SLAVE_MODE;
1176 writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
1180 void exynos_dp_start_video(struct exynos_dp_device *dp)
1184 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
1186 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
1189 int exynos_dp_is_video_stream_on(struct exynos_dp_device *dp)
1193 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
1194 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
1196 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
1197 if (!(reg & STRM_VALID)) {
1198 dev_dbg(dp->dev, "Input video stream is not detected.\n");
1205 void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp,
1206 struct video_info *video_info)
1210 reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1);
1211 reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N);
1212 reg |= MASTER_VID_FUNC_EN_N;
1213 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
1215 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1216 reg &= ~INTERACE_SCAN_CFG;
1217 reg |= (video_info->interlaced << 2);
1218 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1220 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1221 reg &= ~VSYNC_POLARITY_CFG;
1222 reg |= (video_info->v_sync_polarity << 1);
1223 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1225 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1226 reg &= ~HSYNC_POLARITY_CFG;
1227 reg |= (video_info->h_sync_polarity << 0);
1228 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1230 reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
1231 writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
1234 void exynos_dp_enable_scrambling(struct exynos_dp_device *dp)
1238 reg = readl(dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
1239 reg &= ~SCRAMBLING_DISABLE;
1240 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
1243 void exynos_dp_disable_scrambling(struct exynos_dp_device *dp)
1247 reg = readl(dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
1248 reg |= SCRAMBLING_DISABLE;
1249 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);