2 * Samsung DP (Display port) register interface driver.
4 * Copyright (C) 2012 Samsung Electronics Co., Ltd.
5 * Author: Jingoo Han <jg1.han@samsung.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
13 #include <linux/device.h>
15 #include <linux/delay.h>
17 #include <video/exynos_dp.h>
19 #include "exynos_dp_core.h"
20 #include "exynos_dp_reg.h"
22 #define COMMON_INT_MASK_1 (0)
23 #define COMMON_INT_MASK_2 (0)
24 #define COMMON_INT_MASK_3 (0)
25 #define COMMON_INT_MASK_4 (0)
26 #define INT_STA_MASK (0)
28 void exynos_dp_enable_video_mute(struct exynos_dp_device *dp, bool enable)
33 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
34 reg |= HDCP_VIDEO_MUTE;
35 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
37 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
38 reg &= ~HDCP_VIDEO_MUTE;
39 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
43 void exynos_dp_stop_video(struct exynos_dp_device *dp)
47 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
49 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
52 void exynos_dp_lane_swap(struct exynos_dp_device *dp, bool enable)
57 reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 |
58 LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3;
60 reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 |
61 LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0;
63 writel(reg, dp->reg_base + EXYNOS_DP_LANE_MAP);
66 void exynos_dp_init_analog_param(struct exynos_dp_device *dp)
70 reg = TX_TERMINAL_CTRL_50_OHM;
71 writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_1);
73 reg = SEL_24M | TX_DVDD_BIT_1_0625V;
74 writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_2);
76 reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO;
77 writel(reg, dp->reg_base + EXYNOS_DP_ANALOG_CTL_3);
79 reg = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM |
80 TX_CUR1_2X | TX_CUR_16_MA;
81 writel(reg, dp->reg_base + EXYNOS_DP_PLL_FILTER_CTL_1);
83 reg = CH3_AMP_400_MV | CH2_AMP_400_MV |
84 CH1_AMP_400_MV | CH0_AMP_400_MV;
85 writel(reg, dp->reg_base + EXYNOS_DP_TX_AMP_TUNING_CTL);
88 void exynos_dp_init_interrupt(struct exynos_dp_device *dp)
90 /* Set interrupt pin assertion polarity as high */
91 writel(INT_POL, dp->reg_base + EXYNOS_DP_INT_CTL);
93 /* Clear pending regisers */
94 writel(0xff, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
95 writel(0x4f, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_2);
96 writel(0xe0, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_3);
97 writel(0xe7, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
98 writel(0x63, dp->reg_base + EXYNOS_DP_INT_STA);
100 /* 0:mask,1: unmask */
101 writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_1);
102 writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_2);
103 writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_3);
104 writel(0x00, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_4);
105 writel(0x00, dp->reg_base + EXYNOS_DP_INT_STA_MASK);
108 void exynos_dp_reset(struct exynos_dp_device *dp)
112 exynos_dp_stop_video(dp);
113 exynos_dp_enable_video_mute(dp, 0);
115 reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N |
116 AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N |
117 HDCP_FUNC_EN_N | SW_FUNC_EN_N;
118 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
120 reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N |
121 SERDES_FIFO_FUNC_EN_N |
122 LS_CLK_DOMAIN_FUNC_EN_N;
123 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
125 usleep_range(20, 30);
127 exynos_dp_lane_swap(dp, 0);
129 writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
130 writel(0x40, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
131 writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
132 writel(0x0, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
134 writel(0x0, dp->reg_base + EXYNOS_DP_PKT_SEND_CTL);
135 writel(0x0, dp->reg_base + EXYNOS_DP_HDCP_CTL);
137 writel(0x5e, dp->reg_base + EXYNOS_DP_HPD_DEGLITCH_L);
138 writel(0x1a, dp->reg_base + EXYNOS_DP_HPD_DEGLITCH_H);
140 writel(0x10, dp->reg_base + EXYNOS_DP_LINK_DEBUG_CTL);
142 writel(0x0, dp->reg_base + EXYNOS_DP_PHY_TEST);
144 writel(0x0, dp->reg_base + EXYNOS_DP_VIDEO_FIFO_THRD);
145 writel(0x20, dp->reg_base + EXYNOS_DP_AUDIO_MARGIN);
147 writel(0x4, dp->reg_base + EXYNOS_DP_M_VID_GEN_FILTER_TH);
148 writel(0x2, dp->reg_base + EXYNOS_DP_M_AUD_GEN_FILTER_TH);
150 writel(0x00000101, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
153 void exynos_dp_swreset(struct exynos_dp_device *dp)
155 writel(RESET_DP_TX, dp->reg_base + EXYNOS_DP_TX_SW_RESET);
158 void exynos_dp_config_interrupt(struct exynos_dp_device *dp)
162 /* 0: mask, 1: unmask */
163 reg = COMMON_INT_MASK_1;
164 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_1);
166 reg = COMMON_INT_MASK_2;
167 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_2);
169 reg = COMMON_INT_MASK_3;
170 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_3);
172 reg = COMMON_INT_MASK_4;
173 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_MASK_4);
176 writel(reg, dp->reg_base + EXYNOS_DP_INT_STA_MASK);
179 enum pll_status exynos_dp_get_pll_lock_status(struct exynos_dp_device *dp)
183 reg = readl(dp->reg_base + EXYNOS_DP_DEBUG_CTL);
190 void exynos_dp_set_pll_power_down(struct exynos_dp_device *dp, bool enable)
195 reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL);
197 writel(reg, dp->reg_base + EXYNOS_DP_PLL_CTL);
199 reg = readl(dp->reg_base + EXYNOS_DP_PLL_CTL);
201 writel(reg, dp->reg_base + EXYNOS_DP_PLL_CTL);
205 void exynos_dp_set_analog_power_down(struct exynos_dp_device *dp,
206 enum analog_power_block block,
214 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
216 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
218 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
220 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
225 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
227 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
229 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
231 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
236 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
238 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
240 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
242 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
247 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
249 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
251 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
253 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
258 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
260 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
262 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
264 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
269 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
271 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
273 reg = readl(dp->reg_base + EXYNOS_DP_PHY_PD);
275 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
280 reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD |
282 writel(reg, dp->reg_base + EXYNOS_DP_PHY_PD);
284 writel(0x00, dp->reg_base + EXYNOS_DP_PHY_PD);
292 void exynos_dp_init_analog_func(struct exynos_dp_device *dp)
295 int timeout_loop = 0;
297 exynos_dp_set_analog_power_down(dp, POWER_ALL, 0);
300 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
302 reg = readl(dp->reg_base + EXYNOS_DP_DEBUG_CTL);
303 reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL);
304 writel(reg, dp->reg_base + EXYNOS_DP_DEBUG_CTL);
307 if (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
308 exynos_dp_set_pll_power_down(dp, 0);
310 while (exynos_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) {
312 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
313 dev_err(dp->dev, "failed to get pll lock status\n");
316 usleep_range(10, 20);
320 /* Enable Serdes FIFO function and Link symbol clock domain module */
321 reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
322 reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N
324 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
327 void exynos_dp_init_hpd(struct exynos_dp_device *dp)
331 reg = HOTPLUG_CHG | HPD_LOST | PLUG;
332 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_4);
335 writel(reg, dp->reg_base + EXYNOS_DP_INT_STA);
337 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
338 reg &= ~(F_HPD | HPD_CTRL);
339 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
342 void exynos_dp_reset_aux(struct exynos_dp_device *dp)
346 /* Disable AUX channel module */
347 reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
348 reg |= AUX_FUNC_EN_N;
349 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
352 void exynos_dp_init_aux(struct exynos_dp_device *dp)
356 /* Clear inerrupts related to AUX channel */
357 reg = RPLY_RECEIV | AUX_ERR;
358 writel(reg, dp->reg_base + EXYNOS_DP_INT_STA);
360 exynos_dp_reset_aux(dp);
362 /* Disable AUX transaction H/W retry */
363 reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | AUX_HW_RETRY_COUNT_SEL(0)|
364 AUX_HW_RETRY_INTERVAL_600_MICROSECONDS;
365 writel(reg, dp->reg_base + EXYNOS_DP_AUX_HW_RETRY_CTL) ;
367 /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */
368 reg = DEFER_CTRL_EN | DEFER_COUNT(1);
369 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_DEFER_CTL);
371 /* Enable AUX channel module */
372 reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_2);
373 reg &= ~AUX_FUNC_EN_N;
374 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_2);
377 int exynos_dp_get_plug_in_status(struct exynos_dp_device *dp)
381 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
382 if (reg & HPD_STATUS)
388 void exynos_dp_enable_sw_function(struct exynos_dp_device *dp)
392 reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1);
393 reg &= ~SW_FUNC_EN_N;
394 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
397 int exynos_dp_start_aux_transaction(struct exynos_dp_device *dp)
401 int timeout_loop = 0;
403 /* Enable AUX CH operation */
404 reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
406 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
408 /* Is AUX CH command reply received? */
409 reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
410 while (!(reg & RPLY_RECEIV)) {
412 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) {
413 dev_err(dp->dev, "AUX CH command reply failed!\n");
416 reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
417 usleep_range(10, 11);
420 /* Clear interrupt source for AUX CH command reply */
421 writel(RPLY_RECEIV, dp->reg_base + EXYNOS_DP_INT_STA);
423 /* Clear interrupt source for AUX CH access error */
424 reg = readl(dp->reg_base + EXYNOS_DP_INT_STA);
426 writel(AUX_ERR, dp->reg_base + EXYNOS_DP_INT_STA);
430 /* Check AUX CH error access status */
431 reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_STA);
432 if ((reg & AUX_STATUS_MASK) != 0) {
433 dev_err(dp->dev, "AUX CH error happens: %d\n\n",
434 reg & AUX_STATUS_MASK);
441 int exynos_dp_write_byte_to_dpcd(struct exynos_dp_device *dp,
442 unsigned int reg_addr,
449 for (i = 0; i < 3; i++) {
450 /* Clear AUX CH data buffer */
452 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
454 /* Select DPCD device address */
455 reg = AUX_ADDR_7_0(reg_addr);
456 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
457 reg = AUX_ADDR_15_8(reg_addr);
458 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
459 reg = AUX_ADDR_19_16(reg_addr);
460 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
462 /* Write data buffer */
463 reg = (unsigned int)data;
464 writel(reg, dp->reg_base + EXYNOS_DP_BUF_DATA_0);
467 * Set DisplayPort transaction and write 1 byte
468 * If bit 3 is 1, DisplayPort transaction.
469 * If Bit 3 is 0, I2C transaction.
471 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
472 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
474 /* Start AUX transaction */
475 retval = exynos_dp_start_aux_transaction(dp);
479 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
486 int exynos_dp_read_byte_from_dpcd(struct exynos_dp_device *dp,
487 unsigned int reg_addr,
494 for (i = 0; i < 10; i++) {
495 /* Clear AUX CH data buffer */
497 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
499 /* Select DPCD device address */
500 reg = AUX_ADDR_7_0(reg_addr);
501 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
502 reg = AUX_ADDR_15_8(reg_addr);
503 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
504 reg = AUX_ADDR_19_16(reg_addr);
505 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
508 * Set DisplayPort transaction and read 1 byte
509 * If bit 3 is 1, DisplayPort transaction.
510 * If Bit 3 is 0, I2C transaction.
512 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
513 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
515 /* Start AUX transaction */
516 retval = exynos_dp_start_aux_transaction(dp);
520 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
524 /* Read data buffer */
525 reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0);
526 *data = (unsigned char)(reg & 0xff);
531 int exynos_dp_write_bytes_to_dpcd(struct exynos_dp_device *dp,
532 unsigned int reg_addr,
534 unsigned char data[])
537 unsigned int start_offset;
538 unsigned int cur_data_count;
539 unsigned int cur_data_idx;
543 /* Clear AUX CH data buffer */
545 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
548 while (start_offset < count) {
549 /* Buffer size of AUX CH is 16 * 4bytes */
550 if ((count - start_offset) > 16)
553 cur_data_count = count - start_offset;
555 for (i = 0; i < 10; i++) {
556 /* Select DPCD device address */
557 reg = AUX_ADDR_7_0(reg_addr + start_offset);
558 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
559 reg = AUX_ADDR_15_8(reg_addr + start_offset);
560 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
561 reg = AUX_ADDR_19_16(reg_addr + start_offset);
562 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
564 for (cur_data_idx = 0; cur_data_idx < cur_data_count;
566 reg = data[start_offset + cur_data_idx];
567 writel(reg, dp->reg_base + EXYNOS_DP_BUF_DATA_0
572 * Set DisplayPort transaction and write
573 * If bit 3 is 1, DisplayPort transaction.
574 * If Bit 3 is 0, I2C transaction.
576 reg = AUX_LENGTH(cur_data_count) |
577 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE;
578 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
580 /* Start AUX transaction */
581 retval = exynos_dp_start_aux_transaction(dp);
585 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
589 start_offset += cur_data_count;
595 int exynos_dp_read_bytes_from_dpcd(struct exynos_dp_device *dp,
596 unsigned int reg_addr,
598 unsigned char data[])
601 unsigned int start_offset;
602 unsigned int cur_data_count;
603 unsigned int cur_data_idx;
607 /* Clear AUX CH data buffer */
609 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
612 while (start_offset < count) {
613 /* Buffer size of AUX CH is 16 * 4bytes */
614 if ((count - start_offset) > 16)
617 cur_data_count = count - start_offset;
619 /* AUX CH Request Transaction process */
620 for (i = 0; i < 10; i++) {
621 /* Select DPCD device address */
622 reg = AUX_ADDR_7_0(reg_addr + start_offset);
623 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
624 reg = AUX_ADDR_15_8(reg_addr + start_offset);
625 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
626 reg = AUX_ADDR_19_16(reg_addr + start_offset);
627 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
630 * Set DisplayPort transaction and read
631 * If bit 3 is 1, DisplayPort transaction.
632 * If Bit 3 is 0, I2C transaction.
634 reg = AUX_LENGTH(cur_data_count) |
635 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ;
636 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
638 /* Start AUX transaction */
639 retval = exynos_dp_start_aux_transaction(dp);
643 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
647 for (cur_data_idx = 0; cur_data_idx < cur_data_count;
649 reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0
651 data[start_offset + cur_data_idx] =
655 start_offset += cur_data_count;
661 int exynos_dp_select_i2c_device(struct exynos_dp_device *dp,
662 unsigned int device_addr,
663 unsigned int reg_addr)
668 /* Set EDID device address */
670 writel(reg, dp->reg_base + EXYNOS_DP_AUX_ADDR_7_0);
671 writel(0x0, dp->reg_base + EXYNOS_DP_AUX_ADDR_15_8);
672 writel(0x0, dp->reg_base + EXYNOS_DP_AUX_ADDR_19_16);
674 /* Set offset from base address of EDID device */
675 writel(reg_addr, dp->reg_base + EXYNOS_DP_BUF_DATA_0);
678 * Set I2C transaction and write address
679 * If bit 3 is 1, DisplayPort transaction.
680 * If Bit 3 is 0, I2C transaction.
682 reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT |
684 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
686 /* Start AUX transaction */
687 retval = exynos_dp_start_aux_transaction(dp);
689 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__);
694 int exynos_dp_read_byte_from_i2c(struct exynos_dp_device *dp,
695 unsigned int device_addr,
696 unsigned int reg_addr,
703 for (i = 0; i < 10; i++) {
704 /* Clear AUX CH data buffer */
706 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
708 /* Select EDID device */
709 retval = exynos_dp_select_i2c_device(dp, device_addr, reg_addr);
711 dev_err(dp->dev, "Select EDID device fail!\n");
716 * Set I2C transaction and read data
717 * If bit 3 is 1, DisplayPort transaction.
718 * If Bit 3 is 0, I2C transaction.
720 reg = AUX_TX_COMM_I2C_TRANSACTION |
722 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_1);
724 /* Start AUX transaction */
725 retval = exynos_dp_start_aux_transaction(dp);
729 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n",
735 *data = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0);
740 int exynos_dp_read_bytes_from_i2c(struct exynos_dp_device *dp,
741 unsigned int device_addr,
742 unsigned int reg_addr,
744 unsigned char edid[])
748 unsigned int cur_data_idx;
749 unsigned int defer = 0;
752 for (i = 0; i < count; i += 16) {
753 for (j = 0; j < 100; j++) {
754 /* Clear AUX CH data buffer */
756 writel(reg, dp->reg_base + EXYNOS_DP_BUFFER_DATA_CTL);
758 /* Set normal AUX CH command */
759 reg = readl(dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
761 writel(reg, dp->reg_base + EXYNOS_DP_AUX_CH_CTL_2);
764 * If Rx sends defer, Tx sends only reads
765 * request without sending address
768 retval = exynos_dp_select_i2c_device(dp,
769 device_addr, reg_addr + i);
775 * Set I2C transaction and write data
776 * If bit 3 is 1, DisplayPort transaction.
777 * If Bit 3 is 0, I2C transaction.
779 reg = AUX_LENGTH(16) |
780 AUX_TX_COMM_I2C_TRANSACTION |
782 writel(reg, dp->reg_base +
783 EXYNOS_DP_AUX_CH_CTL_1);
785 /* Start AUX transaction */
786 retval = exynos_dp_start_aux_transaction(dp);
791 "%s: Aux Transaction fail!\n",
794 /* Check if Rx sends defer */
795 reg = readl(dp->reg_base + EXYNOS_DP_AUX_RX_COMM);
796 if (reg == AUX_RX_COMM_AUX_DEFER ||
797 reg == AUX_RX_COMM_I2C_DEFER) {
798 dev_err(dp->dev, "Defer: %d\n\n", reg);
803 for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) {
804 reg = readl(dp->reg_base + EXYNOS_DP_BUF_DATA_0
806 edid[i + cur_data_idx] = (unsigned char)reg;
813 void exynos_dp_set_link_bandwidth(struct exynos_dp_device *dp, u32 bwtype)
818 if ((bwtype == LINK_RATE_2_70GBPS) || (bwtype == LINK_RATE_1_62GBPS))
819 writel(reg, dp->reg_base + EXYNOS_DP_LINK_BW_SET);
822 void exynos_dp_get_link_bandwidth(struct exynos_dp_device *dp, u32 *bwtype)
826 reg = readl(dp->reg_base + EXYNOS_DP_LINK_BW_SET);
830 void exynos_dp_set_lane_count(struct exynos_dp_device *dp, u32 count)
835 writel(reg, dp->reg_base + EXYNOS_DP_LANE_COUNT_SET);
838 void exynos_dp_get_lane_count(struct exynos_dp_device *dp, u32 *count)
842 reg = readl(dp->reg_base + EXYNOS_DP_LANE_COUNT_SET);
846 void exynos_dp_enable_enhanced_mode(struct exynos_dp_device *dp, bool enable)
851 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
853 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
855 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
857 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
861 void exynos_dp_set_training_pattern(struct exynos_dp_device *dp,
862 enum pattern_set pattern)
868 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7;
869 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
872 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2;
873 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
876 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1;
877 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
880 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2;
881 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
884 reg = SCRAMBLING_ENABLE |
885 LINK_QUAL_PATTERN_SET_DISABLE |
886 SW_TRAINING_PATTERN_SET_NORMAL;
887 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
894 void exynos_dp_set_lane0_pre_emphasis(struct exynos_dp_device *dp, u32 level)
898 reg = readl(dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
899 reg &= ~PRE_EMPHASIS_SET_MASK;
900 reg |= level << PRE_EMPHASIS_SET_SHIFT;
901 writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
904 void exynos_dp_set_lane1_pre_emphasis(struct exynos_dp_device *dp, u32 level)
908 reg = readl(dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
909 reg &= ~PRE_EMPHASIS_SET_MASK;
910 reg |= level << PRE_EMPHASIS_SET_SHIFT;
911 writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
914 void exynos_dp_set_lane2_pre_emphasis(struct exynos_dp_device *dp, u32 level)
918 reg = readl(dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
919 reg &= ~PRE_EMPHASIS_SET_MASK;
920 reg |= level << PRE_EMPHASIS_SET_SHIFT;
921 writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
924 void exynos_dp_set_lane3_pre_emphasis(struct exynos_dp_device *dp, u32 level)
928 reg = readl(dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
929 reg &= ~PRE_EMPHASIS_SET_MASK;
930 reg |= level << PRE_EMPHASIS_SET_SHIFT;
931 writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
934 void exynos_dp_set_lane0_link_training(struct exynos_dp_device *dp,
940 writel(reg, dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
943 void exynos_dp_set_lane1_link_training(struct exynos_dp_device *dp,
949 writel(reg, dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
952 void exynos_dp_set_lane2_link_training(struct exynos_dp_device *dp,
958 writel(reg, dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
961 void exynos_dp_set_lane3_link_training(struct exynos_dp_device *dp,
967 writel(reg, dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
970 u32 exynos_dp_get_lane0_link_training(struct exynos_dp_device *dp)
974 reg = readl(dp->reg_base + EXYNOS_DP_LN0_LINK_TRAINING_CTL);
978 u32 exynos_dp_get_lane1_link_training(struct exynos_dp_device *dp)
982 reg = readl(dp->reg_base + EXYNOS_DP_LN1_LINK_TRAINING_CTL);
986 u32 exynos_dp_get_lane2_link_training(struct exynos_dp_device *dp)
990 reg = readl(dp->reg_base + EXYNOS_DP_LN2_LINK_TRAINING_CTL);
994 u32 exynos_dp_get_lane3_link_training(struct exynos_dp_device *dp)
998 reg = readl(dp->reg_base + EXYNOS_DP_LN3_LINK_TRAINING_CTL);
1002 void exynos_dp_reset_macro(struct exynos_dp_device *dp)
1006 reg = readl(dp->reg_base + EXYNOS_DP_PHY_TEST);
1008 writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST);
1010 /* 10 us is the minimum reset time. */
1011 usleep_range(10, 20);
1014 writel(reg, dp->reg_base + EXYNOS_DP_PHY_TEST);
1017 void exynos_dp_init_video(struct exynos_dp_device *dp)
1021 reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG;
1022 writel(reg, dp->reg_base + EXYNOS_DP_COMMON_INT_STA_1);
1025 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
1027 reg = CHA_CRI(4) | CHA_CTRL;
1028 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
1031 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
1033 reg = VID_HRES_TH(2) | VID_VRES_TH(0);
1034 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_8);
1037 void exynos_dp_set_video_color_format(struct exynos_dp_device *dp,
1045 /* Configure the input color depth, color space, dynamic range */
1046 reg = (dynamic_range << IN_D_RANGE_SHIFT) |
1047 (color_depth << IN_BPC_SHIFT) |
1048 (color_space << IN_COLOR_F_SHIFT);
1049 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_2);
1051 /* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */
1052 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_3);
1053 reg &= ~IN_YC_COEFFI_MASK;
1055 reg |= IN_YC_COEFFI_ITU709;
1057 reg |= IN_YC_COEFFI_ITU601;
1058 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_3);
1061 int exynos_dp_is_slave_video_stream_clock_on(struct exynos_dp_device *dp)
1065 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1);
1066 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_1);
1068 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_1);
1070 if (!(reg & DET_STA)) {
1071 dev_dbg(dp->dev, "Input stream clock not detected.\n");
1075 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_2);
1076 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_2);
1078 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_2);
1079 dev_dbg(dp->dev, "wait SYS_CTL_2.\n");
1081 if (reg & CHA_STA) {
1082 dev_dbg(dp->dev, "Input stream clk is changing\n");
1089 void exynos_dp_set_video_cr_mn(struct exynos_dp_device *dp,
1090 enum clock_recovery_m_value_type type,
1096 if (type == REGISTER_M) {
1097 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
1099 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
1100 reg = m_value & 0xff;
1101 writel(reg, dp->reg_base + EXYNOS_DP_M_VID_0);
1102 reg = (m_value >> 8) & 0xff;
1103 writel(reg, dp->reg_base + EXYNOS_DP_M_VID_1);
1104 reg = (m_value >> 16) & 0xff;
1105 writel(reg, dp->reg_base + EXYNOS_DP_M_VID_2);
1107 reg = n_value & 0xff;
1108 writel(reg, dp->reg_base + EXYNOS_DP_N_VID_0);
1109 reg = (n_value >> 8) & 0xff;
1110 writel(reg, dp->reg_base + EXYNOS_DP_N_VID_1);
1111 reg = (n_value >> 16) & 0xff;
1112 writel(reg, dp->reg_base + EXYNOS_DP_N_VID_2);
1114 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_4);
1116 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_4);
1118 writel(0x00, dp->reg_base + EXYNOS_DP_N_VID_0);
1119 writel(0x80, dp->reg_base + EXYNOS_DP_N_VID_1);
1120 writel(0x00, dp->reg_base + EXYNOS_DP_N_VID_2);
1124 void exynos_dp_set_video_timing_mode(struct exynos_dp_device *dp, u32 type)
1128 if (type == VIDEO_TIMING_FROM_CAPTURE) {
1129 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1131 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1133 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1135 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1139 void exynos_dp_enable_video_master(struct exynos_dp_device *dp, bool enable)
1144 reg = readl(dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
1145 reg &= ~VIDEO_MODE_MASK;
1146 reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE;
1147 writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
1149 reg = readl(dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
1150 reg &= ~VIDEO_MODE_MASK;
1151 reg |= VIDEO_MODE_SLAVE_MODE;
1152 writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
1156 void exynos_dp_start_video(struct exynos_dp_device *dp)
1160 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
1162 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_1);
1165 int exynos_dp_is_video_stream_on(struct exynos_dp_device *dp)
1169 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
1170 writel(reg, dp->reg_base + EXYNOS_DP_SYS_CTL_3);
1172 reg = readl(dp->reg_base + EXYNOS_DP_SYS_CTL_3);
1173 if (!(reg & STRM_VALID)) {
1174 dev_dbg(dp->dev, "Input video stream is not detected.\n");
1181 void exynos_dp_config_video_slave_mode(struct exynos_dp_device *dp,
1182 struct video_info *video_info)
1186 reg = readl(dp->reg_base + EXYNOS_DP_FUNC_EN_1);
1187 reg &= ~(MASTER_VID_FUNC_EN_N|SLAVE_VID_FUNC_EN_N);
1188 reg |= MASTER_VID_FUNC_EN_N;
1189 writel(reg, dp->reg_base + EXYNOS_DP_FUNC_EN_1);
1191 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1192 reg &= ~INTERACE_SCAN_CFG;
1193 reg |= (video_info->interlaced << 2);
1194 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1196 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1197 reg &= ~VSYNC_POLARITY_CFG;
1198 reg |= (video_info->v_sync_polarity << 1);
1199 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1201 reg = readl(dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1202 reg &= ~HSYNC_POLARITY_CFG;
1203 reg |= (video_info->h_sync_polarity << 0);
1204 writel(reg, dp->reg_base + EXYNOS_DP_VIDEO_CTL_10);
1206 reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE;
1207 writel(reg, dp->reg_base + EXYNOS_DP_SOC_GENERAL_CTL);
1210 void exynos_dp_enable_scrambling(struct exynos_dp_device *dp)
1214 reg = readl(dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
1215 reg &= ~SCRAMBLING_DISABLE;
1216 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
1219 void exynos_dp_disable_scrambling(struct exynos_dp_device *dp)
1223 reg = readl(dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);
1224 reg |= SCRAMBLING_DISABLE;
1225 writel(reg, dp->reg_base + EXYNOS_DP_TRAINING_PTN_SET);