1 /* $Id: aty128fb.c,v 1.1.1.1.36.1 1999/12/11 09:03:05 Exp $
2 * linux/drivers/video/aty128fb.c -- Frame buffer device for ATI Rage128
4 * Copyright (C) 1999-2003, Brad Douglas <brad@neruo.com>
5 * Copyright (C) 1999, Anthony Tong <atong@uiuc.edu>
7 * Ani Joshi / Jeff Garzik
10 * Michel Danzer <michdaen@iiic.ethz.ch>
14 * Benjamin Herrenschmidt
15 * - pmac-specific PM stuff
16 * - various fixes & cleanups
18 * Andreas Hundt <andi@convergence.de>
21 * Paul Mackerras <paulus@samba.org>
22 * - Convert to new framebuffer API,
23 * fix colormap setting at 16 bits/pixel (565)
28 * Jon Smirl <jonsmirl@yahoo.com>
30 * - replace ROM BIOS search
32 * Based off of Geert's atyfb.c and vfb.c.
35 * - monitor sensing (DDC)
37 * - other platform support (only ppc/x86 supported)
38 * - hardware cursor support
40 * Please cc: your patches to brad@neruo.com.
44 * A special note of gratitude to ATI's devrel for providing documentation,
45 * example code and hardware. Thanks Nitya. -atong and brad
49 #include <linux/module.h>
50 #include <linux/moduleparam.h>
51 #include <linux/kernel.h>
52 #include <linux/errno.h>
53 #include <linux/string.h>
55 #include <linux/vmalloc.h>
56 #include <linux/delay.h>
57 #include <linux/interrupt.h>
58 #include <linux/uaccess.h>
60 #include <linux/init.h>
61 #include <linux/pci.h>
62 #include <linux/ioport.h>
63 #include <linux/console.h>
64 #include <linux/backlight.h>
67 #ifdef CONFIG_PPC_PMAC
68 #include <asm/machdep.h>
69 #include <asm/pmac_feature.h>
71 #include <asm/pci-bridge.h>
72 #include "../macmodes.h"
75 #ifdef CONFIG_PMAC_BACKLIGHT
76 #include <asm/backlight.h>
79 #ifdef CONFIG_BOOTX_TEXT
80 #include <asm/btext.h>
81 #endif /* CONFIG_BOOTX_TEXT */
87 #include <video/aty128.h>
93 #define DBG(fmt, args...) \
94 printk(KERN_DEBUG "aty128fb: %s " fmt, __func__, ##args);
96 #define DBG(fmt, args...)
99 #ifndef CONFIG_PPC_PMAC
101 static struct fb_var_screeninfo default_var = {
102 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
103 640, 480, 640, 480, 0, 0, 8, 0,
104 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
105 0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
106 0, FB_VMODE_NONINTERLACED
109 #else /* CONFIG_PPC_PMAC */
110 /* default to 1024x768 at 75Hz on PPC - this will work
111 * on the iMac, the usual 640x480 @ 60Hz doesn't. */
112 static struct fb_var_screeninfo default_var = {
113 /* 1024x768, 75 Hz, Non-Interlaced (78.75 MHz dotclock) */
114 1024, 768, 1024, 768, 0, 0, 8, 0,
115 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
116 0, 0, -1, -1, 0, 12699, 160, 32, 28, 1, 96, 3,
117 FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
118 FB_VMODE_NONINTERLACED
120 #endif /* CONFIG_PPC_PMAC */
122 /* default modedb mode */
123 /* 640x480, 60 Hz, Non-Interlaced (25.172 MHz dotclock) */
124 static struct fb_videomode defaultmode = {
136 .vmode = FB_VMODE_NONINTERLACED
139 /* Chip generations */
151 /* Must match above enum */
152 static char * const r128_family[] = {
164 * PCI driver prototypes
166 static int aty128_probe(struct pci_dev *pdev,
167 const struct pci_device_id *ent);
168 static void aty128_remove(struct pci_dev *pdev);
169 static int aty128_pci_suspend(struct pci_dev *pdev, pm_message_t state);
170 static int aty128_pci_resume(struct pci_dev *pdev);
171 static int aty128_do_resume(struct pci_dev *pdev);
173 /* supported Rage128 chipsets */
174 static struct pci_device_id aty128_pci_tbl[] = {
175 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_LE,
176 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M3_pci },
177 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_LF,
178 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M3 },
179 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_MF,
180 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M4 },
181 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_ML,
182 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_M4 },
183 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PA,
184 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
185 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PB,
186 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
187 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PC,
188 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
189 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PD,
190 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
191 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PE,
192 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
193 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PF,
194 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
195 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PG,
196 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
197 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PH,
198 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
199 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PI,
200 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
201 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PJ,
202 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
203 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PK,
204 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
205 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PL,
206 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
207 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PM,
208 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
209 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PN,
210 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
211 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PO,
212 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
213 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PP,
214 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
215 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PQ,
216 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
217 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PR,
218 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro_pci },
219 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PS,
220 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
221 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PT,
222 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
223 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PU,
224 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
225 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PV,
226 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
227 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PW,
228 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
229 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_PX,
230 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pro },
231 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RE,
232 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
233 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RF,
234 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
235 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RG,
236 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
237 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RK,
238 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
239 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_RL,
240 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
241 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SE,
242 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
243 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SF,
244 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_pci },
245 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SG,
246 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
247 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SH,
248 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
249 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SK,
250 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
251 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SL,
252 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
253 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SM,
254 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
255 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_SN,
256 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128 },
257 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TF,
258 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
259 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TL,
260 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
261 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TR,
262 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
263 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TS,
264 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
265 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TT,
266 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
267 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RAGE128_TU,
268 PCI_ANY_ID, PCI_ANY_ID, 0, 0, rage_128_ultra },
272 MODULE_DEVICE_TABLE(pci, aty128_pci_tbl);
274 static struct pci_driver aty128fb_driver = {
276 .id_table = aty128_pci_tbl,
277 .probe = aty128_probe,
278 .remove = aty128_remove,
279 .suspend = aty128_pci_suspend,
280 .resume = aty128_pci_resume,
283 /* packed BIOS settings */
288 u8 accelerator_entry;
290 u16 VGA_table_offset;
291 u16 POST_table_offset;
297 u16 PCLK_ref_divider;
301 u16 MCLK_ref_divider;
305 u16 XCLK_ref_divider;
308 } __attribute__ ((packed)) PLL_BLOCK;
309 #endif /* !CONFIG_PPC */
311 /* onboard memory information */
312 struct aty128_meminfo {
326 /* various memory configurations */
327 static const struct aty128_meminfo sdr_128 =
328 { 4, 4, 3, 3, 1, 3, 1, 16, 30, 16, "128-bit SDR SGRAM (1:1)" };
329 static const struct aty128_meminfo sdr_64 =
330 { 4, 8, 3, 3, 1, 3, 1, 17, 46, 17, "64-bit SDR SGRAM (1:1)" };
331 static const struct aty128_meminfo sdr_sgram =
332 { 4, 4, 1, 2, 1, 2, 1, 16, 24, 16, "64-bit SDR SGRAM (2:1)" };
333 static const struct aty128_meminfo ddr_sgram =
334 { 4, 4, 3, 3, 2, 3, 1, 16, 31, 16, "64-bit DDR SGRAM" };
336 static struct fb_fix_screeninfo aty128fb_fix = {
338 .type = FB_TYPE_PACKED_PIXELS,
339 .visual = FB_VISUAL_PSEUDOCOLOR,
343 .accel = FB_ACCEL_ATI_RAGE128,
346 static char *mode_option = NULL;
348 #ifdef CONFIG_PPC_PMAC
349 static int default_vmode = VMODE_1024_768_60;
350 static int default_cmode = CMODE_8;
353 static int default_crt_on = 0;
354 static int default_lcd_on = 1;
357 static bool mtrr = true;
360 #ifdef CONFIG_FB_ATY128_BACKLIGHT
361 #ifdef CONFIG_PMAC_BACKLIGHT
362 static int backlight = 1;
364 static int backlight = 0;
369 struct aty128_constants {
381 u32 h_total, h_sync_strt_wid;
382 u32 v_total, v_sync_strt_wid;
384 u32 offset, offset_cntl;
385 u32 xoffset, yoffset;
392 u32 feedback_divider;
396 struct aty128_ddafifo {
401 /* register values for a specific mode */
402 struct aty128fb_par {
403 struct aty128_crtc crtc;
404 struct aty128_pll pll;
405 struct aty128_ddafifo fifo_reg;
407 struct aty128_constants constants; /* PLL and others */
408 void __iomem *regbase; /* remapped mmio */
409 u32 vram_size; /* onboard video ram */
411 const struct aty128_meminfo *mem; /* onboard mem info */
413 struct { int vram; int vram_valid; } mtrr;
415 int blitter_may_be_busy;
416 int fifo_slots; /* free slots in FIFO (64 max) */
419 struct pci_dev *pdev;
420 struct fb_info *next;
424 u8 red[32]; /* see aty128fb_setcolreg */
427 u32 pseudo_palette[16]; /* used for TRUECOLOR */
431 #define round_div(n, d) ((n+(d/2))/d)
433 static int aty128fb_check_var(struct fb_var_screeninfo *var,
434 struct fb_info *info);
435 static int aty128fb_set_par(struct fb_info *info);
436 static int aty128fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
437 u_int transp, struct fb_info *info);
438 static int aty128fb_pan_display(struct fb_var_screeninfo *var,
440 static int aty128fb_blank(int blank, struct fb_info *fb);
441 static int aty128fb_ioctl(struct fb_info *info, u_int cmd, unsigned long arg);
442 static int aty128fb_sync(struct fb_info *info);
448 static int aty128_encode_var(struct fb_var_screeninfo *var,
449 const struct aty128fb_par *par);
450 static int aty128_decode_var(struct fb_var_screeninfo *var,
451 struct aty128fb_par *par);
453 static void aty128_get_pllinfo(struct aty128fb_par *par, void __iomem *bios);
454 static void __iomem *aty128_map_ROM(struct pci_dev *pdev,
455 const struct aty128fb_par *par);
457 static void aty128_timings(struct aty128fb_par *par);
458 static void aty128_init_engine(struct aty128fb_par *par);
459 static void aty128_reset_engine(const struct aty128fb_par *par);
460 static void aty128_flush_pixel_cache(const struct aty128fb_par *par);
461 static void do_wait_for_fifo(u16 entries, struct aty128fb_par *par);
462 static void wait_for_fifo(u16 entries, struct aty128fb_par *par);
463 static void wait_for_idle(struct aty128fb_par *par);
464 static u32 depth_to_dst(u32 depth);
466 #ifdef CONFIG_FB_ATY128_BACKLIGHT
467 static void aty128_bl_set_power(struct fb_info *info, int power);
470 #define BIOS_IN8(v) (readb(bios + (v)))
471 #define BIOS_IN16(v) (readb(bios + (v)) | \
472 (readb(bios + (v) + 1) << 8))
473 #define BIOS_IN32(v) (readb(bios + (v)) | \
474 (readb(bios + (v) + 1) << 8) | \
475 (readb(bios + (v) + 2) << 16) | \
476 (readb(bios + (v) + 3) << 24))
479 static struct fb_ops aty128fb_ops = {
480 .owner = THIS_MODULE,
481 .fb_check_var = aty128fb_check_var,
482 .fb_set_par = aty128fb_set_par,
483 .fb_setcolreg = aty128fb_setcolreg,
484 .fb_pan_display = aty128fb_pan_display,
485 .fb_blank = aty128fb_blank,
486 .fb_ioctl = aty128fb_ioctl,
487 .fb_sync = aty128fb_sync,
488 .fb_fillrect = cfb_fillrect,
489 .fb_copyarea = cfb_copyarea,
490 .fb_imageblit = cfb_imageblit,
494 * Functions to read from/write to the mmio registers
495 * - endian conversions may possibly be avoided by
496 * using the other register aperture. TODO.
498 static inline u32 _aty_ld_le32(volatile unsigned int regindex,
499 const struct aty128fb_par *par)
501 return readl (par->regbase + regindex);
504 static inline void _aty_st_le32(volatile unsigned int regindex, u32 val,
505 const struct aty128fb_par *par)
507 writel (val, par->regbase + regindex);
510 static inline u8 _aty_ld_8(unsigned int regindex,
511 const struct aty128fb_par *par)
513 return readb (par->regbase + regindex);
516 static inline void _aty_st_8(unsigned int regindex, u8 val,
517 const struct aty128fb_par *par)
519 writeb (val, par->regbase + regindex);
522 #define aty_ld_le32(regindex) _aty_ld_le32(regindex, par)
523 #define aty_st_le32(regindex, val) _aty_st_le32(regindex, val, par)
524 #define aty_ld_8(regindex) _aty_ld_8(regindex, par)
525 #define aty_st_8(regindex, val) _aty_st_8(regindex, val, par)
528 * Functions to read from/write to the pll registers
531 #define aty_ld_pll(pll_index) _aty_ld_pll(pll_index, par)
532 #define aty_st_pll(pll_index, val) _aty_st_pll(pll_index, val, par)
535 static u32 _aty_ld_pll(unsigned int pll_index,
536 const struct aty128fb_par *par)
538 aty_st_8(CLOCK_CNTL_INDEX, pll_index & 0x3F);
539 return aty_ld_le32(CLOCK_CNTL_DATA);
543 static void _aty_st_pll(unsigned int pll_index, u32 val,
544 const struct aty128fb_par *par)
546 aty_st_8(CLOCK_CNTL_INDEX, (pll_index & 0x3F) | PLL_WR_EN);
547 aty_st_le32(CLOCK_CNTL_DATA, val);
551 /* return true when the PLL has completed an atomic update */
552 static int aty_pll_readupdate(const struct aty128fb_par *par)
554 return !(aty_ld_pll(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R);
558 static void aty_pll_wait_readupdate(const struct aty128fb_par *par)
560 unsigned long timeout = jiffies + HZ/100; // should be more than enough
563 while (time_before(jiffies, timeout))
564 if (aty_pll_readupdate(par)) {
569 if (reset) /* reset engine?? */
570 printk(KERN_DEBUG "aty128fb: PLL write timeout!\n");
574 /* tell PLL to update */
575 static void aty_pll_writeupdate(const struct aty128fb_par *par)
577 aty_pll_wait_readupdate(par);
579 aty_st_pll(PPLL_REF_DIV,
580 aty_ld_pll(PPLL_REF_DIV) | PPLL_ATOMIC_UPDATE_W);
584 /* write to the scratch register to test r/w functionality */
585 static int register_test(const struct aty128fb_par *par)
590 val = aty_ld_le32(BIOS_0_SCRATCH);
592 aty_st_le32(BIOS_0_SCRATCH, 0x55555555);
593 if (aty_ld_le32(BIOS_0_SCRATCH) == 0x55555555) {
594 aty_st_le32(BIOS_0_SCRATCH, 0xAAAAAAAA);
596 if (aty_ld_le32(BIOS_0_SCRATCH) == 0xAAAAAAAA)
600 aty_st_le32(BIOS_0_SCRATCH, val); // restore value
606 * Accelerator engine functions
608 static void do_wait_for_fifo(u16 entries, struct aty128fb_par *par)
613 for (i = 0; i < 2000000; i++) {
614 par->fifo_slots = aty_ld_le32(GUI_STAT) & 0x0fff;
615 if (par->fifo_slots >= entries)
618 aty128_reset_engine(par);
623 static void wait_for_idle(struct aty128fb_par *par)
627 do_wait_for_fifo(64, par);
630 for (i = 0; i < 2000000; i++) {
631 if (!(aty_ld_le32(GUI_STAT) & (1 << 31))) {
632 aty128_flush_pixel_cache(par);
633 par->blitter_may_be_busy = 0;
637 aty128_reset_engine(par);
642 static void wait_for_fifo(u16 entries, struct aty128fb_par *par)
644 if (par->fifo_slots < entries)
645 do_wait_for_fifo(64, par);
646 par->fifo_slots -= entries;
650 static void aty128_flush_pixel_cache(const struct aty128fb_par *par)
655 tmp = aty_ld_le32(PC_NGUI_CTLSTAT);
658 aty_st_le32(PC_NGUI_CTLSTAT, tmp);
660 for (i = 0; i < 2000000; i++)
661 if (!(aty_ld_le32(PC_NGUI_CTLSTAT) & PC_BUSY))
666 static void aty128_reset_engine(const struct aty128fb_par *par)
668 u32 gen_reset_cntl, clock_cntl_index, mclk_cntl;
670 aty128_flush_pixel_cache(par);
672 clock_cntl_index = aty_ld_le32(CLOCK_CNTL_INDEX);
673 mclk_cntl = aty_ld_pll(MCLK_CNTL);
675 aty_st_pll(MCLK_CNTL, mclk_cntl | 0x00030000);
677 gen_reset_cntl = aty_ld_le32(GEN_RESET_CNTL);
678 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl | SOFT_RESET_GUI);
679 aty_ld_le32(GEN_RESET_CNTL);
680 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl & ~(SOFT_RESET_GUI));
681 aty_ld_le32(GEN_RESET_CNTL);
683 aty_st_pll(MCLK_CNTL, mclk_cntl);
684 aty_st_le32(CLOCK_CNTL_INDEX, clock_cntl_index);
685 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl);
687 /* use old pio mode */
688 aty_st_le32(PM4_BUFFER_CNTL, PM4_BUFFER_CNTL_NONPM4);
694 static void aty128_init_engine(struct aty128fb_par *par)
700 /* 3D scaler not spoken here */
701 wait_for_fifo(1, par);
702 aty_st_le32(SCALE_3D_CNTL, 0x00000000);
704 aty128_reset_engine(par);
706 pitch_value = par->crtc.pitch;
707 if (par->crtc.bpp == 24) {
708 pitch_value = pitch_value * 3;
711 wait_for_fifo(4, par);
712 /* setup engine offset registers */
713 aty_st_le32(DEFAULT_OFFSET, 0x00000000);
715 /* setup engine pitch registers */
716 aty_st_le32(DEFAULT_PITCH, pitch_value);
718 /* set the default scissor register to max dimensions */
719 aty_st_le32(DEFAULT_SC_BOTTOM_RIGHT, (0x1FFF << 16) | 0x1FFF);
721 /* set the drawing controls registers */
722 aty_st_le32(DP_GUI_MASTER_CNTL,
723 GMC_SRC_PITCH_OFFSET_DEFAULT |
724 GMC_DST_PITCH_OFFSET_DEFAULT |
725 GMC_SRC_CLIP_DEFAULT |
726 GMC_DST_CLIP_DEFAULT |
727 GMC_BRUSH_SOLIDCOLOR |
728 (depth_to_dst(par->crtc.depth) << 8) |
730 GMC_BYTE_ORDER_MSB_TO_LSB |
731 GMC_DP_CONVERSION_TEMP_6500 |
735 GMC_DST_CLR_CMP_FCN_CLEAR |
739 wait_for_fifo(8, par);
740 /* clear the line drawing registers */
741 aty_st_le32(DST_BRES_ERR, 0);
742 aty_st_le32(DST_BRES_INC, 0);
743 aty_st_le32(DST_BRES_DEC, 0);
745 /* set brush color registers */
746 aty_st_le32(DP_BRUSH_FRGD_CLR, 0xFFFFFFFF); /* white */
747 aty_st_le32(DP_BRUSH_BKGD_CLR, 0x00000000); /* black */
749 /* set source color registers */
750 aty_st_le32(DP_SRC_FRGD_CLR, 0xFFFFFFFF); /* white */
751 aty_st_le32(DP_SRC_BKGD_CLR, 0x00000000); /* black */
753 /* default write mask */
754 aty_st_le32(DP_WRITE_MASK, 0xFFFFFFFF);
756 /* Wait for all the writes to be completed before returning */
761 /* convert depth values to their register representation */
762 static u32 depth_to_dst(u32 depth)
766 else if (depth <= 15)
768 else if (depth == 16)
770 else if (depth <= 24)
772 else if (depth <= 32)
779 * PLL informations retreival
784 static void __iomem *aty128_map_ROM(const struct aty128fb_par *par,
792 /* Fix from ATI for problem with Rage128 hardware not leaving ROM enabled */
794 temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG);
797 aty_st_le32(RAGE128_MPP_TB_CONFIG, temp);
798 temp = aty_ld_le32(RAGE128_MPP_TB_CONFIG);
800 bios = pci_map_rom(dev, &rom_size);
803 printk(KERN_ERR "aty128fb: ROM failed to map\n");
807 /* Very simple test to make sure it appeared */
808 if (BIOS_IN16(0) != 0xaa55) {
809 printk(KERN_DEBUG "aty128fb: Invalid ROM signature %x should "
810 " be 0xaa55\n", BIOS_IN16(0));
814 /* Look for the PCI data to check the ROM type */
815 dptr = BIOS_IN16(0x18);
817 /* Check the PCI data signature. If it's wrong, we still assume a normal
818 * x86 ROM for now, until I've verified this works everywhere.
819 * The goal here is more to phase out Open Firmware images.
821 * Currently, we only look at the first PCI data, we could iteratre and
822 * deal with them all, and we should use fb_bios_start relative to start
823 * of image and not relative start of ROM, but so far, I never found a
824 * dual-image ATI card.
827 * u32 signature; + 0x00
830 * u16 reserved_1; + 0x08
832 * u8 drevision; + 0x0c
833 * u8 class_hi; + 0x0d
834 * u16 class_lo; + 0x0e
836 * u16 irevision; + 0x12
838 * u8 indicator; + 0x15
839 * u16 reserved_2; + 0x16
842 if (BIOS_IN32(dptr) != (('R' << 24) | ('I' << 16) | ('C' << 8) | 'P')) {
843 printk(KERN_WARNING "aty128fb: PCI DATA signature in ROM incorrect: %08x\n",
847 rom_type = BIOS_IN8(dptr + 0x14);
850 printk(KERN_INFO "aty128fb: Found Intel x86 BIOS ROM Image\n");
853 printk(KERN_INFO "aty128fb: Found Open Firmware ROM Image\n");
856 printk(KERN_INFO "aty128fb: Found HP PA-RISC ROM Image\n");
859 printk(KERN_INFO "aty128fb: Found unknown type %d ROM Image\n",
867 pci_unmap_rom(dev, bios);
871 static void aty128_get_pllinfo(struct aty128fb_par *par,
872 unsigned char __iomem *bios)
874 unsigned int bios_hdr;
875 unsigned int bios_pll;
877 bios_hdr = BIOS_IN16(0x48);
878 bios_pll = BIOS_IN16(bios_hdr + 0x30);
880 par->constants.ppll_max = BIOS_IN32(bios_pll + 0x16);
881 par->constants.ppll_min = BIOS_IN32(bios_pll + 0x12);
882 par->constants.xclk = BIOS_IN16(bios_pll + 0x08);
883 par->constants.ref_divider = BIOS_IN16(bios_pll + 0x10);
884 par->constants.ref_clk = BIOS_IN16(bios_pll + 0x0e);
886 DBG("ppll_max %d ppll_min %d xclk %d ref_divider %d ref clock %d\n",
887 par->constants.ppll_max, par->constants.ppll_min,
888 par->constants.xclk, par->constants.ref_divider,
889 par->constants.ref_clk);
894 static void __iomem *aty128_find_mem_vbios(struct aty128fb_par *par)
896 /* I simplified this code as we used to miss the signatures in
897 * a lot of case. It's now closer to XFree, we just don't check
898 * for signatures at all... Something better will have to be done
899 * if we end up having conflicts
902 unsigned char __iomem *rom_base = NULL;
904 for (segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
905 rom_base = ioremap(segstart, 0x10000);
906 if (rom_base == NULL)
908 if (readb(rom_base) == 0x55 && readb(rom_base + 1) == 0xaa)
916 #endif /* ndef(__sparc__) */
918 /* fill in known card constants if pll_block is not available */
919 static void aty128_timings(struct aty128fb_par *par)
922 /* instead of a table lookup, assume OF has properly
923 * setup the PLL registers and use their values
924 * to set the XCLK values and reference divider values */
926 u32 x_mpll_ref_fb_div;
929 unsigned PostDivSet[] = { 0, 1, 2, 4, 8, 3, 6, 12 };
932 if (!par->constants.ref_clk)
933 par->constants.ref_clk = 2950;
936 x_mpll_ref_fb_div = aty_ld_pll(X_MPLL_REF_FB_DIV);
937 xclk_cntl = aty_ld_pll(XCLK_CNTL) & 0x7;
938 Nx = (x_mpll_ref_fb_div & 0x00ff00) >> 8;
939 M = x_mpll_ref_fb_div & 0x0000ff;
941 par->constants.xclk = round_div((2 * Nx * par->constants.ref_clk),
942 (M * PostDivSet[xclk_cntl]));
944 par->constants.ref_divider =
945 aty_ld_pll(PPLL_REF_DIV) & PPLL_REF_DIV_MASK;
948 if (!par->constants.ref_divider) {
949 par->constants.ref_divider = 0x3b;
951 aty_st_pll(X_MPLL_REF_FB_DIV, 0x004c4c1e);
952 aty_pll_writeupdate(par);
954 aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider);
955 aty_pll_writeupdate(par);
957 /* from documentation */
958 if (!par->constants.ppll_min)
959 par->constants.ppll_min = 12500;
960 if (!par->constants.ppll_max)
961 par->constants.ppll_max = 25000; /* 23000 on some cards? */
962 if (!par->constants.xclk)
963 par->constants.xclk = 0x1d4d; /* same as mclk */
965 par->constants.fifo_width = 128;
966 par->constants.fifo_depth = 32;
968 switch (aty_ld_le32(MEM_CNTL) & 0x3) {
973 par->mem = &sdr_sgram;
976 par->mem = &ddr_sgram;
979 par->mem = &sdr_sgram;
989 /* Program the CRTC registers */
990 static void aty128_set_crtc(const struct aty128_crtc *crtc,
991 const struct aty128fb_par *par)
993 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl);
994 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_total);
995 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid);
996 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_total);
997 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid);
998 aty_st_le32(CRTC_PITCH, crtc->pitch);
999 aty_st_le32(CRTC_OFFSET, crtc->offset);
1000 aty_st_le32(CRTC_OFFSET_CNTL, crtc->offset_cntl);
1001 /* Disable ATOMIC updating. Is this the right place? */
1002 aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~(0x00030000));
1006 static int aty128_var_to_crtc(const struct fb_var_screeninfo *var,
1007 struct aty128_crtc *crtc,
1008 const struct aty128fb_par *par)
1010 u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp, dst;
1011 u32 left, right, upper, lower, hslen, vslen, sync, vmode;
1012 u32 h_total, h_disp, h_sync_strt, h_sync_wid, h_sync_pol;
1013 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1015 u8 mode_bytpp[7] = { 0, 0, 1, 2, 2, 3, 4 };
1020 vxres = var->xres_virtual;
1021 vyres = var->yres_virtual;
1022 xoffset = var->xoffset;
1023 yoffset = var->yoffset;
1024 bpp = var->bits_per_pixel;
1025 left = var->left_margin;
1026 right = var->right_margin;
1027 upper = var->upper_margin;
1028 lower = var->lower_margin;
1029 hslen = var->hsync_len;
1030 vslen = var->vsync_len;
1037 depth = (var->green.length == 6) ? 16 : 15;
1039 /* check for mode eligibility
1040 * accept only non interlaced modes */
1041 if ((vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
1044 /* convert (and round up) and validate */
1045 xres = (xres + 7) & ~7;
1046 xoffset = (xoffset + 7) & ~7;
1048 if (vxres < xres + xoffset)
1049 vxres = xres + xoffset;
1051 if (vyres < yres + yoffset)
1052 vyres = yres + yoffset;
1054 /* convert depth into ATI register depth */
1055 dst = depth_to_dst(depth);
1057 if (dst == -EINVAL) {
1058 printk(KERN_ERR "aty128fb: Invalid depth or RGBA\n");
1062 /* convert register depth to bytes per pixel */
1063 bytpp = mode_bytpp[dst];
1065 /* make sure there is enough video ram for the mode */
1066 if ((u32)(vxres * vyres * bytpp) > par->vram_size) {
1067 printk(KERN_ERR "aty128fb: Not enough memory for mode\n");
1071 h_disp = (xres >> 3) - 1;
1072 h_total = (((xres + right + hslen + left) >> 3) - 1) & 0xFFFFL;
1075 v_total = (yres + upper + vslen + lower - 1) & 0xFFFFL;
1077 /* check to make sure h_total and v_total are in range */
1078 if (((h_total >> 3) - 1) > 0x1ff || (v_total - 1) > 0x7FF) {
1079 printk(KERN_ERR "aty128fb: invalid width ranges\n");
1083 h_sync_wid = (hslen + 7) >> 3;
1084 if (h_sync_wid == 0)
1086 else if (h_sync_wid > 0x3f) /* 0x3f = max hwidth */
1089 h_sync_strt = (h_disp << 3) + right;
1092 if (v_sync_wid == 0)
1094 else if (v_sync_wid > 0x1f) /* 0x1f = max vwidth */
1097 v_sync_strt = v_disp + lower;
1099 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
1100 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
1102 c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
1104 crtc->gen_cntl = 0x3000000L | c_sync | (dst << 8);
1106 crtc->h_total = h_total | (h_disp << 16);
1107 crtc->v_total = v_total | (v_disp << 16);
1109 crtc->h_sync_strt_wid = h_sync_strt | (h_sync_wid << 16) |
1111 crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid << 16) |
1114 crtc->pitch = vxres >> 3;
1118 if ((var->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW)
1119 crtc->offset_cntl = 0x00010000;
1121 crtc->offset_cntl = 0;
1123 crtc->vxres = vxres;
1124 crtc->vyres = vyres;
1125 crtc->xoffset = xoffset;
1126 crtc->yoffset = yoffset;
1127 crtc->depth = depth;
1134 static int aty128_pix_width_to_var(int pix_width, struct fb_var_screeninfo *var)
1137 /* fill in pixel info */
1138 var->red.msb_right = 0;
1139 var->green.msb_right = 0;
1140 var->blue.offset = 0;
1141 var->blue.msb_right = 0;
1142 var->transp.offset = 0;
1143 var->transp.length = 0;
1144 var->transp.msb_right = 0;
1145 switch (pix_width) {
1146 case CRTC_PIX_WIDTH_8BPP:
1147 var->bits_per_pixel = 8;
1148 var->red.offset = 0;
1149 var->red.length = 8;
1150 var->green.offset = 0;
1151 var->green.length = 8;
1152 var->blue.length = 8;
1154 case CRTC_PIX_WIDTH_15BPP:
1155 var->bits_per_pixel = 16;
1156 var->red.offset = 10;
1157 var->red.length = 5;
1158 var->green.offset = 5;
1159 var->green.length = 5;
1160 var->blue.length = 5;
1162 case CRTC_PIX_WIDTH_16BPP:
1163 var->bits_per_pixel = 16;
1164 var->red.offset = 11;
1165 var->red.length = 5;
1166 var->green.offset = 5;
1167 var->green.length = 6;
1168 var->blue.length = 5;
1170 case CRTC_PIX_WIDTH_24BPP:
1171 var->bits_per_pixel = 24;
1172 var->red.offset = 16;
1173 var->red.length = 8;
1174 var->green.offset = 8;
1175 var->green.length = 8;
1176 var->blue.length = 8;
1178 case CRTC_PIX_WIDTH_32BPP:
1179 var->bits_per_pixel = 32;
1180 var->red.offset = 16;
1181 var->red.length = 8;
1182 var->green.offset = 8;
1183 var->green.length = 8;
1184 var->blue.length = 8;
1185 var->transp.offset = 24;
1186 var->transp.length = 8;
1189 printk(KERN_ERR "aty128fb: Invalid pixel width\n");
1197 static int aty128_crtc_to_var(const struct aty128_crtc *crtc,
1198 struct fb_var_screeninfo *var)
1200 u32 xres, yres, left, right, upper, lower, hslen, vslen, sync;
1201 u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid, h_sync_pol;
1202 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1205 /* fun with masking */
1206 h_total = crtc->h_total & 0x1ff;
1207 h_disp = (crtc->h_total >> 16) & 0xff;
1208 h_sync_strt = (crtc->h_sync_strt_wid >> 3) & 0x1ff;
1209 h_sync_dly = crtc->h_sync_strt_wid & 0x7;
1210 h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x3f;
1211 h_sync_pol = (crtc->h_sync_strt_wid >> 23) & 0x1;
1212 v_total = crtc->v_total & 0x7ff;
1213 v_disp = (crtc->v_total >> 16) & 0x7ff;
1214 v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
1215 v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f;
1216 v_sync_pol = (crtc->v_sync_strt_wid >> 23) & 0x1;
1217 c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
1218 pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
1220 /* do conversions */
1221 xres = (h_disp + 1) << 3;
1223 left = ((h_total - h_sync_strt - h_sync_wid) << 3) - h_sync_dly;
1224 right = ((h_sync_strt - h_disp) << 3) + h_sync_dly;
1225 hslen = h_sync_wid << 3;
1226 upper = v_total - v_sync_strt - v_sync_wid;
1227 lower = v_sync_strt - v_disp;
1229 sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
1230 (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
1231 (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
1233 aty128_pix_width_to_var(pix_width, var);
1237 var->xres_virtual = crtc->vxres;
1238 var->yres_virtual = crtc->vyres;
1239 var->xoffset = crtc->xoffset;
1240 var->yoffset = crtc->yoffset;
1241 var->left_margin = left;
1242 var->right_margin = right;
1243 var->upper_margin = upper;
1244 var->lower_margin = lower;
1245 var->hsync_len = hslen;
1246 var->vsync_len = vslen;
1248 var->vmode = FB_VMODE_NONINTERLACED;
1253 static void aty128_set_crt_enable(struct aty128fb_par *par, int on)
1256 aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) |
1258 aty_st_le32(DAC_CNTL, (aty_ld_le32(DAC_CNTL) |
1259 DAC_PALETTE2_SNOOP_EN));
1261 aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) &
1265 static void aty128_set_lcd_enable(struct aty128fb_par *par, int on)
1268 #ifdef CONFIG_FB_ATY128_BACKLIGHT
1269 struct fb_info *info = pci_get_drvdata(par->pdev);
1273 reg = aty_ld_le32(LVDS_GEN_CNTL);
1274 reg |= LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION;
1275 reg &= ~LVDS_DISPLAY_DIS;
1276 aty_st_le32(LVDS_GEN_CNTL, reg);
1277 #ifdef CONFIG_FB_ATY128_BACKLIGHT
1278 aty128_bl_set_power(info, FB_BLANK_UNBLANK);
1281 #ifdef CONFIG_FB_ATY128_BACKLIGHT
1282 aty128_bl_set_power(info, FB_BLANK_POWERDOWN);
1284 reg = aty_ld_le32(LVDS_GEN_CNTL);
1285 reg |= LVDS_DISPLAY_DIS;
1286 aty_st_le32(LVDS_GEN_CNTL, reg);
1288 reg &= ~(LVDS_ON /*| LVDS_EN*/);
1289 aty_st_le32(LVDS_GEN_CNTL, reg);
1293 static void aty128_set_pll(struct aty128_pll *pll,
1294 const struct aty128fb_par *par)
1298 unsigned char post_conv[] = /* register values for post dividers */
1299 { 2, 0, 1, 4, 2, 2, 6, 2, 3, 2, 2, 2, 7 };
1301 /* select PPLL_DIV_3 */
1302 aty_st_le32(CLOCK_CNTL_INDEX, aty_ld_le32(CLOCK_CNTL_INDEX) | (3 << 8));
1305 aty_st_pll(PPLL_CNTL,
1306 aty_ld_pll(PPLL_CNTL) | PPLL_RESET | PPLL_ATOMIC_UPDATE_EN);
1308 /* write the reference divider */
1309 aty_pll_wait_readupdate(par);
1310 aty_st_pll(PPLL_REF_DIV, par->constants.ref_divider & 0x3ff);
1311 aty_pll_writeupdate(par);
1313 div3 = aty_ld_pll(PPLL_DIV_3);
1314 div3 &= ~PPLL_FB3_DIV_MASK;
1315 div3 |= pll->feedback_divider;
1316 div3 &= ~PPLL_POST3_DIV_MASK;
1317 div3 |= post_conv[pll->post_divider] << 16;
1319 /* write feedback and post dividers */
1320 aty_pll_wait_readupdate(par);
1321 aty_st_pll(PPLL_DIV_3, div3);
1322 aty_pll_writeupdate(par);
1324 aty_pll_wait_readupdate(par);
1325 aty_st_pll(HTOTAL_CNTL, 0); /* no horiz crtc adjustment */
1326 aty_pll_writeupdate(par);
1328 /* clear the reset, just in case */
1329 aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~PPLL_RESET);
1333 static int aty128_var_to_pll(u32 period_in_ps, struct aty128_pll *pll,
1334 const struct aty128fb_par *par)
1336 const struct aty128_constants c = par->constants;
1337 unsigned char post_dividers[] = {1,2,4,8,3,6,12};
1339 u32 vclk; /* in .01 MHz */
1343 vclk = 100000000 / period_in_ps; /* convert units to 10 kHz */
1345 /* adjust pixel clock if necessary */
1346 if (vclk > c.ppll_max)
1348 if (vclk * 12 < c.ppll_min)
1349 vclk = c.ppll_min/12;
1351 /* now, find an acceptable divider */
1352 for (i = 0; i < ARRAY_SIZE(post_dividers); i++) {
1353 output_freq = post_dividers[i] * vclk;
1354 if (output_freq >= c.ppll_min && output_freq <= c.ppll_max) {
1355 pll->post_divider = post_dividers[i];
1360 if (i == ARRAY_SIZE(post_dividers))
1363 /* calculate feedback divider */
1364 n = c.ref_divider * output_freq;
1367 pll->feedback_divider = round_div(n, d);
1370 DBG("post %d feedback %d vlck %d output %d ref_divider %d "
1371 "vclk_per: %d\n", pll->post_divider,
1372 pll->feedback_divider, vclk, output_freq,
1373 c.ref_divider, period_in_ps);
1379 static int aty128_pll_to_var(const struct aty128_pll *pll,
1380 struct fb_var_screeninfo *var)
1382 var->pixclock = 100000000 / pll->vclk;
1388 static void aty128_set_fifo(const struct aty128_ddafifo *dsp,
1389 const struct aty128fb_par *par)
1391 aty_st_le32(DDA_CONFIG, dsp->dda_config);
1392 aty_st_le32(DDA_ON_OFF, dsp->dda_on_off);
1396 static int aty128_ddafifo(struct aty128_ddafifo *dsp,
1397 const struct aty128_pll *pll,
1399 const struct aty128fb_par *par)
1401 const struct aty128_meminfo *m = par->mem;
1402 u32 xclk = par->constants.xclk;
1403 u32 fifo_width = par->constants.fifo_width;
1404 u32 fifo_depth = par->constants.fifo_depth;
1405 s32 x, b, p, ron, roff;
1408 /* round up to multiple of 8 */
1409 bpp = (depth+7) & ~7;
1411 n = xclk * fifo_width;
1412 d = pll->vclk * bpp;
1413 x = round_div(n, d);
1416 3 * ((m->Trcd - 2 > 0) ? m->Trcd - 2 : 0) +
1435 x = round_div(n, d);
1436 roff = x * (fifo_depth - 4);
1438 if ((ron + m->Rloop) >= roff) {
1439 printk(KERN_ERR "aty128fb: Mode out of range!\n");
1443 DBG("p: %x rloop: %x x: %x ron: %x roff: %x\n",
1444 p, m->Rloop, x, ron, roff);
1446 dsp->dda_config = p << 16 | m->Rloop << 20 | x;
1447 dsp->dda_on_off = ron << 16 | roff;
1454 * This actually sets the video mode.
1456 static int aty128fb_set_par(struct fb_info *info)
1458 struct aty128fb_par *par = info->par;
1462 if ((err = aty128_decode_var(&info->var, par)) != 0)
1465 if (par->blitter_may_be_busy)
1468 /* clear all registers that may interfere with mode setting */
1469 aty_st_le32(OVR_CLR, 0);
1470 aty_st_le32(OVR_WID_LEFT_RIGHT, 0);
1471 aty_st_le32(OVR_WID_TOP_BOTTOM, 0);
1472 aty_st_le32(OV0_SCALE_CNTL, 0);
1473 aty_st_le32(MPP_TB_CONFIG, 0);
1474 aty_st_le32(MPP_GP_CONFIG, 0);
1475 aty_st_le32(SUBPIC_CNTL, 0);
1476 aty_st_le32(VIPH_CONTROL, 0);
1477 aty_st_le32(I2C_CNTL_1, 0); /* turn off i2c */
1478 aty_st_le32(GEN_INT_CNTL, 0); /* turn off interrupts */
1479 aty_st_le32(CAP0_TRIG_CNTL, 0);
1480 aty_st_le32(CAP1_TRIG_CNTL, 0);
1482 aty_st_8(CRTC_EXT_CNTL + 1, 4); /* turn video off */
1484 aty128_set_crtc(&par->crtc, par);
1485 aty128_set_pll(&par->pll, par);
1486 aty128_set_fifo(&par->fifo_reg, par);
1488 config = aty_ld_le32(CNFG_CNTL) & ~3;
1490 #if defined(__BIG_ENDIAN)
1491 if (par->crtc.bpp == 32)
1492 config |= 2; /* make aperture do 32 bit swapping */
1493 else if (par->crtc.bpp == 16)
1494 config |= 1; /* make aperture do 16 bit swapping */
1497 aty_st_le32(CNFG_CNTL, config);
1498 aty_st_8(CRTC_EXT_CNTL + 1, 0); /* turn the video back on */
1500 info->fix.line_length = (par->crtc.vxres * par->crtc.bpp) >> 3;
1501 info->fix.visual = par->crtc.bpp == 8 ? FB_VISUAL_PSEUDOCOLOR
1502 : FB_VISUAL_DIRECTCOLOR;
1504 if (par->chip_gen == rage_M3) {
1505 aty128_set_crt_enable(par, par->crt_on);
1506 aty128_set_lcd_enable(par, par->lcd_on);
1508 if (par->accel_flags & FB_ACCELF_TEXT)
1509 aty128_init_engine(par);
1511 #ifdef CONFIG_BOOTX_TEXT
1512 btext_update_display(info->fix.smem_start,
1513 (((par->crtc.h_total>>16) & 0xff)+1)*8,
1514 ((par->crtc.v_total>>16) & 0x7ff)+1,
1516 par->crtc.vxres*par->crtc.bpp/8);
1517 #endif /* CONFIG_BOOTX_TEXT */
1523 * encode/decode the User Defined Part of the Display
1526 static int aty128_decode_var(struct fb_var_screeninfo *var,
1527 struct aty128fb_par *par)
1530 struct aty128_crtc crtc;
1531 struct aty128_pll pll;
1532 struct aty128_ddafifo fifo_reg;
1534 if ((err = aty128_var_to_crtc(var, &crtc, par)))
1537 if ((err = aty128_var_to_pll(var->pixclock, &pll, par)))
1540 if ((err = aty128_ddafifo(&fifo_reg, &pll, crtc.depth, par)))
1545 par->fifo_reg = fifo_reg;
1546 par->accel_flags = var->accel_flags;
1552 static int aty128_encode_var(struct fb_var_screeninfo *var,
1553 const struct aty128fb_par *par)
1557 if ((err = aty128_crtc_to_var(&par->crtc, var)))
1560 if ((err = aty128_pll_to_var(&par->pll, var)))
1568 var->accel_flags = par->accel_flags;
1574 static int aty128fb_check_var(struct fb_var_screeninfo *var,
1575 struct fb_info *info)
1577 struct aty128fb_par par;
1580 par = *(struct aty128fb_par *)info->par;
1581 if ((err = aty128_decode_var(var, &par)) != 0)
1583 aty128_encode_var(var, &par);
1589 * Pan or Wrap the Display
1591 static int aty128fb_pan_display(struct fb_var_screeninfo *var,
1594 struct aty128fb_par *par = fb->par;
1595 u32 xoffset, yoffset;
1599 xres = (((par->crtc.h_total >> 16) & 0xff) + 1) << 3;
1600 yres = ((par->crtc.v_total >> 16) & 0x7ff) + 1;
1602 xoffset = (var->xoffset +7) & ~7;
1603 yoffset = var->yoffset;
1605 if (xoffset+xres > par->crtc.vxres || yoffset+yres > par->crtc.vyres)
1608 par->crtc.xoffset = xoffset;
1609 par->crtc.yoffset = yoffset;
1611 offset = ((yoffset * par->crtc.vxres + xoffset) * (par->crtc.bpp >> 3))
1614 if (par->crtc.bpp == 24)
1615 offset += 8 * (offset % 3); /* Must be multiple of 8 and 3 */
1617 aty_st_le32(CRTC_OFFSET, offset);
1624 * Helper function to store a single palette register
1626 static void aty128_st_pal(u_int regno, u_int red, u_int green, u_int blue,
1627 struct aty128fb_par *par)
1629 if (par->chip_gen == rage_M3) {
1631 /* Note: For now, on M3, we set palette on both heads, which may
1632 * be useless. Can someone with a M3 check this ?
1634 * This code would still be useful if using the second CRTC to
1638 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) |
1639 DAC_PALETTE_ACCESS_CNTL);
1640 aty_st_8(PALETTE_INDEX, regno);
1641 aty_st_le32(PALETTE_DATA, (red<<16)|(green<<8)|blue);
1643 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) &
1644 ~DAC_PALETTE_ACCESS_CNTL);
1647 aty_st_8(PALETTE_INDEX, regno);
1648 aty_st_le32(PALETTE_DATA, (red<<16)|(green<<8)|blue);
1651 static int aty128fb_sync(struct fb_info *info)
1653 struct aty128fb_par *par = info->par;
1655 if (par->blitter_may_be_busy)
1661 static int aty128fb_setup(char *options)
1665 if (!options || !*options)
1668 while ((this_opt = strsep(&options, ",")) != NULL) {
1669 if (!strncmp(this_opt, "lcd:", 4)) {
1670 default_lcd_on = simple_strtoul(this_opt+4, NULL, 0);
1672 } else if (!strncmp(this_opt, "crt:", 4)) {
1673 default_crt_on = simple_strtoul(this_opt+4, NULL, 0);
1675 } else if (!strncmp(this_opt, "backlight:", 10)) {
1676 #ifdef CONFIG_FB_ATY128_BACKLIGHT
1677 backlight = simple_strtoul(this_opt+10, NULL, 0);
1682 if(!strncmp(this_opt, "nomtrr", 6)) {
1687 #ifdef CONFIG_PPC_PMAC
1688 /* vmode and cmode deprecated */
1689 if (!strncmp(this_opt, "vmode:", 6)) {
1690 unsigned int vmode = simple_strtoul(this_opt+6, NULL, 0);
1691 if (vmode > 0 && vmode <= VMODE_MAX)
1692 default_vmode = vmode;
1694 } else if (!strncmp(this_opt, "cmode:", 6)) {
1695 unsigned int cmode = simple_strtoul(this_opt+6, NULL, 0);
1699 default_cmode = CMODE_8;
1703 default_cmode = CMODE_16;
1707 default_cmode = CMODE_32;
1712 #endif /* CONFIG_PPC_PMAC */
1713 mode_option = this_opt;
1720 #ifdef CONFIG_FB_ATY128_BACKLIGHT
1721 #define MAX_LEVEL 0xFF
1723 static int aty128_bl_get_level_brightness(struct aty128fb_par *par,
1726 struct fb_info *info = pci_get_drvdata(par->pdev);
1729 /* Get and convert the value */
1730 /* No locking of bl_curve since we read a single value */
1731 atylevel = MAX_LEVEL -
1732 (info->bl_curve[level] * FB_BACKLIGHT_MAX / MAX_LEVEL);
1736 else if (atylevel > MAX_LEVEL)
1737 atylevel = MAX_LEVEL;
1742 /* We turn off the LCD completely instead of just dimming the backlight.
1743 * This provides greater power saving and the display is useless without
1746 #define BACKLIGHT_LVDS_OFF
1747 /* That one prevents proper CRT output with LCD off */
1748 #undef BACKLIGHT_DAC_OFF
1750 static int aty128_bl_update_status(struct backlight_device *bd)
1752 struct aty128fb_par *par = bl_get_data(bd);
1753 unsigned int reg = aty_ld_le32(LVDS_GEN_CNTL);
1756 if (bd->props.power != FB_BLANK_UNBLANK ||
1757 bd->props.fb_blank != FB_BLANK_UNBLANK ||
1761 level = bd->props.brightness;
1763 reg |= LVDS_BL_MOD_EN | LVDS_BLON;
1766 if (!(reg & LVDS_ON)) {
1768 aty_st_le32(LVDS_GEN_CNTL, reg);
1769 aty_ld_le32(LVDS_GEN_CNTL);
1772 aty_st_le32(LVDS_GEN_CNTL, reg);
1774 reg &= ~LVDS_BL_MOD_LEVEL_MASK;
1775 reg |= (aty128_bl_get_level_brightness(par, level) <<
1776 LVDS_BL_MOD_LEVEL_SHIFT);
1777 #ifdef BACKLIGHT_LVDS_OFF
1778 reg |= LVDS_ON | LVDS_EN;
1779 reg &= ~LVDS_DISPLAY_DIS;
1781 aty_st_le32(LVDS_GEN_CNTL, reg);
1782 #ifdef BACKLIGHT_DAC_OFF
1783 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & (~DAC_PDWN));
1786 reg &= ~LVDS_BL_MOD_LEVEL_MASK;
1787 reg |= (aty128_bl_get_level_brightness(par, 0) <<
1788 LVDS_BL_MOD_LEVEL_SHIFT);
1789 #ifdef BACKLIGHT_LVDS_OFF
1790 reg |= LVDS_DISPLAY_DIS;
1791 aty_st_le32(LVDS_GEN_CNTL, reg);
1792 aty_ld_le32(LVDS_GEN_CNTL);
1794 reg &= ~(LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION);
1796 aty_st_le32(LVDS_GEN_CNTL, reg);
1797 #ifdef BACKLIGHT_DAC_OFF
1798 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | DAC_PDWN);
1805 static const struct backlight_ops aty128_bl_data = {
1806 .update_status = aty128_bl_update_status,
1809 static void aty128_bl_set_power(struct fb_info *info, int power)
1812 info->bl_dev->props.power = power;
1813 backlight_update_status(info->bl_dev);
1817 static void aty128_bl_init(struct aty128fb_par *par)
1819 struct backlight_properties props;
1820 struct fb_info *info = pci_get_drvdata(par->pdev);
1821 struct backlight_device *bd;
1824 /* Could be extended to Rage128Pro LVDS output too */
1825 if (par->chip_gen != rage_M3)
1828 #ifdef CONFIG_PMAC_BACKLIGHT
1829 if (!pmac_has_backlight_type("ati"))
1833 snprintf(name, sizeof(name), "aty128bl%d", info->node);
1835 memset(&props, 0, sizeof(struct backlight_properties));
1836 props.type = BACKLIGHT_RAW;
1837 props.max_brightness = FB_BACKLIGHT_LEVELS - 1;
1838 bd = backlight_device_register(name, info->dev, par, &aty128_bl_data,
1841 info->bl_dev = NULL;
1842 printk(KERN_WARNING "aty128: Backlight registration failed\n");
1847 fb_bl_default_curve(info, 0,
1848 63 * FB_BACKLIGHT_MAX / MAX_LEVEL,
1849 219 * FB_BACKLIGHT_MAX / MAX_LEVEL);
1851 bd->props.brightness = bd->props.max_brightness;
1852 bd->props.power = FB_BLANK_UNBLANK;
1853 backlight_update_status(bd);
1855 printk("aty128: Backlight initialized (%s)\n", name);
1863 static void aty128_bl_exit(struct backlight_device *bd)
1865 backlight_device_unregister(bd);
1866 printk("aty128: Backlight unloaded\n");
1868 #endif /* CONFIG_FB_ATY128_BACKLIGHT */
1874 #ifdef CONFIG_PPC_PMAC__disabled
1875 static void aty128_early_resume(void *data)
1877 struct aty128fb_par *par = data;
1879 if (!console_trylock())
1881 pci_restore_state(par->pdev);
1882 aty128_do_resume(par->pdev);
1885 #endif /* CONFIG_PPC_PMAC */
1887 static int aty128_init(struct pci_dev *pdev, const struct pci_device_id *ent)
1889 struct fb_info *info = pci_get_drvdata(pdev);
1890 struct aty128fb_par *par = info->par;
1891 struct fb_var_screeninfo var;
1892 char video_card[50];
1896 /* Get the chip revision */
1897 chip_rev = (aty_ld_le32(CNFG_CNTL) >> 16) & 0x1F;
1899 strcpy(video_card, "Rage128 XX ");
1900 video_card[8] = ent->device >> 8;
1901 video_card[9] = ent->device & 0xFF;
1903 /* range check to make sure */
1904 if (ent->driver_data < ARRAY_SIZE(r128_family))
1905 strlcat(video_card, r128_family[ent->driver_data],
1906 sizeof(video_card));
1908 printk(KERN_INFO "aty128fb: %s [chip rev 0x%x] ", video_card, chip_rev);
1910 if (par->vram_size % (1024 * 1024) == 0)
1911 printk("%dM %s\n", par->vram_size / (1024*1024), par->mem->name);
1913 printk("%dk %s\n", par->vram_size / 1024, par->mem->name);
1915 par->chip_gen = ent->driver_data;
1918 info->fbops = &aty128fb_ops;
1919 info->flags = FBINFO_FLAG_DEFAULT;
1921 par->lcd_on = default_lcd_on;
1922 par->crt_on = default_crt_on;
1925 #ifdef CONFIG_PPC_PMAC
1926 if (machine_is(powermac)) {
1927 /* Indicate sleep capability */
1928 if (par->chip_gen == rage_M3) {
1929 pmac_call_feature(PMAC_FTR_DEVICE_CAN_WAKE, NULL, 0, 1);
1930 #if 0 /* Disable the early video resume hack for now as it's causing problems,
1931 * among others we now rely on the PCI core restoring the config space
1932 * for us, which isn't the case with that hack, and that code path causes
1933 * various things to be called with interrupts off while they shouldn't.
1934 * I'm leaving the code in as it can be useful for debugging purposes
1936 pmac_set_early_video_resume(aty128_early_resume, par);
1940 /* Find default mode */
1942 if (!mac_find_mode(&var, info, mode_option, 8))
1945 if (default_vmode <= 0 || default_vmode > VMODE_MAX)
1946 default_vmode = VMODE_1024_768_60;
1948 /* iMacs need that resolution
1949 * PowerMac2,1 first r128 iMacs
1950 * PowerMac2,2 summer 2000 iMacs
1951 * PowerMac4,1 january 2001 iMacs "flower power"
1953 if (of_machine_is_compatible("PowerMac2,1") ||
1954 of_machine_is_compatible("PowerMac2,2") ||
1955 of_machine_is_compatible("PowerMac4,1"))
1956 default_vmode = VMODE_1024_768_75;
1959 if (of_machine_is_compatible("PowerBook2,2"))
1960 default_vmode = VMODE_800_600_60;
1962 /* PowerBook Firewire (Pismo), iBook Dual USB */
1963 if (of_machine_is_compatible("PowerBook3,1") ||
1964 of_machine_is_compatible("PowerBook4,1"))
1965 default_vmode = VMODE_1024_768_60;
1967 /* PowerBook Titanium */
1968 if (of_machine_is_compatible("PowerBook3,2"))
1969 default_vmode = VMODE_1152_768_60;
1971 if (default_cmode > 16)
1972 default_cmode = CMODE_32;
1973 else if (default_cmode > 8)
1974 default_cmode = CMODE_16;
1976 default_cmode = CMODE_8;
1978 if (mac_vmode_to_var(default_vmode, default_cmode, &var))
1982 #endif /* CONFIG_PPC_PMAC */
1985 if (fb_find_mode(&var, info, mode_option, NULL,
1986 0, &defaultmode, 8) == 0)
1990 var.accel_flags &= ~FB_ACCELF_TEXT;
1991 // var.accel_flags |= FB_ACCELF_TEXT;/* FIXME Will add accel later */
1993 if (aty128fb_check_var(&var, info)) {
1994 printk(KERN_ERR "aty128fb: Cannot set default mode.\n");
1998 /* setup the DAC the way we like it */
1999 dac = aty_ld_le32(DAC_CNTL);
2000 dac |= (DAC_8BIT_EN | DAC_RANGE_CNTL);
2002 if (par->chip_gen == rage_M3)
2003 dac |= DAC_PALETTE2_SNOOP_EN;
2004 aty_st_le32(DAC_CNTL, dac);
2006 /* turn off bus mastering, just in case */
2007 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL) | BUS_MASTER_DIS);
2010 fb_alloc_cmap(&info->cmap, 256, 0);
2012 var.activate = FB_ACTIVATE_NOW;
2014 aty128_init_engine(par);
2018 par->lock_blank = 0;
2020 #ifdef CONFIG_FB_ATY128_BACKLIGHT
2022 aty128_bl_init(par);
2025 if (register_framebuffer(info) < 0)
2028 fb_info(info, "%s frame buffer device on %s\n",
2029 info->fix.id, video_card);
2031 return 1; /* success! */
2035 /* register a card ++ajoshi */
2036 static int aty128_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
2038 unsigned long fb_addr, reg_addr;
2039 struct aty128fb_par *par;
2040 struct fb_info *info;
2043 void __iomem *bios = NULL;
2046 /* Enable device in PCI config */
2047 if ((err = pci_enable_device(pdev))) {
2048 printk(KERN_ERR "aty128fb: Cannot enable PCI device: %d\n",
2053 fb_addr = pci_resource_start(pdev, 0);
2054 if (!request_mem_region(fb_addr, pci_resource_len(pdev, 0),
2056 printk(KERN_ERR "aty128fb: cannot reserve frame "
2061 reg_addr = pci_resource_start(pdev, 2);
2062 if (!request_mem_region(reg_addr, pci_resource_len(pdev, 2),
2064 printk(KERN_ERR "aty128fb: cannot reserve MMIO region\n");
2068 /* We have the resources. Now virtualize them */
2069 info = framebuffer_alloc(sizeof(struct aty128fb_par), &pdev->dev);
2071 printk(KERN_ERR "aty128fb: can't alloc fb_info_aty128\n");
2076 info->pseudo_palette = par->pseudo_palette;
2078 /* Virtualize mmio region */
2079 info->fix.mmio_start = reg_addr;
2080 par->regbase = pci_ioremap_bar(pdev, 2);
2084 /* Grab memory size from the card */
2085 // How does this relate to the resource length from the PCI hardware?
2086 par->vram_size = aty_ld_le32(CNFG_MEMSIZE) & 0x03FFFFFF;
2088 /* Virtualize the framebuffer */
2089 info->screen_base = ioremap(fb_addr, par->vram_size);
2090 if (!info->screen_base)
2093 /* Set up info->fix */
2094 info->fix = aty128fb_fix;
2095 info->fix.smem_start = fb_addr;
2096 info->fix.smem_len = par->vram_size;
2097 info->fix.mmio_start = reg_addr;
2099 /* If we can't test scratch registers, something is seriously wrong */
2100 if (!register_test(par)) {
2101 printk(KERN_ERR "aty128fb: Can't write to video register!\n");
2106 bios = aty128_map_ROM(par, pdev);
2109 bios = aty128_find_mem_vbios(par);
2112 printk(KERN_INFO "aty128fb: BIOS not located, guessing timings.\n");
2114 printk(KERN_INFO "aty128fb: Rage128 BIOS located\n");
2115 aty128_get_pllinfo(par, bios);
2116 pci_unmap_rom(pdev, bios);
2118 #endif /* __sparc__ */
2120 aty128_timings(par);
2121 pci_set_drvdata(pdev, info);
2123 if (!aty128_init(pdev, ent))
2128 par->mtrr.vram = mtrr_add(info->fix.smem_start,
2129 par->vram_size, MTRR_TYPE_WRCOMB, 1);
2130 par->mtrr.vram_valid = 1;
2131 /* let there be speed */
2132 printk(KERN_INFO "aty128fb: Rage128 MTRR set to ON\n");
2134 #endif /* CONFIG_MTRR */
2138 iounmap(info->screen_base);
2140 iounmap(par->regbase);
2142 framebuffer_release(info);
2144 release_mem_region(pci_resource_start(pdev, 2),
2145 pci_resource_len(pdev, 2));
2147 release_mem_region(pci_resource_start(pdev, 0),
2148 pci_resource_len(pdev, 0));
2152 static void aty128_remove(struct pci_dev *pdev)
2154 struct fb_info *info = pci_get_drvdata(pdev);
2155 struct aty128fb_par *par;
2162 unregister_framebuffer(info);
2164 #ifdef CONFIG_FB_ATY128_BACKLIGHT
2165 aty128_bl_exit(info->bl_dev);
2169 if (par->mtrr.vram_valid)
2170 mtrr_del(par->mtrr.vram, info->fix.smem_start,
2172 #endif /* CONFIG_MTRR */
2173 iounmap(par->regbase);
2174 iounmap(info->screen_base);
2176 release_mem_region(pci_resource_start(pdev, 0),
2177 pci_resource_len(pdev, 0));
2178 release_mem_region(pci_resource_start(pdev, 2),
2179 pci_resource_len(pdev, 2));
2180 framebuffer_release(info);
2182 #endif /* CONFIG_PCI */
2187 * Blank the display.
2189 static int aty128fb_blank(int blank, struct fb_info *fb)
2191 struct aty128fb_par *par = fb->par;
2194 if (par->lock_blank || par->asleep)
2198 case FB_BLANK_NORMAL:
2201 case FB_BLANK_VSYNC_SUSPEND:
2204 case FB_BLANK_HSYNC_SUSPEND:
2207 case FB_BLANK_POWERDOWN:
2210 case FB_BLANK_UNBLANK:
2215 aty_st_8(CRTC_EXT_CNTL+1, state);
2217 if (par->chip_gen == rage_M3) {
2218 aty128_set_crt_enable(par, par->crt_on && !blank);
2219 aty128_set_lcd_enable(par, par->lcd_on && !blank);
2226 * Set a single color register. The values supplied are already
2227 * rounded down to the hardware's capabilities (according to the
2228 * entries in the var structure). Return != 0 for invalid regno.
2230 static int aty128fb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
2231 u_int transp, struct fb_info *info)
2233 struct aty128fb_par *par = info->par;
2236 || (par->crtc.depth == 16 && regno > 63)
2237 || (par->crtc.depth == 15 && regno > 31))
2246 u32 *pal = info->pseudo_palette;
2248 switch (par->crtc.depth) {
2250 pal[regno] = (regno << 10) | (regno << 5) | regno;
2253 pal[regno] = (regno << 11) | (regno << 6) | regno;
2256 pal[regno] = (regno << 16) | (regno << 8) | regno;
2259 i = (regno << 8) | regno;
2260 pal[regno] = (i << 16) | i;
2265 if (par->crtc.depth == 16 && regno > 0) {
2267 * With the 5-6-5 split of bits for RGB at 16 bits/pixel, we
2268 * have 32 slots for R and B values but 64 slots for G values.
2269 * Thus the R and B values go in one slot but the G value
2270 * goes in a different slot, and we have to avoid disturbing
2271 * the other fields in the slots we touch.
2273 par->green[regno] = green;
2275 par->red[regno] = red;
2276 par->blue[regno] = blue;
2277 aty128_st_pal(regno * 8, red, par->green[regno*2],
2280 red = par->red[regno/2];
2281 blue = par->blue[regno/2];
2283 } else if (par->crtc.bpp == 16)
2285 aty128_st_pal(regno, red, green, blue, par);
2290 #define ATY_MIRROR_LCD_ON 0x00000001
2291 #define ATY_MIRROR_CRT_ON 0x00000002
2293 /* out param: u32* backlight value: 0 to 15 */
2294 #define FBIO_ATY128_GET_MIRROR _IOR('@', 1, __u32)
2295 /* in param: u32* backlight value: 0 to 15 */
2296 #define FBIO_ATY128_SET_MIRROR _IOW('@', 2, __u32)
2298 static int aty128fb_ioctl(struct fb_info *info, u_int cmd, u_long arg)
2300 struct aty128fb_par *par = info->par;
2305 case FBIO_ATY128_SET_MIRROR:
2306 if (par->chip_gen != rage_M3)
2308 rc = get_user(value, (__u32 __user *)arg);
2311 par->lcd_on = (value & 0x01) != 0;
2312 par->crt_on = (value & 0x02) != 0;
2313 if (!par->crt_on && !par->lcd_on)
2315 aty128_set_crt_enable(par, par->crt_on);
2316 aty128_set_lcd_enable(par, par->lcd_on);
2318 case FBIO_ATY128_GET_MIRROR:
2319 if (par->chip_gen != rage_M3)
2321 value = (par->crt_on << 1) | par->lcd_on;
2322 return put_user(value, (__u32 __user *)arg);
2329 * Accelerated functions
2332 static inline void aty128_rectcopy(int srcx, int srcy, int dstx, int dsty,
2333 u_int width, u_int height,
2334 struct fb_info_aty128 *par)
2336 u32 save_dp_datatype, save_dp_cntl, dstval;
2338 if (!width || !height)
2341 dstval = depth_to_dst(par->current_par.crtc.depth);
2342 if (dstval == DST_24BPP) {
2346 } else if (dstval == -EINVAL) {
2347 printk("aty128fb: invalid depth or RGBA\n");
2351 wait_for_fifo(2, par);
2352 save_dp_datatype = aty_ld_le32(DP_DATATYPE);
2353 save_dp_cntl = aty_ld_le32(DP_CNTL);
2355 wait_for_fifo(6, par);
2356 aty_st_le32(SRC_Y_X, (srcy << 16) | srcx);
2357 aty_st_le32(DP_MIX, ROP3_SRCCOPY | DP_SRC_RECT);
2358 aty_st_le32(DP_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM);
2359 aty_st_le32(DP_DATATYPE, save_dp_datatype | dstval | SRC_DSTCOLOR);
2361 aty_st_le32(DST_Y_X, (dsty << 16) | dstx);
2362 aty_st_le32(DST_HEIGHT_WIDTH, (height << 16) | width);
2364 par->blitter_may_be_busy = 1;
2366 wait_for_fifo(2, par);
2367 aty_st_le32(DP_DATATYPE, save_dp_datatype);
2368 aty_st_le32(DP_CNTL, save_dp_cntl);
2373 * Text mode accelerated functions
2376 static void fbcon_aty128_bmove(struct display *p, int sy, int sx, int dy,
2377 int dx, int height, int width)
2380 sy *= fontheight(p);
2382 dy *= fontheight(p);
2383 width *= fontwidth(p);
2384 height *= fontheight(p);
2386 aty128_rectcopy(sx, sy, dx, dy, width, height,
2387 (struct fb_info_aty128 *)p->fb_info);
2391 static void aty128_set_suspend(struct aty128fb_par *par, int suspend)
2394 struct pci_dev *pdev = par->pdev;
2396 if (!par->pdev->pm_cap)
2399 /* Set the chip into the appropriate suspend mode (we use D2,
2400 * D3 would require a complete re-initialisation of the chip,
2401 * including PCI config registers, clocks, AGP configuration, ...)
2403 * For resume, the core will have already brought us back to D0
2406 /* Make sure CRTC2 is reset. Remove that the day we decide to
2407 * actually use CRTC2 and replace it with real code for disabling
2408 * the CRTC2 output during sleep
2410 aty_st_le32(CRTC2_GEN_CNTL, aty_ld_le32(CRTC2_GEN_CNTL) &
2413 /* Set the power management mode to be PCI based */
2414 /* Use this magic value for now */
2416 aty_st_pll(POWER_MANAGEMENT, pmgt);
2417 (void)aty_ld_pll(POWER_MANAGEMENT);
2418 aty_st_le32(BUS_CNTL1, 0x00000010);
2419 aty_st_le32(MEM_POWER_MISC, 0x0c830000);
2422 /* Switch PCI power management to D2 */
2423 pci_set_power_state(pdev, PCI_D2);
2427 static int aty128_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2429 struct fb_info *info = pci_get_drvdata(pdev);
2430 struct aty128fb_par *par = info->par;
2432 /* Because we may change PCI D state ourselves, we need to
2433 * first save the config space content so the core can
2434 * restore it properly on resume.
2436 pci_save_state(pdev);
2438 /* We don't do anything but D2, for now we return 0, but
2439 * we may want to change that. How do we know if the BIOS
2440 * can properly take care of D3 ? Also, with swsusp, we
2441 * know we'll be rebooted, ...
2443 #ifndef CONFIG_PPC_PMAC
2444 /* HACK ALERT ! Once I find a proper way to say to each driver
2445 * individually what will happen with it's PCI slot, I'll change
2446 * that. On laptops, the AGP slot is just unclocked, so D2 is
2447 * expected, while on desktops, the card is powered off
2450 #endif /* CONFIG_PPC_PMAC */
2452 if (state.event == pdev->dev.power.power_state.event)
2455 printk(KERN_DEBUG "aty128fb: suspending...\n");
2459 fb_set_suspend(info, 1);
2461 /* Make sure engine is reset */
2463 aty128_reset_engine(par);
2466 /* Blank display and LCD */
2467 aty128fb_blank(FB_BLANK_POWERDOWN, info);
2471 par->lock_blank = 1;
2473 #ifdef CONFIG_PPC_PMAC
2474 /* On powermac, we have hooks to properly suspend/resume AGP now,
2475 * use them here. We'll ultimately need some generic support here,
2476 * but the generic code isn't quite ready for that yet
2478 pmac_suspend_agp_for_card(pdev);
2479 #endif /* CONFIG_PPC_PMAC */
2481 /* We need a way to make sure the fbdev layer will _not_ touch the
2482 * framebuffer before we put the chip to suspend state. On 2.4, I
2483 * used dummy fb ops, 2.5 need proper support for this at the
2486 if (state.event != PM_EVENT_ON)
2487 aty128_set_suspend(par, 1);
2491 pdev->dev.power.power_state = state;
2496 static int aty128_do_resume(struct pci_dev *pdev)
2498 struct fb_info *info = pci_get_drvdata(pdev);
2499 struct aty128fb_par *par = info->par;
2501 if (pdev->dev.power.power_state.event == PM_EVENT_ON)
2504 /* PCI state will have been restored by the core, so
2505 * we should be in D0 now with our config space fully
2510 aty128_set_suspend(par, 0);
2513 /* Restore display & engine */
2514 aty128_reset_engine(par);
2516 aty128fb_set_par(info);
2517 fb_pan_display(info, &info->var);
2518 fb_set_cmap(&info->cmap, info);
2521 fb_set_suspend(info, 0);
2524 par->lock_blank = 0;
2525 aty128fb_blank(0, info);
2527 #ifdef CONFIG_PPC_PMAC
2528 /* On powermac, we have hooks to properly suspend/resume AGP now,
2529 * use them here. We'll ultimately need some generic support here,
2530 * but the generic code isn't quite ready for that yet
2532 pmac_resume_agp_for_card(pdev);
2533 #endif /* CONFIG_PPC_PMAC */
2535 pdev->dev.power.power_state = PMSG_ON;
2537 printk(KERN_DEBUG "aty128fb: resumed !\n");
2542 static int aty128_pci_resume(struct pci_dev *pdev)
2547 rc = aty128_do_resume(pdev);
2554 static int aty128fb_init(void)
2557 char *option = NULL;
2559 if (fb_get_options("aty128fb", &option))
2561 aty128fb_setup(option);
2564 return pci_register_driver(&aty128fb_driver);
2567 static void __exit aty128fb_exit(void)
2569 pci_unregister_driver(&aty128fb_driver);
2572 module_init(aty128fb_init);
2574 module_exit(aty128fb_exit);
2576 MODULE_AUTHOR("(c)1999-2003 Brad Douglas <brad@neruo.com>");
2577 MODULE_DESCRIPTION("FBDev driver for ATI Rage128 / Pro cards");
2578 MODULE_LICENSE("GPL");
2579 module_param(mode_option, charp, 0);
2580 MODULE_PARM_DESC(mode_option, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
2582 module_param_named(nomtrr, mtrr, invbool, 0);
2583 MODULE_PARM_DESC(nomtrr, "bool: Disable MTRR support (0 or 1=disabled) (default=0)");