drivers/video/fbdev/i740fb.c

   1 /*
   2  * i740fb - framebuffer driver for Intel740
   3  * Copyright (c) 2011 Ondrej Zary
   4  *
   5  * Based on old i740fb driver (c) 2001-2002 Andrey Ulanov <drey@rt.mipt.ru>
   6  * which was partially based on:
   7  *  VGA 16-color framebuffer driver (c) 1999 Ben Pfaff <pfaffben@debian.org>
   8  *      and Petr Vandrovec <VANDROVE@vc.cvut.cz>
   9  *  i740 driver from XFree86 (c) 1998-1999 Precision Insight, Inc., Cedar Park,
  10  *      Texas.
  11  *  i740fb by Patrick LERDA, v0.9
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/kernel.h>
  16 #include <linux/errno.h>
  17 #include <linux/string.h>
  18 #include <linux/mm.h>
  19 #include <linux/slab.h>
  20 #include <linux/delay.h>
  21 #include <linux/fb.h>
  22 #include <linux/init.h>
  23 #include <linux/pci.h>
  24 #include <linux/pci_ids.h>
  25 #include <linux/i2c.h>
  26 #include <linux/i2c-algo-bit.h>
  27 #include <linux/console.h>
  28 #include <video/vga.h>
  29
  30 #ifdef CONFIG_MTRR
  31 #include <asm/mtrr.h>
  32 #endif
  33
  34 #include "i740_reg.h"
  35
  36 static char *mode_option;
  37
  38 #ifdef CONFIG_MTRR
  39 static int mtrr = 1;
  40 #endif
  41
  42 struct i740fb_par {
  43         unsigned char __iomem *regs;
  44         bool has_sgram;
  45 #ifdef CONFIG_MTRR
  46         int mtrr_reg;
  47 #endif
  48         bool ddc_registered;
  49         struct i2c_adapter ddc_adapter;
  50         struct i2c_algo_bit_data ddc_algo;
  51         u32 pseudo_palette[16];
  52         struct mutex open_lock;
  53         unsigned int ref_count;
  54
  55         u8 crtc[VGA_CRT_C];
  56         u8 atc[VGA_ATT_C];
  57         u8 gdc[VGA_GFX_C];
  58         u8 seq[VGA_SEQ_C];
  59         u8 misc;
  60         u8 vss;
  61
  62         /* i740 specific registers */
  63         u8 display_cntl;
  64         u8 pixelpipe_cfg0;
  65         u8 pixelpipe_cfg1;
  66         u8 pixelpipe_cfg2;
  67         u8 video_clk2_m;
  68         u8 video_clk2_n;
  69         u8 video_clk2_mn_msbs;
  70         u8 video_clk2_div_sel;
  71         u8 pll_cntl;
  72         u8 address_mapping;
  73         u8 io_cntl;
  74         u8 bitblt_cntl;
  75         u8 ext_vert_total;
  76         u8 ext_vert_disp_end;
  77         u8 ext_vert_sync_start;
  78         u8 ext_vert_blank_start;
  79         u8 ext_horiz_total;
  80         u8 ext_horiz_blank;
  81         u8 ext_offset;
  82         u8 interlace_cntl;
  83         u32 lmi_fifo_watermark;
  84         u8 ext_start_addr;
  85         u8 ext_start_addr_hi;
  86 };
  87
  88 #define DACSPEED8       203
  89 #define DACSPEED16      163
  90 #define DACSPEED24_SG   136
  91 #define DACSPEED24_SD   128
  92 #define DACSPEED32      86
  93
  94 static struct fb_fix_screeninfo i740fb_fix = {
  95         .id =           "i740fb",
  96         .type =         FB_TYPE_PACKED_PIXELS,
  97         .visual =       FB_VISUAL_TRUECOLOR,
  98         .xpanstep =     8,
  99         .ypanstep =     1,
 100         .accel =        FB_ACCEL_NONE,
 101 };
 102
 103 static inline void i740outb(struct i740fb_par *par, u16 port, u8 val)
 104 {
 105         vga_mm_w(par->regs, port, val);
 106 }
 107 static inline u8 i740inb(struct i740fb_par *par, u16 port)
 108 {
 109         return vga_mm_r(par->regs, port);
 110 }
 111 static inline void i740outreg(struct i740fb_par *par, u16 port, u8 reg, u8 val)
 112 {
 113         vga_mm_w_fast(par->regs, port, reg, val);
 114 }
 115 static inline u8 i740inreg(struct i740fb_par *par, u16 port, u8 reg)
 116 {
 117         vga_mm_w(par->regs, port, reg);
 118         return vga_mm_r(par->regs, port+1);
 119 }
 120 static inline void i740outreg_mask(struct i740fb_par *par, u16 port, u8 reg,
 121                                    u8 val, u8 mask)
 122 {
 123         vga_mm_w_fast(par->regs, port, reg, (val & mask)
 124                 | (i740inreg(par, port, reg) & ~mask));
 125 }
 126
 127 #define REG_DDC_DRIVE   0x62
 128 #define REG_DDC_STATE   0x63
 129 #define DDC_SCL         (1 << 3)
 130 #define DDC_SDA         (1 << 2)
 131
 132 static void i740fb_ddc_setscl(void *data, int val)
 133 {
 134         struct i740fb_par *par = data;
 135
 136         i740outreg_mask(par, XRX, REG_DDC_DRIVE, DDC_SCL, DDC_SCL);
 137         i740outreg_mask(par, XRX, REG_DDC_STATE, val ? DDC_SCL : 0, DDC_SCL);
 138 }
 139
 140 static void i740fb_ddc_setsda(void *data, int val)
 141 {
 142         struct i740fb_par *par = data;
 143
 144         i740outreg_mask(par, XRX, REG_DDC_DRIVE, DDC_SDA, DDC_SDA);
 145         i740outreg_mask(par, XRX, REG_DDC_STATE, val ? DDC_SDA : 0, DDC_SDA);
 146 }
 147
 148 static int i740fb_ddc_getscl(void *data)
 149 {
 150         struct i740fb_par *par = data;
 151
 152         i740outreg_mask(par, XRX, REG_DDC_DRIVE, 0, DDC_SCL);
 153
 154         return !!(i740inreg(par, XRX, REG_DDC_STATE) & DDC_SCL);
 155 }
 156
 157 static int i740fb_ddc_getsda(void *data)
 158 {
 159         struct i740fb_par *par = data;
 160
 161         i740outreg_mask(par, XRX, REG_DDC_DRIVE, 0, DDC_SDA);
 162
 163         return !!(i740inreg(par, XRX, REG_DDC_STATE) & DDC_SDA);
 164 }
 165
 166 static int i740fb_setup_ddc_bus(struct fb_info *info)
 167 {
 168         struct i740fb_par *par = info->par;
 169
 170         strlcpy(par->ddc_adapter.name, info->fix.id,
 171                 sizeof(par->ddc_adapter.name));
 172         par->ddc_adapter.owner          = THIS_MODULE;
 173         par->ddc_adapter.class          = I2C_CLASS_DDC;
 174         par->ddc_adapter.algo_data      = &par->ddc_algo;
 175         par->ddc_adapter.dev.parent     = info->device;
 176         par->ddc_algo.setsda            = i740fb_ddc_setsda;
 177         par->ddc_algo.setscl            = i740fb_ddc_setscl;
 178         par->ddc_algo.getsda            = i740fb_ddc_getsda;
 179         par->ddc_algo.getscl            = i740fb_ddc_getscl;
 180         par->ddc_algo.udelay            = 10;
 181         par->ddc_algo.timeout           = 20;
 182         par->ddc_algo.data              = par;
 183
 184         i2c_set_adapdata(&par->ddc_adapter, par);
 185
 186         return i2c_bit_add_bus(&par->ddc_adapter);
 187 }
 188
 189 static int i740fb_open(struct fb_info *info, int user)
 190 {
 191         struct i740fb_par *par = info->par;
 192
 193         mutex_lock(&(par->open_lock));
 194         par->ref_count++;
 195         mutex_unlock(&(par->open_lock));
 196
 197         return 0;
 198 }
 199
 200 static int i740fb_release(struct fb_info *info, int user)
 201 {
 202         struct i740fb_par *par = info->par;
 203
 204         mutex_lock(&(par->open_lock));
 205         if (par->ref_count == 0) {
 206                 fb_err(info, "release called with zero refcount\n");
 207                 mutex_unlock(&(par->open_lock));
 208                 return -EINVAL;
 209         }
 210
 211         par->ref_count--;
 212         mutex_unlock(&(par->open_lock));
 213
 214         return 0;
 215 }
 216
 217 static u32 i740_calc_fifo(struct i740fb_par *par, u32 freq, int bpp)
 218 {
 219         /*
 220          * Would like to calculate these values automatically, but a generic
 221          * algorithm does not seem possible.  Note: These FIFO water mark
 222          * values were tested on several cards and seem to eliminate the
 223          * all of the snow and vertical banding, but fine adjustments will
 224          * probably be required for other cards.
 225          */
 226
 227         u32 wm;
 228
 229         switch (bpp) {
 230         case 8:
 231                 if      (freq > 200)
 232                         wm = 0x18120000;
 233                 else if (freq > 175)
 234                         wm = 0x16110000;
 235                 else if (freq > 135)
 236                         wm = 0x120E0000;
 237                 else
 238                         wm = 0x100D0000;
 239                 break;
 240         case 15:
 241         case 16:
 242                 if (par->has_sgram) {
 243                         if      (freq > 140)
 244                                 wm = 0x2C1D0000;
 245                         else if (freq > 120)
 246                                 wm = 0x2C180000;
 247                         else if (freq > 100)
 248                                 wm = 0x24160000;
 249                         else if (freq >  90)
 250                                 wm = 0x18120000;
 251                         else if (freq >  50)
 252                                 wm = 0x16110000;
 253                         else if (freq >  32)
 254                                 wm = 0x13100000;
 255                         else
 256                                 wm = 0x120E0000;
 257                 } else {
 258                         if      (freq > 160)
 259                                 wm = 0x28200000;
 260                         else if (freq > 140)
 261                                 wm = 0x2A1E0000;
 262                         else if (freq > 130)
 263                                 wm = 0x2B1A0000;
 264                         else if (freq > 120)
 265                                 wm = 0x2C180000;
 266                         else if (freq > 100)
 267                                 wm = 0x24180000;
 268                         else if (freq >  90)
 269                                 wm = 0x18120000;
 270                         else if (freq >  50)
 271                                 wm = 0x16110000;
 272                         else if (freq >  32)
 273                                 wm = 0x13100000;
 274                         else
 275                                 wm = 0x120E0000;
 276                 }
 277                 break;
 278         case 24:
 279                 if (par->has_sgram) {
 280                         if      (freq > 130)
 281                                 wm = 0x31200000;
 282                         else if (freq > 120)
 283                                 wm = 0x2E200000;
 284                         else if (freq > 100)
 285                                 wm = 0x2C1D0000;
 286                         else if (freq >  80)
 287                                 wm = 0x25180000;
 288                         else if (freq >  64)
 289                                 wm = 0x24160000;
 290                         else if (freq >  49)
 291                                 wm = 0x18120000;
 292                         else if (freq >  32)
 293                                 wm = 0x16110000;
 294                         else
 295                                 wm = 0x13100000;
 296                 } else {
 297                         if      (freq > 120)
 298                                 wm = 0x311F0000;
 299                         else if (freq > 100)
 300                                 wm = 0x2C1D0000;
 301                         else if (freq >  80)
 302                                 wm = 0x25180000;
 303                         else if (freq >  64)
 304                                 wm = 0x24160000;
 305                         else if (freq >  49)
 306                                 wm = 0x18120000;
 307                         else if (freq >  32)
 308                                 wm = 0x16110000;
 309                         else
 310                                 wm = 0x13100000;
 311                 }
 312                 break;
 313         case 32:
 314                 if (par->has_sgram) {
 315                         if      (freq >  80)
 316                                 wm = 0x2A200000;
 317                         else if (freq >  60)
 318                                 wm = 0x281A0000;
 319                         else if (freq >  49)
 320                                 wm = 0x25180000;
 321                         else if (freq >  32)
 322                                 wm = 0x18120000;
 323                         else
 324                                 wm = 0x16110000;
 325                 } else {
 326                         if      (freq >  80)
 327                                 wm = 0x29200000;
 328                         else if (freq >  60)
 329                                 wm = 0x281A0000;
 330                         else if (freq >  49)
 331                                 wm = 0x25180000;
 332                         else if (freq >  32)
 333                                 wm = 0x18120000;
 334                         else
 335                                 wm = 0x16110000;
 336                 }
 337                 break;
 338         }
 339
 340         return wm;
 341 }
 342
 343 /* clock calculation from i740fb by Patrick LERDA */
 344
 345 #define I740_RFREQ              1000000
 346 #define TARGET_MAX_N            30
 347 #define I740_FFIX               (1 << 8)
 348 #define I740_RFREQ_FIX          (I740_RFREQ / I740_FFIX)
 349 #define I740_REF_FREQ           (6667 * I740_FFIX / 100)        /* 66.67 MHz */
 350 #define I740_MAX_VCO_FREQ       (450 * I740_FFIX)               /* 450 MHz */
 351
 352 static void i740_calc_vclk(u32 freq, struct i740fb_par *par)
 353 {
 354         const u32 err_max    = freq / (200  * I740_RFREQ / I740_FFIX);
 355         const u32 err_target = freq / (1000 * I740_RFREQ / I740_FFIX);
 356         u32 err_best = 512 * I740_FFIX;
 357         u32 f_err, f_vco;
 358         int m_best = 0, n_best = 0, p_best = 0, d_best = 0;
 359         int m, n;
 360
 361         p_best = min(15, ilog2(I740_MAX_VCO_FREQ / (freq / I740_RFREQ_FIX)));
 362         d_best = 0;
 363         f_vco = (freq * (1 << p_best)) / I740_RFREQ_FIX;
 364         freq = freq / I740_RFREQ_FIX;
 365
 366         n = 2;
 367         do {
 368                 n++;
 369                 m = ((f_vco * n) / I740_REF_FREQ + 2) / 4;
 370
 371                 if (m < 3)
 372                         m = 3;
 373
 374                 {
 375                         u32 f_out = (((m * I740_REF_FREQ * (4 << 2 * d_best))
 376                                  / n) + ((1 << p_best) / 2)) / (1 << p_best);
 377
 378                         f_err = (freq - f_out);
 379
 380                         if (abs(f_err) < err_max) {
 381                                 m_best = m;
 382                                 n_best = n;
 383                                 err_best = f_err;
 384                         }
 385                 }
 386         } while ((abs(f_err) >= err_target) &&
 387                  ((n <= TARGET_MAX_N) || (abs(err_best) > err_max)));
 388
 389         if (abs(f_err) < err_target) {
 390                 m_best = m;
 391                 n_best = n;
 392         }
 393
 394         par->video_clk2_m = (m_best - 2) & 0xFF;
 395         par->video_clk2_n = (n_best - 2) & 0xFF;
 396         par->video_clk2_mn_msbs = ((((n_best - 2) >> 4) & VCO_N_MSBS)
 397                                  | (((m_best - 2) >> 8) & VCO_M_MSBS));
 398         par->video_clk2_div_sel =
 399                 ((p_best << 4) | (d_best ? 4 : 0) | REF_DIV_1);
 400 }
 401
 402 static int i740fb_decode_var(const struct fb_var_screeninfo *var,
 403                              struct i740fb_par *par, struct fb_info *info)
 404 {
 405         /*
 406          * Get the video params out of 'var'.
 407          * If a value doesn't fit, round it up, if it's too big, return -EINVAL.
 408          */
 409
 410         u32 xres, right, hslen, left, xtotal;
 411         u32 yres, lower, vslen, upper, ytotal;
 412         u32 vxres, xoffset, vyres, yoffset;
 413         u32 bpp, base, dacspeed24, mem;
 414         u8 r7;
 415         int i;
 416
 417         dev_dbg(info->device, "decode_var: xres: %i, yres: %i, xres_v: %i, xres_v: %i\n",
 418                   var->xres, var->yres, var->xres_virtual, var->xres_virtual);
 419         dev_dbg(info->device, " xoff: %i, yoff: %i, bpp: %i, graysc: %i\n",
 420                   var->xoffset, var->yoffset, var->bits_per_pixel,
 421                   var->grayscale);
 422         dev_dbg(info->device, " activate: %i, nonstd: %i, vmode: %i\n",
 423                   var->activate, var->nonstd, var->vmode);
 424         dev_dbg(info->device, " pixclock: %i, hsynclen:%i, vsynclen:%i\n",
 425                   var->pixclock, var->hsync_len, var->vsync_len);
 426         dev_dbg(info->device, " left: %i, right: %i, up:%i, lower:%i\n",
 427                   var->left_margin, var->right_margin, var->upper_margin,
 428                   var->lower_margin);
 429
 430
 431         bpp = var->bits_per_pixel;
 432         switch (bpp) {
 433         case 1 ... 8:
 434                 bpp = 8;
 435                 if ((1000000 / var->pixclock) > DACSPEED8) {
 436                         dev_err(info->device, "requested pixclock %i MHz out of range (max. %i MHz at 8bpp)\n",
 437                                 1000000 / var->pixclock, DACSPEED8);
 438                         return -EINVAL;
 439                 }
 440                 break;
 441         case 9 ... 15:
 442                 bpp = 15;
 443         case 16:
 444                 if ((1000000 / var->pixclock) > DACSPEED16) {
 445                         dev_err(info->device, "requested pixclock %i MHz out of range (max. %i MHz at 15/16bpp)\n",
 446                                 1000000 / var->pixclock, DACSPEED16);
 447                         return -EINVAL;
 448                 }
 449                 break;
 450         case 17 ... 24:
 451                 bpp = 24;
 452                 dacspeed24 = par->has_sgram ? DACSPEED24_SG : DACSPEED24_SD;
 453                 if ((1000000 / var->pixclock) > dacspeed24) {
 454                         dev_err(info->device, "requested pixclock %i MHz out of range (max. %i MHz at 24bpp)\n",
 455                                 1000000 / var->pixclock, dacspeed24);
 456                         return -EINVAL;
 457                 }
 458                 break;
 459         case 25 ... 32:
 460                 bpp = 32;
 461                 if ((1000000 / var->pixclock) > DACSPEED32) {
 462                         dev_err(info->device, "requested pixclock %i MHz out of range (max. %i MHz at 32bpp)\n",
 463                                 1000000 / var->pixclock, DACSPEED32);
 464                         return -EINVAL;
 465                 }
 466                 break;
 467         default:
 468                 return -EINVAL;
 469         }
 470
 471         xres = ALIGN(var->xres, 8);
 472         vxres = ALIGN(var->xres_virtual, 16);
 473         if (vxres < xres)
 474                 vxres = xres;
 475
 476         xoffset = ALIGN(var->xoffset, 8);
 477         if (xres + xoffset > vxres)
 478                 xoffset = vxres - xres;
 479
 480         left = ALIGN(var->left_margin, 8);
 481         right = ALIGN(var->right_margin, 8);
 482         hslen = ALIGN(var->hsync_len, 8);
 483
 484         yres = var->yres;
 485         vyres = var->yres_virtual;
 486         if (yres > vyres)
 487                 vyres = yres;
 488
 489         yoffset = var->yoffset;
 490         if (yres + yoffset > vyres)
 491                 yoffset = vyres - yres;
 492
 493         lower = var->lower_margin;
 494         vslen = var->vsync_len;
 495         upper = var->upper_margin;
 496
 497         mem = vxres * vyres * ((bpp + 1) / 8);
 498         if (mem > info->screen_size) {
 499                 dev_err(info->device, "not enough video memory (%d KB requested, %ld KB available)\n",
 500                         mem >> 10, info->screen_size >> 10);
 501                 return -ENOMEM;
 502         }
 503
 504         if (yoffset + yres > vyres)
 505                 yoffset = vyres - yres;
 506
 507         xtotal = xres + right + hslen + left;
 508         ytotal = yres + lower + vslen + upper;
 509
 510         par->crtc[VGA_CRTC_H_TOTAL] = (xtotal >> 3) - 5;
 511         par->crtc[VGA_CRTC_H_DISP] = (xres >> 3) - 1;
 512         par->crtc[VGA_CRTC_H_BLANK_START] = ((xres + right) >> 3) - 1;
 513         par->crtc[VGA_CRTC_H_SYNC_START] = (xres + right) >> 3;
 514         par->crtc[VGA_CRTC_H_SYNC_END] = (((xres + right + hslen) >> 3) & 0x1F)
 515                 | ((((xres + right + hslen) >> 3) & 0x20) << 2);
 516         par->crtc[VGA_CRTC_H_BLANK_END] = ((xres + right + hslen) >> 3 & 0x1F)
 517                 | 0x80;
 518
 519         par->crtc[VGA_CRTC_V_TOTAL] = ytotal - 2;
 520
 521         r7 = 0x10;      /* disable linecompare */
 522         if (ytotal & 0x100)
 523                 r7 |= 0x01;
 524         if (ytotal & 0x200)
 525                 r7 |= 0x20;
 526
 527         par->crtc[VGA_CRTC_PRESET_ROW] = 0;
 528         par->crtc[VGA_CRTC_MAX_SCAN] = 0x40;    /* 1 scanline, no linecmp */
 529         if (var->vmode & FB_VMODE_DOUBLE)
 530                 par->crtc[VGA_CRTC_MAX_SCAN] |= 0x80;
 531         par->crtc[VGA_CRTC_CURSOR_START] = 0x00;
 532         par->crtc[VGA_CRTC_CURSOR_END] = 0x00;
 533         par->crtc[VGA_CRTC_CURSOR_HI] = 0x00;
 534         par->crtc[VGA_CRTC_CURSOR_LO] = 0x00;
 535         par->crtc[VGA_CRTC_V_DISP_END] = yres-1;
 536         if ((yres-1) & 0x100)
 537                 r7 |= 0x02;
 538         if ((yres-1) & 0x200)
 539                 r7 |= 0x40;
 540
 541         par->crtc[VGA_CRTC_V_BLANK_START] = yres + lower - 1;
 542         par->crtc[VGA_CRTC_V_SYNC_START] = yres + lower - 1;
 543         if ((yres + lower - 1) & 0x100)
 544                 r7 |= 0x0C;
 545         if ((yres + lower - 1) & 0x200) {
 546                 par->crtc[VGA_CRTC_MAX_SCAN] |= 0x20;
 547                 r7 |= 0x80;
 548         }
 549
 550         /* disabled IRQ */
 551         par->crtc[VGA_CRTC_V_SYNC_END] =
 552                 ((yres + lower - 1 + vslen) & 0x0F) & ~0x10;
 553         /* 0x7F for VGA, but some SVGA chips require all 8 bits to be set */
 554         par->crtc[VGA_CRTC_V_BLANK_END] = (yres + lower - 1 + vslen) & 0xFF;
 555
 556         par->crtc[VGA_CRTC_UNDERLINE] = 0x00;
 557         par->crtc[VGA_CRTC_MODE] = 0xC3 ;
 558         par->crtc[VGA_CRTC_LINE_COMPARE] = 0xFF;
 559         par->crtc[VGA_CRTC_OVERFLOW] = r7;
 560
 561         par->vss = 0x00;        /* 3DA */
 562
 563         for (i = 0x00; i < 0x10; i++)
 564                 par->atc[i] = i;
 565         par->atc[VGA_ATC_MODE] = 0x81;
 566         par->atc[VGA_ATC_OVERSCAN] = 0x00;      /* 0 for EGA, 0xFF for VGA */
 567         par->atc[VGA_ATC_PLANE_ENABLE] = 0x0F;
 568         par->atc[VGA_ATC_COLOR_PAGE] = 0x00;
 569
 570         par->misc = 0xC3;
 571         if (var->sync & FB_SYNC_HOR_HIGH_ACT)
 572                 par->misc &= ~0x40;
 573         if (var->sync & FB_SYNC_VERT_HIGH_ACT)
 574                 par->misc &= ~0x80;
 575
 576         par->seq[VGA_SEQ_CLOCK_MODE] = 0x01;
 577         par->seq[VGA_SEQ_PLANE_WRITE] = 0x0F;
 578         par->seq[VGA_SEQ_CHARACTER_MAP] = 0x00;
 579         par->seq[VGA_SEQ_MEMORY_MODE] = 0x06;
 580
 581         par->gdc[VGA_GFX_SR_VALUE] = 0x00;
 582         par->gdc[VGA_GFX_SR_ENABLE] = 0x00;
 583         par->gdc[VGA_GFX_COMPARE_VALUE] = 0x00;
 584         par->gdc[VGA_GFX_DATA_ROTATE] = 0x00;
 585         par->gdc[VGA_GFX_PLANE_READ] = 0;
 586         par->gdc[VGA_GFX_MODE] = 0x02;
 587         par->gdc[VGA_GFX_MISC] = 0x05;
 588         par->gdc[VGA_GFX_COMPARE_MASK] = 0x0F;
 589         par->gdc[VGA_GFX_BIT_MASK] = 0xFF;
 590
 591         base = (yoffset * vxres + (xoffset & ~7)) >> 2;
 592         switch (bpp) {
 593         case 8:
 594                 par->crtc[VGA_CRTC_OFFSET] = vxres >> 3;
 595                 par->ext_offset = vxres >> 11;
 596                 par->pixelpipe_cfg1 = DISPLAY_8BPP_MODE;
 597                 par->bitblt_cntl = COLEXP_8BPP;
 598                 break;
 599         case 15: /* 0rrrrrgg gggbbbbb */
 600         case 16: /* rrrrrggg gggbbbbb */
 601                 par->pixelpipe_cfg1 = (var->green.length == 6) ?
 602                         DISPLAY_16BPP_MODE : DISPLAY_15BPP_MODE;
 603                 par->crtc[VGA_CRTC_OFFSET] = vxres >> 2;
 604                 par->ext_offset = vxres >> 10;
 605                 par->bitblt_cntl = COLEXP_16BPP;
 606                 base *= 2;
 607                 break;
 608         case 24:
 609                 par->crtc[VGA_CRTC_OFFSET] = (vxres * 3) >> 3;
 610                 par->ext_offset = (vxres * 3) >> 11;
 611                 par->pixelpipe_cfg1 = DISPLAY_24BPP_MODE;
 612                 par->bitblt_cntl = COLEXP_24BPP;
 613                 base &= 0xFFFFFFFE; /* ...ignore the last bit. */
 614                 base *= 3;
 615                 break;
 616         case 32:
 617                 par->crtc[VGA_CRTC_OFFSET] = vxres >> 1;
 618                 par->ext_offset = vxres >> 9;
 619                 par->pixelpipe_cfg1 = DISPLAY_32BPP_MODE;
 620                 par->bitblt_cntl = COLEXP_RESERVED; /* Unimplemented on i740 */
 621                 base *= 4;
 622                 break;
 623         }
 624
 625         par->crtc[VGA_CRTC_START_LO] = base & 0x000000FF;
 626         par->crtc[VGA_CRTC_START_HI] = (base & 0x0000FF00) >>  8;
 627         par->ext_start_addr =
 628                 ((base & 0x003F0000) >> 16) | EXT_START_ADDR_ENABLE;
 629         par->ext_start_addr_hi = (base & 0x3FC00000) >> 22;
 630
 631         par->pixelpipe_cfg0 = DAC_8_BIT;
 632
 633         par->pixelpipe_cfg2 = DISPLAY_GAMMA_ENABLE | OVERLAY_GAMMA_ENABLE;
 634         par->io_cntl = EXTENDED_CRTC_CNTL;
 635         par->address_mapping = LINEAR_MODE_ENABLE | PAGE_MAPPING_ENABLE;
 636         par->display_cntl = HIRES_MODE;
 637
 638         /* Set the MCLK freq */
 639         par->pll_cntl = PLL_MEMCLK_100000KHZ; /* 100 MHz -- use as default */
 640
 641         /* Calculate the extended CRTC regs */
 642         par->ext_vert_total = (ytotal - 2) >> 8;
 643         par->ext_vert_disp_end = (yres - 1) >> 8;
 644         par->ext_vert_sync_start = (yres + lower) >> 8;
 645         par->ext_vert_blank_start = (yres + lower) >> 8;
 646         par->ext_horiz_total = ((xtotal >> 3) - 5) >> 8;
 647         par->ext_horiz_blank = (((xres + right) >> 3) & 0x40) >> 6;
 648
 649         par->interlace_cntl = INTERLACE_DISABLE;
 650
 651         /* Set the overscan color to 0. (NOTE: This only affects >8bpp mode) */
 652         par->atc[VGA_ATC_OVERSCAN] = 0;
 653
 654         /* Calculate VCLK that most closely matches the requested dot clock */
 655         i740_calc_vclk((((u32)1e9) / var->pixclock) * (u32)(1e3), par);
 656
 657         /* Since we program the clocks ourselves, always use VCLK2. */
 658         par->misc |= 0x0C;
 659
 660         /* Calculate the FIFO Watermark and Burst Length. */
 661         par->lmi_fifo_watermark =
 662                 i740_calc_fifo(par, 1000000 / var->pixclock, bpp);
 663
 664         return 0;
 665 }
 666
 667 static int i740fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
 668 {
 669         switch (var->bits_per_pixel) {
 670         case 8:
 671                 var->red.offset = var->green.offset = var->blue.offset = 0;
 672                 var->red.length = var->green.length = var->blue.length = 8;
 673                 break;
 674         case 16:
 675                 switch (var->green.length) {
 676                 default:
 677                 case 5:
 678                         var->red.offset = 10;
 679                         var->green.offset = 5;
 680                         var->blue.offset = 0;
 681                         var->red.length = 5;
 682                         var->green.length = 5;
 683                         var->blue.length = 5;
 684                         break;
 685                 case 6:
 686                         var->red.offset = 11;
 687                         var->green.offset = 5;
 688                         var->blue.offset = 0;
 689                         var->red.length = var->blue.length = 5;
 690                         break;
 691                 }
 692                 break;
 693         case 24:
 694                 var->red.offset = 16;
 695                 var->green.offset = 8;
 696                 var->blue.offset = 0;
 697                 var->red.length = var->green.length = var->blue.length = 8;
 698                 break;
 699         case 32:
 700                 var->transp.offset = 24;
 701                 var->red.offset = 16;
 702                 var->green.offset = 8;
 703                 var->blue.offset = 0;
 704                 var->transp.length = 8;
 705                 var->red.length = var->green.length = var->blue.length = 8;
 706                 break;
 707         default:
 708                 return -EINVAL;
 709         }
 710
 711         if (var->xres > var->xres_virtual)
 712                 var->xres_virtual = var->xres;
 713
 714         if (var->yres > var->yres_virtual)
 715                 var->yres_virtual = var->yres;
 716
 717         if (info->monspecs.hfmax && info->monspecs.vfmax &&
 718             info->monspecs.dclkmax && fb_validate_mode(var, info) < 0)
 719                 return -EINVAL;
 720
 721         return 0;
 722 }
 723
 724 static void vga_protect(struct i740fb_par *par)
 725 {
 726         /* disable the display */
 727         i740outreg_mask(par, VGA_SEQ_I, VGA_SEQ_CLOCK_MODE, 0x20, 0x20);
 728
 729         i740inb(par, 0x3DA);
 730         i740outb(par, VGA_ATT_W, 0x00); /* enable palette access */
 731 }
 732
 733 static void vga_unprotect(struct i740fb_par *par)
 734 {
 735         /* reenable display */
 736         i740outreg_mask(par, VGA_SEQ_I, VGA_SEQ_CLOCK_MODE, 0, 0x20);
 737
 738         i740inb(par, 0x3DA);
 739         i740outb(par, VGA_ATT_W, 0x20); /* disable palette access */
 740 }
 741
 742 static int i740fb_set_par(struct fb_info *info)
 743 {
 744         struct i740fb_par *par = info->par;
 745         u32 itemp;
 746         int i;
 747
 748         i = i740fb_decode_var(&info->var, par, info);
 749         if (i)
 750                 return i;
 751
 752         memset(info->screen_base, 0, info->screen_size);
 753
 754         vga_protect(par);
 755
 756         i740outreg(par, XRX, DRAM_EXT_CNTL, DRAM_REFRESH_DISABLE);
 757
 758         mdelay(1);
 759
 760         i740outreg(par, XRX, VCLK2_VCO_M, par->video_clk2_m);
 761         i740outreg(par, XRX, VCLK2_VCO_N, par->video_clk2_n);
 762         i740outreg(par, XRX, VCLK2_VCO_MN_MSBS, par->video_clk2_mn_msbs);
 763         i740outreg(par, XRX, VCLK2_VCO_DIV_SEL, par->video_clk2_div_sel);
 764
 765         i740outreg_mask(par, XRX, PIXPIPE_CONFIG_0,
 766                         par->pixelpipe_cfg0 & DAC_8_BIT, 0x80);
 767
 768         i740inb(par, 0x3DA);
 769         i740outb(par, 0x3C0, 0x00);
 770
 771         /* update misc output register */
 772         i740outb(par, VGA_MIS_W, par->misc | 0x01);
 773
 774         /* synchronous reset on */
 775         i740outreg(par, VGA_SEQ_I, VGA_SEQ_RESET, 0x01);
 776         /* write sequencer registers */
 777         i740outreg(par, VGA_SEQ_I, VGA_SEQ_CLOCK_MODE,
 778                         par->seq[VGA_SEQ_CLOCK_MODE] | 0x20);
 779         for (i = 2; i < VGA_SEQ_C; i++)
 780                 i740outreg(par, VGA_SEQ_I, i, par->seq[i]);
 781
 782         /* synchronous reset off */
 783         i740outreg(par, VGA_SEQ_I, VGA_SEQ_RESET, 0x03);
 784
 785         /* deprotect CRT registers 0-7 */
 786         i740outreg(par, VGA_CRT_IC, VGA_CRTC_V_SYNC_END,
 787                         par->crtc[VGA_CRTC_V_SYNC_END]);
 788
 789         /* write CRT registers */
 790         for (i = 0; i < VGA_CRT_C; i++)
 791                 i740outreg(par, VGA_CRT_IC, i, par->crtc[i]);
 792
 793         /* write graphics controller registers */
 794         for (i = 0; i < VGA_GFX_C; i++)
 795                 i740outreg(par, VGA_GFX_I, i, par->gdc[i]);
 796
 797         /* write attribute controller registers */
 798         for (i = 0; i < VGA_ATT_C; i++) {
 799                 i740inb(par, VGA_IS1_RC);               /* reset flip-flop */
 800                 i740outb(par, VGA_ATT_IW, i);
 801                 i740outb(par, VGA_ATT_IW, par->atc[i]);
 802         }
 803
 804         i740inb(par, VGA_IS1_RC);
 805         i740outb(par, VGA_ATT_IW, 0x20);
 806
 807         i740outreg(par, VGA_CRT_IC, EXT_VERT_TOTAL, par->ext_vert_total);
 808         i740outreg(par, VGA_CRT_IC, EXT_VERT_DISPLAY, par->ext_vert_disp_end);
 809         i740outreg(par, VGA_CRT_IC, EXT_VERT_SYNC_START,
 810                         par->ext_vert_sync_start);
 811         i740outreg(par, VGA_CRT_IC, EXT_VERT_BLANK_START,
 812                         par->ext_vert_blank_start);
 813         i740outreg(par, VGA_CRT_IC, EXT_HORIZ_TOTAL, par->ext_horiz_total);
 814         i740outreg(par, VGA_CRT_IC, EXT_HORIZ_BLANK, par->ext_horiz_blank);
 815         i740outreg(par, VGA_CRT_IC, EXT_OFFSET, par->ext_offset);
 816         i740outreg(par, VGA_CRT_IC, EXT_START_ADDR_HI, par->ext_start_addr_hi);
 817         i740outreg(par, VGA_CRT_IC, EXT_START_ADDR, par->ext_start_addr);
 818
 819         i740outreg_mask(par, VGA_CRT_IC, INTERLACE_CNTL,
 820                         par->interlace_cntl, INTERLACE_ENABLE);
 821         i740outreg_mask(par, XRX, ADDRESS_MAPPING, par->address_mapping, 0x1F);
 822         i740outreg_mask(par, XRX, BITBLT_CNTL, par->bitblt_cntl, COLEXP_MODE);
 823         i740outreg_mask(par, XRX, DISPLAY_CNTL,
 824                         par->display_cntl, VGA_WRAP_MODE | GUI_MODE);
 825         i740outreg_mask(par, XRX, PIXPIPE_CONFIG_0, par->pixelpipe_cfg0, 0x9B);
 826         i740outreg_mask(par, XRX, PIXPIPE_CONFIG_2, par->pixelpipe_cfg2, 0x0C);
 827
 828         i740outreg(par, XRX, PLL_CNTL, par->pll_cntl);
 829
 830         i740outreg_mask(par, XRX, PIXPIPE_CONFIG_1,
 831                         par->pixelpipe_cfg1, DISPLAY_COLOR_MODE);
 832
 833         itemp = readl(par->regs + FWATER_BLC);
 834         itemp &= ~(LMI_BURST_LENGTH | LMI_FIFO_WATERMARK);
 835         itemp |= par->lmi_fifo_watermark;
 836         writel(itemp, par->regs + FWATER_BLC);
 837
 838         i740outreg(par, XRX, DRAM_EXT_CNTL, DRAM_REFRESH_60HZ);
 839
 840         i740outreg_mask(par, MRX, COL_KEY_CNTL_1, 0, BLANK_DISP_OVERLAY);
 841         i740outreg_mask(par, XRX, IO_CTNL,
 842                         par->io_cntl, EXTENDED_ATTR_CNTL | EXTENDED_CRTC_CNTL);
 843
 844         if (par->pixelpipe_cfg1 != DISPLAY_8BPP_MODE) {
 845                 i740outb(par, VGA_PEL_MSK, 0xFF);
 846                 i740outb(par, VGA_PEL_IW, 0x00);
 847                 for (i = 0; i < 256; i++) {
 848                         itemp = (par->pixelpipe_cfg0 & DAC_8_BIT) ? i : i >> 2;
 849                         i740outb(par, VGA_PEL_D, itemp);
 850                         i740outb(par, VGA_PEL_D, itemp);
 851                         i740outb(par, VGA_PEL_D, itemp);
 852                 }
 853         }
 854
 855         /* Wait for screen to stabilize. */
 856         mdelay(50);
 857         vga_unprotect(par);
 858
 859         info->fix.line_length =
 860                         info->var.xres_virtual * info->var.bits_per_pixel / 8;
 861         if (info->var.bits_per_pixel == 8)
 862                 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
 863         else
 864                 info->fix.visual = FB_VISUAL_TRUECOLOR;
 865
 866         return 0;
 867 }
 868
 869 static int i740fb_setcolreg(unsigned regno, unsigned red, unsigned green,
 870                            unsigned blue, unsigned transp,
 871                            struct fb_info *info)
 872 {
 873         u32 r, g, b;
 874
 875         dev_dbg(info->device, "setcolreg: regno: %i, red=%d, green=%d, blue=%d, transp=%d, bpp=%d\n",
 876                 regno, red, green, blue, transp, info->var.bits_per_pixel);
 877
 878         switch (info->fix.visual) {
 879         case FB_VISUAL_PSEUDOCOLOR:
 880                 if (regno >= 256)
 881                         return -EINVAL;
 882                 i740outb(info->par, VGA_PEL_IW, regno);
 883                 i740outb(info->par, VGA_PEL_D, red >> 8);
 884                 i740outb(info->par, VGA_PEL_D, green >> 8);
 885                 i740outb(info->par, VGA_PEL_D, blue >> 8);
 886                 break;
 887         case FB_VISUAL_TRUECOLOR:
 888                 if (regno >= 16)
 889                         return -EINVAL;
 890                 r = (red >> (16 - info->var.red.length))
 891                         << info->var.red.offset;
 892                 b = (blue >> (16 - info->var.blue.length))
 893                         << info->var.blue.offset;
 894                 g = (green >> (16 - info->var.green.length))
 895                         << info->var.green.offset;
 896                 ((u32 *) info->pseudo_palette)[regno] = r | g | b;
 897                 break;
 898         default:
 899                 return -EINVAL;
 900         }
 901
 902         return 0;
 903 }
 904
 905 static int i740fb_pan_display(struct fb_var_screeninfo *var,
 906                                  struct fb_info *info)
 907 {
 908         struct i740fb_par *par = info->par;
 909         u32 base = (var->yoffset * info->var.xres_virtual
 910                  + (var->xoffset & ~7)) >> 2;
 911
 912         dev_dbg(info->device, "pan_display: xoffset: %i yoffset: %i base: %i\n",
 913                 var->xoffset, var->yoffset, base);
 914
 915         switch (info->var.bits_per_pixel) {
 916         case 8:
 917                 break;
 918         case 15:
 919         case 16:
 920                 base *= 2;
 921                 break;
 922         case 24:
 923                 /*
 924                  * The last bit does not seem to have any effect on the start
 925                  * address register in 24bpp mode, so...
 926                  */
 927                 base &= 0xFFFFFFFE; /* ...ignore the last bit. */
 928                 base *= 3;
 929                 break;
 930         case 32:
 931                 base *= 4;
 932                 break;
 933         }
 934
 935         par->crtc[VGA_CRTC_START_LO] = base & 0x000000FF;
 936         par->crtc[VGA_CRTC_START_HI] = (base & 0x0000FF00) >>  8;
 937         par->ext_start_addr_hi = (base & 0x3FC00000) >> 22;
 938         par->ext_start_addr =
 939                         ((base & 0x003F0000) >> 16) | EXT_START_ADDR_ENABLE;
 940
 941         i740outreg(par, VGA_CRT_IC, VGA_CRTC_START_LO,  base & 0x000000FF);
 942         i740outreg(par, VGA_CRT_IC, VGA_CRTC_START_HI,
 943                         (base & 0x0000FF00) >> 8);
 944         i740outreg(par, VGA_CRT_IC, EXT_START_ADDR_HI,
 945                         (base & 0x3FC00000) >> 22);
 946         i740outreg(par, VGA_CRT_IC, EXT_START_ADDR,
 947                         ((base & 0x003F0000) >> 16) | EXT_START_ADDR_ENABLE);
 948
 949         return 0;
 950 }
 951
 952 static int i740fb_blank(int blank_mode, struct fb_info *info)
 953 {
 954         struct i740fb_par *par = info->par;
 955
 956         unsigned char SEQ01;
 957         int DPMSSyncSelect;
 958
 959         switch (blank_mode) {
 960         case FB_BLANK_UNBLANK:
 961         case FB_BLANK_NORMAL:
 962                 SEQ01 = 0x00;
 963                 DPMSSyncSelect = HSYNC_ON | VSYNC_ON;
 964                 break;
 965         case FB_BLANK_VSYNC_SUSPEND:
 966                 SEQ01 = 0x20;
 967                 DPMSSyncSelect = HSYNC_ON | VSYNC_OFF;
 968                 break;
 969         case FB_BLANK_HSYNC_SUSPEND:
 970                 SEQ01 = 0x20;
 971                 DPMSSyncSelect = HSYNC_OFF | VSYNC_ON;
 972                 break;
 973         case FB_BLANK_POWERDOWN:
 974                 SEQ01 = 0x20;
 975                 DPMSSyncSelect = HSYNC_OFF | VSYNC_OFF;
 976                 break;
 977         default:
 978                 return -EINVAL;
 979         }
 980         /* Turn the screen on/off */
 981         i740outb(par, SRX, 0x01);
 982         SEQ01 |= i740inb(par, SRX + 1) & ~0x20;
 983         i740outb(par, SRX, 0x01);
 984         i740outb(par, SRX + 1, SEQ01);
 985
 986         /* Set the DPMS mode */
 987         i740outreg(par, XRX, DPMS_SYNC_SELECT, DPMSSyncSelect);
 988
 989         /* Let fbcon do a soft blank for us */
 990         return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
 991 }
 992
 993 static struct fb_ops i740fb_ops = {
 994         .owner          = THIS_MODULE,
 995         .fb_open        = i740fb_open,
 996         .fb_release     = i740fb_release,
 997         .fb_check_var   = i740fb_check_var,
 998         .fb_set_par     = i740fb_set_par,
 999         .fb_setcolreg   = i740fb_setcolreg,
1000         .fb_blank       = i740fb_blank,
1001         .fb_pan_display = i740fb_pan_display,
1002         .fb_fillrect    = cfb_fillrect,
1003         .fb_copyarea    = cfb_copyarea,
1004         .fb_imageblit   = cfb_imageblit,
1005 };
1006
1007 /* ------------------------------------------------------------------------- */
1008
1009 static int i740fb_probe(struct pci_dev *dev, const struct pci_device_id *ent)
1010 {
1011         struct fb_info *info;
1012         struct i740fb_par *par;
1013         int ret, tmp;
1014         bool found = false;
1015         u8 *edid;
1016
1017         info = framebuffer_alloc(sizeof(struct i740fb_par), &(dev->dev));
1018         if (!info) {
1019                 dev_err(&(dev->dev), "cannot allocate framebuffer\n");
1020                 return -ENOMEM;
1021         }
1022
1023         par = info->par;
1024         mutex_init(&par->open_lock);
1025
1026         info->var.activate = FB_ACTIVATE_NOW;
1027         info->var.bits_per_pixel = 8;
1028         info->fbops = &i740fb_ops;
1029         info->pseudo_palette = par->pseudo_palette;
1030
1031         ret = pci_enable_device(dev);
1032         if (ret) {
1033                 dev_err(info->device, "cannot enable PCI device\n");
1034                 goto err_enable_device;
1035         }
1036
1037         ret = pci_request_regions(dev, info->fix.id);
1038         if (ret) {
1039                 dev_err(info->device, "error requesting regions\n");
1040                 goto err_request_regions;
1041         }
1042
1043         info->screen_base = pci_ioremap_bar(dev, 0);
1044         if (!info->screen_base) {
1045                 dev_err(info->device, "error remapping base\n");
1046                 ret = -ENOMEM;
1047                 goto err_ioremap_1;
1048         }
1049
1050         par->regs = pci_ioremap_bar(dev, 1);
1051         if (!par->regs) {
1052                 dev_err(info->device, "error remapping MMIO\n");
1053                 ret = -ENOMEM;
1054                 goto err_ioremap_2;
1055         }
1056
1057         /* detect memory size */
1058         if ((i740inreg(par, XRX, DRAM_ROW_TYPE) & DRAM_ROW_1)
1059                                                         == DRAM_ROW_1_SDRAM)
1060                 i740outb(par, XRX, DRAM_ROW_BNDRY_1);
1061         else
1062                 i740outb(par, XRX, DRAM_ROW_BNDRY_0);
1063         info->screen_size = i740inb(par, XRX + 1) * 1024 * 1024;
1064         /* detect memory type */
1065         tmp = i740inreg(par, XRX, DRAM_ROW_CNTL_LO);
1066         par->has_sgram = !((tmp & DRAM_RAS_TIMING) ||
1067                            (tmp & DRAM_RAS_PRECHARGE));
1068
1069         fb_info(info, "Intel740 on %s, %ld KB %s\n",
1070                 pci_name(dev), info->screen_size >> 10,
1071                 par->has_sgram ? "SGRAM" : "SDRAM");
1072
1073         info->fix = i740fb_fix;
1074         info->fix.mmio_start = pci_resource_start(dev, 1);
1075         info->fix.mmio_len = pci_resource_len(dev, 1);
1076         info->fix.smem_start = pci_resource_start(dev, 0);
1077         info->fix.smem_len = info->screen_size;
1078         info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
1079
1080         if (i740fb_setup_ddc_bus(info) == 0) {
1081                 par->ddc_registered = true;
1082                 edid = fb_ddc_read(&par->ddc_adapter);
1083                 if (edid) {
1084                         fb_edid_to_monspecs(edid, &info->monspecs);
1085                         kfree(edid);
1086                         if (!info->monspecs.modedb)
1087                                 dev_err(info->device,
1088                                         "error getting mode database\n");
1089                         else {
1090                                 const struct fb_videomode *m;
1091
1092                                 fb_videomode_to_modelist(
1093                                         info->monspecs.modedb,
1094                                         info->monspecs.modedb_len,
1095                                         &info->modelist);
1096                                 m = fb_find_best_display(&info->monspecs,
1097                                                          &info->modelist);
1098                                 if (m) {
1099                                         fb_videomode_to_var(&info->var, m);
1100                                         /* fill all other info->var's fields */
1101                                         if (!i740fb_check_var(&info->var, info))
1102                                                 found = true;
1103                                 }
1104                         }
1105                 }
1106         }
1107
1108         if (!mode_option && !found)
1109                 mode_option = "640x480-8@60";
1110
1111         if (mode_option) {
1112                 ret = fb_find_mode(&info->var, info, mode_option,
1113                                    info->monspecs.modedb,
1114                                    info->monspecs.modedb_len,
1115                                    NULL, info->var.bits_per_pixel);
1116                 if (!ret || ret == 4) {
1117                         dev_err(info->device, "mode %s not found\n",
1118                                 mode_option);
1119                         ret = -EINVAL;
1120                 }
1121         }
1122
1123         fb_destroy_modedb(info->monspecs.modedb);
1124         info->monspecs.modedb = NULL;
1125
1126         /* maximize virtual vertical size for fast scrolling */
1127         info->var.yres_virtual = info->fix.smem_len * 8 /
1128                         (info->var.bits_per_pixel * info->var.xres_virtual);
1129
1130         if (ret == -EINVAL)
1131                 goto err_find_mode;
1132
1133         ret = fb_alloc_cmap(&info->cmap, 256, 0);
1134         if (ret) {
1135                 dev_err(info->device, "cannot allocate colormap\n");
1136                 goto err_alloc_cmap;
1137         }
1138
1139         ret = register_framebuffer(info);
1140         if (ret) {
1141                 dev_err(info->device, "error registering framebuffer\n");
1142                 goto err_reg_framebuffer;
1143         }
1144
1145         fb_info(info, "%s frame buffer device\n", info->fix.id);
1146         pci_set_drvdata(dev, info);
1147 #ifdef CONFIG_MTRR
1148         if (mtrr) {
1149                 par->mtrr_reg = -1;
1150                 par->mtrr_reg = mtrr_add(info->fix.smem_start,
1151                                 info->fix.smem_len, MTRR_TYPE_WRCOMB, 1);
1152         }
1153 #endif
1154         return 0;
1155
1156 err_reg_framebuffer:
1157         fb_dealloc_cmap(&info->cmap);
1158 err_alloc_cmap:
1159 err_find_mode:
1160         if (par->ddc_registered)
1161                 i2c_del_adapter(&par->ddc_adapter);
1162         pci_iounmap(dev, par->regs);
1163 err_ioremap_2:
1164         pci_iounmap(dev, info->screen_base);
1165 err_ioremap_1:
1166         pci_release_regions(dev);
1167 err_request_regions:
1168 /*      pci_disable_device(dev); */
1169 err_enable_device:
1170         framebuffer_release(info);
1171         return ret;
1172 }
1173
1174 static void i740fb_remove(struct pci_dev *dev)
1175 {
1176         struct fb_info *info = pci_get_drvdata(dev);
1177
1178         if (info) {
1179                 struct i740fb_par *par = info->par;
1180
1181 #ifdef CONFIG_MTRR
1182                 if (par->mtrr_reg >= 0) {
1183                         mtrr_del(par->mtrr_reg, 0, 0);
1184                         par->mtrr_reg = -1;
1185                 }
1186 #endif
1187                 unregister_framebuffer(info);
1188                 fb_dealloc_cmap(&info->cmap);
1189                 if (par->ddc_registered)
1190                         i2c_del_adapter(&par->ddc_adapter);
1191                 pci_iounmap(dev, par->regs);
1192                 pci_iounmap(dev, info->screen_base);
1193                 pci_release_regions(dev);
1194 /*              pci_disable_device(dev); */
1195                 framebuffer_release(info);
1196         }
1197 }
1198
1199 #ifdef CONFIG_PM
1200 static int i740fb_suspend(struct pci_dev *dev, pm_message_t state)
1201 {
1202         struct fb_info *info = pci_get_drvdata(dev);
1203         struct i740fb_par *par = info->par;
1204
1205         /* don't disable console during hibernation and wakeup from it */
1206         if (state.event == PM_EVENT_FREEZE || state.event == PM_EVENT_PRETHAW)
1207                 return 0;
1208
1209         console_lock();
1210         mutex_lock(&(par->open_lock));
1211
1212         /* do nothing if framebuffer is not active */
1213         if (par->ref_count == 0) {
1214                 mutex_unlock(&(par->open_lock));
1215                 console_unlock();
1216                 return 0;
1217         }
1218
1219         fb_set_suspend(info, 1);
1220
1221         pci_save_state(dev);
1222         pci_disable_device(dev);
1223         pci_set_power_state(dev, pci_choose_state(dev, state));
1224
1225         mutex_unlock(&(par->open_lock));
1226         console_unlock();
1227
1228         return 0;
1229 }
1230
1231 static int i740fb_resume(struct pci_dev *dev)
1232 {
1233         struct fb_info *info = pci_get_drvdata(dev);
1234         struct i740fb_par *par = info->par;
1235
1236         console_lock();
1237         mutex_lock(&(par->open_lock));
1238
1239         if (par->ref_count == 0)
1240                 goto fail;
1241
1242         pci_set_power_state(dev, PCI_D0);
1243         pci_restore_state(dev);
1244         if (pci_enable_device(dev))
1245                 goto fail;
1246
1247         i740fb_set_par(info);
1248         fb_set_suspend(info, 0);
1249
1250 fail:
1251         mutex_unlock(&(par->open_lock));
1252         console_unlock();
1253         return 0;
1254 }
1255 #else
1256 #define i740fb_suspend NULL
1257 #define i740fb_resume NULL
1258 #endif /* CONFIG_PM */
1259
1260 #define I740_ID_PCI 0x00d1
1261 #define I740_ID_AGP 0x7800
1262
1263 static const struct pci_device_id i740fb_id_table[] = {
1264         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, I740_ID_PCI) },
1265         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, I740_ID_AGP) },
1266         { 0 }
1267 };
1268 MODULE_DEVICE_TABLE(pci, i740fb_id_table);
1269
1270 static struct pci_driver i740fb_driver = {
1271         .name           = "i740fb",
1272         .id_table       = i740fb_id_table,
1273         .probe          = i740fb_probe,
1274         .remove         = i740fb_remove,
1275         .suspend        = i740fb_suspend,
1276         .resume         = i740fb_resume,
1277 };
1278
1279 #ifndef MODULE
1280 static int  __init i740fb_setup(char *options)
1281 {
1282         char *opt;
1283
1284         if (!options || !*options)
1285                 return 0;
1286
1287         while ((opt = strsep(&options, ",")) != NULL) {
1288                 if (!*opt)
1289                         continue;
1290 #ifdef CONFIG_MTRR
1291                 else if (!strncmp(opt, "mtrr:", 5))
1292                         mtrr = simple_strtoul(opt + 5, NULL, 0);
1293 #endif
1294                 else
1295                         mode_option = opt;
1296         }
1297
1298         return 0;
1299 }
1300 #endif
1301
1302 static int __init i740fb_init(void)
1303 {
1304 #ifndef MODULE
1305         char *option = NULL;
1306
1307         if (fb_get_options("i740fb", &option))
1308                 return -ENODEV;
1309         i740fb_setup(option);
1310 #endif
1311
1312         return pci_register_driver(&i740fb_driver);
1313 }
1314
1315 static void __exit i740fb_exit(void)
1316 {
1317         pci_unregister_driver(&i740fb_driver);
1318 }
1319
1320 module_init(i740fb_init);
1321 module_exit(i740fb_exit);
1322
1323 MODULE_AUTHOR("(c) 2011 Ondrej Zary <linux@rainbow-software.org>");
1324 MODULE_LICENSE("GPL");
1325 MODULE_DESCRIPTION("fbdev driver for Intel740");
1326
1327 module_param(mode_option, charp, 0444);
1328 MODULE_PARM_DESC(mode_option, "Default video mode ('640x480-8@60', etc)");
1329
1330 #ifdef CONFIG_MTRR
1331 module_param(mtrr, int, 0444);
1332 MODULE_PARM_DESC(mtrr, "Enable write-combining with MTRR (1=enable, 0=disable, default=1)");
1333 #endif