2 * drivers/mb862xx/mb862xxfb.c
4 * Fujitsu Carmine/Coral-P(A)/Lime framebuffer driver
6 * (C) 2008 Anatolij Gustschin <agust@denx.de>
7 * DENX Software Engineering
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
18 #include <linux/delay.h>
19 #include <linux/uaccess.h>
20 #include <linux/module.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/pci.h>
24 #if defined(CONFIG_OF)
25 #include <linux/of_platform.h>
27 #include "mb862xxfb.h"
28 #include "mb862xx_reg.h"
30 #define NR_PALETTE 256
31 #define MB862XX_MEM_SIZE 0x1000000
32 #define CORALP_MEM_SIZE 0x2000000
33 #define CARMINE_MEM_SIZE 0x8000000
34 #define DRV_NAME "mb862xxfb"
36 #if defined(CONFIG_SOCRATES)
37 static struct mb862xx_gc_mode socrates_gc_mode = {
38 /* Mode for Prime View PM070WL4 TFT LCD Panel */
39 { "800x480", 45, 800, 480, 40000, 86, 42, 33, 10, 128, 2, 0, 0, 0 },
40 /* 16 bits/pixel, 16MB, 133MHz, SDRAM memory mode value */
41 16, 0x1000000, GC_CCF_COT_133, 0x4157ba63
46 static inline int h_total(struct fb_var_screeninfo *var)
48 return var->xres + var->left_margin +
49 var->right_margin + var->hsync_len;
52 static inline int v_total(struct fb_var_screeninfo *var)
54 return var->yres + var->upper_margin +
55 var->lower_margin + var->vsync_len;
58 static inline int hsp(struct fb_var_screeninfo *var)
60 return var->xres + var->right_margin - 1;
63 static inline int vsp(struct fb_var_screeninfo *var)
65 return var->yres + var->lower_margin - 1;
68 static inline int d_pitch(struct fb_var_screeninfo *var)
70 return var->xres * var->bits_per_pixel / 8;
73 static inline unsigned int chan_to_field(unsigned int chan,
74 struct fb_bitfield *bf)
77 chan >>= 16 - bf->length;
78 return chan << bf->offset;
81 static int mb862xxfb_setcolreg(unsigned regno,
82 unsigned red, unsigned green, unsigned blue,
83 unsigned transp, struct fb_info *info)
85 struct mb862xxfb_par *par = info->par;
88 switch (info->fix.visual) {
89 case FB_VISUAL_TRUECOLOR:
91 val = chan_to_field(red, &info->var.red);
92 val |= chan_to_field(green, &info->var.green);
93 val |= chan_to_field(blue, &info->var.blue);
94 par->pseudo_palette[regno] = val;
97 case FB_VISUAL_PSEUDOCOLOR:
99 val = (red >> 8) << 16;
100 val |= (green >> 8) << 8;
102 outreg(disp, GC_L0PAL0 + (regno * 4), val);
106 return 1; /* unsupported type */
111 static int mb862xxfb_check_var(struct fb_var_screeninfo *var,
117 dev_dbg(fbi->dev, "%s\n", __func__);
119 /* check if these values fit into the registers */
120 if (var->hsync_len > 255 || var->vsync_len > 255)
123 if ((var->xres + var->right_margin) >= 4096)
126 if ((var->yres + var->lower_margin) > 4096)
129 if (h_total(var) > 4096 || v_total(var) > 4096)
132 if (var->xres_virtual > 4096 || var->yres_virtual > 4096)
135 if (var->bits_per_pixel <= 8)
136 var->bits_per_pixel = 8;
137 else if (var->bits_per_pixel <= 16)
138 var->bits_per_pixel = 16;
139 else if (var->bits_per_pixel <= 32)
140 var->bits_per_pixel = 32;
143 * can cope with 8,16 or 24/32bpp if resulting
144 * pitch is divisible by 64 without remainder
146 if (d_pitch(&fbi->var) % GC_L0M_L0W_UNIT) {
149 var->bits_per_pixel = 0;
151 var->bits_per_pixel += 8;
152 r = d_pitch(&fbi->var) % GC_L0M_L0W_UNIT;
153 } while (r && var->bits_per_pixel <= 32);
155 if (d_pitch(&fbi->var) % GC_L0M_L0W_UNIT)
159 /* line length is going to be 128 bit aligned */
160 tmp = (var->xres * var->bits_per_pixel) / 8;
164 /* set r/g/b positions and validate bpp */
165 switch (var->bits_per_pixel) {
167 var->red.length = var->bits_per_pixel;
168 var->green.length = var->bits_per_pixel;
169 var->blue.length = var->bits_per_pixel;
171 var->green.offset = 0;
172 var->blue.offset = 0;
173 var->transp.length = 0;
177 var->green.length = 5;
178 var->blue.length = 5;
179 var->red.offset = 10;
180 var->green.offset = 5;
181 var->blue.offset = 0;
182 var->transp.length = 0;
186 var->transp.length = 8;
188 var->green.length = 8;
189 var->blue.length = 8;
190 var->transp.offset = 24;
191 var->red.offset = 16;
192 var->green.offset = 8;
193 var->blue.offset = 0;
202 * set display parameters
204 static int mb862xxfb_set_par(struct fb_info *fbi)
206 struct mb862xxfb_par *par = fbi->par;
207 unsigned long reg, sc;
209 dev_dbg(par->dev, "%s\n", __func__);
210 if (par->type == BT_CORALP)
211 mb862xxfb_init_accel(fbi, fbi->var.xres);
217 reg = inreg(disp, GC_DCM1);
218 reg &= ~GC_DCM01_DEN;
219 outreg(disp, GC_DCM1, reg);
221 /* set display reference clock div. */
222 sc = par->refclk / (1000000 / fbi->var.pixclock) - 1;
223 reg = inreg(disp, GC_DCM1);
224 reg &= ~(GC_DCM01_CKS | GC_DCM01_RESV | GC_DCM01_SC);
226 outreg(disp, GC_DCM1, reg);
227 dev_dbg(par->dev, "SC 0x%lx\n", sc);
229 /* disp dimension, format */
230 reg = pack(d_pitch(&fbi->var) / GC_L0M_L0W_UNIT,
231 (fbi->var.yres - 1));
232 if (fbi->var.bits_per_pixel == 16)
233 reg |= GC_L0M_L0C_16;
234 outreg(disp, GC_L0M, reg);
236 if (fbi->var.bits_per_pixel == 32) {
237 reg = inreg(disp, GC_L0EM);
238 outreg(disp, GC_L0EM, reg | GC_L0EM_L0EC_24);
240 outreg(disp, GC_WY_WX, 0);
241 reg = pack(fbi->var.yres - 1, fbi->var.xres);
242 outreg(disp, GC_WH_WW, reg);
243 outreg(disp, GC_L0OA0, 0);
244 outreg(disp, GC_L0DA0, 0);
245 outreg(disp, GC_L0DY_L0DX, 0);
246 outreg(disp, GC_L0WY_L0WX, 0);
247 outreg(disp, GC_L0WH_L0WW, reg);
249 /* both HW-cursors off */
250 reg = inreg(disp, GC_CPM_CUTC);
251 reg &= ~(GC_CPM_CEN0 | GC_CPM_CEN1);
252 outreg(disp, GC_CPM_CUTC, reg);
255 reg = pack(fbi->var.xres - 1, fbi->var.xres - 1);
256 outreg(disp, GC_HDB_HDP, reg);
257 reg = pack((fbi->var.yres - 1), vsp(&fbi->var));
258 outreg(disp, GC_VDP_VSP, reg);
259 reg = ((fbi->var.vsync_len - 1) << 24) |
260 pack((fbi->var.hsync_len - 1), hsp(&fbi->var));
261 outreg(disp, GC_VSW_HSW_HSP, reg);
262 outreg(disp, GC_HTP, pack(h_total(&fbi->var) - 1, 0));
263 outreg(disp, GC_VTR, pack(v_total(&fbi->var) - 1, 0));
266 reg = inreg(disp, GC_DCM1);
267 reg |= GC_DCM01_DEN | GC_DCM01_L0E;
268 reg &= ~GC_DCM01_ESY;
269 outreg(disp, GC_DCM1, reg);
273 static int mb862xxfb_pan(struct fb_var_screeninfo *var,
274 struct fb_info *info)
276 struct mb862xxfb_par *par = info->par;
279 reg = pack(var->yoffset, var->xoffset);
280 outreg(disp, GC_L0WY_L0WX, reg);
282 reg = pack(info->var.yres_virtual, info->var.xres_virtual);
283 outreg(disp, GC_L0WH_L0WW, reg);
287 static int mb862xxfb_blank(int mode, struct fb_info *fbi)
289 struct mb862xxfb_par *par = fbi->par;
292 dev_dbg(fbi->dev, "blank mode=%d\n", mode);
295 case FB_BLANK_POWERDOWN:
296 reg = inreg(disp, GC_DCM1);
297 reg &= ~GC_DCM01_DEN;
298 outreg(disp, GC_DCM1, reg);
300 case FB_BLANK_UNBLANK:
301 reg = inreg(disp, GC_DCM1);
303 outreg(disp, GC_DCM1, reg);
305 case FB_BLANK_NORMAL:
306 case FB_BLANK_VSYNC_SUSPEND:
307 case FB_BLANK_HSYNC_SUSPEND:
314 static int mb862xxfb_ioctl(struct fb_info *fbi, unsigned int cmd,
317 struct mb862xxfb_par *par = fbi->par;
318 struct mb862xx_l1_cfg *l1_cfg = &par->l1_cfg;
319 void __user *argp = (void __user *)arg;
324 case MB862XX_L1_GET_CFG:
325 if (copy_to_user(argp, l1_cfg, sizeof(*l1_cfg)))
328 case MB862XX_L1_SET_CFG:
329 if (copy_from_user(l1_cfg, argp, sizeof(*l1_cfg)))
331 if (l1_cfg->dh == 0 || l1_cfg->dw == 0)
333 if ((l1_cfg->sw >= l1_cfg->dw) && (l1_cfg->sh >= l1_cfg->dh)) {
335 outreg(cap, GC_CAP_CSC,
336 pack((l1_cfg->sh << 11) / l1_cfg->dh,
337 (l1_cfg->sw << 11) / l1_cfg->dw));
338 l1em = inreg(disp, GC_L1EM);
340 } else if ((l1_cfg->sw <= l1_cfg->dw) &&
341 (l1_cfg->sh <= l1_cfg->dh)) {
343 outreg(cap, GC_CAP_CSC,
344 pack((l1_cfg->sh << 11) / l1_cfg->dh,
345 (l1_cfg->sw << 11) / l1_cfg->dw));
346 outreg(cap, GC_CAP_CMSS,
347 pack(l1_cfg->sw >> 1, l1_cfg->sh));
348 outreg(cap, GC_CAP_CMDS,
349 pack(l1_cfg->dw >> 1, l1_cfg->dh));
350 l1em = inreg(disp, GC_L1EM);
354 if (l1_cfg->mirror) {
355 outreg(cap, GC_CAP_CBM,
356 inreg(cap, GC_CAP_CBM) | GC_CBM_HRV);
357 l1em |= l1_cfg->dw * 2 - 8;
359 outreg(cap, GC_CAP_CBM,
360 inreg(cap, GC_CAP_CBM) & ~GC_CBM_HRV);
363 outreg(disp, GC_L1EM, l1em);
365 case MB862XX_L1_ENABLE:
368 outreg(disp, GC_L1DA, par->cap_buf);
369 outreg(cap, GC_CAP_IMG_START,
370 pack(l1_cfg->sy >> 1, l1_cfg->sx));
371 outreg(cap, GC_CAP_IMG_END,
372 pack(l1_cfg->sh, l1_cfg->sw));
373 outreg(disp, GC_L1M, GC_L1M_16 | GC_L1M_YC | GC_L1M_CS |
374 (par->l1_stride << 16));
375 outreg(disp, GC_L1WY_L1WX,
376 pack(l1_cfg->dy, l1_cfg->dx));
377 outreg(disp, GC_L1WH_L1WW,
378 pack(l1_cfg->dh - 1, l1_cfg->dw));
379 outreg(disp, GC_DLS, 1);
380 outreg(cap, GC_CAP_VCM,
381 GC_VCM_VIE | GC_VCM_CM | GC_VCM_VS_PAL);
382 outreg(disp, GC_DCM1, inreg(disp, GC_DCM1) |
383 GC_DCM1_DEN | GC_DCM1_L1E);
385 outreg(cap, GC_CAP_VCM,
386 inreg(cap, GC_CAP_VCM) & ~GC_VCM_VIE);
387 outreg(disp, GC_DCM1,
388 inreg(disp, GC_DCM1) & ~GC_DCM1_L1E);
391 case MB862XX_L1_CAP_CTL:
394 outreg(cap, GC_CAP_VCM,
395 inreg(cap, GC_CAP_VCM) | GC_VCM_VIE);
397 outreg(cap, GC_CAP_VCM,
398 inreg(cap, GC_CAP_VCM) & ~GC_VCM_VIE);
407 /* framebuffer ops */
408 static struct fb_ops mb862xxfb_ops = {
409 .owner = THIS_MODULE,
410 .fb_check_var = mb862xxfb_check_var,
411 .fb_set_par = mb862xxfb_set_par,
412 .fb_setcolreg = mb862xxfb_setcolreg,
413 .fb_blank = mb862xxfb_blank,
414 .fb_pan_display = mb862xxfb_pan,
415 .fb_fillrect = cfb_fillrect,
416 .fb_copyarea = cfb_copyarea,
417 .fb_imageblit = cfb_imageblit,
418 .fb_ioctl = mb862xxfb_ioctl,
421 /* initialize fb_info data */
422 static int mb862xxfb_init_fbinfo(struct fb_info *fbi)
424 struct mb862xxfb_par *par = fbi->par;
425 struct mb862xx_gc_mode *mode = par->gc_mode;
429 fbi->fbops = &mb862xxfb_ops;
430 fbi->pseudo_palette = par->pseudo_palette;
431 fbi->screen_base = par->fb_base;
432 fbi->screen_size = par->mapped_vram;
434 strcpy(fbi->fix.id, DRV_NAME);
435 fbi->fix.smem_start = (unsigned long)par->fb_base_phys;
436 fbi->fix.mmio_start = (unsigned long)par->mmio_base_phys;
437 fbi->fix.mmio_len = par->mmio_len;
438 fbi->fix.accel = FB_ACCEL_NONE;
439 fbi->fix.type = FB_TYPE_PACKED_PIXELS;
440 fbi->fix.type_aux = 0;
441 fbi->fix.xpanstep = 1;
442 fbi->fix.ypanstep = 1;
443 fbi->fix.ywrapstep = 0;
445 reg = inreg(disp, GC_DCM1);
446 if (reg & GC_DCM01_DEN && reg & GC_DCM01_L0E) {
447 /* get the disp mode from active display cfg */
448 unsigned long sc = ((reg & GC_DCM01_SC) >> 8) + 1;
449 unsigned long hsp, vsp, ht, vt;
451 dev_dbg(par->dev, "using bootloader's disp. mode\n");
452 fbi->var.pixclock = (sc * 1000000) / par->refclk;
453 fbi->var.xres = (inreg(disp, GC_HDB_HDP) & 0x0fff) + 1;
454 reg = inreg(disp, GC_VDP_VSP);
455 fbi->var.yres = ((reg >> 16) & 0x0fff) + 1;
456 vsp = (reg & 0x0fff) + 1;
457 fbi->var.xres_virtual = fbi->var.xres;
458 fbi->var.yres_virtual = fbi->var.yres;
459 reg = inreg(disp, GC_L0EM);
460 if (reg & GC_L0EM_L0EC_24) {
461 fbi->var.bits_per_pixel = 32;
463 reg = inreg(disp, GC_L0M);
464 if (reg & GC_L0M_L0C_16)
465 fbi->var.bits_per_pixel = 16;
467 fbi->var.bits_per_pixel = 8;
469 reg = inreg(disp, GC_VSW_HSW_HSP);
470 fbi->var.hsync_len = ((reg & 0xff0000) >> 16) + 1;
471 fbi->var.vsync_len = ((reg & 0x3f000000) >> 24) + 1;
472 hsp = (reg & 0xffff) + 1;
473 ht = ((inreg(disp, GC_HTP) & 0xfff0000) >> 16) + 1;
474 fbi->var.right_margin = hsp - fbi->var.xres;
475 fbi->var.left_margin = ht - hsp - fbi->var.hsync_len;
476 vt = ((inreg(disp, GC_VTR) & 0xfff0000) >> 16) + 1;
477 fbi->var.lower_margin = vsp - fbi->var.yres;
478 fbi->var.upper_margin = vt - vsp - fbi->var.vsync_len;
480 dev_dbg(par->dev, "using supplied mode\n");
481 fb_videomode_to_var(&fbi->var, (struct fb_videomode *)mode);
482 fbi->var.bits_per_pixel = mode->def_bpp ? mode->def_bpp : 8;
486 ret = fb_find_mode(&fbi->var, fbi, "640x480-16@60",
488 if (ret == 0 || ret == 4) {
490 "failed to get initial mode\n");
495 fbi->var.xoffset = 0;
496 fbi->var.yoffset = 0;
497 fbi->var.grayscale = 0;
499 fbi->var.height = -1;
501 fbi->var.accel_flags = 0;
502 fbi->var.vmode = FB_VMODE_NONINTERLACED;
503 fbi->var.activate = FB_ACTIVATE_NOW;
504 fbi->flags = FBINFO_DEFAULT |
506 FBINFO_FOREIGN_ENDIAN |
508 FBINFO_HWACCEL_XPAN |
511 /* check and possibly fix bpp */
512 if ((fbi->fbops->fb_check_var)(&fbi->var, fbi))
513 dev_err(par->dev, "check_var() failed on initial setup?\n");
515 fbi->fix.visual = fbi->var.bits_per_pixel == 8 ?
516 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
517 fbi->fix.line_length = (fbi->var.xres_virtual *
518 fbi->var.bits_per_pixel) / 8;
519 fbi->fix.smem_len = fbi->fix.line_length * fbi->var.yres_virtual;
522 * reserve space for capture buffers and two cursors
523 * at the end of vram: 720x576 * 2 * 2.2 + 64x64 * 16.
525 par->cap_buf = par->mapped_vram - 0x1bd800 - 0x10000;
526 par->cap_len = 0x1bd800;
529 par->l1_cfg.sw = 720;
530 par->l1_cfg.sh = 576;
533 par->l1_cfg.dw = 720;
534 par->l1_cfg.dh = 576;
535 stride = par->l1_cfg.sw * (fbi->var.bits_per_pixel / 8);
536 par->l1_stride = stride / 64 + ((stride % 64) ? 1 : 0);
537 outreg(cap, GC_CAP_CBM, GC_CBM_OO | GC_CBM_CBST |
538 (par->l1_stride << 16));
539 outreg(cap, GC_CAP_CBOA, par->cap_buf);
540 outreg(cap, GC_CAP_CBLA, par->cap_buf + par->cap_len);
545 * show some display controller and cursor registers
547 static ssize_t mb862xxfb_show_dispregs(struct device *dev,
548 struct device_attribute *attr, char *buf)
550 struct fb_info *fbi = dev_get_drvdata(dev);
551 struct mb862xxfb_par *par = fbi->par;
555 for (reg = GC_DCM0; reg <= GC_L0DY_L0DX; reg += 4)
556 ptr += sprintf(ptr, "%08x = %08x\n",
557 reg, inreg(disp, reg));
559 for (reg = GC_CPM_CUTC; reg <= GC_CUY1_CUX1; reg += 4)
560 ptr += sprintf(ptr, "%08x = %08x\n",
561 reg, inreg(disp, reg));
563 for (reg = GC_DCM1; reg <= GC_L0WH_L0WW; reg += 4)
564 ptr += sprintf(ptr, "%08x = %08x\n",
565 reg, inreg(disp, reg));
567 for (reg = 0x400; reg <= 0x410; reg += 4)
568 ptr += sprintf(ptr, "geo %08x = %08x\n",
569 reg, inreg(geo, reg));
571 for (reg = 0x400; reg <= 0x410; reg += 4)
572 ptr += sprintf(ptr, "draw %08x = %08x\n",
573 reg, inreg(draw, reg));
575 for (reg = 0x440; reg <= 0x450; reg += 4)
576 ptr += sprintf(ptr, "draw %08x = %08x\n",
577 reg, inreg(draw, reg));
582 static DEVICE_ATTR(dispregs, 0444, mb862xxfb_show_dispregs, NULL);
584 static irqreturn_t mb862xx_intr(int irq, void *dev_id)
586 struct mb862xxfb_par *par = (struct mb862xxfb_par *) dev_id;
587 unsigned long reg_ist, mask;
592 if (par->type == BT_CARMINE) {
593 /* Get Interrupt Status */
594 reg_ist = inreg(ctrl, GC_CTRL_STATUS);
595 mask = inreg(ctrl, GC_CTRL_INT_MASK);
603 /* Clear interrupt status */
604 outreg(ctrl, 0x0, reg_ist);
607 reg_ist = inreg(host, GC_IST);
608 mask = inreg(host, GC_IMASK);
615 outreg(host, GC_IST, ~reg_ist);
620 #if defined(CONFIG_FB_MB862XX_LIME)
622 * GDC (Lime, Coral(B/Q), Mint, ...) on host bus
624 static int mb862xx_gdc_init(struct mb862xxfb_par *par)
626 unsigned long ccf, mmr;
627 unsigned long ver, rev;
632 #if defined(CONFIG_FB_PRE_INIT_FB)
635 par->host = par->mmio_base;
636 par->i2c = par->mmio_base + MB862XX_I2C_BASE;
637 par->disp = par->mmio_base + MB862XX_DISP_BASE;
638 par->cap = par->mmio_base + MB862XX_CAP_BASE;
639 par->draw = par->mmio_base + MB862XX_DRAW_BASE;
640 par->geo = par->mmio_base + MB862XX_GEO_BASE;
641 par->pio = par->mmio_base + MB862XX_PIO_BASE;
643 par->refclk = GC_DISP_REFCLK_400;
645 ver = inreg(host, GC_CID);
646 rev = inreg(pio, GC_REVISION);
647 if ((ver == 0x303) && (rev & 0xffffff00) == 0x20050100) {
648 dev_info(par->dev, "Fujitsu Lime v1.%d found\n",
651 ccf = par->gc_mode ? par->gc_mode->ccf : GC_CCF_COT_100;
652 mmr = par->gc_mode ? par->gc_mode->mmr : 0x414fb7f2;
654 dev_info(par->dev, "? GDC, CID/Rev.: 0x%lx/0x%lx \n", ver, rev);
658 if (!par->pre_init) {
659 outreg(host, GC_CCF, ccf);
661 outreg(host, GC_MMR, mmr);
665 /* interrupt status */
666 outreg(host, GC_IST, 0);
667 outreg(host, GC_IMASK, GC_INT_EN);
671 static int of_platform_mb862xx_probe(struct platform_device *ofdev)
673 struct device_node *np = ofdev->dev.of_node;
674 struct device *dev = &ofdev->dev;
675 struct mb862xxfb_par *par;
676 struct fb_info *info;
678 resource_size_t res_size;
679 unsigned long ret = -ENODEV;
681 if (of_address_to_resource(np, 0, &res)) {
682 dev_err(dev, "Invalid address\n");
686 info = framebuffer_alloc(sizeof(struct mb862xxfb_par), dev);
688 dev_err(dev, "cannot allocate framebuffer\n");
696 par->irq = irq_of_parse_and_map(np, 0);
697 if (par->irq == NO_IRQ) {
698 dev_err(dev, "failed to map irq\n");
703 res_size = resource_size(&res);
704 par->res = request_mem_region(res.start, res_size, DRV_NAME);
705 if (par->res == NULL) {
706 dev_err(dev, "Cannot claim framebuffer/mmio\n");
711 #if defined(CONFIG_SOCRATES)
712 par->gc_mode = &socrates_gc_mode;
715 par->fb_base_phys = res.start;
716 par->mmio_base_phys = res.start + MB862XX_MMIO_BASE;
717 par->mmio_len = MB862XX_MMIO_SIZE;
719 par->mapped_vram = par->gc_mode->max_vram;
721 par->mapped_vram = MB862XX_MEM_SIZE;
723 par->fb_base = ioremap(par->fb_base_phys, par->mapped_vram);
724 if (par->fb_base == NULL) {
725 dev_err(dev, "Cannot map framebuffer\n");
729 par->mmio_base = ioremap(par->mmio_base_phys, par->mmio_len);
730 if (par->mmio_base == NULL) {
731 dev_err(dev, "Cannot map registers\n");
735 dev_dbg(dev, "fb phys 0x%llx 0x%lx\n",
736 (u64)par->fb_base_phys, (ulong)par->mapped_vram);
737 dev_dbg(dev, "mmio phys 0x%llx 0x%lx, (irq = %d)\n",
738 (u64)par->mmio_base_phys, (ulong)par->mmio_len, par->irq);
740 if (mb862xx_gdc_init(par))
743 if (request_irq(par->irq, mb862xx_intr, 0,
744 DRV_NAME, (void *)par)) {
745 dev_err(dev, "Cannot request irq\n");
749 mb862xxfb_init_fbinfo(info);
751 if (fb_alloc_cmap(&info->cmap, NR_PALETTE, 0) < 0) {
752 dev_err(dev, "Could not allocate cmap for fb_info.\n");
756 if ((info->fbops->fb_set_par)(info))
757 dev_err(dev, "set_var() failed on initial setup?\n");
759 if (register_framebuffer(info)) {
760 dev_err(dev, "failed to register framebuffer\n");
764 dev_set_drvdata(dev, info);
766 if (device_create_file(dev, &dev_attr_dispregs))
767 dev_err(dev, "Can't create sysfs regdump file\n");
771 fb_dealloc_cmap(&info->cmap);
773 outreg(host, GC_IMASK, 0);
774 free_irq(par->irq, (void *)par);
776 iounmap(par->mmio_base);
778 iounmap(par->fb_base);
780 release_mem_region(res.start, res_size);
782 irq_dispose_mapping(par->irq);
784 framebuffer_release(info);
788 static int of_platform_mb862xx_remove(struct platform_device *ofdev)
790 struct fb_info *fbi = dev_get_drvdata(&ofdev->dev);
791 struct mb862xxfb_par *par = fbi->par;
792 resource_size_t res_size = resource_size(par->res);
795 dev_dbg(fbi->dev, "%s release\n", fbi->fix.id);
798 reg = inreg(disp, GC_DCM1);
799 reg &= ~(GC_DCM01_DEN | GC_DCM01_L0E);
800 outreg(disp, GC_DCM1, reg);
802 /* disable interrupts */
803 outreg(host, GC_IMASK, 0);
805 free_irq(par->irq, (void *)par);
806 irq_dispose_mapping(par->irq);
808 device_remove_file(&ofdev->dev, &dev_attr_dispregs);
810 unregister_framebuffer(fbi);
811 fb_dealloc_cmap(&fbi->cmap);
813 iounmap(par->mmio_base);
814 iounmap(par->fb_base);
816 release_mem_region(par->res->start, res_size);
817 framebuffer_release(fbi);
824 static struct of_device_id of_platform_mb862xx_tbl[] = {
825 { .compatible = "fujitsu,MB86276", },
826 { .compatible = "fujitsu,lime", },
827 { .compatible = "fujitsu,MB86277", },
828 { .compatible = "fujitsu,mint", },
829 { .compatible = "fujitsu,MB86293", },
830 { .compatible = "fujitsu,MB86294", },
831 { .compatible = "fujitsu,coral", },
835 static struct platform_driver of_platform_mb862xxfb_driver = {
838 .of_match_table = of_platform_mb862xx_tbl,
840 .probe = of_platform_mb862xx_probe,
841 .remove = of_platform_mb862xx_remove,
845 #if defined(CONFIG_FB_MB862XX_PCI_GDC)
846 static int coralp_init(struct mb862xxfb_par *par)
850 par->host = par->mmio_base;
851 par->i2c = par->mmio_base + MB862XX_I2C_BASE;
852 par->disp = par->mmio_base + MB862XX_DISP_BASE;
853 par->cap = par->mmio_base + MB862XX_CAP_BASE;
854 par->draw = par->mmio_base + MB862XX_DRAW_BASE;
855 par->geo = par->mmio_base + MB862XX_GEO_BASE;
856 par->pio = par->mmio_base + MB862XX_PIO_BASE;
858 par->refclk = GC_DISP_REFCLK_400;
860 if (par->mapped_vram >= 0x2000000) {
861 /* relocate gdc registers space */
862 writel(1, par->fb_base + MB862XX_MMIO_BASE + GC_RSW);
863 udelay(1); /* wait at least 20 bus cycles */
866 ver = inreg(host, GC_CID);
867 cn = (ver & GC_CID_CNAME_MSK) >> 8;
868 ver = ver & GC_CID_VERSION_MSK;
872 dev_info(par->dev, "Fujitsu Coral-%s GDC Rev.%d found\n",\
873 (ver == 6) ? "P" : (ver == 8) ? "PA" : "?",
874 par->pdev->revision);
875 reg = inreg(disp, GC_DCM1);
876 if (reg & GC_DCM01_DEN && reg & GC_DCM01_L0E)
879 if (!par->pre_init) {
880 outreg(host, GC_CCF, GC_CCF_CGE_166 | GC_CCF_COT_133);
882 outreg(host, GC_MMR, GC_MMR_CORALP_EVB_VAL);
885 /* Clear interrupt status */
886 outreg(host, GC_IST, 0);
891 mb862xx_i2c_init(par);
895 static int init_dram_ctrl(struct mb862xxfb_par *par)
900 * Set io mode first! Spec. says IC may be destroyed
901 * if not set to SSTL2/LVCMOS before init.
903 outreg(dram_ctrl, GC_DCTL_IOCONT1_IOCONT0, GC_EVB_DCTL_IOCONT1_IOCONT0);
906 outreg(dram_ctrl, GC_DCTL_MODE_ADD, GC_EVB_DCTL_MODE_ADD);
907 outreg(dram_ctrl, GC_DCTL_SETTIME1_EMODE, GC_EVB_DCTL_SETTIME1_EMODE);
908 outreg(dram_ctrl, GC_DCTL_REFRESH_SETTIME2,
909 GC_EVB_DCTL_REFRESH_SETTIME2);
910 outreg(dram_ctrl, GC_DCTL_RSV2_RSV1, GC_EVB_DCTL_RSV2_RSV1);
911 outreg(dram_ctrl, GC_DCTL_DDRIF2_DDRIF1, GC_EVB_DCTL_DDRIF2_DDRIF1);
912 outreg(dram_ctrl, GC_DCTL_RSV0_STATES, GC_EVB_DCTL_RSV0_STATES);
914 /* DLL reset done? */
915 while ((inreg(dram_ctrl, GC_DCTL_RSV0_STATES) & GC_DCTL_STATES_MSK)) {
916 udelay(GC_DCTL_INIT_WAIT_INTERVAL);
917 if (i++ > GC_DCTL_INIT_WAIT_CNT) {
918 dev_err(par->dev, "VRAM init failed.\n");
922 outreg(dram_ctrl, GC_DCTL_MODE_ADD, GC_EVB_DCTL_MODE_ADD_AFT_RST);
923 outreg(dram_ctrl, GC_DCTL_RSV0_STATES, GC_EVB_DCTL_RSV0_STATES_AFT_RST);
927 static int carmine_init(struct mb862xxfb_par *par)
931 par->ctrl = par->mmio_base + MB86297_CTRL_BASE;
932 par->i2c = par->mmio_base + MB86297_I2C_BASE;
933 par->disp = par->mmio_base + MB86297_DISP0_BASE;
934 par->disp1 = par->mmio_base + MB86297_DISP1_BASE;
935 par->cap = par->mmio_base + MB86297_CAP0_BASE;
936 par->cap1 = par->mmio_base + MB86297_CAP1_BASE;
937 par->draw = par->mmio_base + MB86297_DRAW_BASE;
938 par->dram_ctrl = par->mmio_base + MB86297_DRAMCTRL_BASE;
939 par->wrback = par->mmio_base + MB86297_WRBACK_BASE;
941 par->refclk = GC_DISP_REFCLK_533;
944 reg = GC_CTRL_CLK_EN_DRAM | GC_CTRL_CLK_EN_2D3D | GC_CTRL_CLK_EN_DISP0;
945 outreg(ctrl, GC_CTRL_CLK_ENABLE, reg);
947 /* check for engine module revision */
948 if (inreg(draw, GC_2D3D_REV) == GC_RE_REVISION)
949 dev_info(par->dev, "Fujitsu Carmine GDC Rev.%d found\n",
950 par->pdev->revision);
954 reg &= ~GC_CTRL_CLK_EN_2D3D;
955 outreg(ctrl, GC_CTRL_CLK_ENABLE, reg);
958 if (init_dram_ctrl(par) < 0)
961 outreg(ctrl, GC_CTRL_INT_MASK, 0);
965 outreg(ctrl, GC_CTRL_CLK_ENABLE, 0);
969 static inline int mb862xx_pci_gdc_init(struct mb862xxfb_par *par)
973 return coralp_init(par);
975 return carmine_init(par);
981 #define CHIP_ID(id) \
982 { PCI_DEVICE(PCI_VENDOR_ID_FUJITSU_LIMITED, id) }
984 static struct pci_device_id mb862xx_pci_tbl[] = {
985 /* MB86295/MB86296 */
986 CHIP_ID(PCI_DEVICE_ID_FUJITSU_CORALP),
987 CHIP_ID(PCI_DEVICE_ID_FUJITSU_CORALPA),
989 CHIP_ID(PCI_DEVICE_ID_FUJITSU_CARMINE),
993 MODULE_DEVICE_TABLE(pci, mb862xx_pci_tbl);
995 static int mb862xx_pci_probe(struct pci_dev *pdev,
996 const struct pci_device_id *ent)
998 struct mb862xxfb_par *par;
999 struct fb_info *info;
1000 struct device *dev = &pdev->dev;
1003 ret = pci_enable_device(pdev);
1005 dev_err(dev, "Cannot enable PCI device\n");
1009 info = framebuffer_alloc(sizeof(struct mb862xxfb_par), dev);
1011 dev_err(dev, "framebuffer alloc failed\n");
1020 par->irq = pdev->irq;
1022 ret = pci_request_regions(pdev, DRV_NAME);
1024 dev_err(dev, "Cannot reserve region(s) for PCI device\n");
1028 switch (pdev->device) {
1029 case PCI_DEVICE_ID_FUJITSU_CORALP:
1030 case PCI_DEVICE_ID_FUJITSU_CORALPA:
1031 par->fb_base_phys = pci_resource_start(par->pdev, 0);
1032 par->mapped_vram = CORALP_MEM_SIZE;
1033 if (par->mapped_vram >= 0x2000000) {
1034 par->mmio_base_phys = par->fb_base_phys +
1035 MB862XX_MMIO_HIGH_BASE;
1037 par->mmio_base_phys = par->fb_base_phys +
1040 par->mmio_len = MB862XX_MMIO_SIZE;
1041 par->type = BT_CORALP;
1043 case PCI_DEVICE_ID_FUJITSU_CARMINE:
1044 par->fb_base_phys = pci_resource_start(par->pdev, 2);
1045 par->mmio_base_phys = pci_resource_start(par->pdev, 3);
1046 par->mmio_len = pci_resource_len(par->pdev, 3);
1047 par->mapped_vram = CARMINE_MEM_SIZE;
1048 par->type = BT_CARMINE;
1051 /* should never occur */
1056 par->fb_base = ioremap(par->fb_base_phys, par->mapped_vram);
1057 if (par->fb_base == NULL) {
1058 dev_err(dev, "Cannot map framebuffer\n");
1063 par->mmio_base = ioremap(par->mmio_base_phys, par->mmio_len);
1064 if (par->mmio_base == NULL) {
1065 dev_err(dev, "Cannot map registers\n");
1070 dev_dbg(dev, "fb phys 0x%llx 0x%lx\n",
1071 (unsigned long long)par->fb_base_phys, (ulong)par->mapped_vram);
1072 dev_dbg(dev, "mmio phys 0x%llx 0x%lx\n",
1073 (unsigned long long)par->mmio_base_phys, (ulong)par->mmio_len);
1075 ret = mb862xx_pci_gdc_init(par);
1079 ret = request_irq(par->irq, mb862xx_intr, IRQF_SHARED,
1080 DRV_NAME, (void *)par);
1082 dev_err(dev, "Cannot request irq\n");
1086 mb862xxfb_init_fbinfo(info);
1088 if (fb_alloc_cmap(&info->cmap, NR_PALETTE, 0) < 0) {
1089 dev_err(dev, "Could not allocate cmap for fb_info.\n");
1094 if ((info->fbops->fb_set_par)(info))
1095 dev_err(dev, "set_var() failed on initial setup?\n");
1097 ret = register_framebuffer(info);
1099 dev_err(dev, "failed to register framebuffer\n");
1103 pci_set_drvdata(pdev, info);
1105 if (device_create_file(dev, &dev_attr_dispregs))
1106 dev_err(dev, "Can't create sysfs regdump file\n");
1108 if (par->type == BT_CARMINE)
1109 outreg(ctrl, GC_CTRL_INT_MASK, GC_CARMINE_INT_EN);
1111 outreg(host, GC_IMASK, GC_INT_EN);
1116 fb_dealloc_cmap(&info->cmap);
1118 free_irq(par->irq, (void *)par);
1120 iounmap(par->mmio_base);
1122 iounmap(par->fb_base);
1124 pci_release_regions(pdev);
1126 framebuffer_release(info);
1128 pci_disable_device(pdev);
1133 static void mb862xx_pci_remove(struct pci_dev *pdev)
1135 struct fb_info *fbi = pci_get_drvdata(pdev);
1136 struct mb862xxfb_par *par = fbi->par;
1139 dev_dbg(fbi->dev, "%s release\n", fbi->fix.id);
1142 reg = inreg(disp, GC_DCM1);
1143 reg &= ~(GC_DCM01_DEN | GC_DCM01_L0E);
1144 outreg(disp, GC_DCM1, reg);
1146 if (par->type == BT_CARMINE) {
1147 outreg(ctrl, GC_CTRL_INT_MASK, 0);
1148 outreg(ctrl, GC_CTRL_CLK_ENABLE, 0);
1150 outreg(host, GC_IMASK, 0);
1153 mb862xx_i2c_exit(par);
1155 device_remove_file(&pdev->dev, &dev_attr_dispregs);
1157 unregister_framebuffer(fbi);
1158 fb_dealloc_cmap(&fbi->cmap);
1160 free_irq(par->irq, (void *)par);
1161 iounmap(par->mmio_base);
1162 iounmap(par->fb_base);
1164 pci_release_regions(pdev);
1165 framebuffer_release(fbi);
1166 pci_disable_device(pdev);
1169 static struct pci_driver mb862xxfb_pci_driver = {
1171 .id_table = mb862xx_pci_tbl,
1172 .probe = mb862xx_pci_probe,
1173 .remove = mb862xx_pci_remove,
1177 static int mb862xxfb_init(void)
1181 #if defined(CONFIG_FB_MB862XX_LIME)
1182 ret = platform_driver_register(&of_platform_mb862xxfb_driver);
1184 #if defined(CONFIG_FB_MB862XX_PCI_GDC)
1185 ret = pci_register_driver(&mb862xxfb_pci_driver);
1190 static void __exit mb862xxfb_exit(void)
1192 #if defined(CONFIG_FB_MB862XX_LIME)
1193 platform_driver_unregister(&of_platform_mb862xxfb_driver);
1195 #if defined(CONFIG_FB_MB862XX_PCI_GDC)
1196 pci_unregister_driver(&mb862xxfb_pci_driver);
1200 module_init(mb862xxfb_init);
1201 module_exit(mb862xxfb_exit);
1203 MODULE_DESCRIPTION("Fujitsu MB862xx Framebuffer driver");
1204 MODULE_AUTHOR("Anatolij Gustschin <agust@denx.de>");
1205 MODULE_LICENSE("GPL v2");