2 * linux/drivers/video/omap2/dss/dpi.c
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * Some code and ideas taken from drivers/video/omap/ driver
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
23 #define DSS_SUBSYS_NAME "DPI"
25 #include <linux/kernel.h>
26 #include <linux/delay.h>
27 #include <linux/export.h>
28 #include <linux/err.h>
29 #include <linux/errno.h>
30 #include <linux/platform_device.h>
31 #include <linux/regulator/consumer.h>
32 #include <linux/string.h>
35 #include <video/omapdss.h>
38 #include "dss_features.h"
41 struct platform_device *pdev;
43 struct regulator *vdds_dsi_reg;
44 struct platform_device *dsidev;
48 struct omap_video_timings timings;
49 struct dss_lcd_mgr_config mgr_config;
52 struct omap_dss_device output;
54 bool port_initialized;
57 static struct platform_device *dpi_get_dsidev(enum omap_channel channel)
60 * XXX we can't currently use DSI PLL for DPI with OMAP3, as the DSI PLL
61 * would also be used for DISPC fclk. Meaning, when the DPI output is
62 * disabled, DISPC clock will be disabled, and TV out will stop.
64 switch (omapdss_get_version()) {
65 case OMAPDSS_VER_OMAP24xx:
66 case OMAPDSS_VER_OMAP34xx_ES1:
67 case OMAPDSS_VER_OMAP34xx_ES3:
68 case OMAPDSS_VER_OMAP3630:
69 case OMAPDSS_VER_AM35xx:
70 case OMAPDSS_VER_AM43xx:
73 case OMAPDSS_VER_OMAP4430_ES1:
74 case OMAPDSS_VER_OMAP4430_ES2:
75 case OMAPDSS_VER_OMAP4:
77 case OMAP_DSS_CHANNEL_LCD:
78 return dsi_get_dsidev_from_id(0);
79 case OMAP_DSS_CHANNEL_LCD2:
80 return dsi_get_dsidev_from_id(1);
85 case OMAPDSS_VER_OMAP5:
87 case OMAP_DSS_CHANNEL_LCD:
88 return dsi_get_dsidev_from_id(0);
89 case OMAP_DSS_CHANNEL_LCD3:
90 return dsi_get_dsidev_from_id(1);
100 static enum omap_dss_clk_source dpi_get_alt_clk_src(enum omap_channel channel)
103 case OMAP_DSS_CHANNEL_LCD:
104 return OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC;
105 case OMAP_DSS_CHANNEL_LCD2:
106 return OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC;
107 case OMAP_DSS_CHANNEL_LCD3:
108 return OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC;
110 /* this shouldn't happen */
112 return OMAP_DSS_CLK_SRC_FCK;
116 struct dpi_clk_calc_ctx {
117 struct platform_device *dsidev;
121 unsigned long pck_min, pck_max;
125 struct dsi_clock_info dsi_cinfo;
127 struct dispc_clock_info dispc_cinfo;
130 static bool dpi_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
131 unsigned long pck, void *data)
133 struct dpi_clk_calc_ctx *ctx = data;
136 * Odd dividers give us uneven duty cycle, causing problem when level
137 * shifted. So skip all odd dividers when the pixel clock is on the
140 if (ctx->pck_min >= 100000000) {
141 if (lckd > 1 && lckd % 2 != 0)
144 if (pckd > 1 && pckd % 2 != 0)
148 ctx->dispc_cinfo.lck_div = lckd;
149 ctx->dispc_cinfo.pck_div = pckd;
150 ctx->dispc_cinfo.lck = lck;
151 ctx->dispc_cinfo.pck = pck;
157 static bool dpi_calc_hsdiv_cb(int regm_dispc, unsigned long dispc,
160 struct dpi_clk_calc_ctx *ctx = data;
163 * Odd dividers give us uneven duty cycle, causing problem when level
164 * shifted. So skip all odd dividers when the pixel clock is on the
167 if (regm_dispc > 1 && regm_dispc % 2 != 0 && ctx->pck_min >= 100000000)
170 ctx->dsi_cinfo.regm_dispc = regm_dispc;
171 ctx->dsi_cinfo.dsi_pll_hsdiv_dispc_clk = dispc;
173 return dispc_div_calc(dispc, ctx->pck_min, ctx->pck_max,
174 dpi_calc_dispc_cb, ctx);
178 static bool dpi_calc_pll_cb(int regn, int regm, unsigned long fint,
182 struct dpi_clk_calc_ctx *ctx = data;
184 ctx->dsi_cinfo.regn = regn;
185 ctx->dsi_cinfo.regm = regm;
186 ctx->dsi_cinfo.fint = fint;
187 ctx->dsi_cinfo.clkin4ddr = pll;
189 return dsi_hsdiv_calc(ctx->dsidev, pll, ctx->pck_min,
190 dpi_calc_hsdiv_cb, ctx);
193 static bool dpi_calc_dss_cb(unsigned long fck, void *data)
195 struct dpi_clk_calc_ctx *ctx = data;
199 return dispc_div_calc(fck, ctx->pck_min, ctx->pck_max,
200 dpi_calc_dispc_cb, ctx);
203 static bool dpi_dsi_clk_calc(unsigned long pck, struct dpi_clk_calc_ctx *ctx)
206 unsigned long pll_min, pll_max;
208 clkin = dsi_get_pll_clkin(dpi.dsidev);
210 memset(ctx, 0, sizeof(*ctx));
211 ctx->dsidev = dpi.dsidev;
212 ctx->pck_min = pck - 1000;
213 ctx->pck_max = pck + 1000;
214 ctx->dsi_cinfo.clkin = clkin;
219 return dsi_pll_calc(dpi.dsidev, clkin,
221 dpi_calc_pll_cb, ctx);
224 static bool dpi_dss_clk_calc(unsigned long pck, struct dpi_clk_calc_ctx *ctx)
229 * DSS fck gives us very few possibilities, so finding a good pixel
230 * clock may not be possible. We try multiple times to find the clock,
231 * each time widening the pixel clock range we look for, up to
235 for (i = 0; i < 25; ++i) {
238 memset(ctx, 0, sizeof(*ctx));
239 if (pck > 1000 * i * i * i)
240 ctx->pck_min = max(pck - 1000 * i * i * i, 0lu);
243 ctx->pck_max = pck + 1000 * i * i * i;
245 ok = dss_div_calc(pck, ctx->pck_min, dpi_calc_dss_cb, ctx);
255 static int dpi_set_dsi_clk(enum omap_channel channel,
256 unsigned long pck_req, unsigned long *fck, int *lck_div,
259 struct dpi_clk_calc_ctx ctx;
263 ok = dpi_dsi_clk_calc(pck_req, &ctx);
267 r = dsi_pll_set_clock_div(dpi.dsidev, &ctx.dsi_cinfo);
271 dss_select_lcd_clk_source(channel,
272 dpi_get_alt_clk_src(channel));
274 dpi.mgr_config.clock_info = ctx.dispc_cinfo;
276 *fck = ctx.dsi_cinfo.dsi_pll_hsdiv_dispc_clk;
277 *lck_div = ctx.dispc_cinfo.lck_div;
278 *pck_div = ctx.dispc_cinfo.pck_div;
283 static int dpi_set_dispc_clk(unsigned long pck_req, unsigned long *fck,
284 int *lck_div, int *pck_div)
286 struct dpi_clk_calc_ctx ctx;
290 ok = dpi_dss_clk_calc(pck_req, &ctx);
294 r = dss_set_fck_rate(ctx.fck);
298 dpi.mgr_config.clock_info = ctx.dispc_cinfo;
301 *lck_div = ctx.dispc_cinfo.lck_div;
302 *pck_div = ctx.dispc_cinfo.pck_div;
307 static int dpi_set_mode(struct omap_overlay_manager *mgr)
309 struct omap_video_timings *t = &dpi.timings;
310 int lck_div = 0, pck_div = 0;
311 unsigned long fck = 0;
316 r = dpi_set_dsi_clk(mgr->id, t->pixelclock, &fck,
319 r = dpi_set_dispc_clk(t->pixelclock, &fck,
324 pck = fck / lck_div / pck_div;
326 if (pck != t->pixelclock) {
327 DSSWARN("Could not find exact pixel clock. Requested %d Hz, got %lu Hz\n",
333 dss_mgr_set_timings(mgr, t);
338 static void dpi_config_lcd_manager(struct omap_overlay_manager *mgr)
340 dpi.mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
342 dpi.mgr_config.stallmode = false;
343 dpi.mgr_config.fifohandcheck = false;
345 dpi.mgr_config.video_port_width = dpi.data_lines;
347 dpi.mgr_config.lcden_sig_polarity = 0;
349 dss_mgr_set_lcd_config(mgr, &dpi.mgr_config);
352 static int dpi_display_enable(struct omap_dss_device *dssdev)
354 struct omap_dss_device *out = &dpi.output;
357 mutex_lock(&dpi.lock);
359 if (dss_has_feature(FEAT_DPI_USES_VDDS_DSI) && !dpi.vdds_dsi_reg) {
360 DSSERR("no VDSS_DSI regulator\n");
365 if (out == NULL || out->manager == NULL) {
366 DSSERR("failed to enable display: no output/manager\n");
371 if (dss_has_feature(FEAT_DPI_USES_VDDS_DSI)) {
372 r = regulator_enable(dpi.vdds_dsi_reg);
377 r = dispc_runtime_get();
381 r = dss_dpi_select_source(out->manager->id);
386 r = dsi_runtime_get(dpi.dsidev);
390 r = dsi_pll_init(dpi.dsidev, 0, 1);
392 goto err_dsi_pll_init;
395 r = dpi_set_mode(out->manager);
399 dpi_config_lcd_manager(out->manager);
403 r = dss_mgr_enable(out->manager);
407 mutex_unlock(&dpi.lock);
414 dsi_pll_uninit(dpi.dsidev, true);
417 dsi_runtime_put(dpi.dsidev);
422 if (dss_has_feature(FEAT_DPI_USES_VDDS_DSI))
423 regulator_disable(dpi.vdds_dsi_reg);
427 mutex_unlock(&dpi.lock);
431 static void dpi_display_disable(struct omap_dss_device *dssdev)
433 struct omap_overlay_manager *mgr = dpi.output.manager;
435 mutex_lock(&dpi.lock);
437 dss_mgr_disable(mgr);
440 dss_select_lcd_clk_source(mgr->id, OMAP_DSS_CLK_SRC_FCK);
441 dsi_pll_uninit(dpi.dsidev, true);
442 dsi_runtime_put(dpi.dsidev);
447 if (dss_has_feature(FEAT_DPI_USES_VDDS_DSI))
448 regulator_disable(dpi.vdds_dsi_reg);
450 mutex_unlock(&dpi.lock);
453 static void dpi_set_timings(struct omap_dss_device *dssdev,
454 struct omap_video_timings *timings)
456 DSSDBG("dpi_set_timings\n");
458 mutex_lock(&dpi.lock);
460 dpi.timings = *timings;
462 mutex_unlock(&dpi.lock);
465 static void dpi_get_timings(struct omap_dss_device *dssdev,
466 struct omap_video_timings *timings)
468 mutex_lock(&dpi.lock);
470 *timings = dpi.timings;
472 mutex_unlock(&dpi.lock);
475 static int dpi_check_timings(struct omap_dss_device *dssdev,
476 struct omap_video_timings *timings)
478 struct omap_overlay_manager *mgr = dpi.output.manager;
479 int lck_div, pck_div;
482 struct dpi_clk_calc_ctx ctx;
485 if (mgr && !dispc_mgr_timings_ok(mgr->id, timings))
488 if (timings->pixelclock == 0)
492 ok = dpi_dsi_clk_calc(timings->pixelclock, &ctx);
496 fck = ctx.dsi_cinfo.dsi_pll_hsdiv_dispc_clk;
498 ok = dpi_dss_clk_calc(timings->pixelclock, &ctx);
505 lck_div = ctx.dispc_cinfo.lck_div;
506 pck_div = ctx.dispc_cinfo.pck_div;
508 pck = fck / lck_div / pck_div;
510 timings->pixelclock = pck;
515 static void dpi_set_data_lines(struct omap_dss_device *dssdev, int data_lines)
517 mutex_lock(&dpi.lock);
519 dpi.data_lines = data_lines;
521 mutex_unlock(&dpi.lock);
524 static int dpi_verify_dsi_pll(struct platform_device *dsidev)
528 /* do initial setup with the PLL to see if it is operational */
530 r = dsi_runtime_get(dsidev);
534 r = dsi_pll_init(dsidev, 0, 1);
536 dsi_runtime_put(dsidev);
540 dsi_pll_uninit(dsidev, true);
541 dsi_runtime_put(dsidev);
546 static int dpi_init_regulator(void)
548 struct regulator *vdds_dsi;
550 if (!dss_has_feature(FEAT_DPI_USES_VDDS_DSI))
553 if (dpi.vdds_dsi_reg)
556 vdds_dsi = devm_regulator_get(&dpi.pdev->dev, "vdds_dsi");
557 if (IS_ERR(vdds_dsi)) {
558 if (PTR_ERR(vdds_dsi) != -EPROBE_DEFER)
559 DSSERR("can't get VDDS_DSI regulator\n");
560 return PTR_ERR(vdds_dsi);
563 dpi.vdds_dsi_reg = vdds_dsi;
568 static void dpi_init_pll(void)
570 struct platform_device *dsidev;
575 dsidev = dpi_get_dsidev(dpi.output.dispc_channel);
579 if (dpi_verify_dsi_pll(dsidev)) {
580 DSSWARN("DSI PLL not operational\n");
588 * Return a hardcoded channel for the DPI output. This should work for
589 * current use cases, but this can be later expanded to either resolve
590 * the channel in some more dynamic manner, or get the channel as a user
593 static enum omap_channel dpi_get_channel(void)
595 switch (omapdss_get_version()) {
596 case OMAPDSS_VER_OMAP24xx:
597 case OMAPDSS_VER_OMAP34xx_ES1:
598 case OMAPDSS_VER_OMAP34xx_ES3:
599 case OMAPDSS_VER_OMAP3630:
600 case OMAPDSS_VER_AM35xx:
601 case OMAPDSS_VER_AM43xx:
602 return OMAP_DSS_CHANNEL_LCD;
604 case OMAPDSS_VER_OMAP4430_ES1:
605 case OMAPDSS_VER_OMAP4430_ES2:
606 case OMAPDSS_VER_OMAP4:
607 return OMAP_DSS_CHANNEL_LCD2;
609 case OMAPDSS_VER_OMAP5:
610 return OMAP_DSS_CHANNEL_LCD3;
613 DSSWARN("unsupported DSS version\n");
614 return OMAP_DSS_CHANNEL_LCD;
618 static int dpi_connect(struct omap_dss_device *dssdev,
619 struct omap_dss_device *dst)
621 struct omap_overlay_manager *mgr;
624 r = dpi_init_regulator();
630 mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel);
634 r = dss_mgr_connect(mgr, dssdev);
638 r = omapdss_output_set_device(dssdev, dst);
640 DSSERR("failed to connect output to new device: %s\n",
642 dss_mgr_disconnect(mgr, dssdev);
649 static void dpi_disconnect(struct omap_dss_device *dssdev,
650 struct omap_dss_device *dst)
652 WARN_ON(dst != dssdev->dst);
654 if (dst != dssdev->dst)
657 omapdss_output_unset_device(dssdev);
660 dss_mgr_disconnect(dssdev->manager, dssdev);
663 static const struct omapdss_dpi_ops dpi_ops = {
664 .connect = dpi_connect,
665 .disconnect = dpi_disconnect,
667 .enable = dpi_display_enable,
668 .disable = dpi_display_disable,
670 .check_timings = dpi_check_timings,
671 .set_timings = dpi_set_timings,
672 .get_timings = dpi_get_timings,
674 .set_data_lines = dpi_set_data_lines,
677 static void dpi_init_output(struct platform_device *pdev)
679 struct omap_dss_device *out = &dpi.output;
681 out->dev = &pdev->dev;
682 out->id = OMAP_DSS_OUTPUT_DPI;
683 out->output_type = OMAP_DISPLAY_TYPE_DPI;
685 out->dispc_channel = dpi_get_channel();
686 out->ops.dpi = &dpi_ops;
687 out->owner = THIS_MODULE;
689 omapdss_register_output(out);
692 static void __exit dpi_uninit_output(struct platform_device *pdev)
694 struct omap_dss_device *out = &dpi.output;
696 omapdss_unregister_output(out);
699 static int omap_dpi_probe(struct platform_device *pdev)
703 mutex_init(&dpi.lock);
705 dpi_init_output(pdev);
710 static int __exit omap_dpi_remove(struct platform_device *pdev)
712 dpi_uninit_output(pdev);
717 static struct platform_driver omap_dpi_driver = {
718 .probe = omap_dpi_probe,
719 .remove = __exit_p(omap_dpi_remove),
721 .name = "omapdss_dpi",
722 .owner = THIS_MODULE,
726 int __init dpi_init_platform_driver(void)
728 return platform_driver_register(&omap_dpi_driver);
731 void __exit dpi_uninit_platform_driver(void)
733 platform_driver_unregister(&omap_dpi_driver);
736 int __init dpi_init_port(struct platform_device *pdev, struct device_node *port)
738 struct device_node *ep;
742 ep = omapdss_of_get_next_endpoint(port, NULL);
746 r = of_property_read_u32(ep, "data-lines", &datalines);
748 DSSERR("failed to parse datalines\n");
752 dpi.data_lines = datalines;
758 mutex_init(&dpi.lock);
760 dpi_init_output(pdev);
762 dpi.port_initialized = true;
772 void __exit dpi_uninit_port(void)
774 if (!dpi.port_initialized)
777 dpi_uninit_output(dpi.pdev);