2 * linux/drivers/video/omap2/dss/dss.h
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * Some code and ideas taken from drivers/video/omap/ driver
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
26 #include <linux/interrupt.h>
32 #ifdef DSS_SUBSYS_NAME
33 #define pr_fmt(fmt) DSS_SUBSYS_NAME ": " fmt
35 #define pr_fmt(fmt) fmt
38 #define DSSDBG(format, ...) \
39 pr_debug(format, ## __VA_ARGS__)
41 #ifdef DSS_SUBSYS_NAME
42 #define DSSERR(format, ...) \
43 printk(KERN_ERR "omapdss " DSS_SUBSYS_NAME " error: " format, \
46 #define DSSERR(format, ...) \
47 printk(KERN_ERR "omapdss error: " format, ## __VA_ARGS__)
50 #ifdef DSS_SUBSYS_NAME
51 #define DSSINFO(format, ...) \
52 printk(KERN_INFO "omapdss " DSS_SUBSYS_NAME ": " format, \
55 #define DSSINFO(format, ...) \
56 printk(KERN_INFO "omapdss: " format, ## __VA_ARGS__)
59 #ifdef DSS_SUBSYS_NAME
60 #define DSSWARN(format, ...) \
61 printk(KERN_WARNING "omapdss " DSS_SUBSYS_NAME ": " format, \
64 #define DSSWARN(format, ...) \
65 printk(KERN_WARNING "omapdss: " format, ## __VA_ARGS__)
68 /* OMAP TRM gives bitfields as start:end, where start is the higher bit
69 number. For example 7:0 */
70 #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
71 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
72 #define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
73 #define FLD_MOD(orig, val, start, end) \
74 (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
76 enum dss_io_pad_mode {
77 DSS_IO_PAD_MODE_RESET,
79 DSS_IO_PAD_MODE_BYPASS,
82 enum dss_hdmi_venc_clk_source_select {
87 enum dss_dsi_content_type {
89 DSS_DSI_CONTENT_GENERIC,
92 enum dss_writeback_channel {
103 struct dispc_clock_info {
104 /* rates that we get with dividers below */
113 struct dsi_clock_info {
114 /* rates that we get with dividers below */
116 unsigned long clkin4ddr;
118 unsigned long dsi_pll_hsdiv_dispc_clk; /* OMAP3: DSI1_PLL_CLK
119 * OMAP4: PLLx_CLK1 */
120 unsigned long dsi_pll_hsdiv_dsi_clk; /* OMAP3: DSI2_PLL_CLK
121 * OMAP4: PLLx_CLK2 */
122 unsigned long lp_clk;
127 u16 regm_dispc; /* OMAP3: REGM3
129 u16 regm_dsi; /* OMAP3: REGM4
134 struct dss_lcd_mgr_config {
135 enum dss_io_pad_mode io_pad_mode;
140 struct dispc_clock_info clock_info;
142 int video_port_width;
144 int lcden_sig_polarity;
148 struct platform_device;
151 struct platform_device *dss_get_core_pdev(void);
152 int dss_dsi_enable_pads(int dsi_id, unsigned lane_mask);
153 void dss_dsi_disable_pads(int dsi_id, unsigned lane_mask);
154 int dss_set_min_bus_tput(struct device *dev, unsigned long tput);
155 int dss_debugfs_create_file(const char *name, void (*write)(struct seq_file *));
158 int dss_suspend_all_devices(void);
159 int dss_resume_all_devices(void);
160 void dss_disable_all_devices(void);
162 int display_init_sysfs(struct platform_device *pdev);
163 void display_uninit_sysfs(struct platform_device *pdev);
166 int dss_init_overlay_managers(void);
167 void dss_uninit_overlay_managers(void);
168 int dss_init_overlay_managers_sysfs(struct platform_device *pdev);
169 void dss_uninit_overlay_managers_sysfs(struct platform_device *pdev);
170 int dss_mgr_simple_check(struct omap_overlay_manager *mgr,
171 const struct omap_overlay_manager_info *info);
172 int dss_mgr_check_timings(struct omap_overlay_manager *mgr,
173 const struct omap_video_timings *timings);
174 int dss_mgr_check(struct omap_overlay_manager *mgr,
175 struct omap_overlay_manager_info *info,
176 const struct omap_video_timings *mgr_timings,
177 const struct dss_lcd_mgr_config *config,
178 struct omap_overlay_info **overlay_infos);
180 static inline bool dss_mgr_is_lcd(enum omap_channel id)
182 if (id == OMAP_DSS_CHANNEL_LCD || id == OMAP_DSS_CHANNEL_LCD2 ||
183 id == OMAP_DSS_CHANNEL_LCD3)
189 int dss_manager_kobj_init(struct omap_overlay_manager *mgr,
190 struct platform_device *pdev);
191 void dss_manager_kobj_uninit(struct omap_overlay_manager *mgr);
194 void dss_init_overlays(struct platform_device *pdev);
195 void dss_uninit_overlays(struct platform_device *pdev);
196 void dss_overlay_setup_dispc_manager(struct omap_overlay_manager *mgr);
197 int dss_ovl_simple_check(struct omap_overlay *ovl,
198 const struct omap_overlay_info *info);
199 int dss_ovl_check(struct omap_overlay *ovl, struct omap_overlay_info *info,
200 const struct omap_video_timings *mgr_timings);
201 bool dss_ovl_use_replication(struct dss_lcd_mgr_config config,
202 enum omap_color_mode mode);
203 int dss_overlay_kobj_init(struct omap_overlay *ovl,
204 struct platform_device *pdev);
205 void dss_overlay_kobj_uninit(struct omap_overlay *ovl);
208 int dss_init_platform_driver(void) __init;
209 void dss_uninit_platform_driver(void);
211 unsigned long dss_get_dispc_clk_rate(void);
212 int dss_dpi_select_source(enum omap_channel channel);
213 void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select);
214 enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void);
215 const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src);
216 void dss_dump_clocks(struct seq_file *s);
218 #if defined(CONFIG_OMAP2_DSS_DEBUGFS)
219 void dss_debug_dump_clocks(struct seq_file *s);
222 void dss_sdi_init(int datapairs);
223 int dss_sdi_enable(void);
224 void dss_sdi_disable(void);
226 void dss_select_dsi_clk_source(int dsi_module,
227 enum omap_dss_clk_source clk_src);
228 void dss_select_lcd_clk_source(enum omap_channel channel,
229 enum omap_dss_clk_source clk_src);
230 enum omap_dss_clk_source dss_get_dispc_clk_source(void);
231 enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module);
232 enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel);
234 void dss_set_venc_output(enum omap_dss_venc_type type);
235 void dss_set_dac_pwrdn_bgz(bool enable);
237 int dss_set_fck_rate(unsigned long rate);
239 typedef bool (*dss_div_calc_func)(unsigned long fck, void *data);
240 bool dss_div_calc(unsigned long pck, unsigned long fck_min,
241 dss_div_calc_func func, void *data);
244 int sdi_init_platform_driver(void) __init;
245 void sdi_uninit_platform_driver(void) __exit;
247 #ifdef CONFIG_OMAP2_DSS_SDI
248 int sdi_init_port(struct platform_device *pdev, struct device_node *port) __init;
249 void sdi_uninit_port(struct device_node *port) __exit;
251 static inline int __init sdi_init_port(struct platform_device *pdev,
252 struct device_node *port)
256 static inline void __exit sdi_uninit_port(struct device_node *port)
263 typedef bool (*dsi_pll_calc_func)(int regn, int regm, unsigned long fint,
264 unsigned long pll, void *data);
265 typedef bool (*dsi_hsdiv_calc_func)(int regm_dispc, unsigned long dispc,
268 #ifdef CONFIG_OMAP2_DSS_DSI
271 struct file_operations;
273 int dsi_init_platform_driver(void) __init;
274 void dsi_uninit_platform_driver(void) __exit;
276 int dsi_runtime_get(struct platform_device *dsidev);
277 void dsi_runtime_put(struct platform_device *dsidev);
279 void dsi_dump_clocks(struct seq_file *s);
281 void dsi_irq_handler(void);
282 u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt);
284 unsigned long dsi_get_pll_clkin(struct platform_device *dsidev);
286 bool dsi_hsdiv_calc(struct platform_device *dsidev, unsigned long pll,
287 unsigned long out_min, dsi_hsdiv_calc_func func, void *data);
288 bool dsi_pll_calc(struct platform_device *dsidev, unsigned long clkin,
289 unsigned long pll_min, unsigned long pll_max,
290 dsi_pll_calc_func func, void *data);
292 unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev);
293 int dsi_pll_set_clock_div(struct platform_device *dsidev,
294 struct dsi_clock_info *cinfo);
295 int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk,
297 void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes);
298 void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev);
299 void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev);
300 struct platform_device *dsi_get_dsidev_from_id(int module);
302 static inline int dsi_runtime_get(struct platform_device *dsidev)
306 static inline void dsi_runtime_put(struct platform_device *dsidev)
309 static inline u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
311 WARN("%s: DSI not compiled in, returning pixel_size as 0\n", __func__);
314 static inline unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev)
316 WARN("%s: DSI not compiled in, returning rate as 0\n", __func__);
319 static inline int dsi_pll_set_clock_div(struct platform_device *dsidev,
320 struct dsi_clock_info *cinfo)
322 WARN("%s: DSI not compiled in\n", __func__);
325 static inline int dsi_pll_init(struct platform_device *dsidev,
326 bool enable_hsclk, bool enable_hsdiv)
328 WARN("%s: DSI not compiled in\n", __func__);
331 static inline void dsi_pll_uninit(struct platform_device *dsidev,
332 bool disconnect_lanes)
335 static inline void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev)
338 static inline void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev)
341 static inline struct platform_device *dsi_get_dsidev_from_id(int module)
346 static inline unsigned long dsi_get_pll_clkin(struct platform_device *dsidev)
351 static inline bool dsi_hsdiv_calc(struct platform_device *dsidev,
352 unsigned long pll, unsigned long out_min,
353 dsi_hsdiv_calc_func func, void *data)
358 static inline bool dsi_pll_calc(struct platform_device *dsidev,
360 unsigned long pll_min, unsigned long pll_max,
361 dsi_pll_calc_func func, void *data)
369 int dpi_init_platform_driver(void) __init;
370 void dpi_uninit_platform_driver(void) __exit;
372 #ifdef CONFIG_OMAP2_DSS_DPI
373 int dpi_init_port(struct platform_device *pdev, struct device_node *port) __init;
374 void dpi_uninit_port(struct device_node *port) __exit;
376 static inline int __init dpi_init_port(struct platform_device *pdev,
377 struct device_node *port)
381 static inline void __exit dpi_uninit_port(struct device_node *port)
387 int dispc_init_platform_driver(void) __init;
388 void dispc_uninit_platform_driver(void) __exit;
389 void dispc_dump_clocks(struct seq_file *s);
391 void dispc_enable_sidle(void);
392 void dispc_disable_sidle(void);
394 void dispc_lcd_enable_signal(bool enable);
395 void dispc_pck_free_enable(bool enable);
396 void dispc_enable_fifomerge(bool enable);
397 void dispc_enable_gamma_table(bool enable);
398 void dispc_set_loadmode(enum omap_dss_load_mode mode);
400 typedef bool (*dispc_div_calc_func)(int lckd, int pckd, unsigned long lck,
401 unsigned long pck, void *data);
402 bool dispc_div_calc(unsigned long dispc,
403 unsigned long pck_min, unsigned long pck_max,
404 dispc_div_calc_func func, void *data);
406 bool dispc_mgr_timings_ok(enum omap_channel channel,
407 const struct omap_video_timings *timings);
408 unsigned long dispc_fclk_rate(void);
409 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
410 struct dispc_clock_info *cinfo);
413 void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high);
414 void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
415 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
418 unsigned long dispc_mgr_lclk_rate(enum omap_channel channel);
419 unsigned long dispc_mgr_pclk_rate(enum omap_channel channel);
420 unsigned long dispc_core_clk_rate(void);
421 void dispc_mgr_set_clock_div(enum omap_channel channel,
422 const struct dispc_clock_info *cinfo);
423 int dispc_mgr_get_clock_div(enum omap_channel channel,
424 struct dispc_clock_info *cinfo);
425 void dispc_set_tv_pclk(unsigned long pclk);
427 u32 dispc_wb_get_framedone_irq(void);
428 bool dispc_wb_go_busy(void);
429 void dispc_wb_go(void);
430 void dispc_wb_enable(bool enable);
431 bool dispc_wb_is_enabled(void);
432 void dispc_wb_set_channel_in(enum dss_writeback_channel channel);
433 int dispc_wb_setup(const struct omap_dss_writeback_info *wi,
434 bool mem_to_mem, const struct omap_video_timings *timings);
437 int venc_init_platform_driver(void) __init;
438 void venc_uninit_platform_driver(void) __exit;
441 int hdmi4_init_platform_driver(void) __init;
442 void hdmi4_uninit_platform_driver(void) __exit;
444 int hdmi5_init_platform_driver(void) __init;
445 void hdmi5_uninit_platform_driver(void) __exit;
448 int rfbi_init_platform_driver(void) __init;
449 void rfbi_uninit_platform_driver(void) __exit;
452 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
453 static inline void dss_collect_irq_stats(u32 irqstatus, unsigned *irq_arr)
456 for (b = 0; b < 32; ++b) {
457 if (irqstatus & (1 << b))