4 * Copyright (C) 2013 Texas Instruments Incorporated
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published by
8 * the Free Software Foundation.
11 #define DSS_SUBSYS_NAME "HDMIPLL"
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/err.h>
17 #include <linux/platform_device.h>
18 #include <video/omapdss.h>
23 #define HDMI_DEFAULT_REGN 16
24 #define HDMI_DEFAULT_REGM2 1
26 struct hdmi_pll_features {
28 /* this is a hack, need to replace it with a better computation of M2 */
30 unsigned long fint_min, fint_max;
32 unsigned long dcofreq_low_min, dcofreq_low_max;
33 unsigned long dcofreq_high_min, dcofreq_high_max;
36 static const struct hdmi_pll_features *pll_feat;
38 void hdmi_pll_dump(struct hdmi_pll_data *pll, struct seq_file *s)
40 #define DUMPPLL(r) seq_printf(s, "%-35s %08x\n", #r,\
41 hdmi_read_reg(pll->base, r))
43 DUMPPLL(PLLCTRL_PLL_CONTROL);
44 DUMPPLL(PLLCTRL_PLL_STATUS);
45 DUMPPLL(PLLCTRL_PLL_GO);
46 DUMPPLL(PLLCTRL_CFG1);
47 DUMPPLL(PLLCTRL_CFG2);
48 DUMPPLL(PLLCTRL_CFG3);
49 DUMPPLL(PLLCTRL_SSC_CFG1);
50 DUMPPLL(PLLCTRL_SSC_CFG2);
51 DUMPPLL(PLLCTRL_CFG4);
54 void hdmi_pll_compute(struct hdmi_pll_data *pll, unsigned long clkin, int phy)
56 struct hdmi_pll_info *pi = &pll->info;
60 /* use our funky units */
64 * Input clock is predivided by N + 1
65 * out put of which is reference clk
68 pi->regn = HDMI_DEFAULT_REGN;
70 refclk = clkin / pi->regn;
72 /* temorary hack to make sure DCO freq isn't calculated too low */
73 if (pll_feat->bound_dcofreq && phy <= 65000)
76 pi->regm2 = HDMI_DEFAULT_REGM2;
79 * multiplier is pixel_clk/ref_clk
80 * Multiplying by 100 to avoid fractional part removal
82 pi->regm = phy * pi->regm2 / refclk;
85 * fractional multiplier is remainder of the difference between
86 * multiplier and actual phy(required pixel clock thus should be
87 * multiplied by 2^18(262144) divided by the reference clock
89 mf = (phy - pi->regm / pi->regm2 * refclk) * 262144;
90 pi->regmf = pi->regm2 * mf / refclk;
93 * Dcofreq should be set to 1 if required pixel clock
94 * is greater than 1000MHz
96 pi->dcofreq = phy > 1000 * 100;
97 pi->regsd = ((pi->regm * clkin / 10) / (pi->regn * 250) + 5) / 10;
99 /* Set the reference clock to sysclk reference */
100 pi->refsel = HDMI_REFSEL_SYSCLK;
102 DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf);
103 DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd);
107 static int hdmi_pll_config(struct hdmi_pll_data *pll)
110 struct hdmi_pll_info *fmt = &pll->info;
112 /* PLL start always use manual mode */
113 REG_FLD_MOD(pll->base, PLLCTRL_PLL_CONTROL, 0x0, 0, 0);
115 r = hdmi_read_reg(pll->base, PLLCTRL_CFG1);
116 r = FLD_MOD(r, fmt->regm, 20, 9); /* CFG1_PLL_REGM */
117 r = FLD_MOD(r, fmt->regn - 1, 8, 1); /* CFG1_PLL_REGN */
118 hdmi_write_reg(pll->base, PLLCTRL_CFG1, r);
120 r = hdmi_read_reg(pll->base, PLLCTRL_CFG2);
122 r = FLD_MOD(r, 0x0, 12, 12); /* PLL_HIGHFREQ divide by 2 */
123 r = FLD_MOD(r, 0x1, 13, 13); /* PLL_REFEN */
124 r = FLD_MOD(r, 0x0, 14, 14); /* PHY_CLKINEN de-assert during locking */
125 r = FLD_MOD(r, fmt->refsel, 22, 21); /* REFSEL */
128 r = FLD_MOD(r, 0x4, 3, 1); /* 1000MHz and 2000MHz */
130 r = FLD_MOD(r, 0x2, 3, 1); /* 500MHz and 1000MHz */
132 hdmi_write_reg(pll->base, PLLCTRL_CFG2, r);
134 REG_FLD_MOD(pll->base, PLLCTRL_CFG3, fmt->regsd, 17, 10);
136 r = hdmi_read_reg(pll->base, PLLCTRL_CFG4);
137 r = FLD_MOD(r, fmt->regm2, 24, 18);
138 r = FLD_MOD(r, fmt->regmf, 17, 0);
139 hdmi_write_reg(pll->base, PLLCTRL_CFG4, r);
142 REG_FLD_MOD(pll->base, PLLCTRL_PLL_GO, 0x1, 0, 0);
144 /* wait for bit change */
145 if (hdmi_wait_for_bit_change(pll->base, PLLCTRL_PLL_GO,
147 DSSERR("PLL GO bit not clearing\n");
151 /* Wait till the lock bit is set in PLL status */
152 if (hdmi_wait_for_bit_change(pll->base,
153 PLLCTRL_PLL_STATUS, 1, 1, 1) != 1) {
154 DSSERR("cannot lock PLL\n");
155 DSSERR("CFG1 0x%x\n",
156 hdmi_read_reg(pll->base, PLLCTRL_CFG1));
157 DSSERR("CFG2 0x%x\n",
158 hdmi_read_reg(pll->base, PLLCTRL_CFG2));
159 DSSERR("CFG4 0x%x\n",
160 hdmi_read_reg(pll->base, PLLCTRL_CFG4));
164 DSSDBG("PLL locked!\n");
169 static int hdmi_pll_reset(struct hdmi_pll_data *pll)
171 /* SYSRESET controlled by power FSM */
172 REG_FLD_MOD(pll->base, PLLCTRL_PLL_CONTROL, pll_feat->sys_reset, 3, 3);
174 /* READ 0x0 reset is in progress */
175 if (hdmi_wait_for_bit_change(pll->base, PLLCTRL_PLL_STATUS, 0, 0, 1)
177 DSSERR("Failed to sysreset PLL\n");
184 int hdmi_pll_enable(struct hdmi_pll_data *pll, struct hdmi_wp_data *wp)
188 r = hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_ALLOFF);
192 r = hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_BOTHON_ALLCLKS);
196 r = hdmi_pll_reset(pll);
200 r = hdmi_pll_config(pll);
207 void hdmi_pll_disable(struct hdmi_pll_data *pll, struct hdmi_wp_data *wp)
209 hdmi_wp_set_pll_pwr(wp, HDMI_PLLPWRCMD_ALLOFF);
212 static const struct hdmi_pll_features omap44xx_pll_feats = {
214 .bound_dcofreq = false,
218 .dcofreq_low_min = 500000000,
219 .dcofreq_low_max = 1000000000,
220 .dcofreq_high_min = 1000000000,
221 .dcofreq_high_max = 2000000000,
224 static const struct hdmi_pll_features omap54xx_pll_feats = {
226 .bound_dcofreq = true,
230 .dcofreq_low_min = 750000000,
231 .dcofreq_low_max = 1500000000,
232 .dcofreq_high_min = 1250000000,
233 .dcofreq_high_max = 2500000000UL,
236 static int hdmi_pll_init_features(struct platform_device *pdev)
238 struct hdmi_pll_features *dst;
239 const struct hdmi_pll_features *src;
241 dst = devm_kzalloc(&pdev->dev, sizeof(*dst), GFP_KERNEL);
243 dev_err(&pdev->dev, "Failed to allocate HDMI PHY Features\n");
247 switch (omapdss_get_version()) {
248 case OMAPDSS_VER_OMAP4430_ES1:
249 case OMAPDSS_VER_OMAP4430_ES2:
250 case OMAPDSS_VER_OMAP4:
251 src = &omap44xx_pll_feats;
254 case OMAPDSS_VER_OMAP5:
255 src = &omap54xx_pll_feats;
262 memcpy(dst, src, sizeof(*dst));
268 int hdmi_pll_init(struct platform_device *pdev, struct hdmi_pll_data *pll)
271 struct resource *res;
273 r = hdmi_pll_init_features(pdev);
277 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pll");
279 DSSERR("can't get PLL mem resource\n");
283 pll->base = devm_ioremap_resource(&pdev->dev, res);
284 if (IS_ERR(pll->base)) {
285 DSSERR("can't ioremap PLLCTRL\n");
286 return PTR_ERR(pll->base);