drivers/video/fbdev/pxafb.c

   1 /*
   2  *  linux/drivers/video/pxafb.c
   3  *
   4  *  Copyright (C) 1999 Eric A. Thomas.
   5  *  Copyright (C) 2004 Jean-Frederic Clere.
   6  *  Copyright (C) 2004 Ian Campbell.
   7  *  Copyright (C) 2004 Jeff Lackey.
   8  *   Based on sa1100fb.c Copyright (C) 1999 Eric A. Thomas
   9  *  which in turn is
  10  *   Based on acornfb.c Copyright (C) Russell King.
  11  *
  12  * This file is subject to the terms and conditions of the GNU General Public
  13  * License.  See the file COPYING in the main directory of this archive for
  14  * more details.
  15  *
  16  *              Intel PXA250/210 LCD Controller Frame Buffer Driver
  17  *
  18  * Please direct your questions and comments on this driver to the following
  19  * email address:
  20  *
  21  *      linux-arm-kernel@lists.arm.linux.org.uk
  22  *
  23  * Add support for overlay1 and overlay2 based on pxafb_overlay.c:
  24  *
  25  *   Copyright (C) 2004, Intel Corporation
  26  *
  27  *     2003/08/27: <yu.tang@intel.com>
  28  *     2004/03/10: <stanley.cai@intel.com>
  29  *     2004/10/28: <yan.yin@intel.com>
  30  *
  31  *   Copyright (C) 2006-2008 Marvell International Ltd.
  32  *   All Rights Reserved
  33  */
  34
  35 #include <linux/module.h>
  36 #include <linux/moduleparam.h>
  37 #include <linux/kernel.h>
  38 #include <linux/sched.h>
  39 #include <linux/errno.h>
  40 #include <linux/string.h>
  41 #include <linux/interrupt.h>
  42 #include <linux/slab.h>
  43 #include <linux/mm.h>
  44 #include <linux/fb.h>
  45 #include <linux/delay.h>
  46 #include <linux/init.h>
  47 #include <linux/ioport.h>
  48 #include <linux/cpufreq.h>
  49 #include <linux/platform_device.h>
  50 #include <linux/dma-mapping.h>
  51 #include <linux/clk.h>
  52 #include <linux/err.h>
  53 #include <linux/completion.h>
  54 #include <linux/mutex.h>
  55 #include <linux/kthread.h>
  56 #include <linux/freezer.h>
  57 #include <linux/console.h>
  58
  59 #include <mach/hardware.h>
  60 #include <asm/io.h>
  61 #include <asm/irq.h>
  62 #include <asm/div64.h>
  63 #include <mach/bitfield.h>
  64 #include <linux/platform_data/video-pxafb.h>
  65
  66 /*
  67  * Complain if VAR is out of range.
  68  */
  69 #define DEBUG_VAR 1
  70
  71 #include "pxafb.h"
  72
  73 /* Bits which should not be set in machine configuration structures */
  74 #define LCCR0_INVALID_CONFIG_MASK       (LCCR0_OUM | LCCR0_BM | LCCR0_QDM |\
  75                                          LCCR0_DIS | LCCR0_EFM | LCCR0_IUM |\
  76                                          LCCR0_SFM | LCCR0_LDM | LCCR0_ENB)
  77
  78 #define LCCR3_INVALID_CONFIG_MASK       (LCCR3_HSP | LCCR3_VSP |\
  79                                          LCCR3_PCD | LCCR3_BPP(0xf))
  80
  81 static int pxafb_activate_var(struct fb_var_screeninfo *var,
  82                                 struct pxafb_info *);
  83 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state);
  84 static void setup_base_frame(struct pxafb_info *fbi,
  85                              struct fb_var_screeninfo *var, int branch);
  86 static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
  87                            unsigned long offset, size_t size);
  88
  89 static unsigned long video_mem_size = 0;
  90
  91 static inline unsigned long
  92 lcd_readl(struct pxafb_info *fbi, unsigned int off)
  93 {
  94         return __raw_readl(fbi->mmio_base + off);
  95 }
  96
  97 static inline void
  98 lcd_writel(struct pxafb_info *fbi, unsigned int off, unsigned long val)
  99 {
 100         __raw_writel(val, fbi->mmio_base + off);
 101 }
 102
 103 static inline void pxafb_schedule_work(struct pxafb_info *fbi, u_int state)
 104 {
 105         unsigned long flags;
 106
 107         local_irq_save(flags);
 108         /*
 109          * We need to handle two requests being made at the same time.
 110          * There are two important cases:
 111          *  1. When we are changing VT (C_REENABLE) while unblanking
 112          *     (C_ENABLE) We must perform the unblanking, which will
 113          *     do our REENABLE for us.
 114          *  2. When we are blanking, but immediately unblank before
 115          *     we have blanked.  We do the "REENABLE" thing here as
 116          *     well, just to be sure.
 117          */
 118         if (fbi->task_state == C_ENABLE && state == C_REENABLE)
 119                 state = (u_int) -1;
 120         if (fbi->task_state == C_DISABLE && state == C_ENABLE)
 121                 state = C_REENABLE;
 122
 123         if (state != (u_int)-1) {
 124                 fbi->task_state = state;
 125                 schedule_work(&fbi->task);
 126         }
 127         local_irq_restore(flags);
 128 }
 129
 130 static inline u_int chan_to_field(u_int chan, struct fb_bitfield *bf)
 131 {
 132         chan &= 0xffff;
 133         chan >>= 16 - bf->length;
 134         return chan << bf->offset;
 135 }
 136
 137 static int
 138 pxafb_setpalettereg(u_int regno, u_int red, u_int green, u_int blue,
 139                        u_int trans, struct fb_info *info)
 140 {
 141         struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
 142         u_int val;
 143
 144         if (regno >= fbi->palette_size)
 145                 return 1;
 146
 147         if (fbi->fb.var.grayscale) {
 148                 fbi->palette_cpu[regno] = ((blue >> 8) & 0x00ff);
 149                 return 0;
 150         }
 151
 152         switch (fbi->lccr4 & LCCR4_PAL_FOR_MASK) {
 153         case LCCR4_PAL_FOR_0:
 154                 val  = ((red   >>  0) & 0xf800);
 155                 val |= ((green >>  5) & 0x07e0);
 156                 val |= ((blue  >> 11) & 0x001f);
 157                 fbi->palette_cpu[regno] = val;
 158                 break;
 159         case LCCR4_PAL_FOR_1:
 160                 val  = ((red   << 8) & 0x00f80000);
 161                 val |= ((green >> 0) & 0x0000fc00);
 162                 val |= ((blue  >> 8) & 0x000000f8);
 163                 ((u32 *)(fbi->palette_cpu))[regno] = val;
 164                 break;
 165         case LCCR4_PAL_FOR_2:
 166                 val  = ((red   << 8) & 0x00fc0000);
 167                 val |= ((green >> 0) & 0x0000fc00);
 168                 val |= ((blue  >> 8) & 0x000000fc);
 169                 ((u32 *)(fbi->palette_cpu))[regno] = val;
 170                 break;
 171         case LCCR4_PAL_FOR_3:
 172                 val  = ((red   << 8) & 0x00ff0000);
 173                 val |= ((green >> 0) & 0x0000ff00);
 174                 val |= ((blue  >> 8) & 0x000000ff);
 175                 ((u32 *)(fbi->palette_cpu))[regno] = val;
 176                 break;
 177         }
 178
 179         return 0;
 180 }
 181
 182 static int
 183 pxafb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
 184                    u_int trans, struct fb_info *info)
 185 {
 186         struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
 187         unsigned int val;
 188         int ret = 1;
 189
 190         /*
 191          * If inverse mode was selected, invert all the colours
 192          * rather than the register number.  The register number
 193          * is what you poke into the framebuffer to produce the
 194          * colour you requested.
 195          */
 196         if (fbi->cmap_inverse) {
 197                 red   = 0xffff - red;
 198                 green = 0xffff - green;
 199                 blue  = 0xffff - blue;
 200         }
 201
 202         /*
 203          * If greyscale is true, then we convert the RGB value
 204          * to greyscale no matter what visual we are using.
 205          */
 206         if (fbi->fb.var.grayscale)
 207                 red = green = blue = (19595 * red + 38470 * green +
 208                                         7471 * blue) >> 16;
 209
 210         switch (fbi->fb.fix.visual) {
 211         case FB_VISUAL_TRUECOLOR:
 212                 /*
 213                  * 16-bit True Colour.  We encode the RGB value
 214                  * according to the RGB bitfield information.
 215                  */
 216                 if (regno < 16) {
 217                         u32 *pal = fbi->fb.pseudo_palette;
 218
 219                         val  = chan_to_field(red, &fbi->fb.var.red);
 220                         val |= chan_to_field(green, &fbi->fb.var.green);
 221                         val |= chan_to_field(blue, &fbi->fb.var.blue);
 222
 223                         pal[regno] = val;
 224                         ret = 0;
 225                 }
 226                 break;
 227
 228         case FB_VISUAL_STATIC_PSEUDOCOLOR:
 229         case FB_VISUAL_PSEUDOCOLOR:
 230                 ret = pxafb_setpalettereg(regno, red, green, blue, trans, info);
 231                 break;
 232         }
 233
 234         return ret;
 235 }
 236
 237 /* calculate pixel depth, transparency bit included, >=16bpp formats _only_ */
 238 static inline int var_to_depth(struct fb_var_screeninfo *var)
 239 {
 240         return var->red.length + var->green.length +
 241                 var->blue.length + var->transp.length;
 242 }
 243
 244 /* calculate 4-bit BPP value for LCCR3 and OVLxC1 */
 245 static int pxafb_var_to_bpp(struct fb_var_screeninfo *var)
 246 {
 247         int bpp = -EINVAL;
 248
 249         switch (var->bits_per_pixel) {
 250         case 1:  bpp = 0; break;
 251         case 2:  bpp = 1; break;
 252         case 4:  bpp = 2; break;
 253         case 8:  bpp = 3; break;
 254         case 16: bpp = 4; break;
 255         case 24:
 256                 switch (var_to_depth(var)) {
 257                 case 18: bpp = 6; break; /* 18-bits/pixel packed */
 258                 case 19: bpp = 8; break; /* 19-bits/pixel packed */
 259                 case 24: bpp = 9; break;
 260                 }
 261                 break;
 262         case 32:
 263                 switch (var_to_depth(var)) {
 264                 case 18: bpp = 5; break; /* 18-bits/pixel unpacked */
 265                 case 19: bpp = 7; break; /* 19-bits/pixel unpacked */
 266                 case 25: bpp = 10; break;
 267                 }
 268                 break;
 269         }
 270         return bpp;
 271 }
 272
 273 /*
 274  *  pxafb_var_to_lccr3():
 275  *    Convert a bits per pixel value to the correct bit pattern for LCCR3
 276  *
 277  *  NOTE: for PXA27x with overlays support, the LCCR3_PDFOR_x bits have an
 278  *  implication of the acutal use of transparency bit,  which we handle it
 279  *  here separatedly. See PXA27x Developer's Manual, Section <<7.4.6 Pixel
 280  *  Formats>> for the valid combination of PDFOR, PAL_FOR for various BPP.
 281  *
 282  *  Transparency for palette pixel formats is not supported at the moment.
 283  */
 284 static uint32_t pxafb_var_to_lccr3(struct fb_var_screeninfo *var)
 285 {
 286         int bpp = pxafb_var_to_bpp(var);
 287         uint32_t lccr3;
 288
 289         if (bpp < 0)
 290                 return 0;
 291
 292         lccr3 = LCCR3_BPP(bpp);
 293
 294         switch (var_to_depth(var)) {
 295         case 16: lccr3 |= var->transp.length ? LCCR3_PDFOR_3 : 0; break;
 296         case 18: lccr3 |= LCCR3_PDFOR_3; break;
 297         case 24: lccr3 |= var->transp.length ? LCCR3_PDFOR_2 : LCCR3_PDFOR_3;
 298                  break;
 299         case 19:
 300         case 25: lccr3 |= LCCR3_PDFOR_0; break;
 301         }
 302         return lccr3;
 303 }
 304
 305 #define SET_PIXFMT(v, r, g, b, t)                               \
 306 ({                                                              \
 307         (v)->transp.offset = (t) ? (r) + (g) + (b) : 0;         \
 308         (v)->transp.length = (t) ? (t) : 0;                     \
 309         (v)->blue.length   = (b); (v)->blue.offset = 0;         \
 310         (v)->green.length  = (g); (v)->green.offset = (b);      \
 311         (v)->red.length    = (r); (v)->red.offset = (b) + (g);  \
 312 })
 313
 314 /* set the RGBT bitfields of fb_var_screeninf according to
 315  * var->bits_per_pixel and given depth
 316  */
 317 static void pxafb_set_pixfmt(struct fb_var_screeninfo *var, int depth)
 318 {
 319         if (depth == 0)
 320                 depth = var->bits_per_pixel;
 321
 322         if (var->bits_per_pixel < 16) {
 323                 /* indexed pixel formats */
 324                 var->red.offset    = 0; var->red.length    = 8;
 325                 var->green.offset  = 0; var->green.length  = 8;
 326                 var->blue.offset   = 0; var->blue.length   = 8;
 327                 var->transp.offset = 0; var->transp.length = 8;
 328         }
 329
 330         switch (depth) {
 331         case 16: var->transp.length ?
 332                  SET_PIXFMT(var, 5, 5, 5, 1) :          /* RGBT555 */
 333                  SET_PIXFMT(var, 5, 6, 5, 0); break;    /* RGB565 */
 334         case 18: SET_PIXFMT(var, 6, 6, 6, 0); break;    /* RGB666 */
 335         case 19: SET_PIXFMT(var, 6, 6, 6, 1); break;    /* RGBT666 */
 336         case 24: var->transp.length ?
 337                  SET_PIXFMT(var, 8, 8, 7, 1) :          /* RGBT887 */
 338                  SET_PIXFMT(var, 8, 8, 8, 0); break;    /* RGB888 */
 339         case 25: SET_PIXFMT(var, 8, 8, 8, 1); break;    /* RGBT888 */
 340         }
 341 }
 342
 343 #ifdef CONFIG_CPU_FREQ
 344 /*
 345  *  pxafb_display_dma_period()
 346  *    Calculate the minimum period (in picoseconds) between two DMA
 347  *    requests for the LCD controller.  If we hit this, it means we're
 348  *    doing nothing but LCD DMA.
 349  */
 350 static unsigned int pxafb_display_dma_period(struct fb_var_screeninfo *var)
 351 {
 352         /*
 353          * Period = pixclock * bits_per_byte * bytes_per_transfer
 354          *              / memory_bits_per_pixel;
 355          */
 356         return var->pixclock * 8 * 16 / var->bits_per_pixel;
 357 }
 358 #endif
 359
 360 /*
 361  * Select the smallest mode that allows the desired resolution to be
 362  * displayed. If desired parameters can be rounded up.
 363  */
 364 static struct pxafb_mode_info *pxafb_getmode(struct pxafb_mach_info *mach,
 365                                              struct fb_var_screeninfo *var)
 366 {
 367         struct pxafb_mode_info *mode = NULL;
 368         struct pxafb_mode_info *modelist = mach->modes;
 369         unsigned int best_x = 0xffffffff, best_y = 0xffffffff;
 370         unsigned int i;
 371
 372         for (i = 0; i < mach->num_modes; i++) {
 373                 if (modelist[i].xres >= var->xres &&
 374                     modelist[i].yres >= var->yres &&
 375                     modelist[i].xres < best_x &&
 376                     modelist[i].yres < best_y &&
 377                     modelist[i].bpp >= var->bits_per_pixel) {
 378                         best_x = modelist[i].xres;
 379                         best_y = modelist[i].yres;
 380                         mode = &modelist[i];
 381                 }
 382         }
 383
 384         return mode;
 385 }
 386
 387 static void pxafb_setmode(struct fb_var_screeninfo *var,
 388                           struct pxafb_mode_info *mode)
 389 {
 390         var->xres               = mode->xres;
 391         var->yres               = mode->yres;
 392         var->bits_per_pixel     = mode->bpp;
 393         var->pixclock           = mode->pixclock;
 394         var->hsync_len          = mode->hsync_len;
 395         var->left_margin        = mode->left_margin;
 396         var->right_margin       = mode->right_margin;
 397         var->vsync_len          = mode->vsync_len;
 398         var->upper_margin       = mode->upper_margin;
 399         var->lower_margin       = mode->lower_margin;
 400         var->sync               = mode->sync;
 401         var->grayscale          = mode->cmap_greyscale;
 402         var->transp.length      = mode->transparency;
 403
 404         /* set the initial RGBA bitfields */
 405         pxafb_set_pixfmt(var, mode->depth);
 406 }
 407
 408 static int pxafb_adjust_timing(struct pxafb_info *fbi,
 409                                struct fb_var_screeninfo *var)
 410 {
 411         int line_length;
 412
 413         var->xres = max_t(int, var->xres, MIN_XRES);
 414         var->yres = max_t(int, var->yres, MIN_YRES);
 415
 416         if (!(fbi->lccr0 & LCCR0_LCDT)) {
 417                 clamp_val(var->hsync_len, 1, 64);
 418                 clamp_val(var->vsync_len, 1, 64);
 419                 clamp_val(var->left_margin,  1, 255);
 420                 clamp_val(var->right_margin, 1, 255);
 421                 clamp_val(var->upper_margin, 1, 255);
 422                 clamp_val(var->lower_margin, 1, 255);
 423         }
 424
 425         /* make sure each line is aligned on word boundary */
 426         line_length = var->xres * var->bits_per_pixel / 8;
 427         line_length = ALIGN(line_length, 4);
 428         var->xres = line_length * 8 / var->bits_per_pixel;
 429
 430         /* we don't support xpan, force xres_virtual to be equal to xres */
 431         var->xres_virtual = var->xres;
 432
 433         if (var->accel_flags & FB_ACCELF_TEXT)
 434                 var->yres_virtual = fbi->fb.fix.smem_len / line_length;
 435         else
 436                 var->yres_virtual = max(var->yres_virtual, var->yres);
 437
 438         /* check for limits */
 439         if (var->xres > MAX_XRES || var->yres > MAX_YRES)
 440                 return -EINVAL;
 441
 442         if (var->yres > var->yres_virtual)
 443                 return -EINVAL;
 444
 445         return 0;
 446 }
 447
 448 /*
 449  *  pxafb_check_var():
 450  *    Get the video params out of 'var'. If a value doesn't fit, round it up,
 451  *    if it's too big, return -EINVAL.
 452  *
 453  *    Round up in the following order: bits_per_pixel, xres,
 454  *    yres, xres_virtual, yres_virtual, xoffset, yoffset, grayscale,
 455  *    bitfields, horizontal timing, vertical timing.
 456  */
 457 static int pxafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
 458 {
 459         struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
 460         struct pxafb_mach_info *inf = dev_get_platdata(fbi->dev);
 461         int err;
 462
 463         if (inf->fixed_modes) {
 464                 struct pxafb_mode_info *mode;
 465
 466                 mode = pxafb_getmode(inf, var);
 467                 if (!mode)
 468                         return -EINVAL;
 469                 pxafb_setmode(var, mode);
 470         }
 471
 472         /* do a test conversion to BPP fields to check the color formats */
 473         err = pxafb_var_to_bpp(var);
 474         if (err < 0)
 475                 return err;
 476
 477         pxafb_set_pixfmt(var, var_to_depth(var));
 478
 479         err = pxafb_adjust_timing(fbi, var);
 480         if (err)
 481                 return err;
 482
 483 #ifdef CONFIG_CPU_FREQ
 484         pr_debug("pxafb: dma period = %d ps\n",
 485                  pxafb_display_dma_period(var));
 486 #endif
 487
 488         return 0;
 489 }
 490
 491 /*
 492  * pxafb_set_par():
 493  *      Set the user defined part of the display for the specified console
 494  */
 495 static int pxafb_set_par(struct fb_info *info)
 496 {
 497         struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
 498         struct fb_var_screeninfo *var = &info->var;
 499
 500         if (var->bits_per_pixel >= 16)
 501                 fbi->fb.fix.visual = FB_VISUAL_TRUECOLOR;
 502         else if (!fbi->cmap_static)
 503                 fbi->fb.fix.visual = FB_VISUAL_PSEUDOCOLOR;
 504         else {
 505                 /*
 506                  * Some people have weird ideas about wanting static
 507                  * pseudocolor maps.  I suspect their user space
 508                  * applications are broken.
 509                  */
 510                 fbi->fb.fix.visual = FB_VISUAL_STATIC_PSEUDOCOLOR;
 511         }
 512
 513         fbi->fb.fix.line_length = var->xres_virtual *
 514                                   var->bits_per_pixel / 8;
 515         if (var->bits_per_pixel >= 16)
 516                 fbi->palette_size = 0;
 517         else
 518                 fbi->palette_size = var->bits_per_pixel == 1 ?
 519                                         4 : 1 << var->bits_per_pixel;
 520
 521         fbi->palette_cpu = (u16 *)&fbi->dma_buff->palette[0];
 522
 523         if (fbi->fb.var.bits_per_pixel >= 16)
 524                 fb_dealloc_cmap(&fbi->fb.cmap);
 525         else
 526                 fb_alloc_cmap(&fbi->fb.cmap, 1<<fbi->fb.var.bits_per_pixel, 0);
 527
 528         pxafb_activate_var(var, fbi);
 529
 530         return 0;
 531 }
 532
 533 static int pxafb_pan_display(struct fb_var_screeninfo *var,
 534                              struct fb_info *info)
 535 {
 536         struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
 537         struct fb_var_screeninfo newvar;
 538         int dma = DMA_MAX + DMA_BASE;
 539
 540         if (fbi->state != C_ENABLE)
 541                 return 0;
 542
 543         /* Only take .xoffset, .yoffset and .vmode & FB_VMODE_YWRAP from what
 544          * was passed in and copy the rest from the old screeninfo.
 545          */
 546         memcpy(&newvar, &fbi->fb.var, sizeof(newvar));
 547         newvar.xoffset = var->xoffset;
 548         newvar.yoffset = var->yoffset;
 549         newvar.vmode &= ~FB_VMODE_YWRAP;
 550         newvar.vmode |= var->vmode & FB_VMODE_YWRAP;
 551
 552         setup_base_frame(fbi, &newvar, 1);
 553
 554         if (fbi->lccr0 & LCCR0_SDS)
 555                 lcd_writel(fbi, FBR1, fbi->fdadr[dma + 1] | 0x1);
 556
 557         lcd_writel(fbi, FBR0, fbi->fdadr[dma] | 0x1);
 558         return 0;
 559 }
 560
 561 /*
 562  * pxafb_blank():
 563  *      Blank the display by setting all palette values to zero.  Note, the
 564  *      16 bpp mode does not really use the palette, so this will not
 565  *      blank the display in all modes.
 566  */
 567 static int pxafb_blank(int blank, struct fb_info *info)
 568 {
 569         struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
 570         int i;
 571
 572         switch (blank) {
 573         case FB_BLANK_POWERDOWN:
 574         case FB_BLANK_VSYNC_SUSPEND:
 575         case FB_BLANK_HSYNC_SUSPEND:
 576         case FB_BLANK_NORMAL:
 577                 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
 578                     fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
 579                         for (i = 0; i < fbi->palette_size; i++)
 580                                 pxafb_setpalettereg(i, 0, 0, 0, 0, info);
 581
 582                 pxafb_schedule_work(fbi, C_DISABLE);
 583                 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
 584                 break;
 585
 586         case FB_BLANK_UNBLANK:
 587                 /* TODO if (pxafb_blank_helper) pxafb_blank_helper(blank); */
 588                 if (fbi->fb.fix.visual == FB_VISUAL_PSEUDOCOLOR ||
 589                     fbi->fb.fix.visual == FB_VISUAL_STATIC_PSEUDOCOLOR)
 590                         fb_set_cmap(&fbi->fb.cmap, info);
 591                 pxafb_schedule_work(fbi, C_ENABLE);
 592         }
 593         return 0;
 594 }
 595
 596 static struct fb_ops pxafb_ops = {
 597         .owner          = THIS_MODULE,
 598         .fb_check_var   = pxafb_check_var,
 599         .fb_set_par     = pxafb_set_par,
 600         .fb_pan_display = pxafb_pan_display,
 601         .fb_setcolreg   = pxafb_setcolreg,
 602         .fb_fillrect    = cfb_fillrect,
 603         .fb_copyarea    = cfb_copyarea,
 604         .fb_imageblit   = cfb_imageblit,
 605         .fb_blank       = pxafb_blank,
 606 };
 607
 608 #ifdef CONFIG_FB_PXA_OVERLAY
 609 static void overlay1fb_setup(struct pxafb_layer *ofb)
 610 {
 611         int size = ofb->fb.fix.line_length * ofb->fb.var.yres_virtual;
 612         unsigned long start = ofb->video_mem_phys;
 613         setup_frame_dma(ofb->fbi, DMA_OV1, PAL_NONE, start, size);
 614 }
 615
 616 /* Depending on the enable status of overlay1/2, the DMA should be
 617  * updated from FDADRx (when disabled) or FBRx (when enabled).
 618  */
 619 static void overlay1fb_enable(struct pxafb_layer *ofb)
 620 {
 621         int enabled = lcd_readl(ofb->fbi, OVL1C1) & OVLxC1_OEN;
 622         uint32_t fdadr1 = ofb->fbi->fdadr[DMA_OV1] | (enabled ? 0x1 : 0);
 623
 624         lcd_writel(ofb->fbi, enabled ? FBR1 : FDADR1, fdadr1);
 625         lcd_writel(ofb->fbi, OVL1C2, ofb->control[1]);
 626         lcd_writel(ofb->fbi, OVL1C1, ofb->control[0] | OVLxC1_OEN);
 627 }
 628
 629 static void overlay1fb_disable(struct pxafb_layer *ofb)
 630 {
 631         uint32_t lccr5;
 632
 633         if (!(lcd_readl(ofb->fbi, OVL1C1) & OVLxC1_OEN))
 634                 return;
 635
 636         lccr5 = lcd_readl(ofb->fbi, LCCR5);
 637
 638         lcd_writel(ofb->fbi, OVL1C1, ofb->control[0] & ~OVLxC1_OEN);
 639
 640         lcd_writel(ofb->fbi, LCSR1, LCSR1_BS(1));
 641         lcd_writel(ofb->fbi, LCCR5, lccr5 & ~LCSR1_BS(1));
 642         lcd_writel(ofb->fbi, FBR1, ofb->fbi->fdadr[DMA_OV1] | 0x3);
 643
 644         if (wait_for_completion_timeout(&ofb->branch_done, 1 * HZ) == 0)
 645                 pr_warning("%s: timeout disabling overlay1\n", __func__);
 646
 647         lcd_writel(ofb->fbi, LCCR5, lccr5);
 648 }
 649
 650 static void overlay2fb_setup(struct pxafb_layer *ofb)
 651 {
 652         int size, div = 1, pfor = NONSTD_TO_PFOR(ofb->fb.var.nonstd);
 653         unsigned long start[3] = { ofb->video_mem_phys, 0, 0 };
 654
 655         if (pfor == OVERLAY_FORMAT_RGB || pfor == OVERLAY_FORMAT_YUV444_PACKED) {
 656                 size = ofb->fb.fix.line_length * ofb->fb.var.yres_virtual;
 657                 setup_frame_dma(ofb->fbi, DMA_OV2_Y, -1, start[0], size);
 658         } else {
 659                 size = ofb->fb.var.xres_virtual * ofb->fb.var.yres_virtual;
 660                 switch (pfor) {
 661                 case OVERLAY_FORMAT_YUV444_PLANAR: div = 1; break;
 662                 case OVERLAY_FORMAT_YUV422_PLANAR: div = 2; break;
 663                 case OVERLAY_FORMAT_YUV420_PLANAR: div = 4; break;
 664                 }
 665                 start[1] = start[0] + size;
 666                 start[2] = start[1] + size / div;
 667                 setup_frame_dma(ofb->fbi, DMA_OV2_Y,  -1, start[0], size);
 668                 setup_frame_dma(ofb->fbi, DMA_OV2_Cb, -1, start[1], size / div);
 669                 setup_frame_dma(ofb->fbi, DMA_OV2_Cr, -1, start[2], size / div);
 670         }
 671 }
 672
 673 static void overlay2fb_enable(struct pxafb_layer *ofb)
 674 {
 675         int pfor = NONSTD_TO_PFOR(ofb->fb.var.nonstd);
 676         int enabled = lcd_readl(ofb->fbi, OVL2C1) & OVLxC1_OEN;
 677         uint32_t fdadr2 = ofb->fbi->fdadr[DMA_OV2_Y]  | (enabled ? 0x1 : 0);
 678         uint32_t fdadr3 = ofb->fbi->fdadr[DMA_OV2_Cb] | (enabled ? 0x1 : 0);
 679         uint32_t fdadr4 = ofb->fbi->fdadr[DMA_OV2_Cr] | (enabled ? 0x1 : 0);
 680
 681         if (pfor == OVERLAY_FORMAT_RGB || pfor == OVERLAY_FORMAT_YUV444_PACKED)
 682                 lcd_writel(ofb->fbi, enabled ? FBR2 : FDADR2, fdadr2);
 683         else {
 684                 lcd_writel(ofb->fbi, enabled ? FBR2 : FDADR2, fdadr2);
 685                 lcd_writel(ofb->fbi, enabled ? FBR3 : FDADR3, fdadr3);
 686                 lcd_writel(ofb->fbi, enabled ? FBR4 : FDADR4, fdadr4);
 687         }
 688         lcd_writel(ofb->fbi, OVL2C2, ofb->control[1]);
 689         lcd_writel(ofb->fbi, OVL2C1, ofb->control[0] | OVLxC1_OEN);
 690 }
 691
 692 static void overlay2fb_disable(struct pxafb_layer *ofb)
 693 {
 694         uint32_t lccr5;
 695
 696         if (!(lcd_readl(ofb->fbi, OVL2C1) & OVLxC1_OEN))
 697                 return;
 698
 699         lccr5 = lcd_readl(ofb->fbi, LCCR5);
 700
 701         lcd_writel(ofb->fbi, OVL2C1, ofb->control[0] & ~OVLxC1_OEN);
 702
 703         lcd_writel(ofb->fbi, LCSR1, LCSR1_BS(2));
 704         lcd_writel(ofb->fbi, LCCR5, lccr5 & ~LCSR1_BS(2));
 705         lcd_writel(ofb->fbi, FBR2, ofb->fbi->fdadr[DMA_OV2_Y]  | 0x3);
 706         lcd_writel(ofb->fbi, FBR3, ofb->fbi->fdadr[DMA_OV2_Cb] | 0x3);
 707         lcd_writel(ofb->fbi, FBR4, ofb->fbi->fdadr[DMA_OV2_Cr] | 0x3);
 708
 709         if (wait_for_completion_timeout(&ofb->branch_done, 1 * HZ) == 0)
 710                 pr_warning("%s: timeout disabling overlay2\n", __func__);
 711 }
 712
 713 static struct pxafb_layer_ops ofb_ops[] = {
 714         [0] = {
 715                 .enable         = overlay1fb_enable,
 716                 .disable        = overlay1fb_disable,
 717                 .setup          = overlay1fb_setup,
 718         },
 719         [1] = {
 720                 .enable         = overlay2fb_enable,
 721                 .disable        = overlay2fb_disable,
 722                 .setup          = overlay2fb_setup,
 723         },
 724 };
 725
 726 static int overlayfb_open(struct fb_info *info, int user)
 727 {
 728         struct pxafb_layer *ofb = container_of(info, struct pxafb_layer, fb);
 729
 730         /* no support for framebuffer console on overlay */
 731         if (user == 0)
 732                 return -ENODEV;
 733
 734         if (ofb->usage++ == 0) {
 735                 /* unblank the base framebuffer */
 736                 console_lock();
 737                 fb_blank(&ofb->fbi->fb, FB_BLANK_UNBLANK);
 738                 console_unlock();
 739         }
 740
 741         return 0;
 742 }
 743
 744 static int overlayfb_release(struct fb_info *info, int user)
 745 {
 746         struct pxafb_layer *ofb = container_of(info, struct pxafb_layer, fb);
 747
 748         if (ofb->usage == 1) {
 749                 ofb->ops->disable(ofb);
 750                 ofb->fb.var.height      = -1;
 751                 ofb->fb.var.width       = -1;
 752                 ofb->fb.var.xres = ofb->fb.var.xres_virtual = 0;
 753                 ofb->fb.var.yres = ofb->fb.var.yres_virtual = 0;
 754
 755                 ofb->usage--;
 756         }
 757         return 0;
 758 }
 759
 760 static int overlayfb_check_var(struct fb_var_screeninfo *var,
 761                                struct fb_info *info)
 762 {
 763         struct pxafb_layer *ofb = container_of(info, struct pxafb_layer, fb);
 764         struct fb_var_screeninfo *base_var = &ofb->fbi->fb.var;
 765         int xpos, ypos, pfor, bpp;
 766
 767         xpos = NONSTD_TO_XPOS(var->nonstd);
 768         ypos = NONSTD_TO_YPOS(var->nonstd);
 769         pfor = NONSTD_TO_PFOR(var->nonstd);
 770
 771         bpp = pxafb_var_to_bpp(var);
 772         if (bpp < 0)
 773                 return -EINVAL;
 774
 775         /* no support for YUV format on overlay1 */
 776         if (ofb->id == OVERLAY1 && pfor != 0)
 777                 return -EINVAL;
 778
 779         /* for YUV packed formats, bpp = 'minimum bpp of YUV components' */
 780         switch (pfor) {
 781         case OVERLAY_FORMAT_RGB:
 782                 bpp = pxafb_var_to_bpp(var);
 783                 if (bpp < 0)
 784                         return -EINVAL;
 785
 786                 pxafb_set_pixfmt(var, var_to_depth(var));
 787                 break;
 788         case OVERLAY_FORMAT_YUV444_PACKED: bpp = 24; break;
 789         case OVERLAY_FORMAT_YUV444_PLANAR: bpp = 8; break;
 790         case OVERLAY_FORMAT_YUV422_PLANAR: bpp = 4; break;
 791         case OVERLAY_FORMAT_YUV420_PLANAR: bpp = 2; break;
 792         default:
 793                 return -EINVAL;
 794         }
 795
 796         /* each line must start at a 32-bit word boundary */
 797         if ((xpos * bpp) % 32)
 798                 return -EINVAL;
 799
 800         /* xres must align on 32-bit word boundary */
 801         var->xres = roundup(var->xres * bpp, 32) / bpp;
 802
 803         if ((xpos + var->xres > base_var->xres) ||
 804             (ypos + var->yres > base_var->yres))
 805                 return -EINVAL;
 806
 807         var->xres_virtual = var->xres;
 808         var->yres_virtual = max(var->yres, var->yres_virtual);
 809         return 0;
 810 }
 811
 812 static int overlayfb_check_video_memory(struct pxafb_layer *ofb)
 813 {
 814         struct fb_var_screeninfo *var = &ofb->fb.var;
 815         int pfor = NONSTD_TO_PFOR(var->nonstd);
 816         int size, bpp = 0;
 817
 818         switch (pfor) {
 819         case OVERLAY_FORMAT_RGB: bpp = var->bits_per_pixel; break;
 820         case OVERLAY_FORMAT_YUV444_PACKED: bpp = 24; break;
 821         case OVERLAY_FORMAT_YUV444_PLANAR: bpp = 24; break;
 822         case OVERLAY_FORMAT_YUV422_PLANAR: bpp = 16; break;
 823         case OVERLAY_FORMAT_YUV420_PLANAR: bpp = 12; break;
 824         }
 825
 826         ofb->fb.fix.line_length = var->xres_virtual * bpp / 8;
 827
 828         size = PAGE_ALIGN(ofb->fb.fix.line_length * var->yres_virtual);
 829
 830         if (ofb->video_mem) {
 831                 if (ofb->video_mem_size >= size)
 832                         return 0;
 833         }
 834         return -EINVAL;
 835 }
 836
 837 static int overlayfb_set_par(struct fb_info *info)
 838 {
 839         struct pxafb_layer *ofb = container_of(info, struct pxafb_layer, fb);
 840         struct fb_var_screeninfo *var = &info->var;
 841         int xpos, ypos, pfor, bpp, ret;
 842
 843         ret = overlayfb_check_video_memory(ofb);
 844         if (ret)
 845                 return ret;
 846
 847         bpp  = pxafb_var_to_bpp(var);
 848         xpos = NONSTD_TO_XPOS(var->nonstd);
 849         ypos = NONSTD_TO_YPOS(var->nonstd);
 850         pfor = NONSTD_TO_PFOR(var->nonstd);
 851
 852         ofb->control[0] = OVLxC1_PPL(var->xres) | OVLxC1_LPO(var->yres) |
 853                           OVLxC1_BPP(bpp);
 854         ofb->control[1] = OVLxC2_XPOS(xpos) | OVLxC2_YPOS(ypos);
 855
 856         if (ofb->id == OVERLAY2)
 857                 ofb->control[1] |= OVL2C2_PFOR(pfor);
 858
 859         ofb->ops->setup(ofb);
 860         ofb->ops->enable(ofb);
 861         return 0;
 862 }
 863
 864 static struct fb_ops overlay_fb_ops = {
 865         .owner                  = THIS_MODULE,
 866         .fb_open                = overlayfb_open,
 867         .fb_release             = overlayfb_release,
 868         .fb_check_var           = overlayfb_check_var,
 869         .fb_set_par             = overlayfb_set_par,
 870 };
 871
 872 static void init_pxafb_overlay(struct pxafb_info *fbi, struct pxafb_layer *ofb,
 873                                int id)
 874 {
 875         sprintf(ofb->fb.fix.id, "overlay%d", id + 1);
 876
 877         ofb->fb.fix.type                = FB_TYPE_PACKED_PIXELS;
 878         ofb->fb.fix.xpanstep            = 0;
 879         ofb->fb.fix.ypanstep            = 1;
 880
 881         ofb->fb.var.activate            = FB_ACTIVATE_NOW;
 882         ofb->fb.var.height              = -1;
 883         ofb->fb.var.width               = -1;
 884         ofb->fb.var.vmode               = FB_VMODE_NONINTERLACED;
 885
 886         ofb->fb.fbops                   = &overlay_fb_ops;
 887         ofb->fb.flags                   = FBINFO_FLAG_DEFAULT;
 888         ofb->fb.node                    = -1;
 889         ofb->fb.pseudo_palette          = NULL;
 890
 891         ofb->id = id;
 892         ofb->ops = &ofb_ops[id];
 893         ofb->usage = 0;
 894         ofb->fbi = fbi;
 895         init_completion(&ofb->branch_done);
 896 }
 897
 898 static inline int pxafb_overlay_supported(void)
 899 {
 900         if (cpu_is_pxa27x() || cpu_is_pxa3xx())
 901                 return 1;
 902
 903         return 0;
 904 }
 905
 906 static int pxafb_overlay_map_video_memory(struct pxafb_info *pxafb,
 907                                           struct pxafb_layer *ofb)
 908 {
 909         /* We assume that user will use at most video_mem_size for overlay fb,
 910          * anyway, it's useless to use 16bpp main plane and 24bpp overlay
 911          */
 912         ofb->video_mem = alloc_pages_exact(PAGE_ALIGN(pxafb->video_mem_size),
 913                 GFP_KERNEL | __GFP_ZERO);
 914         if (ofb->video_mem == NULL)
 915                 return -ENOMEM;
 916
 917         ofb->video_mem_phys = virt_to_phys(ofb->video_mem);
 918         ofb->video_mem_size = PAGE_ALIGN(pxafb->video_mem_size);
 919
 920         mutex_lock(&ofb->fb.mm_lock);
 921         ofb->fb.fix.smem_start  = ofb->video_mem_phys;
 922         ofb->fb.fix.smem_len    = pxafb->video_mem_size;
 923         mutex_unlock(&ofb->fb.mm_lock);
 924
 925         ofb->fb.screen_base     = ofb->video_mem;
 926
 927         return 0;
 928 }
 929
 930 static void pxafb_overlay_init(struct pxafb_info *fbi)
 931 {
 932         int i, ret;
 933
 934         if (!pxafb_overlay_supported())
 935                 return;
 936
 937         for (i = 0; i < 2; i++) {
 938                 struct pxafb_layer *ofb = &fbi->overlay[i];
 939                 init_pxafb_overlay(fbi, ofb, i);
 940                 ret = register_framebuffer(&ofb->fb);
 941                 if (ret) {
 942                         dev_err(fbi->dev, "failed to register overlay %d\n", i);
 943                         continue;
 944                 }
 945                 ret = pxafb_overlay_map_video_memory(fbi, ofb);
 946                 if (ret) {
 947                         dev_err(fbi->dev,
 948                                 "failed to map video memory for overlay %d\n",
 949                                 i);
 950                         unregister_framebuffer(&ofb->fb);
 951                         continue;
 952                 }
 953                 ofb->registered = 1;
 954         }
 955
 956         /* mask all IU/BS/EOF/SOF interrupts */
 957         lcd_writel(fbi, LCCR5, ~0);
 958
 959         pr_info("PXA Overlay driver loaded successfully!\n");
 960 }
 961
 962 static void pxafb_overlay_exit(struct pxafb_info *fbi)
 963 {
 964         int i;
 965
 966         if (!pxafb_overlay_supported())
 967                 return;
 968
 969         for (i = 0; i < 2; i++) {
 970                 struct pxafb_layer *ofb = &fbi->overlay[i];
 971                 if (ofb->registered) {
 972                         if (ofb->video_mem)
 973                                 free_pages_exact(ofb->video_mem,
 974                                         ofb->video_mem_size);
 975                         unregister_framebuffer(&ofb->fb);
 976                 }
 977         }
 978 }
 979 #else
 980 static inline void pxafb_overlay_init(struct pxafb_info *fbi) {}
 981 static inline void pxafb_overlay_exit(struct pxafb_info *fbi) {}
 982 #endif /* CONFIG_FB_PXA_OVERLAY */
 983
 984 /*
 985  * Calculate the PCD value from the clock rate (in picoseconds).
 986  * We take account of the PPCR clock setting.
 987  * From PXA Developer's Manual:
 988  *
 989  *   PixelClock =      LCLK
 990  *                -------------
 991  *                2 ( PCD + 1 )
 992  *
 993  *   PCD =      LCLK
 994  *         ------------- - 1
 995  *         2(PixelClock)
 996  *
 997  * Where:
 998  *   LCLK = LCD/Memory Clock
 999  *   PCD = LCCR3[7:0]
1000  *
1001  * PixelClock here is in Hz while the pixclock argument given is the
1002  * period in picoseconds. Hence PixelClock = 1 / ( pixclock * 10^-12 )
1003  *
1004  * The function get_lclk_frequency_10khz returns LCLK in units of
1005  * 10khz. Calling the result of this function lclk gives us the
1006  * following
1007  *
1008  *    PCD = (lclk * 10^4 ) * ( pixclock * 10^-12 )
1009  *          -------------------------------------- - 1
1010  *                          2
1011  *
1012  * Factoring the 10^4 and 10^-12 out gives 10^-8 == 1 / 100000000 as used below.
1013  */
1014 static inline unsigned int get_pcd(struct pxafb_info *fbi,
1015                                    unsigned int pixclock)
1016 {
1017         unsigned long long pcd;
1018
1019         /* FIXME: Need to take into account Double Pixel Clock mode
1020          * (DPC) bit? or perhaps set it based on the various clock
1021          * speeds */
1022         pcd = (unsigned long long)(clk_get_rate(fbi->clk) / 10000);
1023         pcd *= pixclock;
1024         do_div(pcd, 100000000 * 2);
1025         /* no need for this, since we should subtract 1 anyway. they cancel */
1026         /* pcd += 1; */ /* make up for integer math truncations */
1027         return (unsigned int)pcd;
1028 }
1029
1030 /*
1031  * Some touchscreens need hsync information from the video driver to
1032  * function correctly. We export it here.  Note that 'hsync_time' and
1033  * the value returned from pxafb_get_hsync_time() is the *reciprocal*
1034  * of the hsync period in seconds.
1035  */
1036 static inline void set_hsync_time(struct pxafb_info *fbi, unsigned int pcd)
1037 {
1038         unsigned long htime;
1039
1040         if ((pcd == 0) || (fbi->fb.var.hsync_len == 0)) {
1041                 fbi->hsync_time = 0;
1042                 return;
1043         }
1044
1045         htime = clk_get_rate(fbi->clk) / (pcd * fbi->fb.var.hsync_len);
1046
1047         fbi->hsync_time = htime;
1048 }
1049
1050 unsigned long pxafb_get_hsync_time(struct device *dev)
1051 {
1052         struct pxafb_info *fbi = dev_get_drvdata(dev);
1053
1054         /* If display is blanked/suspended, hsync isn't active */
1055         if (!fbi || (fbi->state != C_ENABLE))
1056                 return 0;
1057
1058         return fbi->hsync_time;
1059 }
1060 EXPORT_SYMBOL(pxafb_get_hsync_time);
1061
1062 static int setup_frame_dma(struct pxafb_info *fbi, int dma, int pal,
1063                            unsigned long start, size_t size)
1064 {
1065         struct pxafb_dma_descriptor *dma_desc, *pal_desc;
1066         unsigned int dma_desc_off, pal_desc_off;
1067
1068         if (dma < 0 || dma >= DMA_MAX * 2)
1069                 return -EINVAL;
1070
1071         dma_desc = &fbi->dma_buff->dma_desc[dma];
1072         dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[dma]);
1073
1074         dma_desc->fsadr = start;
1075         dma_desc->fidr  = 0;
1076         dma_desc->ldcmd = size;
1077
1078         if (pal < 0 || pal >= PAL_MAX * 2) {
1079                 dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
1080                 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
1081         } else {
1082                 pal_desc = &fbi->dma_buff->pal_desc[pal];
1083                 pal_desc_off = offsetof(struct pxafb_dma_buff, pal_desc[pal]);
1084
1085                 pal_desc->fsadr = fbi->dma_buff_phys + pal * PALETTE_SIZE;
1086                 pal_desc->fidr  = 0;
1087
1088                 if ((fbi->lccr4 & LCCR4_PAL_FOR_MASK) == LCCR4_PAL_FOR_0)
1089                         pal_desc->ldcmd = fbi->palette_size * sizeof(u16);
1090                 else
1091                         pal_desc->ldcmd = fbi->palette_size * sizeof(u32);
1092
1093                 pal_desc->ldcmd |= LDCMD_PAL;
1094
1095                 /* flip back and forth between palette and frame buffer */
1096                 pal_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
1097                 dma_desc->fdadr = fbi->dma_buff_phys + pal_desc_off;
1098                 fbi->fdadr[dma] = fbi->dma_buff_phys + dma_desc_off;
1099         }
1100
1101         return 0;
1102 }
1103
1104 static void setup_base_frame(struct pxafb_info *fbi,
1105                              struct fb_var_screeninfo *var,
1106                              int branch)
1107 {
1108         struct fb_fix_screeninfo *fix = &fbi->fb.fix;
1109         int nbytes, dma, pal, bpp = var->bits_per_pixel;
1110         unsigned long offset;
1111
1112         dma = DMA_BASE + (branch ? DMA_MAX : 0);
1113         pal = (bpp >= 16) ? PAL_NONE : PAL_BASE + (branch ? PAL_MAX : 0);
1114
1115         nbytes = fix->line_length * var->yres;
1116         offset = fix->line_length * var->yoffset + fbi->video_mem_phys;
1117
1118         if (fbi->lccr0 & LCCR0_SDS) {
1119                 nbytes = nbytes / 2;
1120                 setup_frame_dma(fbi, dma + 1, PAL_NONE, offset + nbytes, nbytes);
1121         }
1122
1123         setup_frame_dma(fbi, dma, pal, offset, nbytes);
1124 }
1125
1126 #ifdef CONFIG_FB_PXA_SMARTPANEL
1127 static int setup_smart_dma(struct pxafb_info *fbi)
1128 {
1129         struct pxafb_dma_descriptor *dma_desc;
1130         unsigned long dma_desc_off, cmd_buff_off;
1131
1132         dma_desc = &fbi->dma_buff->dma_desc[DMA_CMD];
1133         dma_desc_off = offsetof(struct pxafb_dma_buff, dma_desc[DMA_CMD]);
1134         cmd_buff_off = offsetof(struct pxafb_dma_buff, cmd_buff);
1135
1136         dma_desc->fdadr = fbi->dma_buff_phys + dma_desc_off;
1137         dma_desc->fsadr = fbi->dma_buff_phys + cmd_buff_off;
1138         dma_desc->fidr  = 0;
1139         dma_desc->ldcmd = fbi->n_smart_cmds * sizeof(uint16_t);
1140
1141         fbi->fdadr[DMA_CMD] = dma_desc->fdadr;
1142         return 0;
1143 }
1144
1145 int pxafb_smart_flush(struct fb_info *info)
1146 {
1147         struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
1148         uint32_t prsr;
1149         int ret = 0;
1150
1151         /* disable controller until all registers are set up */
1152         lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
1153
1154         /* 1. make it an even number of commands to align on 32-bit boundary
1155          * 2. add the interrupt command to the end of the chain so we can
1156          *    keep track of the end of the transfer
1157          */
1158
1159         while (fbi->n_smart_cmds & 1)
1160                 fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_NOOP;
1161
1162         fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_INTERRUPT;
1163         fbi->smart_cmds[fbi->n_smart_cmds++] = SMART_CMD_WAIT_FOR_VSYNC;
1164         setup_smart_dma(fbi);
1165
1166         /* continue to execute next command */
1167         prsr = lcd_readl(fbi, PRSR) | PRSR_ST_OK | PRSR_CON_NT;
1168         lcd_writel(fbi, PRSR, prsr);
1169
1170         /* stop the processor in case it executed "wait for sync" cmd */
1171         lcd_writel(fbi, CMDCR, 0x0001);
1172
1173         /* don't send interrupts for fifo underruns on channel 6 */
1174         lcd_writel(fbi, LCCR5, LCCR5_IUM(6));
1175
1176         lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
1177         lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
1178         lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
1179         lcd_writel(fbi, LCCR4, fbi->reg_lccr4);
1180         lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
1181         lcd_writel(fbi, FDADR6, fbi->fdadr[6]);
1182
1183         /* begin sending */
1184         lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
1185
1186         if (wait_for_completion_timeout(&fbi->command_done, HZ/2) == 0) {
1187                 pr_warning("%s: timeout waiting for command done\n",
1188                                 __func__);
1189                 ret = -ETIMEDOUT;
1190         }
1191
1192         /* quick disable */
1193         prsr = lcd_readl(fbi, PRSR) & ~(PRSR_ST_OK | PRSR_CON_NT);
1194         lcd_writel(fbi, PRSR, prsr);
1195         lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
1196         lcd_writel(fbi, FDADR6, 0);
1197         fbi->n_smart_cmds = 0;
1198         return ret;
1199 }
1200
1201 int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int n_cmds)
1202 {
1203         int i;
1204         struct pxafb_info *fbi = container_of(info, struct pxafb_info, fb);
1205
1206         for (i = 0; i < n_cmds; i++, cmds++) {
1207                 /* if it is a software delay, flush and delay */
1208                 if ((*cmds & 0xff00) == SMART_CMD_DELAY) {
1209                         pxafb_smart_flush(info);
1210                         mdelay(*cmds & 0xff);
1211                         continue;
1212                 }
1213
1214                 /* leave 2 commands for INTERRUPT and WAIT_FOR_SYNC */
1215                 if (fbi->n_smart_cmds == CMD_BUFF_SIZE - 8)
1216                         pxafb_smart_flush(info);
1217
1218                 fbi->smart_cmds[fbi->n_smart_cmds++] = *cmds;
1219         }
1220
1221         return 0;
1222 }
1223
1224 static unsigned int __smart_timing(unsigned time_ns, unsigned long lcd_clk)
1225 {
1226         unsigned int t = (time_ns * (lcd_clk / 1000000) / 1000);
1227         return (t == 0) ? 1 : t;
1228 }
1229
1230 static void setup_smart_timing(struct pxafb_info *fbi,
1231                                 struct fb_var_screeninfo *var)
1232 {
1233         struct pxafb_mach_info *inf = dev_get_platdata(fbi->dev);
1234         struct pxafb_mode_info *mode = &inf->modes[0];
1235         unsigned long lclk = clk_get_rate(fbi->clk);
1236         unsigned t1, t2, t3, t4;
1237
1238         t1 = max(mode->a0csrd_set_hld, mode->a0cswr_set_hld);
1239         t2 = max(mode->rd_pulse_width, mode->wr_pulse_width);
1240         t3 = mode->op_hold_time;
1241         t4 = mode->cmd_inh_time;
1242
1243         fbi->reg_lccr1 =
1244                 LCCR1_DisWdth(var->xres) |
1245                 LCCR1_BegLnDel(__smart_timing(t1, lclk)) |
1246                 LCCR1_EndLnDel(__smart_timing(t2, lclk)) |
1247                 LCCR1_HorSnchWdth(__smart_timing(t3, lclk));
1248
1249         fbi->reg_lccr2 = LCCR2_DisHght(var->yres);
1250         fbi->reg_lccr3 = fbi->lccr3 | LCCR3_PixClkDiv(__smart_timing(t4, lclk));
1251         fbi->reg_lccr3 |= (var->sync & FB_SYNC_HOR_HIGH_ACT) ? LCCR3_HSP : 0;
1252         fbi->reg_lccr3 |= (var->sync & FB_SYNC_VERT_HIGH_ACT) ? LCCR3_VSP : 0;
1253
1254         /* FIXME: make this configurable */
1255         fbi->reg_cmdcr = 1;
1256 }
1257
1258 static int pxafb_smart_thread(void *arg)
1259 {
1260         struct pxafb_info *fbi = arg;
1261         struct pxafb_mach_info *inf = dev_get_platdata(fbi->dev);
1262
1263         if (!inf->smart_update) {
1264                 pr_err("%s: not properly initialized, thread terminated\n",
1265                                 __func__);
1266                 return -EINVAL;
1267         }
1268         inf = dev_get_platdata(fbi->dev);
1269
1270         pr_debug("%s(): task starting\n", __func__);
1271
1272         set_freezable();
1273         while (!kthread_should_stop()) {
1274
1275                 if (try_to_freeze())
1276                         continue;
1277
1278                 mutex_lock(&fbi->ctrlr_lock);
1279
1280                 if (fbi->state == C_ENABLE) {
1281                         inf->smart_update(&fbi->fb);
1282                         complete(&fbi->refresh_done);
1283                 }
1284
1285                 mutex_unlock(&fbi->ctrlr_lock);
1286
1287                 set_current_state(TASK_INTERRUPTIBLE);
1288                 schedule_timeout(30 * HZ / 1000);
1289         }
1290
1291         pr_debug("%s(): task ending\n", __func__);
1292         return 0;
1293 }
1294
1295 static int pxafb_smart_init(struct pxafb_info *fbi)
1296 {
1297         if (!(fbi->lccr0 & LCCR0_LCDT))
1298                 return 0;
1299
1300         fbi->smart_cmds = (uint16_t *) fbi->dma_buff->cmd_buff;
1301         fbi->n_smart_cmds = 0;
1302
1303         init_completion(&fbi->command_done);
1304         init_completion(&fbi->refresh_done);
1305
1306         fbi->smart_thread = kthread_run(pxafb_smart_thread, fbi,
1307                                         "lcd_refresh");
1308         if (IS_ERR(fbi->smart_thread)) {
1309                 pr_err("%s: unable to create kernel thread\n", __func__);
1310                 return PTR_ERR(fbi->smart_thread);
1311         }
1312
1313         return 0;
1314 }
1315 #else
1316 static inline int pxafb_smart_init(struct pxafb_info *fbi) { return 0; }
1317 #endif /* CONFIG_FB_PXA_SMARTPANEL */
1318
1319 static void setup_parallel_timing(struct pxafb_info *fbi,
1320                                   struct fb_var_screeninfo *var)
1321 {
1322         unsigned int lines_per_panel, pcd = get_pcd(fbi, var->pixclock);
1323
1324         fbi->reg_lccr1 =
1325                 LCCR1_DisWdth(var->xres) +
1326                 LCCR1_HorSnchWdth(var->hsync_len) +
1327                 LCCR1_BegLnDel(var->left_margin) +
1328                 LCCR1_EndLnDel(var->right_margin);
1329
1330         /*
1331          * If we have a dual scan LCD, we need to halve
1332          * the YRES parameter.
1333          */
1334         lines_per_panel = var->yres;
1335         if ((fbi->lccr0 & LCCR0_SDS) == LCCR0_Dual)
1336                 lines_per_panel /= 2;
1337
1338         fbi->reg_lccr2 =
1339                 LCCR2_DisHght(lines_per_panel) +
1340                 LCCR2_VrtSnchWdth(var->vsync_len) +
1341                 LCCR2_BegFrmDel(var->upper_margin) +
1342                 LCCR2_EndFrmDel(var->lower_margin);
1343
1344         fbi->reg_lccr3 = fbi->lccr3 |
1345                 (var->sync & FB_SYNC_HOR_HIGH_ACT ?
1346                  LCCR3_HorSnchH : LCCR3_HorSnchL) |
1347                 (var->sync & FB_SYNC_VERT_HIGH_ACT ?
1348                  LCCR3_VrtSnchH : LCCR3_VrtSnchL);
1349
1350         if (pcd) {
1351                 fbi->reg_lccr3 |= LCCR3_PixClkDiv(pcd);
1352                 set_hsync_time(fbi, pcd);
1353         }
1354 }
1355
1356 /*
1357  * pxafb_activate_var():
1358  *      Configures LCD Controller based on entries in var parameter.
1359  *      Settings are only written to the controller if changes were made.
1360  */
1361 static int pxafb_activate_var(struct fb_var_screeninfo *var,
1362                               struct pxafb_info *fbi)
1363 {
1364         u_long flags;
1365
1366         /* Update shadow copy atomically */
1367         local_irq_save(flags);
1368
1369 #ifdef CONFIG_FB_PXA_SMARTPANEL
1370         if (fbi->lccr0 & LCCR0_LCDT)
1371                 setup_smart_timing(fbi, var);
1372         else
1373 #endif
1374                 setup_parallel_timing(fbi, var);
1375
1376         setup_base_frame(fbi, var, 0);
1377
1378         fbi->reg_lccr0 = fbi->lccr0 |
1379                 (LCCR0_LDM | LCCR0_SFM | LCCR0_IUM | LCCR0_EFM |
1380                  LCCR0_QDM | LCCR0_BM  | LCCR0_OUM);
1381
1382         fbi->reg_lccr3 |= pxafb_var_to_lccr3(var);
1383
1384         fbi->reg_lccr4 = lcd_readl(fbi, LCCR4) & ~LCCR4_PAL_FOR_MASK;
1385         fbi->reg_lccr4 |= (fbi->lccr4 & LCCR4_PAL_FOR_MASK);
1386         local_irq_restore(flags);
1387
1388         /*
1389          * Only update the registers if the controller is enabled
1390          * and something has changed.
1391          */
1392         if ((lcd_readl(fbi, LCCR0) != fbi->reg_lccr0) ||
1393             (lcd_readl(fbi, LCCR1) != fbi->reg_lccr1) ||
1394             (lcd_readl(fbi, LCCR2) != fbi->reg_lccr2) ||
1395             (lcd_readl(fbi, LCCR3) != fbi->reg_lccr3) ||
1396             (lcd_readl(fbi, LCCR4) != fbi->reg_lccr4) ||
1397             (lcd_readl(fbi, FDADR0) != fbi->fdadr[0]) ||
1398             ((fbi->lccr0 & LCCR0_SDS) &&
1399             (lcd_readl(fbi, FDADR1) != fbi->fdadr[1])))
1400                 pxafb_schedule_work(fbi, C_REENABLE);
1401
1402         return 0;
1403 }
1404
1405 /*
1406  * NOTE!  The following functions are purely helpers for set_ctrlr_state.
1407  * Do not call them directly; set_ctrlr_state does the correct serialisation
1408  * to ensure that things happen in the right way 100% of time time.
1409  *      -- rmk
1410  */
1411 static inline void __pxafb_backlight_power(struct pxafb_info *fbi, int on)
1412 {
1413         pr_debug("pxafb: backlight o%s\n", on ? "n" : "ff");
1414
1415         if (fbi->backlight_power)
1416                 fbi->backlight_power(on);
1417 }
1418
1419 static inline void __pxafb_lcd_power(struct pxafb_info *fbi, int on)
1420 {
1421         pr_debug("pxafb: LCD power o%s\n", on ? "n" : "ff");
1422
1423         if (fbi->lcd_power)
1424                 fbi->lcd_power(on, &fbi->fb.var);
1425 }
1426
1427 static void pxafb_enable_controller(struct pxafb_info *fbi)
1428 {
1429         pr_debug("pxafb: Enabling LCD controller\n");
1430         pr_debug("fdadr0 0x%08x\n", (unsigned int) fbi->fdadr[0]);
1431         pr_debug("fdadr1 0x%08x\n", (unsigned int) fbi->fdadr[1]);
1432         pr_debug("reg_lccr0 0x%08x\n", (unsigned int) fbi->reg_lccr0);
1433         pr_debug("reg_lccr1 0x%08x\n", (unsigned int) fbi->reg_lccr1);
1434         pr_debug("reg_lccr2 0x%08x\n", (unsigned int) fbi->reg_lccr2);
1435         pr_debug("reg_lccr3 0x%08x\n", (unsigned int) fbi->reg_lccr3);
1436
1437         /* enable LCD controller clock */
1438         clk_prepare_enable(fbi->clk);
1439
1440         if (fbi->lccr0 & LCCR0_LCDT)
1441                 return;
1442
1443         /* Sequence from 11.7.10 */
1444         lcd_writel(fbi, LCCR4, fbi->reg_lccr4);
1445         lcd_writel(fbi, LCCR3, fbi->reg_lccr3);
1446         lcd_writel(fbi, LCCR2, fbi->reg_lccr2);
1447         lcd_writel(fbi, LCCR1, fbi->reg_lccr1);
1448         lcd_writel(fbi, LCCR0, fbi->reg_lccr0 & ~LCCR0_ENB);
1449
1450         lcd_writel(fbi, FDADR0, fbi->fdadr[0]);
1451         if (fbi->lccr0 & LCCR0_SDS)
1452                 lcd_writel(fbi, FDADR1, fbi->fdadr[1]);
1453         lcd_writel(fbi, LCCR0, fbi->reg_lccr0 | LCCR0_ENB);
1454 }
1455
1456 static void pxafb_disable_controller(struct pxafb_info *fbi)
1457 {
1458         uint32_t lccr0;
1459
1460 #ifdef CONFIG_FB_PXA_SMARTPANEL
1461         if (fbi->lccr0 & LCCR0_LCDT) {
1462                 wait_for_completion_timeout(&fbi->refresh_done,
1463                                 200 * HZ / 1000);
1464                 return;
1465         }
1466 #endif
1467
1468         /* Clear LCD Status Register */
1469         lcd_writel(fbi, LCSR, 0xffffffff);
1470
1471         lccr0 = lcd_readl(fbi, LCCR0) & ~LCCR0_LDM;
1472         lcd_writel(fbi, LCCR0, lccr0);
1473         lcd_writel(fbi, LCCR0, lccr0 | LCCR0_DIS);
1474
1475         wait_for_completion_timeout(&fbi->disable_done, 200 * HZ / 1000);
1476
1477         /* disable LCD controller clock */
1478         clk_disable_unprepare(fbi->clk);
1479 }
1480
1481 /*
1482  *  pxafb_handle_irq: Handle 'LCD DONE' interrupts.
1483  */
1484 static irqreturn_t pxafb_handle_irq(int irq, void *dev_id)
1485 {
1486         struct pxafb_info *fbi = dev_id;
1487         unsigned int lccr0, lcsr;
1488
1489         lcsr = lcd_readl(fbi, LCSR);
1490         if (lcsr & LCSR_LDD) {
1491                 lccr0 = lcd_readl(fbi, LCCR0);
1492                 lcd_writel(fbi, LCCR0, lccr0 | LCCR0_LDM);
1493                 complete(&fbi->disable_done);
1494         }
1495
1496 #ifdef CONFIG_FB_PXA_SMARTPANEL
1497         if (lcsr & LCSR_CMD_INT)
1498                 complete(&fbi->command_done);
1499 #endif
1500         lcd_writel(fbi, LCSR, lcsr);
1501
1502 #ifdef CONFIG_FB_PXA_OVERLAY
1503         {
1504                 unsigned int lcsr1 = lcd_readl(fbi, LCSR1);
1505                 if (lcsr1 & LCSR1_BS(1))
1506                         complete(&fbi->overlay[0].branch_done);
1507
1508                 if (lcsr1 & LCSR1_BS(2))
1509                         complete(&fbi->overlay[1].branch_done);
1510
1511                 lcd_writel(fbi, LCSR1, lcsr1);
1512         }
1513 #endif
1514         return IRQ_HANDLED;
1515 }
1516
1517 /*
1518  * This function must be called from task context only, since it will
1519  * sleep when disabling the LCD controller, or if we get two contending
1520  * processes trying to alter state.
1521  */
1522 static void set_ctrlr_state(struct pxafb_info *fbi, u_int state)
1523 {
1524         u_int old_state;
1525
1526         mutex_lock(&fbi->ctrlr_lock);
1527
1528         old_state = fbi->state;
1529
1530         /*
1531          * Hack around fbcon initialisation.
1532          */
1533         if (old_state == C_STARTUP && state == C_REENABLE)
1534                 state = C_ENABLE;
1535
1536         switch (state) {
1537         case C_DISABLE_CLKCHANGE:
1538                 /*
1539                  * Disable controller for clock change.  If the
1540                  * controller is already disabled, then do nothing.
1541                  */
1542                 if (old_state != C_DISABLE && old_state != C_DISABLE_PM) {
1543                         fbi->state = state;
1544                         /* TODO __pxafb_lcd_power(fbi, 0); */
1545                         pxafb_disable_controller(fbi);
1546                 }
1547                 break;
1548
1549         case C_DISABLE_PM:
1550         case C_DISABLE:
1551                 /*
1552                  * Disable controller
1553                  */
1554                 if (old_state != C_DISABLE) {
1555                         fbi->state = state;
1556                         __pxafb_backlight_power(fbi, 0);
1557                         __pxafb_lcd_power(fbi, 0);
1558                         if (old_state != C_DISABLE_CLKCHANGE)
1559                                 pxafb_disable_controller(fbi);
1560                 }
1561                 break;
1562
1563         case C_ENABLE_CLKCHANGE:
1564                 /*
1565                  * Enable the controller after clock change.  Only
1566                  * do this if we were disabled for the clock change.
1567                  */
1568                 if (old_state == C_DISABLE_CLKCHANGE) {
1569                         fbi->state = C_ENABLE;
1570                         pxafb_enable_controller(fbi);
1571                         /* TODO __pxafb_lcd_power(fbi, 1); */
1572                 }
1573                 break;
1574
1575         case C_REENABLE:
1576                 /*
1577                  * Re-enable the controller only if it was already
1578                  * enabled.  This is so we reprogram the control
1579                  * registers.
1580                  */
1581                 if (old_state == C_ENABLE) {
1582                         __pxafb_lcd_power(fbi, 0);
1583                         pxafb_disable_controller(fbi);
1584                         pxafb_enable_controller(fbi);
1585                         __pxafb_lcd_power(fbi, 1);
1586                 }
1587                 break;
1588
1589         case C_ENABLE_PM:
1590                 /*
1591                  * Re-enable the controller after PM.  This is not
1592                  * perfect - think about the case where we were doing
1593                  * a clock change, and we suspended half-way through.
1594                  */
1595                 if (old_state != C_DISABLE_PM)
1596                         break;
1597                 /* fall through */
1598
1599         case C_ENABLE:
1600                 /*
1601                  * Power up the LCD screen, enable controller, and
1602                  * turn on the backlight.
1603                  */
1604                 if (old_state != C_ENABLE) {
1605                         fbi->state = C_ENABLE;
1606                         pxafb_enable_controller(fbi);
1607                         __pxafb_lcd_power(fbi, 1);
1608                         __pxafb_backlight_power(fbi, 1);
1609                 }
1610                 break;
1611         }
1612         mutex_unlock(&fbi->ctrlr_lock);
1613 }
1614
1615 /*
1616  * Our LCD controller task (which is called when we blank or unblank)
1617  * via keventd.
1618  */
1619 static void pxafb_task(struct work_struct *work)
1620 {
1621         struct pxafb_info *fbi =
1622                 container_of(work, struct pxafb_info, task);
1623         u_int state = xchg(&fbi->task_state, -1);
1624
1625         set_ctrlr_state(fbi, state);
1626 }
1627
1628 #ifdef CONFIG_CPU_FREQ
1629 /*
1630  * CPU clock speed change handler.  We need to adjust the LCD timing
1631  * parameters when the CPU clock is adjusted by the power management
1632  * subsystem.
1633  *
1634  * TODO: Determine why f->new != 10*get_lclk_frequency_10khz()
1635  */
1636 static int
1637 pxafb_freq_transition(struct notifier_block *nb, unsigned long val, void *data)
1638 {
1639         struct pxafb_info *fbi = TO_INF(nb, freq_transition);
1640         /* TODO struct cpufreq_freqs *f = data; */
1641         u_int pcd;
1642
1643         switch (val) {
1644         case CPUFREQ_PRECHANGE:
1645 #ifdef CONFIG_FB_PXA_OVERLAY
1646                 if (!(fbi->overlay[0].usage || fbi->overlay[1].usage))
1647 #endif
1648                         set_ctrlr_state(fbi, C_DISABLE_CLKCHANGE);
1649                 break;
1650
1651         case CPUFREQ_POSTCHANGE:
1652                 pcd = get_pcd(fbi, fbi->fb.var.pixclock);
1653                 set_hsync_time(fbi, pcd);
1654                 fbi->reg_lccr3 = (fbi->reg_lccr3 & ~0xff) |
1655                                   LCCR3_PixClkDiv(pcd);
1656                 set_ctrlr_state(fbi, C_ENABLE_CLKCHANGE);
1657                 break;
1658         }
1659         return 0;
1660 }
1661
1662 static int
1663 pxafb_freq_policy(struct notifier_block *nb, unsigned long val, void *data)
1664 {
1665         struct pxafb_info *fbi = TO_INF(nb, freq_policy);
1666         struct fb_var_screeninfo *var = &fbi->fb.var;
1667         struct cpufreq_policy *policy = data;
1668
1669         switch (val) {
1670         case CPUFREQ_ADJUST:
1671         case CPUFREQ_INCOMPATIBLE:
1672                 pr_debug("min dma period: %d ps, "
1673                         "new clock %d kHz\n", pxafb_display_dma_period(var),
1674                         policy->max);
1675                 /* TODO: fill in min/max values */
1676                 break;
1677         }
1678         return 0;
1679 }
1680 #endif
1681
1682 #ifdef CONFIG_PM
1683 /*
1684  * Power management hooks.  Note that we won't be called from IRQ context,
1685  * unlike the blank functions above, so we may sleep.
1686  */
1687 static int pxafb_suspend(struct device *dev)
1688 {
1689         struct pxafb_info *fbi = dev_get_drvdata(dev);
1690
1691         set_ctrlr_state(fbi, C_DISABLE_PM);
1692         return 0;
1693 }
1694
1695 static int pxafb_resume(struct device *dev)
1696 {
1697         struct pxafb_info *fbi = dev_get_drvdata(dev);
1698
1699         set_ctrlr_state(fbi, C_ENABLE_PM);
1700         return 0;
1701 }
1702
1703 static const struct dev_pm_ops pxafb_pm_ops = {
1704         .suspend        = pxafb_suspend,
1705         .resume         = pxafb_resume,
1706 };
1707 #endif
1708
1709 static int pxafb_init_video_memory(struct pxafb_info *fbi)
1710 {
1711         int size = PAGE_ALIGN(fbi->video_mem_size);
1712
1713         fbi->video_mem = alloc_pages_exact(size, GFP_KERNEL | __GFP_ZERO);
1714         if (fbi->video_mem == NULL)
1715                 return -ENOMEM;
1716
1717         fbi->video_mem_phys = virt_to_phys(fbi->video_mem);
1718         fbi->video_mem_size = size;
1719
1720         fbi->fb.fix.smem_start  = fbi->video_mem_phys;
1721         fbi->fb.fix.smem_len    = fbi->video_mem_size;
1722         fbi->fb.screen_base     = fbi->video_mem;
1723
1724         return fbi->video_mem ? 0 : -ENOMEM;
1725 }
1726
1727 static void pxafb_decode_mach_info(struct pxafb_info *fbi,
1728                                    struct pxafb_mach_info *inf)
1729 {
1730         unsigned int lcd_conn = inf->lcd_conn;
1731         struct pxafb_mode_info *m;
1732         int i;
1733
1734         fbi->cmap_inverse       = inf->cmap_inverse;
1735         fbi->cmap_static        = inf->cmap_static;
1736         fbi->lccr4              = inf->lccr4;
1737
1738         switch (lcd_conn & LCD_TYPE_MASK) {
1739         case LCD_TYPE_MONO_STN:
1740                 fbi->lccr0 = LCCR0_CMS;
1741                 break;
1742         case LCD_TYPE_MONO_DSTN:
1743                 fbi->lccr0 = LCCR0_CMS | LCCR0_SDS;
1744                 break;
1745         case LCD_TYPE_COLOR_STN:
1746                 fbi->lccr0 = 0;
1747                 break;
1748         case LCD_TYPE_COLOR_DSTN:
1749                 fbi->lccr0 = LCCR0_SDS;
1750                 break;
1751         case LCD_TYPE_COLOR_TFT:
1752                 fbi->lccr0 = LCCR0_PAS;
1753                 break;
1754         case LCD_TYPE_SMART_PANEL:
1755                 fbi->lccr0 = LCCR0_LCDT | LCCR0_PAS;
1756                 break;
1757         default:
1758                 /* fall back to backward compatibility way */
1759                 fbi->lccr0 = inf->lccr0;
1760                 fbi->lccr3 = inf->lccr3;
1761                 goto decode_mode;
1762         }
1763
1764         if (lcd_conn == LCD_MONO_STN_8BPP)
1765                 fbi->lccr0 |= LCCR0_DPD;
1766
1767         fbi->lccr0 |= (lcd_conn & LCD_ALTERNATE_MAPPING) ? LCCR0_LDDALT : 0;
1768
1769         fbi->lccr3 = LCCR3_Acb((inf->lcd_conn >> 10) & 0xff);
1770         fbi->lccr3 |= (lcd_conn & LCD_BIAS_ACTIVE_LOW) ? LCCR3_OEP : 0;
1771         fbi->lccr3 |= (lcd_conn & LCD_PCLK_EDGE_FALL)  ? LCCR3_PCP : 0;
1772
1773 decode_mode:
1774         pxafb_setmode(&fbi->fb.var, &inf->modes[0]);
1775
1776         /* decide video memory size as follows:
1777          * 1. default to mode of maximum resolution
1778          * 2. allow platform to override
1779          * 3. allow module parameter to override
1780          */
1781         for (i = 0, m = &inf->modes[0]; i < inf->num_modes; i++, m++)
1782                 fbi->video_mem_size = max_t(size_t, fbi->video_mem_size,
1783                                 m->xres * m->yres * m->bpp / 8);
1784
1785         if (inf->video_mem_size > fbi->video_mem_size)
1786                 fbi->video_mem_size = inf->video_mem_size;
1787
1788         if (video_mem_size > fbi->video_mem_size)
1789                 fbi->video_mem_size = video_mem_size;
1790 }
1791
1792 static struct pxafb_info *pxafb_init_fbinfo(struct device *dev)
1793 {
1794         struct pxafb_info *fbi;
1795         void *addr;
1796         struct pxafb_mach_info *inf = dev_get_platdata(dev);
1797
1798         /* Alloc the pxafb_info and pseudo_palette in one step */
1799         fbi = kmalloc(sizeof(struct pxafb_info) + sizeof(u32) * 16, GFP_KERNEL);
1800         if (!fbi)
1801                 return NULL;
1802
1803         memset(fbi, 0, sizeof(struct pxafb_info));
1804         fbi->dev = dev;
1805
1806         fbi->clk = clk_get(dev, NULL);
1807         if (IS_ERR(fbi->clk)) {
1808                 kfree(fbi);
1809                 return NULL;
1810         }
1811
1812         strcpy(fbi->fb.fix.id, PXA_NAME);
1813
1814         fbi->fb.fix.type        = FB_TYPE_PACKED_PIXELS;
1815         fbi->fb.fix.type_aux    = 0;
1816         fbi->fb.fix.xpanstep    = 0;
1817         fbi->fb.fix.ypanstep    = 1;
1818         fbi->fb.fix.ywrapstep   = 0;
1819         fbi->fb.fix.accel       = FB_ACCEL_NONE;
1820
1821         fbi->fb.var.nonstd      = 0;
1822         fbi->fb.var.activate    = FB_ACTIVATE_NOW;
1823         fbi->fb.var.height      = -1;
1824         fbi->fb.var.width       = -1;
1825         fbi->fb.var.accel_flags = FB_ACCELF_TEXT;
1826         fbi->fb.var.vmode       = FB_VMODE_NONINTERLACED;
1827
1828         fbi->fb.fbops           = &pxafb_ops;
1829         fbi->fb.flags           = FBINFO_DEFAULT;
1830         fbi->fb.node            = -1;
1831
1832         addr = fbi;
1833         addr = addr + sizeof(struct pxafb_info);
1834         fbi->fb.pseudo_palette  = addr;
1835
1836         fbi->state              = C_STARTUP;
1837         fbi->task_state         = (u_char)-1;
1838
1839         pxafb_decode_mach_info(fbi, inf);
1840
1841 #ifdef CONFIG_FB_PXA_OVERLAY
1842         /* place overlay(s) on top of base */
1843         if (pxafb_overlay_supported())
1844                 fbi->lccr0 |= LCCR0_OUC;
1845 #endif
1846
1847         init_waitqueue_head(&fbi->ctrlr_wait);
1848         INIT_WORK(&fbi->task, pxafb_task);
1849         mutex_init(&fbi->ctrlr_lock);
1850         init_completion(&fbi->disable_done);
1851
1852         return fbi;
1853 }
1854
1855 #ifdef CONFIG_FB_PXA_PARAMETERS
1856 static int parse_opt_mode(struct device *dev, const char *this_opt)
1857 {
1858         struct pxafb_mach_info *inf = dev_get_platdata(dev);
1859
1860         const char *name = this_opt+5;
1861         unsigned int namelen = strlen(name);
1862         int res_specified = 0, bpp_specified = 0;
1863         unsigned int xres = 0, yres = 0, bpp = 0;
1864         int yres_specified = 0;
1865         int i;
1866         for (i = namelen-1; i >= 0; i--) {
1867                 switch (name[i]) {
1868                 case '-':
1869                         namelen = i;
1870                         if (!bpp_specified && !yres_specified) {
1871                                 bpp = simple_strtoul(&name[i+1], NULL, 0);
1872                                 bpp_specified = 1;
1873                         } else
1874                                 goto done;
1875                         break;
1876                 case 'x':
1877                         if (!yres_specified) {
1878                                 yres = simple_strtoul(&name[i+1], NULL, 0);
1879                                 yres_specified = 1;
1880                         } else
1881                                 goto done;
1882                         break;
1883                 case '0' ... '9':
1884                         break;
1885                 default:
1886                         goto done;
1887                 }
1888         }
1889         if (i < 0 && yres_specified) {
1890                 xres = simple_strtoul(name, NULL, 0);
1891                 res_specified = 1;
1892         }
1893 done:
1894         if (res_specified) {
1895                 dev_info(dev, "overriding resolution: %dx%d\n", xres, yres);
1896                 inf->modes[0].xres = xres; inf->modes[0].yres = yres;
1897         }
1898         if (bpp_specified)
1899                 switch (bpp) {
1900                 case 1:
1901                 case 2:
1902                 case 4:
1903                 case 8:
1904                 case 16:
1905                         inf->modes[0].bpp = bpp;
1906                         dev_info(dev, "overriding bit depth: %d\n", bpp);
1907                         break;
1908                 default:
1909                         dev_err(dev, "Depth %d is not valid\n", bpp);
1910                         return -EINVAL;
1911                 }
1912         return 0;
1913 }
1914
1915 static int parse_opt(struct device *dev, char *this_opt)
1916 {
1917         struct pxafb_mach_info *inf = dev_get_platdata(dev);
1918         struct pxafb_mode_info *mode = &inf->modes[0];
1919         char s[64];
1920
1921         s[0] = '\0';
1922
1923         if (!strncmp(this_opt, "vmem:", 5)) {
1924                 video_mem_size = memparse(this_opt + 5, NULL);
1925         } else if (!strncmp(this_opt, "mode:", 5)) {
1926                 return parse_opt_mode(dev, this_opt);
1927         } else if (!strncmp(this_opt, "pixclock:", 9)) {
1928                 mode->pixclock = simple_strtoul(this_opt+9, NULL, 0);
1929                 sprintf(s, "pixclock: %ld\n", mode->pixclock);
1930         } else if (!strncmp(this_opt, "left:", 5)) {
1931                 mode->left_margin = simple_strtoul(this_opt+5, NULL, 0);
1932                 sprintf(s, "left: %u\n", mode->left_margin);
1933         } else if (!strncmp(this_opt, "right:", 6)) {
1934                 mode->right_margin = simple_strtoul(this_opt+6, NULL, 0);
1935                 sprintf(s, "right: %u\n", mode->right_margin);
1936         } else if (!strncmp(this_opt, "upper:", 6)) {
1937                 mode->upper_margin = simple_strtoul(this_opt+6, NULL, 0);
1938                 sprintf(s, "upper: %u\n", mode->upper_margin);
1939         } else if (!strncmp(this_opt, "lower:", 6)) {
1940                 mode->lower_margin = simple_strtoul(this_opt+6, NULL, 0);
1941                 sprintf(s, "lower: %u\n", mode->lower_margin);
1942         } else if (!strncmp(this_opt, "hsynclen:", 9)) {
1943                 mode->hsync_len = simple_strtoul(this_opt+9, NULL, 0);
1944                 sprintf(s, "hsynclen: %u\n", mode->hsync_len);
1945         } else if (!strncmp(this_opt, "vsynclen:", 9)) {
1946                 mode->vsync_len = simple_strtoul(this_opt+9, NULL, 0);
1947                 sprintf(s, "vsynclen: %u\n", mode->vsync_len);
1948         } else if (!strncmp(this_opt, "hsync:", 6)) {
1949                 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1950                         sprintf(s, "hsync: Active Low\n");
1951                         mode->sync &= ~FB_SYNC_HOR_HIGH_ACT;
1952                 } else {
1953                         sprintf(s, "hsync: Active High\n");
1954                         mode->sync |= FB_SYNC_HOR_HIGH_ACT;
1955                 }
1956         } else if (!strncmp(this_opt, "vsync:", 6)) {
1957                 if (simple_strtoul(this_opt+6, NULL, 0) == 0) {
1958                         sprintf(s, "vsync: Active Low\n");
1959                         mode->sync &= ~FB_SYNC_VERT_HIGH_ACT;
1960                 } else {
1961                         sprintf(s, "vsync: Active High\n");
1962                         mode->sync |= FB_SYNC_VERT_HIGH_ACT;
1963                 }
1964         } else if (!strncmp(this_opt, "dpc:", 4)) {
1965                 if (simple_strtoul(this_opt+4, NULL, 0) == 0) {
1966                         sprintf(s, "double pixel clock: false\n");
1967                         inf->lccr3 &= ~LCCR3_DPC;
1968                 } else {
1969                         sprintf(s, "double pixel clock: true\n");
1970                         inf->lccr3 |= LCCR3_DPC;
1971                 }
1972         } else if (!strncmp(this_opt, "outputen:", 9)) {
1973                 if (simple_strtoul(this_opt+9, NULL, 0) == 0) {
1974                         sprintf(s, "output enable: active low\n");
1975                         inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnL;
1976                 } else {
1977                         sprintf(s, "output enable: active high\n");
1978                         inf->lccr3 = (inf->lccr3 & ~LCCR3_OEP) | LCCR3_OutEnH;
1979                 }
1980         } else if (!strncmp(this_opt, "pixclockpol:", 12)) {
1981                 if (simple_strtoul(this_opt+12, NULL, 0) == 0) {
1982                         sprintf(s, "pixel clock polarity: falling edge\n");
1983                         inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixFlEdg;
1984                 } else {
1985                         sprintf(s, "pixel clock polarity: rising edge\n");
1986                         inf->lccr3 = (inf->lccr3 & ~LCCR3_PCP) | LCCR3_PixRsEdg;
1987                 }
1988         } else if (!strncmp(this_opt, "color", 5)) {
1989                 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Color;
1990         } else if (!strncmp(this_opt, "mono", 4)) {
1991                 inf->lccr0 = (inf->lccr0 & ~LCCR0_CMS) | LCCR0_Mono;
1992         } else if (!strncmp(this_opt, "active", 6)) {
1993                 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Act;
1994         } else if (!strncmp(this_opt, "passive", 7)) {
1995                 inf->lccr0 = (inf->lccr0 & ~LCCR0_PAS) | LCCR0_Pas;
1996         } else if (!strncmp(this_opt, "single", 6)) {
1997                 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Sngl;
1998         } else if (!strncmp(this_opt, "dual", 4)) {
1999                 inf->lccr0 = (inf->lccr0 & ~LCCR0_SDS) | LCCR0_Dual;
2000         } else if (!strncmp(this_opt, "4pix", 4)) {
2001                 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_4PixMono;
2002         } else if (!strncmp(this_opt, "8pix", 4)) {
2003                 inf->lccr0 = (inf->lccr0 & ~LCCR0_DPD) | LCCR0_8PixMono;
2004         } else {
2005                 dev_err(dev, "unknown option: %s\n", this_opt);
2006                 return -EINVAL;
2007         }
2008
2009         if (s[0] != '\0')
2010                 dev_info(dev, "override %s", s);
2011
2012         return 0;
2013 }
2014
2015 static int pxafb_parse_options(struct device *dev, char *options)
2016 {
2017         char *this_opt;
2018         int ret;
2019
2020         if (!options || !*options)
2021                 return 0;
2022
2023         dev_dbg(dev, "options are \"%s\"\n", options ? options : "null");
2024
2025         /* could be made table driven or similar?... */
2026         while ((this_opt = strsep(&options, ",")) != NULL) {
2027                 ret = parse_opt(dev, this_opt);
2028                 if (ret)
2029                         return ret;
2030         }
2031         return 0;
2032 }
2033
2034 static char g_options[256] = "";
2035
2036 #ifndef MODULE
2037 static int __init pxafb_setup_options(void)
2038 {
2039         char *options = NULL;
2040
2041         if (fb_get_options("pxafb", &options))
2042                 return -ENODEV;
2043
2044         if (options)
2045                 strlcpy(g_options, options, sizeof(g_options));
2046
2047         return 0;
2048 }
2049 #else
2050 #define pxafb_setup_options()           (0)
2051
2052 module_param_string(options, g_options, sizeof(g_options), 0);
2053 MODULE_PARM_DESC(options, "LCD parameters (see Documentation/fb/pxafb.txt)");
2054 #endif
2055
2056 #else
2057 #define pxafb_parse_options(...)        (0)
2058 #define pxafb_setup_options()           (0)
2059 #endif
2060
2061 #ifdef DEBUG_VAR
2062 /* Check for various illegal bit-combinations. Currently only
2063  * a warning is given. */
2064 static void pxafb_check_options(struct device *dev, struct pxafb_mach_info *inf)
2065 {
2066         if (inf->lcd_conn)
2067                 return;
2068
2069         if (inf->lccr0 & LCCR0_INVALID_CONFIG_MASK)
2070                 dev_warn(dev, "machine LCCR0 setting contains "
2071                                 "illegal bits: %08x\n",
2072                         inf->lccr0 & LCCR0_INVALID_CONFIG_MASK);
2073         if (inf->lccr3 & LCCR3_INVALID_CONFIG_MASK)
2074                 dev_warn(dev, "machine LCCR3 setting contains "
2075                                 "illegal bits: %08x\n",
2076                         inf->lccr3 & LCCR3_INVALID_CONFIG_MASK);
2077         if (inf->lccr0 & LCCR0_DPD &&
2078             ((inf->lccr0 & LCCR0_PAS) != LCCR0_Pas ||
2079              (inf->lccr0 & LCCR0_SDS) != LCCR0_Sngl ||
2080              (inf->lccr0 & LCCR0_CMS) != LCCR0_Mono))
2081                 dev_warn(dev, "Double Pixel Data (DPD) mode is "
2082                                 "only valid in passive mono"
2083                                 " single panel mode\n");
2084         if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Act &&
2085             (inf->lccr0 & LCCR0_SDS) == LCCR0_Dual)
2086                 dev_warn(dev, "Dual panel only valid in passive mode\n");
2087         if ((inf->lccr0 & LCCR0_PAS) == LCCR0_Pas &&
2088              (inf->modes->upper_margin || inf->modes->lower_margin))
2089                 dev_warn(dev, "Upper and lower margins must be 0 in "
2090                                 "passive mode\n");
2091 }
2092 #else
2093 #define pxafb_check_options(...)        do {} while (0)
2094 #endif
2095
2096 static int pxafb_probe(struct platform_device *dev)
2097 {
2098         struct pxafb_info *fbi;
2099         struct pxafb_mach_info *inf;
2100         struct resource *r;
2101         int irq, ret;
2102
2103         dev_dbg(&dev->dev, "pxafb_probe\n");
2104
2105         inf = dev_get_platdata(&dev->dev);
2106         ret = -ENOMEM;
2107         fbi = NULL;
2108         if (!inf)
2109                 goto failed;
2110
2111         ret = pxafb_parse_options(&dev->dev, g_options);
2112         if (ret < 0)
2113                 goto failed;
2114
2115         pxafb_check_options(&dev->dev, inf);
2116
2117         dev_dbg(&dev->dev, "got a %dx%dx%d LCD\n",
2118                         inf->modes->xres,
2119                         inf->modes->yres,
2120                         inf->modes->bpp);
2121         if (inf->modes->xres == 0 ||
2122             inf->modes->yres == 0 ||
2123             inf->modes->bpp == 0) {
2124                 dev_err(&dev->dev, "Invalid resolution or bit depth\n");
2125                 ret = -EINVAL;
2126                 goto failed;
2127         }
2128
2129         fbi = pxafb_init_fbinfo(&dev->dev);
2130         if (!fbi) {
2131                 /* only reason for pxafb_init_fbinfo to fail is kmalloc */
2132                 dev_err(&dev->dev, "Failed to initialize framebuffer device\n");
2133                 ret = -ENOMEM;
2134                 goto failed;
2135         }
2136
2137         if (cpu_is_pxa3xx() && inf->acceleration_enabled)
2138                 fbi->fb.fix.accel = FB_ACCEL_PXA3XX;
2139
2140         fbi->backlight_power = inf->pxafb_backlight_power;
2141         fbi->lcd_power = inf->pxafb_lcd_power;
2142
2143         r = platform_get_resource(dev, IORESOURCE_MEM, 0);
2144         if (r == NULL) {
2145                 dev_err(&dev->dev, "no I/O memory resource defined\n");
2146                 ret = -ENODEV;
2147                 goto failed_fbi;
2148         }
2149
2150         r = request_mem_region(r->start, resource_size(r), dev->name);
2151         if (r == NULL) {
2152                 dev_err(&dev->dev, "failed to request I/O memory\n");
2153                 ret = -EBUSY;
2154                 goto failed_fbi;
2155         }
2156
2157         fbi->mmio_base = ioremap(r->start, resource_size(r));
2158         if (fbi->mmio_base == NULL) {
2159                 dev_err(&dev->dev, "failed to map I/O memory\n");
2160                 ret = -EBUSY;
2161                 goto failed_free_res;
2162         }
2163
2164         fbi->dma_buff_size = PAGE_ALIGN(sizeof(struct pxafb_dma_buff));
2165         fbi->dma_buff = dma_alloc_coherent(fbi->dev, fbi->dma_buff_size,
2166                                 &fbi->dma_buff_phys, GFP_KERNEL);
2167         if (fbi->dma_buff == NULL) {
2168                 dev_err(&dev->dev, "failed to allocate memory for DMA\n");
2169                 ret = -ENOMEM;
2170                 goto failed_free_io;
2171         }
2172
2173         ret = pxafb_init_video_memory(fbi);
2174         if (ret) {
2175                 dev_err(&dev->dev, "Failed to allocate video RAM: %d\n", ret);
2176                 ret = -ENOMEM;
2177                 goto failed_free_dma;
2178         }
2179
2180         irq = platform_get_irq(dev, 0);
2181         if (irq < 0) {
2182                 dev_err(&dev->dev, "no IRQ defined\n");
2183                 ret = -ENODEV;
2184                 goto failed_free_mem;
2185         }
2186
2187         ret = request_irq(irq, pxafb_handle_irq, 0, "LCD", fbi);
2188         if (ret) {
2189                 dev_err(&dev->dev, "request_irq failed: %d\n", ret);
2190                 ret = -EBUSY;
2191                 goto failed_free_mem;
2192         }
2193
2194         ret = pxafb_smart_init(fbi);
2195         if (ret) {
2196                 dev_err(&dev->dev, "failed to initialize smartpanel\n");
2197                 goto failed_free_irq;
2198         }
2199
2200         /*
2201          * This makes sure that our colour bitfield
2202          * descriptors are correctly initialised.
2203          */
2204         ret = pxafb_check_var(&fbi->fb.var, &fbi->fb);
2205         if (ret) {
2206                 dev_err(&dev->dev, "failed to get suitable mode\n");
2207                 goto failed_free_irq;
2208         }
2209
2210         ret = pxafb_set_par(&fbi->fb);
2211         if (ret) {
2212                 dev_err(&dev->dev, "Failed to set parameters\n");
2213                 goto failed_free_irq;
2214         }
2215
2216         platform_set_drvdata(dev, fbi);
2217
2218         ret = register_framebuffer(&fbi->fb);
2219         if (ret < 0) {
2220                 dev_err(&dev->dev,
2221                         "Failed to register framebuffer device: %d\n", ret);
2222                 goto failed_free_cmap;
2223         }
2224
2225         pxafb_overlay_init(fbi);
2226
2227 #ifdef CONFIG_CPU_FREQ
2228         fbi->freq_transition.notifier_call = pxafb_freq_transition;
2229         fbi->freq_policy.notifier_call = pxafb_freq_policy;
2230         cpufreq_register_notifier(&fbi->freq_transition,
2231                                 CPUFREQ_TRANSITION_NOTIFIER);
2232         cpufreq_register_notifier(&fbi->freq_policy,
2233                                 CPUFREQ_POLICY_NOTIFIER);
2234 #endif
2235
2236         /*
2237          * Ok, now enable the LCD controller
2238          */
2239         set_ctrlr_state(fbi, C_ENABLE);
2240
2241         return 0;
2242
2243 failed_free_cmap:
2244         if (fbi->fb.cmap.len)
2245                 fb_dealloc_cmap(&fbi->fb.cmap);
2246 failed_free_irq:
2247         free_irq(irq, fbi);
2248 failed_free_mem:
2249         free_pages_exact(fbi->video_mem, fbi->video_mem_size);
2250 failed_free_dma:
2251         dma_free_coherent(&dev->dev, fbi->dma_buff_size,
2252                         fbi->dma_buff, fbi->dma_buff_phys);
2253 failed_free_io:
2254         iounmap(fbi->mmio_base);
2255 failed_free_res:
2256         release_mem_region(r->start, resource_size(r));
2257 failed_fbi:
2258         clk_put(fbi->clk);
2259         kfree(fbi);
2260 failed:
2261         return ret;
2262 }
2263
2264 static int pxafb_remove(struct platform_device *dev)
2265 {
2266         struct pxafb_info *fbi = platform_get_drvdata(dev);
2267         struct resource *r;
2268         int irq;
2269         struct fb_info *info;
2270
2271         if (!fbi)
2272                 return 0;
2273
2274         info = &fbi->fb;
2275
2276         pxafb_overlay_exit(fbi);
2277         unregister_framebuffer(info);
2278
2279         pxafb_disable_controller(fbi);
2280
2281         if (fbi->fb.cmap.len)
2282                 fb_dealloc_cmap(&fbi->fb.cmap);
2283
2284         irq = platform_get_irq(dev, 0);
2285         free_irq(irq, fbi);
2286
2287         free_pages_exact(fbi->video_mem, fbi->video_mem_size);
2288
2289         dma_free_writecombine(&dev->dev, fbi->dma_buff_size,
2290                         fbi->dma_buff, fbi->dma_buff_phys);
2291
2292         iounmap(fbi->mmio_base);
2293
2294         r = platform_get_resource(dev, IORESOURCE_MEM, 0);
2295         release_mem_region(r->start, resource_size(r));
2296
2297         clk_put(fbi->clk);
2298         kfree(fbi);
2299
2300         return 0;
2301 }
2302
2303 static struct platform_driver pxafb_driver = {
2304         .probe          = pxafb_probe,
2305         .remove         = pxafb_remove,
2306         .driver         = {
2307                 .owner  = THIS_MODULE,
2308                 .name   = "pxa2xx-fb",
2309 #ifdef CONFIG_PM
2310                 .pm     = &pxafb_pm_ops,
2311 #endif
2312         },
2313 };
2314
2315 static int __init pxafb_init(void)
2316 {
2317         if (pxafb_setup_options())
2318                 return -EINVAL;
2319
2320         return platform_driver_register(&pxafb_driver);
2321 }
2322
2323 static void __exit pxafb_exit(void)
2324 {
2325         platform_driver_unregister(&pxafb_driver);
2326 }
2327
2328 module_init(pxafb_init);
2329 module_exit(pxafb_exit);
2330
2331 MODULE_DESCRIPTION("loadable framebuffer driver for PXA");
2332 MODULE_LICENSE("GPL");