2 * Frame buffer driver for Trident TGUI, Blade and Image series
4 * Copyright 2001, 2002 - Jani Monoses <jani@iv.ro>
5 * Copyright 2009 Krzysztof Helt <krzysztof.h1@wp.pl>
7 * CREDITS:(in order of appearance)
8 * skeletonfb.c by Geert Uytterhoeven and other fb code in drivers/video
9 * Special thanks ;) to Mattia Crivellini <tia@mclink.it>
10 * much inspired by the XFree86 4.x Trident driver sources
11 * by Alan Hourihane the FreeVGA project
12 * Francesco Salvestrini <salvestrini@users.sf.net> XP support,
15 * timing value tweaking so it looks good on every monitor in every mode
18 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/pci.h>
22 #include <linux/slab.h>
24 #include <linux/delay.h>
25 #include <video/vga.h>
26 #include <video/trident.h>
28 struct tridentfb_par {
29 void __iomem *io_virt; /* iospace virtual memory address */
33 void (*init_accel) (struct tridentfb_par *, int, int);
34 void (*wait_engine) (struct tridentfb_par *);
36 (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
38 (struct tridentfb_par *par, u32, u32, u32, u32, u32, u32);
40 (struct tridentfb_par *par, const char*,
41 u32, u32, u32, u32, u32, u32);
42 unsigned char eng_oper; /* engine operation... */
45 static struct fb_fix_screeninfo tridentfb_fix = {
47 .type = FB_TYPE_PACKED_PIXELS,
49 .visual = FB_VISUAL_PSEUDOCOLOR,
50 .accel = FB_ACCEL_NONE,
53 /* defaults which are normally overriden by user values */
56 static char *mode_option = "640x480-8@60";
71 module_param(mode_option, charp, 0);
72 MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'");
73 module_param_named(mode, mode_option, charp, 0);
74 MODULE_PARM_DESC(mode, "Initial video mode e.g. '648x480-8@60' (deprecated)");
75 module_param(bpp, int, 0);
76 module_param(center, int, 0);
77 module_param(stretch, int, 0);
78 module_param(noaccel, int, 0);
79 module_param(memsize, int, 0);
80 module_param(memdiff, int, 0);
81 module_param(nativex, int, 0);
82 module_param(fp, int, 0);
83 MODULE_PARM_DESC(fp, "Define if flatpanel is connected");
84 module_param(crt, int, 0);
85 MODULE_PARM_DESC(crt, "Define if CRT is connected");
87 static inline int is_oldclock(int id)
89 return (id == TGUI9440) ||
94 static inline int is_oldprotect(int id)
96 return is_oldclock(id) ||
97 (id == PROVIDIA9685) ||
102 static inline int is_blade(int id)
104 return (id == BLADE3D) ||
105 (id == CYBERBLADEE4) ||
106 (id == CYBERBLADEi7) ||
107 (id == CYBERBLADEi7D) ||
108 (id == CYBERBLADEi1) ||
109 (id == CYBERBLADEi1D) ||
110 (id == CYBERBLADEAi1) ||
111 (id == CYBERBLADEAi1D);
114 static inline int is_xp(int id)
116 return (id == CYBERBLADEXPAi1) ||
117 (id == CYBERBLADEXPm8) ||
118 (id == CYBERBLADEXPm16);
121 static inline int is3Dchip(int id)
123 return is_blade(id) || is_xp(id) ||
124 (id == CYBER9397) || (id == CYBER9397DVD) ||
125 (id == CYBER9520) || (id == CYBER9525DVD) ||
126 (id == IMAGE975) || (id == IMAGE985);
129 static inline int iscyber(int id)
145 case CYBERBLADEXPAi1:
149 case CYBERBLADEi7: /* VIA MPV4 integrated version */
151 /* case CYBERBLDAEXPm8: Strange */
152 /* case CYBERBLDAEXPm16: Strange */
157 static inline void t_outb(struct tridentfb_par *p, u8 val, u16 reg)
159 fb_writeb(val, p->io_virt + reg);
162 static inline u8 t_inb(struct tridentfb_par *p, u16 reg)
164 return fb_readb(p->io_virt + reg);
167 static inline void writemmr(struct tridentfb_par *par, u16 r, u32 v)
169 fb_writel(v, par->io_virt + r);
172 static inline u32 readmmr(struct tridentfb_par *par, u16 r)
174 return fb_readl(par->io_virt + r);
178 * Blade specific acceleration.
181 #define point(x, y) ((y) << 16 | (x))
183 static void blade_init_accel(struct tridentfb_par *par, int pitch, int bpp)
185 int v1 = (pitch >> 3) << 20;
186 int tmp = bpp == 24 ? 2 : (bpp >> 4);
187 int v2 = v1 | (tmp << 29);
189 writemmr(par, 0x21C0, v2);
190 writemmr(par, 0x21C4, v2);
191 writemmr(par, 0x21B8, v2);
192 writemmr(par, 0x21BC, v2);
193 writemmr(par, 0x21D0, v1);
194 writemmr(par, 0x21D4, v1);
195 writemmr(par, 0x21C8, v1);
196 writemmr(par, 0x21CC, v1);
197 writemmr(par, 0x216C, 0);
200 static void blade_wait_engine(struct tridentfb_par *par)
202 while (readmmr(par, STATUS) & 0xFA800000)
206 static void blade_fill_rect(struct tridentfb_par *par,
207 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
209 writemmr(par, COLOR, c);
210 writemmr(par, ROP, rop ? ROP_X : ROP_S);
211 writemmr(par, CMD, 0x20000000 | 1 << 19 | 1 << 4 | 2 << 2);
213 writemmr(par, DST1, point(x, y));
214 writemmr(par, DST2, point(x + w - 1, y + h - 1));
217 static void blade_image_blit(struct tridentfb_par *par, const char *data,
218 u32 x, u32 y, u32 w, u32 h, u32 c, u32 b)
220 unsigned size = ((w + 31) >> 5) * h;
222 writemmr(par, COLOR, c);
223 writemmr(par, BGCOLOR, b);
224 writemmr(par, CMD, 0xa0000000 | 3 << 19);
226 writemmr(par, DST1, point(x, y));
227 writemmr(par, DST2, point(x + w - 1, y + h - 1));
229 iowrite32_rep(par->io_virt + 0x10000, data, size);
232 static void blade_copy_rect(struct tridentfb_par *par,
233 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
236 u32 s1 = point(x1, y1);
237 u32 s2 = point(x1 + w - 1, y1 + h - 1);
238 u32 d1 = point(x2, y2);
239 u32 d2 = point(x2 + w - 1, y2 + h - 1);
241 if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
244 writemmr(par, ROP, ROP_S);
245 writemmr(par, CMD, 0xE0000000 | 1 << 19 | 1 << 4 | 1 << 2 | direction);
247 writemmr(par, SRC1, direction ? s2 : s1);
248 writemmr(par, SRC2, direction ? s1 : s2);
249 writemmr(par, DST1, direction ? d2 : d1);
250 writemmr(par, DST2, direction ? d1 : d2);
254 * BladeXP specific acceleration functions
257 static void xp_init_accel(struct tridentfb_par *par, int pitch, int bpp)
259 unsigned char x = bpp == 24 ? 3 : (bpp >> 4);
260 int v1 = pitch << (bpp == 24 ? 20 : (18 + x));
262 switch (pitch << (bpp >> 3)) {
278 t_outb(par, x, 0x2125);
280 par->eng_oper = x | 0x40;
282 writemmr(par, 0x2154, v1);
283 writemmr(par, 0x2150, v1);
284 t_outb(par, 3, 0x2126);
287 static void xp_wait_engine(struct tridentfb_par *par)
292 while (t_inb(par, STATUS) & 0x80) {
294 if (count == 10000000) {
300 t_outb(par, 0x00, STATUS);
308 static void xp_fill_rect(struct tridentfb_par *par,
309 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
311 writemmr(par, 0x2127, ROP_P);
312 writemmr(par, 0x2158, c);
313 writemmr(par, DRAWFL, 0x4000);
314 writemmr(par, OLDDIM, point(h, w));
315 writemmr(par, OLDDST, point(y, x));
316 t_outb(par, 0x01, OLDCMD);
317 t_outb(par, par->eng_oper, 0x2125);
320 static void xp_copy_rect(struct tridentfb_par *par,
321 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
323 u32 x1_tmp, x2_tmp, y1_tmp, y2_tmp;
324 int direction = 0x0004;
326 if ((x1 < x2) && (y1 == y2)) {
344 writemmr(par, DRAWFL, direction);
345 t_outb(par, ROP_S, 0x2127);
346 writemmr(par, OLDSRC, point(y1_tmp, x1_tmp));
347 writemmr(par, OLDDST, point(y2_tmp, x2_tmp));
348 writemmr(par, OLDDIM, point(h, w));
349 t_outb(par, 0x01, OLDCMD);
353 * Image specific acceleration functions
355 static void image_init_accel(struct tridentfb_par *par, int pitch, int bpp)
357 int tmp = bpp == 24 ? 2: (bpp >> 4);
359 writemmr(par, 0x2120, 0xF0000000);
360 writemmr(par, 0x2120, 0x40000000 | tmp);
361 writemmr(par, 0x2120, 0x80000000);
362 writemmr(par, 0x2144, 0x00000000);
363 writemmr(par, 0x2148, 0x00000000);
364 writemmr(par, 0x2150, 0x00000000);
365 writemmr(par, 0x2154, 0x00000000);
366 writemmr(par, 0x2120, 0x60000000 | (pitch << 16) | pitch);
367 writemmr(par, 0x216C, 0x00000000);
368 writemmr(par, 0x2170, 0x00000000);
369 writemmr(par, 0x217C, 0x00000000);
370 writemmr(par, 0x2120, 0x10000000);
371 writemmr(par, 0x2130, (2047 << 16) | 2047);
374 static void image_wait_engine(struct tridentfb_par *par)
376 while (readmmr(par, 0x2164) & 0xF0000000)
380 static void image_fill_rect(struct tridentfb_par *par,
381 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
383 writemmr(par, 0x2120, 0x80000000);
384 writemmr(par, 0x2120, 0x90000000 | ROP_S);
386 writemmr(par, 0x2144, c);
388 writemmr(par, DST1, point(x, y));
389 writemmr(par, DST2, point(x + w - 1, y + h - 1));
391 writemmr(par, 0x2124, 0x80000000 | 3 << 22 | 1 << 10 | 1 << 9);
394 static void image_copy_rect(struct tridentfb_par *par,
395 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
398 u32 s1 = point(x1, y1);
399 u32 s2 = point(x1 + w - 1, y1 + h - 1);
400 u32 d1 = point(x2, y2);
401 u32 d2 = point(x2 + w - 1, y2 + h - 1);
403 if ((y1 > y2) || ((y1 == y2) && (x1 > x2)))
406 writemmr(par, 0x2120, 0x80000000);
407 writemmr(par, 0x2120, 0x90000000 | ROP_S);
409 writemmr(par, SRC1, direction ? s2 : s1);
410 writemmr(par, SRC2, direction ? s1 : s2);
411 writemmr(par, DST1, direction ? d2 : d1);
412 writemmr(par, DST2, direction ? d1 : d2);
413 writemmr(par, 0x2124,
414 0x80000000 | 1 << 22 | 1 << 10 | 1 << 7 | direction);
418 * TGUI 9440/96XX acceleration
421 static void tgui_init_accel(struct tridentfb_par *par, int pitch, int bpp)
423 unsigned char x = bpp == 24 ? 3 : (bpp >> 4);
425 /* disable clipping */
426 writemmr(par, 0x2148, 0);
427 writemmr(par, 0x214C, point(4095, 2047));
429 switch ((pitch * bpp) / 8) {
445 fb_writew(x, par->io_virt + 0x2122);
448 static void tgui_fill_rect(struct tridentfb_par *par,
449 u32 x, u32 y, u32 w, u32 h, u32 c, u32 rop)
451 t_outb(par, ROP_P, 0x2127);
452 writemmr(par, OLDCLR, c);
453 writemmr(par, DRAWFL, 0x4020);
454 writemmr(par, OLDDIM, point(w - 1, h - 1));
455 writemmr(par, OLDDST, point(x, y));
456 t_outb(par, 1, OLDCMD);
459 static void tgui_copy_rect(struct tridentfb_par *par,
460 u32 x1, u32 y1, u32 x2, u32 y2, u32 w, u32 h)
463 u16 x1_tmp, x2_tmp, y1_tmp, y2_tmp;
465 if ((x1 < x2) && (y1 == y2)) {
483 writemmr(par, DRAWFL, 0x4 | flags);
484 t_outb(par, ROP_S, 0x2127);
485 writemmr(par, OLDSRC, point(x1_tmp, y1_tmp));
486 writemmr(par, OLDDST, point(x2_tmp, y2_tmp));
487 writemmr(par, OLDDIM, point(w - 1, h - 1));
488 t_outb(par, 1, OLDCMD);
492 * Accel functions called by the upper layers
494 static void tridentfb_fillrect(struct fb_info *info,
495 const struct fb_fillrect *fr)
497 struct tridentfb_par *par = info->par;
500 if (info->flags & FBINFO_HWACCEL_DISABLED) {
501 cfb_fillrect(info, fr);
504 if (info->var.bits_per_pixel == 8) {
509 col = ((u32 *)(info->pseudo_palette))[fr->color];
511 par->wait_engine(par);
512 par->fill_rect(par, fr->dx, fr->dy, fr->width,
513 fr->height, col, fr->rop);
516 static void tridentfb_imageblit(struct fb_info *info,
517 const struct fb_image *img)
519 struct tridentfb_par *par = info->par;
522 if ((info->flags & FBINFO_HWACCEL_DISABLED) || img->depth != 1) {
523 cfb_imageblit(info, img);
526 if (info->var.bits_per_pixel == 8) {
530 bgcol = img->bg_color;
532 bgcol |= bgcol << 16;
534 col = ((u32 *)(info->pseudo_palette))[img->fg_color];
535 bgcol = ((u32 *)(info->pseudo_palette))[img->bg_color];
538 par->wait_engine(par);
540 par->image_blit(par, img->data, img->dx, img->dy,
541 img->width, img->height, col, bgcol);
543 cfb_imageblit(info, img);
546 static void tridentfb_copyarea(struct fb_info *info,
547 const struct fb_copyarea *ca)
549 struct tridentfb_par *par = info->par;
551 if (info->flags & FBINFO_HWACCEL_DISABLED) {
552 cfb_copyarea(info, ca);
555 par->wait_engine(par);
556 par->copy_rect(par, ca->sx, ca->sy, ca->dx, ca->dy,
557 ca->width, ca->height);
560 static int tridentfb_sync(struct fb_info *info)
562 struct tridentfb_par *par = info->par;
564 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
565 par->wait_engine(par);
570 * Hardware access functions
573 static inline unsigned char read3X4(struct tridentfb_par *par, int reg)
575 return vga_mm_rcrt(par->io_virt, reg);
578 static inline void write3X4(struct tridentfb_par *par, int reg,
581 vga_mm_wcrt(par->io_virt, reg, val);
584 static inline unsigned char read3CE(struct tridentfb_par *par,
587 return vga_mm_rgfx(par->io_virt, reg);
590 static inline void writeAttr(struct tridentfb_par *par, int reg,
593 fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */
594 vga_mm_wattr(par->io_virt, reg, val);
597 static inline void write3CE(struct tridentfb_par *par, int reg,
600 vga_mm_wgfx(par->io_virt, reg, val);
603 static void enable_mmio(struct tridentfb_par *par)
608 /* Unprotect registers */
609 vga_io_wseq(NewMode1, 0x80);
610 if (!is_oldprotect(par->chip_id))
611 vga_io_wseq(Protection, 0x92);
615 outb(inb(0x3D5) | 0x01, 0x3D5);
618 static void disable_mmio(struct tridentfb_par *par)
621 vga_mm_rseq(par->io_virt, 0x0B);
623 /* Unprotect registers */
624 vga_mm_wseq(par->io_virt, NewMode1, 0x80);
625 if (!is_oldprotect(par->chip_id))
626 vga_mm_wseq(par->io_virt, Protection, 0x92);
629 t_outb(par, PCIReg, 0x3D4);
630 t_outb(par, t_inb(par, 0x3D5) & ~0x01, 0x3D5);
633 static inline void crtc_unlock(struct tridentfb_par *par)
635 write3X4(par, VGA_CRTC_V_SYNC_END,
636 read3X4(par, VGA_CRTC_V_SYNC_END) & 0x7F);
639 /* Return flat panel's maximum x resolution */
640 static int get_nativex(struct tridentfb_par *par)
647 tmp = (read3CE(par, VertStretch) >> 4) & 3;
668 output("%dx%d flat panel found\n", x, y);
673 static inline void set_lwidth(struct tridentfb_par *par, int width)
675 write3X4(par, VGA_CRTC_OFFSET, width & 0xFF);
676 /* chips older than TGUI9660 have only 1 width bit in AddColReg */
677 /* touching the other one breaks I2C/DDC */
678 if (par->chip_id == TGUI9440 || par->chip_id == CYBER9320)
679 write3X4(par, AddColReg,
680 (read3X4(par, AddColReg) & 0xEF) | ((width & 0x100) >> 4));
682 write3X4(par, AddColReg,
683 (read3X4(par, AddColReg) & 0xCF) | ((width & 0x300) >> 4));
686 /* For resolutions smaller than FP resolution stretch */
687 static void screen_stretch(struct tridentfb_par *par)
689 if (par->chip_id != CYBERBLADEXPAi1)
690 write3CE(par, BiosReg, 0);
692 write3CE(par, BiosReg, 8);
693 write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 1);
694 write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 1);
697 /* For resolutions smaller than FP resolution center */
698 static inline void screen_center(struct tridentfb_par *par)
700 write3CE(par, VertStretch, (read3CE(par, VertStretch) & 0x7C) | 0x80);
701 write3CE(par, HorStretch, (read3CE(par, HorStretch) & 0x7C) | 0x80);
704 /* Address of first shown pixel in display memory */
705 static void set_screen_start(struct tridentfb_par *par, int base)
708 write3X4(par, VGA_CRTC_START_LO, base & 0xFF);
709 write3X4(par, VGA_CRTC_START_HI, (base & 0xFF00) >> 8);
710 tmp = read3X4(par, CRTCModuleTest) & 0xDF;
711 write3X4(par, CRTCModuleTest, tmp | ((base & 0x10000) >> 11));
712 tmp = read3X4(par, CRTHiOrd) & 0xF8;
713 write3X4(par, CRTHiOrd, tmp | ((base & 0xE0000) >> 17));
716 /* Set dotclock frequency */
717 static void set_vclk(struct tridentfb_par *par, unsigned long freq)
720 unsigned long fi, d, di;
721 unsigned char best_m = 0, best_n = 0, best_k = 0;
722 unsigned char hi, lo;
723 unsigned char shift = !is_oldclock(par->chip_id) ? 2 : 1;
726 for (k = shift; k >= 0; k--)
727 for (m = 1; m < 32; m++) {
728 n = ((m + 2) << shift) - 8;
729 for (n = (n < 0 ? 0 : n); n < 122; n++) {
730 fi = ((14318l * (n + 8)) / (m + 2)) >> k;
732 if (di < d || (di == d && k == best_k)) {
743 if (is_oldclock(par->chip_id)) {
744 lo = best_n | (best_m << 7);
745 hi = (best_m >> 1) | (best_k << 4);
748 hi = best_m | (best_k << 6);
751 if (is3Dchip(par->chip_id)) {
752 vga_mm_wseq(par->io_virt, ClockHigh, hi);
753 vga_mm_wseq(par->io_virt, ClockLow, lo);
755 t_outb(par, lo, 0x43C8);
756 t_outb(par, hi, 0x43C9);
758 debug("VCLK = %X %X\n", hi, lo);
761 /* Set number of lines for flat panels*/
762 static void set_number_of_lines(struct tridentfb_par *par, int lines)
764 int tmp = read3CE(par, CyberEnhance) & 0x8F;
767 else if (lines > 768)
769 else if (lines > 600)
771 else if (lines > 480)
773 write3CE(par, CyberEnhance, tmp);
777 * If we see that FP is active we assume we have one.
778 * Otherwise we have a CRT display. User can override.
780 static int is_flatpanel(struct tridentfb_par *par)
784 if (crt || !iscyber(par->chip_id))
786 return (read3CE(par, FPConfig) & 0x10) ? 1 : 0;
789 /* Try detecting the video memory size */
790 static unsigned int get_memsize(struct tridentfb_par *par)
792 unsigned char tmp, tmp2;
795 /* If memory size provided by user */
799 switch (par->chip_id) {
804 tmp = read3X4(par, SPR) & 0x0F;
820 k = 10 * Mb; /* XP */
826 k = 12 * Mb; /* XP */
829 k = 14 * Mb; /* XP */
832 k = 16 * Mb; /* XP */
836 tmp2 = vga_mm_rseq(par->io_virt, 0xC1);
866 output("framebuffer size = %d Kb\n", k / Kb);
870 /* See if we can handle the video mode described in var */
871 static int tridentfb_check_var(struct fb_var_screeninfo *var,
872 struct fb_info *info)
874 struct tridentfb_par *par = info->par;
875 int bpp = var->bits_per_pixel;
877 int ramdac = 230000; /* 230MHz for most 3D chips */
880 /* check color depth */
882 bpp = var->bits_per_pixel = 32;
883 if (bpp != 8 && bpp != 16 && bpp != 32)
885 if (par->chip_id == TGUI9440 && bpp == 32)
887 /* check whether resolution fits on panel and in memory */
888 if (par->flatpanel && nativex && var->xres > nativex)
890 /* various resolution checks */
891 var->xres = (var->xres + 7) & ~0x7;
892 if (var->xres > var->xres_virtual)
893 var->xres_virtual = var->xres;
894 if (var->yres > var->yres_virtual)
895 var->yres_virtual = var->yres;
896 if (var->xres_virtual > 4095 || var->yres > 2048)
898 /* prevent from position overflow for acceleration */
899 if (var->yres_virtual > 0xffff)
901 line_length = var->xres_virtual * bpp / 8;
903 if (!is3Dchip(par->chip_id) &&
904 !(info->flags & FBINFO_HWACCEL_DISABLED)) {
905 /* acceleration requires line length to be power of 2 */
906 if (line_length <= 512)
907 var->xres_virtual = 512 * 8 / bpp;
908 else if (line_length <= 1024)
909 var->xres_virtual = 1024 * 8 / bpp;
910 else if (line_length <= 2048)
911 var->xres_virtual = 2048 * 8 / bpp;
912 else if (line_length <= 4096)
913 var->xres_virtual = 4096 * 8 / bpp;
914 else if (line_length <= 8192)
915 var->xres_virtual = 8192 * 8 / bpp;
919 line_length = var->xres_virtual * bpp / 8;
922 /* datasheet specifies how to set panning only up to 4 MB */
923 if (line_length * (var->yres_virtual - var->yres) > (4 << 20))
924 var->yres_virtual = ((4 << 20) / line_length) + var->yres;
926 if (line_length * var->yres_virtual > info->fix.smem_len)
933 var->green = var->red;
934 var->blue = var->red;
937 var->red.offset = 11;
938 var->green.offset = 5;
939 var->blue.offset = 0;
941 var->green.length = 6;
942 var->blue.length = 5;
945 var->red.offset = 16;
946 var->green.offset = 8;
947 var->blue.offset = 0;
949 var->green.length = 8;
950 var->blue.length = 8;
956 if (is_xp(par->chip_id))
959 switch (par->chip_id) {
961 ramdac = (bpp >= 16) ? 45000 : 90000;
975 /* The clock is doubled for 32 bpp */
979 if (PICOS2KHZ(var->pixclock) > ramdac)
988 /* Pan the display */
989 static int tridentfb_pan_display(struct fb_var_screeninfo *var,
990 struct fb_info *info)
992 struct tridentfb_par *par = info->par;
996 offset = (var->xoffset + (var->yoffset * info->var.xres_virtual))
997 * info->var.bits_per_pixel / 32;
998 set_screen_start(par, offset);
1003 static inline void shadowmode_on(struct tridentfb_par *par)
1005 write3CE(par, CyberControl, read3CE(par, CyberControl) | 0x81);
1008 static inline void shadowmode_off(struct tridentfb_par *par)
1010 write3CE(par, CyberControl, read3CE(par, CyberControl) & 0x7E);
1013 /* Set the hardware to the requested video mode */
1014 static int tridentfb_set_par(struct fb_info *info)
1016 struct tridentfb_par *par = info->par;
1017 u32 htotal, hdispend, hsyncstart, hsyncend, hblankstart, hblankend;
1018 u32 vtotal, vdispend, vsyncstart, vsyncend, vblankstart, vblankend;
1019 struct fb_var_screeninfo *var = &info->var;
1020 int bpp = var->bits_per_pixel;
1025 hdispend = var->xres / 8 - 1;
1026 hsyncstart = (var->xres + var->right_margin) / 8;
1027 hsyncend = (var->xres + var->right_margin + var->hsync_len) / 8;
1028 htotal = (var->xres + var->left_margin + var->right_margin +
1029 var->hsync_len) / 8 - 5;
1030 hblankstart = hdispend + 1;
1031 hblankend = htotal + 3;
1033 vdispend = var->yres - 1;
1034 vsyncstart = var->yres + var->lower_margin;
1035 vsyncend = vsyncstart + var->vsync_len;
1036 vtotal = var->upper_margin + vsyncend - 2;
1037 vblankstart = vdispend + 1;
1040 if (info->var.vmode & FB_VMODE_INTERLACED) {
1051 write3CE(par, CyberControl, 8);
1053 if (var->sync & FB_SYNC_HOR_HIGH_ACT)
1055 if (var->sync & FB_SYNC_VERT_HIGH_ACT)
1058 if (par->flatpanel && var->xres < nativex) {
1060 * on flat panels with native size larger
1061 * than requested resolution decide whether
1062 * we stretch or center
1064 t_outb(par, tmp | 0xC0, VGA_MIS_W);
1071 screen_stretch(par);
1074 t_outb(par, tmp, VGA_MIS_W);
1075 write3CE(par, CyberControl, 8);
1078 /* vertical timing values */
1079 write3X4(par, VGA_CRTC_V_TOTAL, vtotal & 0xFF);
1080 write3X4(par, VGA_CRTC_V_DISP_END, vdispend & 0xFF);
1081 write3X4(par, VGA_CRTC_V_SYNC_START, vsyncstart & 0xFF);
1082 write3X4(par, VGA_CRTC_V_SYNC_END, (vsyncend & 0x0F));
1083 write3X4(par, VGA_CRTC_V_BLANK_START, vblankstart & 0xFF);
1084 write3X4(par, VGA_CRTC_V_BLANK_END, vblankend & 0xFF);
1086 /* horizontal timing values */
1087 write3X4(par, VGA_CRTC_H_TOTAL, htotal & 0xFF);
1088 write3X4(par, VGA_CRTC_H_DISP, hdispend & 0xFF);
1089 write3X4(par, VGA_CRTC_H_SYNC_START, hsyncstart & 0xFF);
1090 write3X4(par, VGA_CRTC_H_SYNC_END,
1091 (hsyncend & 0x1F) | ((hblankend & 0x20) << 2));
1092 write3X4(par, VGA_CRTC_H_BLANK_START, hblankstart & 0xFF);
1093 write3X4(par, VGA_CRTC_H_BLANK_END, hblankend & 0x1F);
1095 /* higher bits of vertical timing values */
1097 if (vtotal & 0x100) tmp |= 0x01;
1098 if (vdispend & 0x100) tmp |= 0x02;
1099 if (vsyncstart & 0x100) tmp |= 0x04;
1100 if (vblankstart & 0x100) tmp |= 0x08;
1102 if (vtotal & 0x200) tmp |= 0x20;
1103 if (vdispend & 0x200) tmp |= 0x40;
1104 if (vsyncstart & 0x200) tmp |= 0x80;
1105 write3X4(par, VGA_CRTC_OVERFLOW, tmp);
1107 tmp = read3X4(par, CRTHiOrd) & 0x07;
1108 tmp |= 0x08; /* line compare bit 10 */
1109 if (vtotal & 0x400) tmp |= 0x80;
1110 if (vblankstart & 0x400) tmp |= 0x40;
1111 if (vsyncstart & 0x400) tmp |= 0x20;
1112 if (vdispend & 0x400) tmp |= 0x10;
1113 write3X4(par, CRTHiOrd, tmp);
1115 tmp = (htotal >> 8) & 0x01;
1116 tmp |= (hdispend >> 7) & 0x02;
1117 tmp |= (hsyncstart >> 5) & 0x08;
1118 tmp |= (hblankstart >> 4) & 0x10;
1119 write3X4(par, HorizOverflow, tmp);
1122 if (vblankstart & 0x200) tmp |= 0x20;
1123 //FIXME if (info->var.vmode & FB_VMODE_DOUBLE) tmp |= 0x80; /* double scan for 200 line modes */
1124 write3X4(par, VGA_CRTC_MAX_SCAN, tmp);
1126 write3X4(par, VGA_CRTC_LINE_COMPARE, 0xFF);
1127 write3X4(par, VGA_CRTC_PRESET_ROW, 0);
1128 write3X4(par, VGA_CRTC_MODE, 0xC3);
1130 write3X4(par, LinearAddReg, 0x20); /* enable linear addressing */
1132 tmp = (info->var.vmode & FB_VMODE_INTERLACED) ? 0x84 : 0x80;
1133 /* enable access extended memory */
1134 write3X4(par, CRTCModuleTest, tmp);
1135 tmp = read3CE(par, MiscIntContReg) & ~0x4;
1136 if (info->var.vmode & FB_VMODE_INTERLACED)
1138 write3CE(par, MiscIntContReg, tmp);
1140 /* enable GE for text acceleration */
1141 write3X4(par, GraphEngReg, 0x80);
1158 write3X4(par, PixelBusReg, tmp);
1160 tmp = read3X4(par, DRAMControl);
1161 if (!is_oldprotect(par->chip_id))
1163 if (iscyber(par->chip_id))
1165 write3X4(par, DRAMControl, tmp); /* both IO, linear enable */
1167 write3X4(par, InterfaceSel, read3X4(par, InterfaceSel) | 0x40);
1168 if (!is_xp(par->chip_id))
1169 write3X4(par, Performance, read3X4(par, Performance) | 0x10);
1170 /* MMIO & PCI read and write burst enable */
1171 if (par->chip_id != TGUI9440 && par->chip_id != IMAGE975)
1172 write3X4(par, PCIReg, read3X4(par, PCIReg) | 0x06);
1174 vga_mm_wseq(par->io_virt, 0, 3);
1175 vga_mm_wseq(par->io_virt, 1, 1); /* set char clock 8 dots wide */
1176 /* enable 4 maps because needed in chain4 mode */
1177 vga_mm_wseq(par->io_virt, 2, 0x0F);
1178 vga_mm_wseq(par->io_virt, 3, 0);
1179 vga_mm_wseq(par->io_virt, 4, 0x0E); /* memory mode enable bitmaps ?? */
1181 /* convert from picoseconds to kHz */
1182 vclk = PICOS2KHZ(info->var.pixclock);
1184 /* divide clock by 2 if 32bpp chain4 mode display and CPU path */
1185 tmp = read3CE(par, MiscExtFunc) & 0xF0;
1186 if (bpp == 32 || (par->chip_id == TGUI9440 && bpp == 16)) {
1190 set_vclk(par, vclk);
1191 write3CE(par, MiscExtFunc, tmp | 0x12);
1192 write3CE(par, 0x5, 0x40); /* no CGA compat, allow 256 col */
1193 write3CE(par, 0x6, 0x05); /* graphics mode */
1194 write3CE(par, 0x7, 0x0F); /* planes? */
1196 /* graphics mode and support 256 color modes */
1197 writeAttr(par, 0x10, 0x41);
1198 writeAttr(par, 0x12, 0x0F); /* planes */
1199 writeAttr(par, 0x13, 0); /* horizontal pel panning */
1202 for (tmp = 0; tmp < 0x10; tmp++)
1203 writeAttr(par, tmp, tmp);
1204 fb_readb(par->io_virt + VGA_IS1_RC); /* flip-flop to index */
1205 t_outb(par, 0x20, VGA_ATT_W); /* enable attr */
1220 t_inb(par, VGA_PEL_IW);
1221 t_inb(par, VGA_PEL_MSK);
1222 t_inb(par, VGA_PEL_MSK);
1223 t_inb(par, VGA_PEL_MSK);
1224 t_inb(par, VGA_PEL_MSK);
1225 t_outb(par, tmp, VGA_PEL_MSK);
1226 t_inb(par, VGA_PEL_IW);
1229 set_number_of_lines(par, info->var.yres);
1230 info->fix.line_length = info->var.xres_virtual * bpp / 8;
1231 set_lwidth(par, info->fix.line_length / 8);
1233 if (!(info->flags & FBINFO_HWACCEL_DISABLED))
1234 par->init_accel(par, info->var.xres_virtual, bpp);
1236 info->fix.visual = (bpp == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
1237 info->cmap.len = (bpp == 8) ? 256 : 16;
1242 /* Set one color register */
1243 static int tridentfb_setcolreg(unsigned regno, unsigned red, unsigned green,
1244 unsigned blue, unsigned transp,
1245 struct fb_info *info)
1247 int bpp = info->var.bits_per_pixel;
1248 struct tridentfb_par *par = info->par;
1250 if (regno >= info->cmap.len)
1254 t_outb(par, 0xFF, VGA_PEL_MSK);
1255 t_outb(par, regno, VGA_PEL_IW);
1257 t_outb(par, red >> 10, VGA_PEL_D);
1258 t_outb(par, green >> 10, VGA_PEL_D);
1259 t_outb(par, blue >> 10, VGA_PEL_D);
1261 } else if (regno < 16) {
1262 if (bpp == 16) { /* RGB 565 */
1265 col = (red & 0xF800) | ((green & 0xFC00) >> 5) |
1266 ((blue & 0xF800) >> 11);
1268 ((u32 *)(info->pseudo_palette))[regno] = col;
1269 } else if (bpp == 32) /* ARGB 8888 */
1270 ((u32 *)info->pseudo_palette)[regno] =
1271 ((transp & 0xFF00) << 16) |
1272 ((red & 0xFF00) << 8) |
1273 ((green & 0xFF00)) |
1274 ((blue & 0xFF00) >> 8);
1280 /* Try blanking the screen. For flat panels it does nothing */
1281 static int tridentfb_blank(int blank_mode, struct fb_info *info)
1283 unsigned char PMCont, DPMSCont;
1284 struct tridentfb_par *par = info->par;
1289 t_outb(par, 0x04, 0x83C8); /* Read DPMS Control */
1290 PMCont = t_inb(par, 0x83C6) & 0xFC;
1291 DPMSCont = read3CE(par, PowerStatus) & 0xFC;
1292 switch (blank_mode) {
1293 case FB_BLANK_UNBLANK:
1294 /* Screen: On, HSync: On, VSync: On */
1295 case FB_BLANK_NORMAL:
1296 /* Screen: Off, HSync: On, VSync: On */
1300 case FB_BLANK_HSYNC_SUSPEND:
1301 /* Screen: Off, HSync: Off, VSync: On */
1305 case FB_BLANK_VSYNC_SUSPEND:
1306 /* Screen: Off, HSync: On, VSync: Off */
1310 case FB_BLANK_POWERDOWN:
1311 /* Screen: Off, HSync: Off, VSync: Off */
1317 write3CE(par, PowerStatus, DPMSCont);
1318 t_outb(par, 4, 0x83C8);
1319 t_outb(par, PMCont, 0x83C6);
1323 /* let fbcon do a softblank for us */
1324 return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
1327 static struct fb_ops tridentfb_ops = {
1328 .owner = THIS_MODULE,
1329 .fb_setcolreg = tridentfb_setcolreg,
1330 .fb_pan_display = tridentfb_pan_display,
1331 .fb_blank = tridentfb_blank,
1332 .fb_check_var = tridentfb_check_var,
1333 .fb_set_par = tridentfb_set_par,
1334 .fb_fillrect = tridentfb_fillrect,
1335 .fb_copyarea = tridentfb_copyarea,
1336 .fb_imageblit = tridentfb_imageblit,
1337 .fb_sync = tridentfb_sync,
1340 static int trident_pci_probe(struct pci_dev *dev,
1341 const struct pci_device_id *id)
1344 unsigned char revision;
1345 struct fb_info *info;
1346 struct tridentfb_par *default_par;
1350 err = pci_enable_device(dev);
1354 info = framebuffer_alloc(sizeof(struct tridentfb_par), &dev->dev);
1357 default_par = info->par;
1359 chip_id = id->device;
1361 /* If PCI id is 0x9660 then further detect chip type */
1363 if (chip_id == TGUI9660) {
1364 revision = vga_io_rseq(RevisionID);
1368 chip_id = PROVIDIA9685;
1372 chip_id = CYBER9397;
1375 chip_id = CYBER9397DVD;
1384 chip_id = CYBER9385;
1387 chip_id = CYBER9382;
1390 chip_id = CYBER9388;
1397 chip3D = is3Dchip(chip_id);
1399 if (is_xp(chip_id)) {
1400 default_par->init_accel = xp_init_accel;
1401 default_par->wait_engine = xp_wait_engine;
1402 default_par->fill_rect = xp_fill_rect;
1403 default_par->copy_rect = xp_copy_rect;
1404 tridentfb_fix.accel = FB_ACCEL_TRIDENT_BLADEXP;
1405 } else if (is_blade(chip_id)) {
1406 default_par->init_accel = blade_init_accel;
1407 default_par->wait_engine = blade_wait_engine;
1408 default_par->fill_rect = blade_fill_rect;
1409 default_par->copy_rect = blade_copy_rect;
1410 default_par->image_blit = blade_image_blit;
1411 tridentfb_fix.accel = FB_ACCEL_TRIDENT_BLADE3D;
1412 } else if (chip3D) { /* 3DImage family left */
1413 default_par->init_accel = image_init_accel;
1414 default_par->wait_engine = image_wait_engine;
1415 default_par->fill_rect = image_fill_rect;
1416 default_par->copy_rect = image_copy_rect;
1417 tridentfb_fix.accel = FB_ACCEL_TRIDENT_3DIMAGE;
1418 } else { /* TGUI 9440/96XX family */
1419 default_par->init_accel = tgui_init_accel;
1420 default_par->wait_engine = xp_wait_engine;
1421 default_par->fill_rect = tgui_fill_rect;
1422 default_par->copy_rect = tgui_copy_rect;
1423 tridentfb_fix.accel = FB_ACCEL_TRIDENT_TGUI;
1426 default_par->chip_id = chip_id;
1428 /* setup MMIO region */
1429 tridentfb_fix.mmio_start = pci_resource_start(dev, 1);
1430 tridentfb_fix.mmio_len = pci_resource_len(dev, 1);
1432 if (!request_mem_region(tridentfb_fix.mmio_start,
1433 tridentfb_fix.mmio_len, "tridentfb")) {
1434 debug("request_region failed!\n");
1435 framebuffer_release(info);
1439 default_par->io_virt = ioremap_nocache(tridentfb_fix.mmio_start,
1440 tridentfb_fix.mmio_len);
1442 if (!default_par->io_virt) {
1443 debug("ioremap failed\n");
1448 enable_mmio(default_par);
1450 /* setup framebuffer memory */
1451 tridentfb_fix.smem_start = pci_resource_start(dev, 0);
1452 tridentfb_fix.smem_len = get_memsize(default_par);
1454 if (!request_mem_region(tridentfb_fix.smem_start,
1455 tridentfb_fix.smem_len, "tridentfb")) {
1456 debug("request_mem_region failed!\n");
1457 disable_mmio(info->par);
1462 info->screen_base = ioremap_nocache(tridentfb_fix.smem_start,
1463 tridentfb_fix.smem_len);
1465 if (!info->screen_base) {
1466 debug("ioremap failed\n");
1471 default_par->flatpanel = is_flatpanel(default_par);
1473 if (default_par->flatpanel)
1474 nativex = get_nativex(default_par);
1476 info->fix = tridentfb_fix;
1477 info->fbops = &tridentfb_ops;
1478 info->pseudo_palette = default_par->pseudo_pal;
1480 info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
1481 if (!noaccel && default_par->init_accel) {
1482 info->flags &= ~FBINFO_HWACCEL_DISABLED;
1483 info->flags |= FBINFO_HWACCEL_COPYAREA;
1484 info->flags |= FBINFO_HWACCEL_FILLRECT;
1486 info->flags |= FBINFO_HWACCEL_DISABLED;
1488 if (is_blade(chip_id) && chip_id != BLADE3D)
1489 info->flags |= FBINFO_READS_FAST;
1491 info->pixmap.addr = kmalloc(4096, GFP_KERNEL);
1492 if (!info->pixmap.addr) {
1497 info->pixmap.size = 4096;
1498 info->pixmap.buf_align = 4;
1499 info->pixmap.scan_align = 1;
1500 info->pixmap.access_align = 32;
1501 info->pixmap.flags = FB_PIXMAP_SYSTEM;
1503 if (default_par->image_blit) {
1504 info->flags |= FBINFO_HWACCEL_IMAGEBLIT;
1505 info->pixmap.scan_align = 4;
1509 printk(KERN_DEBUG "disabling acceleration\n");
1510 info->flags |= FBINFO_HWACCEL_DISABLED;
1511 info->pixmap.scan_align = 1;
1514 if (!fb_find_mode(&info->var, info,
1515 mode_option, NULL, 0, NULL, bpp)) {
1519 err = fb_alloc_cmap(&info->cmap, 256, 0);
1523 info->var.activate |= FB_ACTIVATE_NOW;
1524 info->device = &dev->dev;
1525 if (register_framebuffer(info) < 0) {
1526 printk(KERN_ERR "tridentfb: could not register framebuffer\n");
1527 fb_dealloc_cmap(&info->cmap);
1531 output("fb%d: %s frame buffer device %dx%d-%dbpp\n",
1532 info->node, info->fix.id, info->var.xres,
1533 info->var.yres, info->var.bits_per_pixel);
1535 pci_set_drvdata(dev, info);
1539 kfree(info->pixmap.addr);
1540 if (info->screen_base)
1541 iounmap(info->screen_base);
1542 release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len);
1543 disable_mmio(info->par);
1545 if (default_par->io_virt)
1546 iounmap(default_par->io_virt);
1547 release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
1548 framebuffer_release(info);
1552 static void trident_pci_remove(struct pci_dev *dev)
1554 struct fb_info *info = pci_get_drvdata(dev);
1555 struct tridentfb_par *par = info->par;
1557 unregister_framebuffer(info);
1558 iounmap(par->io_virt);
1559 iounmap(info->screen_base);
1560 release_mem_region(tridentfb_fix.smem_start, tridentfb_fix.smem_len);
1561 release_mem_region(tridentfb_fix.mmio_start, tridentfb_fix.mmio_len);
1562 kfree(info->pixmap.addr);
1563 fb_dealloc_cmap(&info->cmap);
1564 framebuffer_release(info);
1567 /* List of boards that we are trying to support */
1568 static struct pci_device_id trident_devices[] = {
1569 {PCI_VENDOR_ID_TRIDENT, BLADE3D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1570 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1571 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi7D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1572 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1573 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1574 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1575 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEAi1D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1576 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEE4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1577 {PCI_VENDOR_ID_TRIDENT, TGUI9440, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1578 {PCI_VENDOR_ID_TRIDENT, TGUI9660, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1579 {PCI_VENDOR_ID_TRIDENT, IMAGE975, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1580 {PCI_VENDOR_ID_TRIDENT, IMAGE985, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1581 {PCI_VENDOR_ID_TRIDENT, CYBER9320, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1582 {PCI_VENDOR_ID_TRIDENT, CYBER9388, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1583 {PCI_VENDOR_ID_TRIDENT, CYBER9520, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1584 {PCI_VENDOR_ID_TRIDENT, CYBER9525DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1585 {PCI_VENDOR_ID_TRIDENT, CYBER9397, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1586 {PCI_VENDOR_ID_TRIDENT, CYBER9397DVD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1587 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPAi1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1588 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1589 {PCI_VENDOR_ID_TRIDENT, CYBERBLADEXPm16, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1593 MODULE_DEVICE_TABLE(pci, trident_devices);
1595 static struct pci_driver tridentfb_pci_driver = {
1596 .name = "tridentfb",
1597 .id_table = trident_devices,
1598 .probe = trident_pci_probe,
1599 .remove = trident_pci_remove,
1603 * Parse user specified options (`video=trident:')
1605 * video=trident:800x600,bpp=16,noaccel
1608 static int __init tridentfb_setup(char *options)
1611 if (!options || !*options)
1613 while ((opt = strsep(&options, ",")) != NULL) {
1616 if (!strncmp(opt, "noaccel", 7))
1618 else if (!strncmp(opt, "fp", 2))
1620 else if (!strncmp(opt, "crt", 3))
1622 else if (!strncmp(opt, "bpp=", 4))
1623 bpp = simple_strtoul(opt + 4, NULL, 0);
1624 else if (!strncmp(opt, "center", 6))
1626 else if (!strncmp(opt, "stretch", 7))
1628 else if (!strncmp(opt, "memsize=", 8))
1629 memsize = simple_strtoul(opt + 8, NULL, 0);
1630 else if (!strncmp(opt, "memdiff=", 8))
1631 memdiff = simple_strtoul(opt + 8, NULL, 0);
1632 else if (!strncmp(opt, "nativex=", 8))
1633 nativex = simple_strtoul(opt + 8, NULL, 0);
1641 static int __init tridentfb_init(void)
1644 char *option = NULL;
1646 if (fb_get_options("tridentfb", &option))
1648 tridentfb_setup(option);
1650 return pci_register_driver(&tridentfb_pci_driver);
1653 static void __exit tridentfb_exit(void)
1655 pci_unregister_driver(&tridentfb_pci_driver);
1658 module_init(tridentfb_init);
1659 module_exit(tridentfb_exit);
1661 MODULE_AUTHOR("Jani Monoses <jani@iv.ro>");
1662 MODULE_DESCRIPTION("Framebuffer driver for Trident cards");
1663 MODULE_LICENSE("GPL");
1664 MODULE_ALIAS("cyblafb");