2 * linux/drivers/video/omap2/dss/dispc.c
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * Some code and ideas taken from drivers/video/omap/ driver
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
23 #define DSS_SUBSYS_NAME "DISPC"
25 #include <linux/kernel.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/vmalloc.h>
28 #include <linux/export.h>
29 #include <linux/clk.h>
31 #include <linux/jiffies.h>
32 #include <linux/seq_file.h>
33 #include <linux/delay.h>
34 #include <linux/workqueue.h>
35 #include <linux/hardirq.h>
36 #include <linux/interrupt.h>
37 #include <linux/platform_device.h>
38 #include <linux/pm_runtime.h>
40 #include <plat/sram.h>
41 #include <plat/clock.h>
43 #include <video/omapdss.h>
46 #include "dss_features.h"
50 #define DISPC_SZ_REGS SZ_4K
52 #define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
54 DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
55 DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
56 DISPC_IRQ_SYNC_LOST | \
57 DISPC_IRQ_SYNC_LOST_DIGIT)
59 #define DISPC_MAX_NR_ISRS 8
61 struct omap_dispc_isr_data {
83 enum omap_burst_size {
89 #define REG_GET(idx, start, end) \
90 FLD_GET(dispc_read_reg(idx), start, end)
92 #define REG_FLD_MOD(idx, val, start, end) \
93 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
95 struct dispc_irq_stats {
96 unsigned long last_reset;
102 struct platform_device *pdev;
110 u32 fifo_size[MAX_DSS_OVERLAYS];
114 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
116 struct work_struct error_work;
119 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
121 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
122 spinlock_t irq_stats_lock;
123 struct dispc_irq_stats irq_stats;
127 enum omap_color_component {
128 /* used for all color formats for OMAP3 and earlier
129 * and for RGB and Y color component on OMAP4
131 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
132 /* used for UV component for
133 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
134 * color formats on OMAP4
136 DISPC_COLOR_COMPONENT_UV = 1 << 1,
139 static void _omap_dispc_set_irqs(void);
141 static inline void dispc_write_reg(const u16 idx, u32 val)
143 __raw_writel(val, dispc.base + idx);
146 static inline u32 dispc_read_reg(const u16 idx)
148 return __raw_readl(dispc.base + idx);
151 static int dispc_get_ctx_loss_count(void)
153 struct device *dev = &dispc.pdev->dev;
154 struct omap_display_platform_data *pdata = dev->platform_data;
155 struct omap_dss_board_info *board_data = pdata->board_data;
158 if (!board_data->get_context_loss_count)
161 cnt = board_data->get_context_loss_count(dev);
163 WARN_ONCE(cnt < 0, "get_context_loss_count failed: %d\n", cnt);
169 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
171 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
173 static void dispc_save_context(void)
177 DSSDBG("dispc_save_context\n");
183 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
184 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
186 if (dss_has_feature(FEAT_MGR_LCD2)) {
191 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
192 SR(DEFAULT_COLOR(i));
195 if (i == OMAP_DSS_CHANNEL_DIGIT)
206 if (dss_has_feature(FEAT_CPR)) {
213 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
218 SR(OVL_ATTRIBUTES(i));
219 SR(OVL_FIFO_THRESHOLD(i));
221 SR(OVL_PIXEL_INC(i));
222 if (dss_has_feature(FEAT_PRELOAD))
224 if (i == OMAP_DSS_GFX) {
225 SR(OVL_WINDOW_SKIP(i));
230 SR(OVL_PICTURE_SIZE(i));
234 for (j = 0; j < 8; j++)
235 SR(OVL_FIR_COEF_H(i, j));
237 for (j = 0; j < 8; j++)
238 SR(OVL_FIR_COEF_HV(i, j));
240 for (j = 0; j < 5; j++)
241 SR(OVL_CONV_COEF(i, j));
243 if (dss_has_feature(FEAT_FIR_COEF_V)) {
244 for (j = 0; j < 8; j++)
245 SR(OVL_FIR_COEF_V(i, j));
248 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
255 for (j = 0; j < 8; j++)
256 SR(OVL_FIR_COEF_H2(i, j));
258 for (j = 0; j < 8; j++)
259 SR(OVL_FIR_COEF_HV2(i, j));
261 for (j = 0; j < 8; j++)
262 SR(OVL_FIR_COEF_V2(i, j));
264 if (dss_has_feature(FEAT_ATTR2))
265 SR(OVL_ATTRIBUTES2(i));
268 if (dss_has_feature(FEAT_CORE_CLK_DIV))
271 dispc.ctx_loss_cnt = dispc_get_ctx_loss_count();
272 dispc.ctx_valid = true;
274 DSSDBG("context saved, ctx_loss_count %d\n", dispc.ctx_loss_cnt);
277 static void dispc_restore_context(void)
281 DSSDBG("dispc_restore_context\n");
283 if (!dispc.ctx_valid)
286 ctx = dispc_get_ctx_loss_count();
288 if (ctx >= 0 && ctx == dispc.ctx_loss_cnt)
291 DSSDBG("ctx_loss_count: saved %d, current %d\n",
292 dispc.ctx_loss_cnt, ctx);
298 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
299 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
301 if (dss_has_feature(FEAT_MGR_LCD2))
304 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
305 RR(DEFAULT_COLOR(i));
308 if (i == OMAP_DSS_CHANNEL_DIGIT)
319 if (dss_has_feature(FEAT_CPR)) {
326 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
331 RR(OVL_ATTRIBUTES(i));
332 RR(OVL_FIFO_THRESHOLD(i));
334 RR(OVL_PIXEL_INC(i));
335 if (dss_has_feature(FEAT_PRELOAD))
337 if (i == OMAP_DSS_GFX) {
338 RR(OVL_WINDOW_SKIP(i));
343 RR(OVL_PICTURE_SIZE(i));
347 for (j = 0; j < 8; j++)
348 RR(OVL_FIR_COEF_H(i, j));
350 for (j = 0; j < 8; j++)
351 RR(OVL_FIR_COEF_HV(i, j));
353 for (j = 0; j < 5; j++)
354 RR(OVL_CONV_COEF(i, j));
356 if (dss_has_feature(FEAT_FIR_COEF_V)) {
357 for (j = 0; j < 8; j++)
358 RR(OVL_FIR_COEF_V(i, j));
361 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
368 for (j = 0; j < 8; j++)
369 RR(OVL_FIR_COEF_H2(i, j));
371 for (j = 0; j < 8; j++)
372 RR(OVL_FIR_COEF_HV2(i, j));
374 for (j = 0; j < 8; j++)
375 RR(OVL_FIR_COEF_V2(i, j));
377 if (dss_has_feature(FEAT_ATTR2))
378 RR(OVL_ATTRIBUTES2(i));
381 if (dss_has_feature(FEAT_CORE_CLK_DIV))
384 /* enable last, because LCD & DIGIT enable are here */
386 if (dss_has_feature(FEAT_MGR_LCD2))
388 /* clear spurious SYNC_LOST_DIGIT interrupts */
389 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
392 * enable last so IRQs won't trigger before
393 * the context is fully restored
397 DSSDBG("context restored\n");
403 int dispc_runtime_get(void)
407 DSSDBG("dispc_runtime_get\n");
409 r = pm_runtime_get_sync(&dispc.pdev->dev);
411 return r < 0 ? r : 0;
414 void dispc_runtime_put(void)
418 DSSDBG("dispc_runtime_put\n");
420 r = pm_runtime_put(&dispc.pdev->dev);
424 static inline bool dispc_mgr_is_lcd(enum omap_channel channel)
426 if (channel == OMAP_DSS_CHANNEL_LCD ||
427 channel == OMAP_DSS_CHANNEL_LCD2)
433 static struct omap_dss_device *dispc_mgr_get_device(enum omap_channel channel)
435 struct omap_overlay_manager *mgr =
436 omap_dss_get_overlay_manager(channel);
438 return mgr ? mgr->device : NULL;
441 bool dispc_mgr_go_busy(enum omap_channel channel)
445 if (dispc_mgr_is_lcd(channel))
448 bit = 6; /* GODIGIT */
450 if (channel == OMAP_DSS_CHANNEL_LCD2)
451 return REG_GET(DISPC_CONTROL2, bit, bit) == 1;
453 return REG_GET(DISPC_CONTROL, bit, bit) == 1;
456 void dispc_mgr_go(enum omap_channel channel)
459 bool enable_bit, go_bit;
461 if (dispc_mgr_is_lcd(channel))
462 bit = 0; /* LCDENABLE */
464 bit = 1; /* DIGITALENABLE */
466 /* if the channel is not enabled, we don't need GO */
467 if (channel == OMAP_DSS_CHANNEL_LCD2)
468 enable_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
470 enable_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
475 if (dispc_mgr_is_lcd(channel))
478 bit = 6; /* GODIGIT */
480 if (channel == OMAP_DSS_CHANNEL_LCD2)
481 go_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
483 go_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
486 DSSERR("GO bit not down for channel %d\n", channel);
490 DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" :
491 (channel == OMAP_DSS_CHANNEL_LCD2 ? "LCD2" : "DIGIT"));
493 if (channel == OMAP_DSS_CHANNEL_LCD2)
494 REG_FLD_MOD(DISPC_CONTROL2, 1, bit, bit);
496 REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
499 static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
501 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
504 static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
506 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
509 static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
511 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
514 static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
516 BUG_ON(plane == OMAP_DSS_GFX);
518 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
521 static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
524 BUG_ON(plane == OMAP_DSS_GFX);
526 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
529 static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
531 BUG_ON(plane == OMAP_DSS_GFX);
533 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
536 static void dispc_ovl_set_scale_coef(enum omap_plane plane, int hscaleup,
537 int vscaleup, int five_taps,
538 enum omap_color_component color_comp)
540 /* Coefficients for horizontal up-sampling */
541 static const struct dispc_h_coef coef_hup[8] = {
543 { -1, 13, 124, -8, 0 },
544 { -2, 30, 112, -11, -1 },
545 { -5, 51, 95, -11, -2 },
546 { 0, -9, 73, 73, -9 },
547 { -2, -11, 95, 51, -5 },
548 { -1, -11, 112, 30, -2 },
549 { 0, -8, 124, 13, -1 },
552 /* Coefficients for vertical up-sampling */
553 static const struct dispc_v_coef coef_vup_3tap[8] = {
556 { 0, 12, 111, 5, 0 },
560 { 0, 5, 111, 12, 0 },
564 static const struct dispc_v_coef coef_vup_5tap[8] = {
566 { -1, 13, 124, -8, 0 },
567 { -2, 30, 112, -11, -1 },
568 { -5, 51, 95, -11, -2 },
569 { 0, -9, 73, 73, -9 },
570 { -2, -11, 95, 51, -5 },
571 { -1, -11, 112, 30, -2 },
572 { 0, -8, 124, 13, -1 },
575 /* Coefficients for horizontal down-sampling */
576 static const struct dispc_h_coef coef_hdown[8] = {
577 { 0, 36, 56, 36, 0 },
578 { 4, 40, 55, 31, -2 },
579 { 8, 44, 54, 27, -5 },
580 { 12, 48, 53, 22, -7 },
581 { -9, 17, 52, 51, 17 },
582 { -7, 22, 53, 48, 12 },
583 { -5, 27, 54, 44, 8 },
584 { -2, 31, 55, 40, 4 },
587 /* Coefficients for vertical down-sampling */
588 static const struct dispc_v_coef coef_vdown_3tap[8] = {
589 { 0, 36, 56, 36, 0 },
590 { 0, 40, 57, 31, 0 },
591 { 0, 45, 56, 27, 0 },
592 { 0, 50, 55, 23, 0 },
593 { 0, 18, 55, 55, 0 },
594 { 0, 23, 55, 50, 0 },
595 { 0, 27, 56, 45, 0 },
596 { 0, 31, 57, 40, 0 },
599 static const struct dispc_v_coef coef_vdown_5tap[8] = {
600 { 0, 36, 56, 36, 0 },
601 { 4, 40, 55, 31, -2 },
602 { 8, 44, 54, 27, -5 },
603 { 12, 48, 53, 22, -7 },
604 { -9, 17, 52, 51, 17 },
605 { -7, 22, 53, 48, 12 },
606 { -5, 27, 54, 44, 8 },
607 { -2, 31, 55, 40, 4 },
610 const struct dispc_h_coef *h_coef;
611 const struct dispc_v_coef *v_coef;
620 v_coef = five_taps ? coef_vup_5tap : coef_vup_3tap;
622 v_coef = five_taps ? coef_vdown_5tap : coef_vdown_3tap;
624 for (i = 0; i < 8; i++) {
627 h = FLD_VAL(h_coef[i].hc0, 7, 0)
628 | FLD_VAL(h_coef[i].hc1, 15, 8)
629 | FLD_VAL(h_coef[i].hc2, 23, 16)
630 | FLD_VAL(h_coef[i].hc3, 31, 24);
631 hv = FLD_VAL(h_coef[i].hc4, 7, 0)
632 | FLD_VAL(v_coef[i].vc0, 15, 8)
633 | FLD_VAL(v_coef[i].vc1, 23, 16)
634 | FLD_VAL(v_coef[i].vc2, 31, 24);
636 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
637 dispc_ovl_write_firh_reg(plane, i, h);
638 dispc_ovl_write_firhv_reg(plane, i, hv);
640 dispc_ovl_write_firh2_reg(plane, i, h);
641 dispc_ovl_write_firhv2_reg(plane, i, hv);
647 for (i = 0; i < 8; i++) {
649 v = FLD_VAL(v_coef[i].vc00, 7, 0)
650 | FLD_VAL(v_coef[i].vc22, 15, 8);
651 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
652 dispc_ovl_write_firv_reg(plane, i, v);
654 dispc_ovl_write_firv2_reg(plane, i, v);
659 static void _dispc_setup_color_conv_coef(void)
662 const struct color_conv_coef {
663 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
666 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
669 const struct color_conv_coef *ct;
671 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
675 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
676 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 0),
677 CVAL(ct->rcr, ct->ry));
678 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 1),
679 CVAL(ct->gy, ct->rcb));
680 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 2),
681 CVAL(ct->gcb, ct->gcr));
682 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 3),
683 CVAL(ct->bcr, ct->by));
684 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 4),
687 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), ct->full_range,
695 static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
697 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
700 static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
702 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
705 static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
707 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
710 static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
712 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
715 static void dispc_ovl_set_pos(enum omap_plane plane, int x, int y)
717 u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
719 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
722 static void dispc_ovl_set_pic_size(enum omap_plane plane, int width, int height)
724 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
726 if (plane == OMAP_DSS_GFX)
727 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
729 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
732 static void dispc_ovl_set_vid_size(enum omap_plane plane, int width, int height)
736 BUG_ON(plane == OMAP_DSS_GFX);
738 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
740 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
743 static void dispc_ovl_set_zorder(enum omap_plane plane, u8 zorder)
745 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
747 if ((ovl->caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
750 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
753 static void dispc_ovl_enable_zorder_planes(void)
757 if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
760 for (i = 0; i < dss_feat_get_num_ovls(); i++)
761 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
764 static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane, bool enable)
766 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
768 if ((ovl->caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
771 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
774 static void dispc_ovl_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
776 static const unsigned shifts[] = { 0, 8, 16, 24, };
778 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
780 if ((ovl->caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
783 shift = shifts[plane];
784 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
787 static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
789 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
792 static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
794 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
797 static void dispc_ovl_set_color_mode(enum omap_plane plane,
798 enum omap_color_mode color_mode)
801 if (plane != OMAP_DSS_GFX) {
802 switch (color_mode) {
803 case OMAP_DSS_COLOR_NV12:
805 case OMAP_DSS_COLOR_RGB12U:
807 case OMAP_DSS_COLOR_RGBA16:
809 case OMAP_DSS_COLOR_RGBX16:
811 case OMAP_DSS_COLOR_ARGB16:
813 case OMAP_DSS_COLOR_RGB16:
815 case OMAP_DSS_COLOR_ARGB16_1555:
817 case OMAP_DSS_COLOR_RGB24U:
819 case OMAP_DSS_COLOR_RGB24P:
821 case OMAP_DSS_COLOR_YUV2:
823 case OMAP_DSS_COLOR_UYVY:
825 case OMAP_DSS_COLOR_ARGB32:
827 case OMAP_DSS_COLOR_RGBA32:
829 case OMAP_DSS_COLOR_RGBX32:
831 case OMAP_DSS_COLOR_XRGB16_1555:
837 switch (color_mode) {
838 case OMAP_DSS_COLOR_CLUT1:
840 case OMAP_DSS_COLOR_CLUT2:
842 case OMAP_DSS_COLOR_CLUT4:
844 case OMAP_DSS_COLOR_CLUT8:
846 case OMAP_DSS_COLOR_RGB12U:
848 case OMAP_DSS_COLOR_ARGB16:
850 case OMAP_DSS_COLOR_RGB16:
852 case OMAP_DSS_COLOR_ARGB16_1555:
854 case OMAP_DSS_COLOR_RGB24U:
856 case OMAP_DSS_COLOR_RGB24P:
858 case OMAP_DSS_COLOR_YUV2:
860 case OMAP_DSS_COLOR_UYVY:
862 case OMAP_DSS_COLOR_ARGB32:
864 case OMAP_DSS_COLOR_RGBA32:
866 case OMAP_DSS_COLOR_RGBX32:
868 case OMAP_DSS_COLOR_XRGB16_1555:
875 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
878 void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
882 int chan = 0, chan2 = 0;
888 case OMAP_DSS_VIDEO1:
889 case OMAP_DSS_VIDEO2:
890 case OMAP_DSS_VIDEO3:
898 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
899 if (dss_has_feature(FEAT_MGR_LCD2)) {
901 case OMAP_DSS_CHANNEL_LCD:
905 case OMAP_DSS_CHANNEL_DIGIT:
909 case OMAP_DSS_CHANNEL_LCD2:
917 val = FLD_MOD(val, chan, shift, shift);
918 val = FLD_MOD(val, chan2, 31, 30);
920 val = FLD_MOD(val, channel, shift, shift);
922 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
925 static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
929 enum omap_channel channel;
935 case OMAP_DSS_VIDEO1:
936 case OMAP_DSS_VIDEO2:
937 case OMAP_DSS_VIDEO3:
944 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
946 if (dss_has_feature(FEAT_MGR_LCD2)) {
947 if (FLD_GET(val, 31, 30) == 0)
948 channel = FLD_GET(val, shift, shift);
950 channel = OMAP_DSS_CHANNEL_LCD2;
952 channel = FLD_GET(val, shift, shift);
958 static void dispc_ovl_set_burst_size(enum omap_plane plane,
959 enum omap_burst_size burst_size)
961 static const unsigned shifts[] = { 6, 14, 14, 14, };
964 shift = shifts[plane];
965 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
968 static void dispc_configure_burst_sizes(void)
971 const int burst_size = BURST_SIZE_X8;
973 /* Configure burst size always to maximum size */
974 for (i = 0; i < omap_dss_get_num_overlays(); ++i)
975 dispc_ovl_set_burst_size(i, burst_size);
978 u32 dispc_ovl_get_burst_size(enum omap_plane plane)
980 unsigned unit = dss_feat_get_burst_size_unit();
981 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
985 void dispc_enable_gamma_table(bool enable)
988 * This is partially implemented to support only disabling of
992 DSSWARN("Gamma table enabling for TV not yet supported");
996 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
999 static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
1003 if (channel == OMAP_DSS_CHANNEL_LCD)
1005 else if (channel == OMAP_DSS_CHANNEL_LCD2)
1006 reg = DISPC_CONFIG2;
1010 REG_FLD_MOD(reg, enable, 15, 15);
1013 static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
1014 struct omap_dss_cpr_coefs *coefs)
1016 u32 coef_r, coef_g, coef_b;
1018 if (!dispc_mgr_is_lcd(channel))
1021 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
1022 FLD_VAL(coefs->rb, 9, 0);
1023 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
1024 FLD_VAL(coefs->gb, 9, 0);
1025 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
1026 FLD_VAL(coefs->bb, 9, 0);
1028 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
1029 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
1030 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
1033 static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
1037 BUG_ON(plane == OMAP_DSS_GFX);
1039 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1040 val = FLD_MOD(val, enable, 9, 9);
1041 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
1044 static void dispc_ovl_enable_replication(enum omap_plane plane, bool enable)
1046 static const unsigned shifts[] = { 5, 10, 10, 10 };
1049 shift = shifts[plane];
1050 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
1053 void dispc_mgr_set_lcd_size(enum omap_channel channel, u16 width, u16 height)
1056 BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
1057 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
1058 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
1061 void dispc_set_digit_size(u16 width, u16 height)
1064 BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
1065 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
1066 dispc_write_reg(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT), val);
1069 static void dispc_read_plane_fifo_sizes(void)
1076 unit = dss_feat_get_buffer_size_unit();
1078 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
1080 for (plane = 0; plane < dss_feat_get_num_ovls(); ++plane) {
1081 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(plane), start, end);
1083 dispc.fifo_size[plane] = size;
1087 u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
1089 return dispc.fifo_size[plane];
1092 void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
1094 u8 hi_start, hi_end, lo_start, lo_end;
1097 unit = dss_feat_get_buffer_size_unit();
1099 WARN_ON(low % unit != 0);
1100 WARN_ON(high % unit != 0);
1105 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1106 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1108 DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n",
1110 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1112 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1116 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
1117 FLD_VAL(high, hi_start, hi_end) |
1118 FLD_VAL(low, lo_start, lo_end));
1121 void dispc_enable_fifomerge(bool enable)
1123 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1124 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1127 static void dispc_ovl_set_fir(enum omap_plane plane,
1129 enum omap_color_component color_comp)
1133 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1134 u8 hinc_start, hinc_end, vinc_start, vinc_end;
1136 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1137 &hinc_start, &hinc_end);
1138 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1139 &vinc_start, &vinc_end);
1140 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1141 FLD_VAL(hinc, hinc_start, hinc_end);
1143 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1145 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1146 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1150 static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1153 u8 hor_start, hor_end, vert_start, vert_end;
1155 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1156 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1158 val = FLD_VAL(vaccu, vert_start, vert_end) |
1159 FLD_VAL(haccu, hor_start, hor_end);
1161 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
1164 static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1167 u8 hor_start, hor_end, vert_start, vert_end;
1169 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1170 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1172 val = FLD_VAL(vaccu, vert_start, vert_end) |
1173 FLD_VAL(haccu, hor_start, hor_end);
1175 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
1178 static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1183 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1184 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1187 static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1192 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1193 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1196 static void dispc_ovl_set_scale_param(enum omap_plane plane,
1197 u16 orig_width, u16 orig_height,
1198 u16 out_width, u16 out_height,
1199 bool five_taps, u8 rotation,
1200 enum omap_color_component color_comp)
1202 int fir_hinc, fir_vinc;
1203 int hscaleup, vscaleup;
1205 hscaleup = orig_width <= out_width;
1206 vscaleup = orig_height <= out_height;
1208 dispc_ovl_set_scale_coef(plane, hscaleup, vscaleup, five_taps,
1211 fir_hinc = 1024 * orig_width / out_width;
1212 fir_vinc = 1024 * orig_height / out_height;
1214 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
1217 static void dispc_ovl_set_scaling_common(enum omap_plane plane,
1218 u16 orig_width, u16 orig_height,
1219 u16 out_width, u16 out_height,
1220 bool ilace, bool five_taps,
1221 bool fieldmode, enum omap_color_mode color_mode,
1228 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1229 out_width, out_height, five_taps,
1230 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
1231 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1233 /* RESIZEENABLE and VERTICALTAPS */
1234 l &= ~((0x3 << 5) | (0x1 << 21));
1235 l |= (orig_width != out_width) ? (1 << 5) : 0;
1236 l |= (orig_height != out_height) ? (1 << 6) : 0;
1237 l |= five_taps ? (1 << 21) : 0;
1239 /* VRESIZECONF and HRESIZECONF */
1240 if (dss_has_feature(FEAT_RESIZECONF)) {
1242 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1243 l |= (orig_height <= out_height) ? 0 : (1 << 8);
1246 /* LINEBUFFERSPLIT */
1247 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1249 l |= five_taps ? (1 << 22) : 0;
1252 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
1255 * field 0 = even field = bottom field
1256 * field 1 = odd field = top field
1258 if (ilace && !fieldmode) {
1260 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
1261 if (accu0 >= 1024/2) {
1267 dispc_ovl_set_vid_accu0(plane, 0, accu0);
1268 dispc_ovl_set_vid_accu1(plane, 0, accu1);
1271 static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
1272 u16 orig_width, u16 orig_height,
1273 u16 out_width, u16 out_height,
1274 bool ilace, bool five_taps,
1275 bool fieldmode, enum omap_color_mode color_mode,
1278 int scale_x = out_width != orig_width;
1279 int scale_y = out_height != orig_height;
1281 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1283 if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1284 color_mode != OMAP_DSS_COLOR_UYVY &&
1285 color_mode != OMAP_DSS_COLOR_NV12)) {
1286 /* reset chroma resampling for RGB formats */
1287 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1290 switch (color_mode) {
1291 case OMAP_DSS_COLOR_NV12:
1292 /* UV is subsampled by 2 vertically*/
1294 /* UV is subsampled by 2 horz.*/
1297 case OMAP_DSS_COLOR_YUV2:
1298 case OMAP_DSS_COLOR_UYVY:
1299 /*For YUV422 with 90/270 rotation,
1300 *we don't upsample chroma
1302 if (rotation == OMAP_DSS_ROT_0 ||
1303 rotation == OMAP_DSS_ROT_180)
1304 /* UV is subsampled by 2 hrz*/
1306 /* must use FIR for YUV422 if rotated */
1307 if (rotation != OMAP_DSS_ROT_0)
1308 scale_x = scale_y = true;
1314 if (out_width != orig_width)
1316 if (out_height != orig_height)
1319 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1320 out_width, out_height, five_taps,
1321 rotation, DISPC_COLOR_COMPONENT_UV);
1323 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1324 (scale_x || scale_y) ? 1 : 0, 8, 8);
1326 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1328 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1330 dispc_ovl_set_vid_accu2_0(plane, 0x80, 0);
1331 dispc_ovl_set_vid_accu2_1(plane, 0x80, 0);
1334 static void dispc_ovl_set_scaling(enum omap_plane plane,
1335 u16 orig_width, u16 orig_height,
1336 u16 out_width, u16 out_height,
1337 bool ilace, bool five_taps,
1338 bool fieldmode, enum omap_color_mode color_mode,
1341 BUG_ON(plane == OMAP_DSS_GFX);
1343 dispc_ovl_set_scaling_common(plane,
1344 orig_width, orig_height,
1345 out_width, out_height,
1347 fieldmode, color_mode,
1350 dispc_ovl_set_scaling_uv(plane,
1351 orig_width, orig_height,
1352 out_width, out_height,
1354 fieldmode, color_mode,
1358 static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1359 bool mirroring, enum omap_color_mode color_mode)
1361 bool row_repeat = false;
1364 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1365 color_mode == OMAP_DSS_COLOR_UYVY) {
1369 case OMAP_DSS_ROT_0:
1372 case OMAP_DSS_ROT_90:
1375 case OMAP_DSS_ROT_180:
1378 case OMAP_DSS_ROT_270:
1384 case OMAP_DSS_ROT_0:
1387 case OMAP_DSS_ROT_90:
1390 case OMAP_DSS_ROT_180:
1393 case OMAP_DSS_ROT_270:
1399 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
1405 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
1406 if (dss_has_feature(FEAT_ROWREPEATENABLE))
1407 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1408 row_repeat ? 1 : 0, 18, 18);
1411 static int color_mode_to_bpp(enum omap_color_mode color_mode)
1413 switch (color_mode) {
1414 case OMAP_DSS_COLOR_CLUT1:
1416 case OMAP_DSS_COLOR_CLUT2:
1418 case OMAP_DSS_COLOR_CLUT4:
1420 case OMAP_DSS_COLOR_CLUT8:
1421 case OMAP_DSS_COLOR_NV12:
1423 case OMAP_DSS_COLOR_RGB12U:
1424 case OMAP_DSS_COLOR_RGB16:
1425 case OMAP_DSS_COLOR_ARGB16:
1426 case OMAP_DSS_COLOR_YUV2:
1427 case OMAP_DSS_COLOR_UYVY:
1428 case OMAP_DSS_COLOR_RGBA16:
1429 case OMAP_DSS_COLOR_RGBX16:
1430 case OMAP_DSS_COLOR_ARGB16_1555:
1431 case OMAP_DSS_COLOR_XRGB16_1555:
1433 case OMAP_DSS_COLOR_RGB24P:
1435 case OMAP_DSS_COLOR_RGB24U:
1436 case OMAP_DSS_COLOR_ARGB32:
1437 case OMAP_DSS_COLOR_RGBA32:
1438 case OMAP_DSS_COLOR_RGBX32:
1445 static s32 pixinc(int pixels, u8 ps)
1449 else if (pixels > 1)
1450 return 1 + (pixels - 1) * ps;
1451 else if (pixels < 0)
1452 return 1 - (-pixels + 1) * ps;
1457 static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1459 u16 width, u16 height,
1460 enum omap_color_mode color_mode, bool fieldmode,
1461 unsigned int field_offset,
1462 unsigned *offset0, unsigned *offset1,
1463 s32 *row_inc, s32 *pix_inc)
1467 /* FIXME CLUT formats */
1468 switch (color_mode) {
1469 case OMAP_DSS_COLOR_CLUT1:
1470 case OMAP_DSS_COLOR_CLUT2:
1471 case OMAP_DSS_COLOR_CLUT4:
1472 case OMAP_DSS_COLOR_CLUT8:
1475 case OMAP_DSS_COLOR_YUV2:
1476 case OMAP_DSS_COLOR_UYVY:
1480 ps = color_mode_to_bpp(color_mode) / 8;
1484 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1488 * field 0 = even field = bottom field
1489 * field 1 = odd field = top field
1491 switch (rotation + mirror * 4) {
1492 case OMAP_DSS_ROT_0:
1493 case OMAP_DSS_ROT_180:
1495 * If the pixel format is YUV or UYVY divide the width
1496 * of the image by 2 for 0 and 180 degree rotation.
1498 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1499 color_mode == OMAP_DSS_COLOR_UYVY)
1501 case OMAP_DSS_ROT_90:
1502 case OMAP_DSS_ROT_270:
1505 *offset0 = field_offset * screen_width * ps;
1509 *row_inc = pixinc(1 + (screen_width - width) +
1510 (fieldmode ? screen_width : 0),
1512 *pix_inc = pixinc(1, ps);
1515 case OMAP_DSS_ROT_0 + 4:
1516 case OMAP_DSS_ROT_180 + 4:
1517 /* If the pixel format is YUV or UYVY divide the width
1518 * of the image by 2 for 0 degree and 180 degree
1520 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1521 color_mode == OMAP_DSS_COLOR_UYVY)
1523 case OMAP_DSS_ROT_90 + 4:
1524 case OMAP_DSS_ROT_270 + 4:
1527 *offset0 = field_offset * screen_width * ps;
1530 *row_inc = pixinc(1 - (screen_width + width) -
1531 (fieldmode ? screen_width : 0),
1533 *pix_inc = pixinc(1, ps);
1541 static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1543 u16 width, u16 height,
1544 enum omap_color_mode color_mode, bool fieldmode,
1545 unsigned int field_offset,
1546 unsigned *offset0, unsigned *offset1,
1547 s32 *row_inc, s32 *pix_inc)
1552 /* FIXME CLUT formats */
1553 switch (color_mode) {
1554 case OMAP_DSS_COLOR_CLUT1:
1555 case OMAP_DSS_COLOR_CLUT2:
1556 case OMAP_DSS_COLOR_CLUT4:
1557 case OMAP_DSS_COLOR_CLUT8:
1561 ps = color_mode_to_bpp(color_mode) / 8;
1565 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1568 /* width & height are overlay sizes, convert to fb sizes */
1570 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1579 * field 0 = even field = bottom field
1580 * field 1 = odd field = top field
1582 switch (rotation + mirror * 4) {
1583 case OMAP_DSS_ROT_0:
1586 *offset0 = *offset1 + field_offset * screen_width * ps;
1588 *offset0 = *offset1;
1589 *row_inc = pixinc(1 + (screen_width - fbw) +
1590 (fieldmode ? screen_width : 0),
1592 *pix_inc = pixinc(1, ps);
1594 case OMAP_DSS_ROT_90:
1595 *offset1 = screen_width * (fbh - 1) * ps;
1597 *offset0 = *offset1 + field_offset * ps;
1599 *offset0 = *offset1;
1600 *row_inc = pixinc(screen_width * (fbh - 1) + 1 +
1601 (fieldmode ? 1 : 0), ps);
1602 *pix_inc = pixinc(-screen_width, ps);
1604 case OMAP_DSS_ROT_180:
1605 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1607 *offset0 = *offset1 - field_offset * screen_width * ps;
1609 *offset0 = *offset1;
1610 *row_inc = pixinc(-1 -
1611 (screen_width - fbw) -
1612 (fieldmode ? screen_width : 0),
1614 *pix_inc = pixinc(-1, ps);
1616 case OMAP_DSS_ROT_270:
1617 *offset1 = (fbw - 1) * ps;
1619 *offset0 = *offset1 - field_offset * ps;
1621 *offset0 = *offset1;
1622 *row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
1623 (fieldmode ? 1 : 0), ps);
1624 *pix_inc = pixinc(screen_width, ps);
1628 case OMAP_DSS_ROT_0 + 4:
1629 *offset1 = (fbw - 1) * ps;
1631 *offset0 = *offset1 + field_offset * screen_width * ps;
1633 *offset0 = *offset1;
1634 *row_inc = pixinc(screen_width * 2 - 1 +
1635 (fieldmode ? screen_width : 0),
1637 *pix_inc = pixinc(-1, ps);
1640 case OMAP_DSS_ROT_90 + 4:
1643 *offset0 = *offset1 + field_offset * ps;
1645 *offset0 = *offset1;
1646 *row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
1647 (fieldmode ? 1 : 0),
1649 *pix_inc = pixinc(screen_width, ps);
1652 case OMAP_DSS_ROT_180 + 4:
1653 *offset1 = screen_width * (fbh - 1) * ps;
1655 *offset0 = *offset1 - field_offset * screen_width * ps;
1657 *offset0 = *offset1;
1658 *row_inc = pixinc(1 - screen_width * 2 -
1659 (fieldmode ? screen_width : 0),
1661 *pix_inc = pixinc(1, ps);
1664 case OMAP_DSS_ROT_270 + 4:
1665 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1667 *offset0 = *offset1 - field_offset * ps;
1669 *offset0 = *offset1;
1670 *row_inc = pixinc(screen_width * (fbh - 1) - 1 -
1671 (fieldmode ? 1 : 0),
1673 *pix_inc = pixinc(-screen_width, ps);
1681 static unsigned long calc_fclk_five_taps(enum omap_channel channel, u16 width,
1682 u16 height, u16 out_width, u16 out_height,
1683 enum omap_color_mode color_mode)
1686 u64 tmp, pclk = dispc_mgr_pclk_rate(channel);
1688 if (height > out_height) {
1689 struct omap_dss_device *dssdev = dispc_mgr_get_device(channel);
1690 unsigned int ppl = dssdev->panel.timings.x_res;
1692 tmp = pclk * height * out_width;
1693 do_div(tmp, 2 * out_height * ppl);
1696 if (height > 2 * out_height) {
1697 if (ppl == out_width)
1700 tmp = pclk * (height - 2 * out_height) * out_width;
1701 do_div(tmp, 2 * out_height * (ppl - out_width));
1702 fclk = max(fclk, (u32) tmp);
1706 if (width > out_width) {
1708 do_div(tmp, out_width);
1709 fclk = max(fclk, (u32) tmp);
1711 if (color_mode == OMAP_DSS_COLOR_RGB24U)
1718 static unsigned long calc_fclk(enum omap_channel channel, u16 width,
1719 u16 height, u16 out_width, u16 out_height)
1721 unsigned int hf, vf;
1724 * FIXME how to determine the 'A' factor
1725 * for the no downscaling case ?
1728 if (width > 3 * out_width)
1730 else if (width > 2 * out_width)
1732 else if (width > out_width)
1737 if (height > out_height)
1742 return dispc_mgr_pclk_rate(channel) * vf * hf;
1745 static int dispc_ovl_calc_scaling(enum omap_plane plane,
1746 enum omap_channel channel, u16 width, u16 height,
1747 u16 out_width, u16 out_height,
1748 enum omap_color_mode color_mode, bool *five_taps)
1750 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
1751 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
1752 unsigned long fclk = 0;
1754 if (width == out_width && height == out_height)
1757 if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
1760 if (out_width < width / maxdownscale ||
1761 out_width > width * 8)
1764 if (out_height < height / maxdownscale ||
1765 out_height > height * 8)
1768 /* Must use 5-tap filter? */
1769 *five_taps = height > out_height * 2;
1772 fclk = calc_fclk(channel, width, height, out_width,
1775 /* Try 5-tap filter if 3-tap fclk is too high */
1776 if (cpu_is_omap34xx() && height > out_height &&
1777 fclk > dispc_fclk_rate())
1781 if (width > (2048 >> *five_taps)) {
1782 DSSERR("failed to set up scaling, fclk too low\n");
1787 fclk = calc_fclk_five_taps(channel, width, height,
1788 out_width, out_height, color_mode);
1790 DSSDBG("required fclk rate = %lu Hz\n", fclk);
1791 DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
1793 if (!fclk || fclk > dispc_fclk_rate()) {
1794 DSSERR("failed to set up scaling, "
1795 "required fclk rate = %lu Hz, "
1796 "current fclk rate = %lu Hz\n",
1797 fclk, dispc_fclk_rate());
1804 int dispc_ovl_setup(enum omap_plane plane, struct omap_overlay_info *oi,
1805 bool ilace, bool replication)
1807 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
1808 bool five_taps = false;
1811 unsigned offset0, offset1;
1814 u16 frame_height = oi->height;
1815 unsigned int field_offset = 0;
1817 enum omap_channel channel;
1819 channel = dispc_ovl_get_channel_out(plane);
1821 DSSDBG("dispc_ovl_setup %d, pa %x, pa_uv %x, sw %d, %d,%d, %dx%d -> "
1822 "%dx%d, cmode %x, rot %d, mir %d, ilace %d chan %d repl %d\n",
1823 plane, oi->paddr, oi->p_uv_addr,
1824 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
1825 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
1826 oi->mirror, ilace, channel, replication);
1831 outw = oi->out_width == 0 ? oi->width : oi->out_width;
1832 outh = oi->out_height == 0 ? oi->height : oi->out_height;
1834 if (ilace && oi->height == outh)
1843 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
1845 oi->height, oi->pos_y, outh);
1848 if (!dss_feat_color_mode_supported(plane, oi->color_mode))
1851 r = dispc_ovl_calc_scaling(plane, channel, oi->width, oi->height,
1852 outw, outh, oi->color_mode,
1857 if (oi->color_mode == OMAP_DSS_COLOR_YUV2 ||
1858 oi->color_mode == OMAP_DSS_COLOR_UYVY ||
1859 oi->color_mode == OMAP_DSS_COLOR_NV12)
1862 if (ilace && !fieldmode) {
1864 * when downscaling the bottom field may have to start several
1865 * source lines below the top field. Unfortunately ACCUI
1866 * registers will only hold the fractional part of the offset
1867 * so the integer part must be added to the base address of the
1870 if (!oi->height || oi->height == outh)
1873 field_offset = oi->height / outh / 2;
1876 /* Fields are independent but interleaved in memory. */
1880 if (oi->rotation_type == OMAP_DSS_ROT_DMA)
1881 calc_dma_rotation_offset(oi->rotation, oi->mirror,
1882 oi->screen_width, oi->width, frame_height,
1883 oi->color_mode, fieldmode, field_offset,
1884 &offset0, &offset1, &row_inc, &pix_inc);
1886 calc_vrfb_rotation_offset(oi->rotation, oi->mirror,
1887 oi->screen_width, oi->width, frame_height,
1888 oi->color_mode, fieldmode, field_offset,
1889 &offset0, &offset1, &row_inc, &pix_inc);
1891 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
1892 offset0, offset1, row_inc, pix_inc);
1894 dispc_ovl_set_color_mode(plane, oi->color_mode);
1896 dispc_ovl_set_ba0(plane, oi->paddr + offset0);
1897 dispc_ovl_set_ba1(plane, oi->paddr + offset1);
1899 if (OMAP_DSS_COLOR_NV12 == oi->color_mode) {
1900 dispc_ovl_set_ba0_uv(plane, oi->p_uv_addr + offset0);
1901 dispc_ovl_set_ba1_uv(plane, oi->p_uv_addr + offset1);
1905 dispc_ovl_set_row_inc(plane, row_inc);
1906 dispc_ovl_set_pix_inc(plane, pix_inc);
1908 DSSDBG("%d,%d %dx%d -> %dx%d\n", oi->pos_x, oi->pos_y, oi->width,
1909 oi->height, outw, outh);
1911 dispc_ovl_set_pos(plane, oi->pos_x, oi->pos_y);
1913 dispc_ovl_set_pic_size(plane, oi->width, oi->height);
1915 if (ovl->caps & OMAP_DSS_OVL_CAP_SCALE) {
1916 dispc_ovl_set_scaling(plane, oi->width, oi->height,
1918 ilace, five_taps, fieldmode,
1919 oi->color_mode, oi->rotation);
1920 dispc_ovl_set_vid_size(plane, outw, outh);
1921 dispc_ovl_set_vid_color_conv(plane, cconv);
1924 dispc_ovl_set_rotation_attrs(plane, oi->rotation, oi->mirror,
1927 dispc_ovl_set_zorder(plane, oi->zorder);
1928 dispc_ovl_set_pre_mult_alpha(plane, oi->pre_mult_alpha);
1929 dispc_ovl_setup_global_alpha(plane, oi->global_alpha);
1931 dispc_ovl_enable_replication(plane, replication);
1936 int dispc_ovl_enable(enum omap_plane plane, bool enable)
1938 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
1940 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
1945 static void dispc_disable_isr(void *data, u32 mask)
1947 struct completion *compl = data;
1951 static void _enable_lcd_out(enum omap_channel channel, bool enable)
1953 if (channel == OMAP_DSS_CHANNEL_LCD2) {
1954 REG_FLD_MOD(DISPC_CONTROL2, enable ? 1 : 0, 0, 0);
1955 /* flush posted write */
1956 dispc_read_reg(DISPC_CONTROL2);
1958 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
1959 dispc_read_reg(DISPC_CONTROL);
1963 static void dispc_mgr_enable_lcd_out(enum omap_channel channel, bool enable)
1965 struct completion frame_done_completion;
1970 /* When we disable LCD output, we need to wait until frame is done.
1971 * Otherwise the DSS is still working, and turning off the clocks
1972 * prevents DSS from going to OFF mode */
1973 is_on = channel == OMAP_DSS_CHANNEL_LCD2 ?
1974 REG_GET(DISPC_CONTROL2, 0, 0) :
1975 REG_GET(DISPC_CONTROL, 0, 0);
1977 irq = channel == OMAP_DSS_CHANNEL_LCD2 ? DISPC_IRQ_FRAMEDONE2 :
1978 DISPC_IRQ_FRAMEDONE;
1980 if (!enable && is_on) {
1981 init_completion(&frame_done_completion);
1983 r = omap_dispc_register_isr(dispc_disable_isr,
1984 &frame_done_completion, irq);
1987 DSSERR("failed to register FRAMEDONE isr\n");
1990 _enable_lcd_out(channel, enable);
1992 if (!enable && is_on) {
1993 if (!wait_for_completion_timeout(&frame_done_completion,
1994 msecs_to_jiffies(100)))
1995 DSSERR("timeout waiting for FRAME DONE\n");
1997 r = omap_dispc_unregister_isr(dispc_disable_isr,
1998 &frame_done_completion, irq);
2001 DSSERR("failed to unregister FRAMEDONE isr\n");
2005 static void _enable_digit_out(bool enable)
2007 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
2008 /* flush posted write */
2009 dispc_read_reg(DISPC_CONTROL);
2012 static void dispc_mgr_enable_digit_out(bool enable)
2014 struct completion frame_done_completion;
2015 enum dss_hdmi_venc_clk_source_select src;
2020 if (REG_GET(DISPC_CONTROL, 1, 1) == enable)
2023 src = dss_get_hdmi_venc_clk_source();
2026 unsigned long flags;
2027 /* When we enable digit output, we'll get an extra digit
2028 * sync lost interrupt, that we need to ignore */
2029 spin_lock_irqsave(&dispc.irq_lock, flags);
2030 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
2031 _omap_dispc_set_irqs();
2032 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2035 /* When we disable digit output, we need to wait until fields are done.
2036 * Otherwise the DSS is still working, and turning off the clocks
2037 * prevents DSS from going to OFF mode. And when enabling, we need to
2038 * wait for the extra sync losts */
2039 init_completion(&frame_done_completion);
2041 if (src == DSS_HDMI_M_PCLK && enable == false) {
2042 irq_mask = DISPC_IRQ_FRAMEDONETV;
2045 irq_mask = DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD;
2046 /* XXX I understand from TRM that we should only wait for the
2047 * current field to complete. But it seems we have to wait for
2052 r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
2055 DSSERR("failed to register %x isr\n", irq_mask);
2057 _enable_digit_out(enable);
2059 for (i = 0; i < num_irqs; ++i) {
2060 if (!wait_for_completion_timeout(&frame_done_completion,
2061 msecs_to_jiffies(100)))
2062 DSSERR("timeout waiting for digit out to %s\n",
2063 enable ? "start" : "stop");
2066 r = omap_dispc_unregister_isr(dispc_disable_isr, &frame_done_completion,
2069 DSSERR("failed to unregister %x isr\n", irq_mask);
2072 unsigned long flags;
2073 spin_lock_irqsave(&dispc.irq_lock, flags);
2074 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST_DIGIT;
2075 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
2076 _omap_dispc_set_irqs();
2077 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2081 bool dispc_mgr_is_enabled(enum omap_channel channel)
2083 if (channel == OMAP_DSS_CHANNEL_LCD)
2084 return !!REG_GET(DISPC_CONTROL, 0, 0);
2085 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
2086 return !!REG_GET(DISPC_CONTROL, 1, 1);
2087 else if (channel == OMAP_DSS_CHANNEL_LCD2)
2088 return !!REG_GET(DISPC_CONTROL2, 0, 0);
2093 void dispc_mgr_enable(enum omap_channel channel, bool enable)
2095 if (dispc_mgr_is_lcd(channel))
2096 dispc_mgr_enable_lcd_out(channel, enable);
2097 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
2098 dispc_mgr_enable_digit_out(enable);
2103 void dispc_lcd_enable_signal_polarity(bool act_high)
2105 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2108 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
2111 void dispc_lcd_enable_signal(bool enable)
2113 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2116 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
2119 void dispc_pck_free_enable(bool enable)
2121 if (!dss_has_feature(FEAT_PCKFREEENABLE))
2124 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
2127 void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
2129 if (channel == OMAP_DSS_CHANNEL_LCD2)
2130 REG_FLD_MOD(DISPC_CONFIG2, enable ? 1 : 0, 16, 16);
2132 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
2136 void dispc_mgr_set_lcd_display_type(enum omap_channel channel,
2137 enum omap_lcd_display_type type)
2142 case OMAP_DSS_LCD_DISPLAY_STN:
2146 case OMAP_DSS_LCD_DISPLAY_TFT:
2155 if (channel == OMAP_DSS_CHANNEL_LCD2)
2156 REG_FLD_MOD(DISPC_CONTROL2, mode, 3, 3);
2158 REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
2161 void dispc_set_loadmode(enum omap_dss_load_mode mode)
2163 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
2167 static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
2169 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
2172 static void dispc_mgr_set_trans_key(enum omap_channel ch,
2173 enum omap_dss_trans_key_type type,
2176 if (ch == OMAP_DSS_CHANNEL_LCD)
2177 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
2178 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2179 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
2180 else /* OMAP_DSS_CHANNEL_LCD2 */
2181 REG_FLD_MOD(DISPC_CONFIG2, type, 11, 11);
2183 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
2186 static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
2188 if (ch == OMAP_DSS_CHANNEL_LCD)
2189 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
2190 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2191 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
2192 else /* OMAP_DSS_CHANNEL_LCD2 */
2193 REG_FLD_MOD(DISPC_CONFIG2, enable, 10, 10);
2196 static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2199 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
2202 if (ch == OMAP_DSS_CHANNEL_LCD)
2203 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2204 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2205 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2208 void dispc_mgr_setup(enum omap_channel channel,
2209 struct omap_overlay_manager_info *info)
2211 dispc_mgr_set_default_color(channel, info->default_color);
2212 dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
2213 dispc_mgr_enable_trans_key(channel, info->trans_enabled);
2214 dispc_mgr_enable_alpha_fixed_zorder(channel,
2215 info->partial_alpha_enabled);
2216 if (dss_has_feature(FEAT_CPR)) {
2217 dispc_mgr_enable_cpr(channel, info->cpr_enable);
2218 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
2222 void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
2226 switch (data_lines) {
2244 if (channel == OMAP_DSS_CHANNEL_LCD2)
2245 REG_FLD_MOD(DISPC_CONTROL2, code, 9, 8);
2247 REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
2250 void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
2256 case DSS_IO_PAD_MODE_RESET:
2260 case DSS_IO_PAD_MODE_RFBI:
2264 case DSS_IO_PAD_MODE_BYPASS:
2273 l = dispc_read_reg(DISPC_CONTROL);
2274 l = FLD_MOD(l, gpout0, 15, 15);
2275 l = FLD_MOD(l, gpout1, 16, 16);
2276 dispc_write_reg(DISPC_CONTROL, l);
2279 void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
2281 if (channel == OMAP_DSS_CHANNEL_LCD2)
2282 REG_FLD_MOD(DISPC_CONTROL2, enable, 11, 11);
2284 REG_FLD_MOD(DISPC_CONTROL, enable, 11, 11);
2287 static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2288 int vsw, int vfp, int vbp)
2290 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2291 if (hsw < 1 || hsw > 64 ||
2292 hfp < 1 || hfp > 256 ||
2293 hbp < 1 || hbp > 256 ||
2294 vsw < 1 || vsw > 64 ||
2295 vfp < 0 || vfp > 255 ||
2296 vbp < 0 || vbp > 255)
2299 if (hsw < 1 || hsw > 256 ||
2300 hfp < 1 || hfp > 4096 ||
2301 hbp < 1 || hbp > 4096 ||
2302 vsw < 1 || vsw > 256 ||
2303 vfp < 0 || vfp > 4095 ||
2304 vbp < 0 || vbp > 4095)
2311 bool dispc_lcd_timings_ok(struct omap_video_timings *timings)
2313 return _dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2314 timings->hbp, timings->vsw,
2315 timings->vfp, timings->vbp);
2318 static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
2319 int hfp, int hbp, int vsw, int vfp, int vbp)
2321 u32 timing_h, timing_v;
2323 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2324 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
2325 FLD_VAL(hbp-1, 27, 20);
2327 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
2328 FLD_VAL(vbp, 27, 20);
2330 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
2331 FLD_VAL(hbp-1, 31, 20);
2333 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
2334 FLD_VAL(vbp, 31, 20);
2337 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2338 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
2341 /* change name to mode? */
2342 void dispc_mgr_set_lcd_timings(enum omap_channel channel,
2343 struct omap_video_timings *timings)
2345 unsigned xtot, ytot;
2346 unsigned long ht, vt;
2348 if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2349 timings->hbp, timings->vsw,
2350 timings->vfp, timings->vbp))
2353 _dispc_mgr_set_lcd_timings(channel, timings->hsw, timings->hfp,
2354 timings->hbp, timings->vsw, timings->vfp,
2357 dispc_mgr_set_lcd_size(channel, timings->x_res, timings->y_res);
2359 xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
2360 ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
2362 ht = (timings->pixel_clock * 1000) / xtot;
2363 vt = (timings->pixel_clock * 1000) / xtot / ytot;
2365 DSSDBG("channel %d xres %u yres %u\n", channel, timings->x_res,
2367 DSSDBG("pck %u\n", timings->pixel_clock);
2368 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2369 timings->hsw, timings->hfp, timings->hbp,
2370 timings->vsw, timings->vfp, timings->vbp);
2372 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2375 static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
2378 BUG_ON(lck_div < 1);
2379 BUG_ON(pck_div < 1);
2381 dispc_write_reg(DISPC_DIVISORo(channel),
2382 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
2385 static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2389 l = dispc_read_reg(DISPC_DIVISORo(channel));
2390 *lck_div = FLD_GET(l, 23, 16);
2391 *pck_div = FLD_GET(l, 7, 0);
2394 unsigned long dispc_fclk_rate(void)
2396 struct platform_device *dsidev;
2397 unsigned long r = 0;
2399 switch (dss_get_dispc_clk_source()) {
2400 case OMAP_DSS_CLK_SRC_FCK:
2401 r = clk_get_rate(dispc.dss_clk);
2403 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
2404 dsidev = dsi_get_dsidev_from_id(0);
2405 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2407 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2408 dsidev = dsi_get_dsidev_from_id(1);
2409 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2418 unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
2420 struct platform_device *dsidev;
2425 l = dispc_read_reg(DISPC_DIVISORo(channel));
2427 lcd = FLD_GET(l, 23, 16);
2429 switch (dss_get_lcd_clk_source(channel)) {
2430 case OMAP_DSS_CLK_SRC_FCK:
2431 r = clk_get_rate(dispc.dss_clk);
2433 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
2434 dsidev = dsi_get_dsidev_from_id(0);
2435 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2437 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2438 dsidev = dsi_get_dsidev_from_id(1);
2439 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2448 unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
2452 if (dispc_mgr_is_lcd(channel)) {
2456 l = dispc_read_reg(DISPC_DIVISORo(channel));
2458 pcd = FLD_GET(l, 7, 0);
2460 r = dispc_mgr_lclk_rate(channel);
2464 struct omap_dss_device *dssdev =
2465 dispc_mgr_get_device(channel);
2467 switch (dssdev->type) {
2468 case OMAP_DISPLAY_TYPE_VENC:
2469 return venc_get_pixel_clock();
2470 case OMAP_DISPLAY_TYPE_HDMI:
2471 return hdmi_get_pixel_clock();
2478 void dispc_dump_clocks(struct seq_file *s)
2482 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
2483 enum omap_dss_clk_source lcd_clk_src;
2485 if (dispc_runtime_get())
2488 seq_printf(s, "- DISPC -\n");
2490 seq_printf(s, "dispc fclk source = %s (%s)\n",
2491 dss_get_generic_clk_source_name(dispc_clk_src),
2492 dss_feat_get_clk_source_name(dispc_clk_src));
2494 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2496 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
2497 seq_printf(s, "- DISPC-CORE-CLK -\n");
2498 l = dispc_read_reg(DISPC_DIVISOR);
2499 lcd = FLD_GET(l, 23, 16);
2501 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2502 (dispc_fclk_rate()/lcd), lcd);
2504 seq_printf(s, "- LCD1 -\n");
2506 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD);
2508 seq_printf(s, "lcd1_clk source = %s (%s)\n",
2509 dss_get_generic_clk_source_name(lcd_clk_src),
2510 dss_feat_get_clk_source_name(lcd_clk_src));
2512 dispc_mgr_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD, &lcd, &pcd);
2514 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2515 dispc_mgr_lclk_rate(OMAP_DSS_CHANNEL_LCD), lcd);
2516 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2517 dispc_mgr_pclk_rate(OMAP_DSS_CHANNEL_LCD), pcd);
2518 if (dss_has_feature(FEAT_MGR_LCD2)) {
2519 seq_printf(s, "- LCD2 -\n");
2521 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD2);
2523 seq_printf(s, "lcd2_clk source = %s (%s)\n",
2524 dss_get_generic_clk_source_name(lcd_clk_src),
2525 dss_feat_get_clk_source_name(lcd_clk_src));
2527 dispc_mgr_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD2, &lcd, &pcd);
2529 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2530 dispc_mgr_lclk_rate(OMAP_DSS_CHANNEL_LCD2), lcd);
2531 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2532 dispc_mgr_pclk_rate(OMAP_DSS_CHANNEL_LCD2), pcd);
2535 dispc_runtime_put();
2538 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2539 void dispc_dump_irqs(struct seq_file *s)
2541 unsigned long flags;
2542 struct dispc_irq_stats stats;
2544 spin_lock_irqsave(&dispc.irq_stats_lock, flags);
2546 stats = dispc.irq_stats;
2547 memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
2548 dispc.irq_stats.last_reset = jiffies;
2550 spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
2552 seq_printf(s, "period %u ms\n",
2553 jiffies_to_msecs(jiffies - stats.last_reset));
2555 seq_printf(s, "irqs %d\n", stats.irq_count);
2557 seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
2563 PIS(ACBIAS_COUNT_STAT);
2565 PIS(GFX_FIFO_UNDERFLOW);
2567 PIS(PAL_GAMMA_MASK);
2569 PIS(VID1_FIFO_UNDERFLOW);
2571 PIS(VID2_FIFO_UNDERFLOW);
2573 if (dss_feat_get_num_ovls() > 3) {
2574 PIS(VID3_FIFO_UNDERFLOW);
2578 PIS(SYNC_LOST_DIGIT);
2580 if (dss_has_feature(FEAT_MGR_LCD2)) {
2583 PIS(ACBIAS_COUNT_STAT2);
2590 void dispc_dump_regs(struct seq_file *s)
2593 const char *mgr_names[] = {
2594 [OMAP_DSS_CHANNEL_LCD] = "LCD",
2595 [OMAP_DSS_CHANNEL_DIGIT] = "TV",
2596 [OMAP_DSS_CHANNEL_LCD2] = "LCD2",
2598 const char *ovl_names[] = {
2599 [OMAP_DSS_GFX] = "GFX",
2600 [OMAP_DSS_VIDEO1] = "VID1",
2601 [OMAP_DSS_VIDEO2] = "VID2",
2602 [OMAP_DSS_VIDEO3] = "VID3",
2604 const char **p_names;
2606 #define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
2608 if (dispc_runtime_get())
2611 /* DISPC common registers */
2612 DUMPREG(DISPC_REVISION);
2613 DUMPREG(DISPC_SYSCONFIG);
2614 DUMPREG(DISPC_SYSSTATUS);
2615 DUMPREG(DISPC_IRQSTATUS);
2616 DUMPREG(DISPC_IRQENABLE);
2617 DUMPREG(DISPC_CONTROL);
2618 DUMPREG(DISPC_CONFIG);
2619 DUMPREG(DISPC_CAPABLE);
2620 DUMPREG(DISPC_LINE_STATUS);
2621 DUMPREG(DISPC_LINE_NUMBER);
2622 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
2623 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
2624 DUMPREG(DISPC_GLOBAL_ALPHA);
2625 if (dss_has_feature(FEAT_MGR_LCD2)) {
2626 DUMPREG(DISPC_CONTROL2);
2627 DUMPREG(DISPC_CONFIG2);
2632 #define DISPC_REG(i, name) name(i)
2633 #define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
2634 48 - strlen(#r) - strlen(p_names[i]), " ", \
2635 dispc_read_reg(DISPC_REG(i, r)))
2637 p_names = mgr_names;
2639 /* DISPC channel specific registers */
2640 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
2641 DUMPREG(i, DISPC_DEFAULT_COLOR);
2642 DUMPREG(i, DISPC_TRANS_COLOR);
2643 DUMPREG(i, DISPC_SIZE_MGR);
2645 if (i == OMAP_DSS_CHANNEL_DIGIT)
2648 DUMPREG(i, DISPC_DEFAULT_COLOR);
2649 DUMPREG(i, DISPC_TRANS_COLOR);
2650 DUMPREG(i, DISPC_TIMING_H);
2651 DUMPREG(i, DISPC_TIMING_V);
2652 DUMPREG(i, DISPC_POL_FREQ);
2653 DUMPREG(i, DISPC_DIVISORo);
2654 DUMPREG(i, DISPC_SIZE_MGR);
2656 DUMPREG(i, DISPC_DATA_CYCLE1);
2657 DUMPREG(i, DISPC_DATA_CYCLE2);
2658 DUMPREG(i, DISPC_DATA_CYCLE3);
2660 if (dss_has_feature(FEAT_CPR)) {
2661 DUMPREG(i, DISPC_CPR_COEF_R);
2662 DUMPREG(i, DISPC_CPR_COEF_G);
2663 DUMPREG(i, DISPC_CPR_COEF_B);
2667 p_names = ovl_names;
2669 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
2670 DUMPREG(i, DISPC_OVL_BA0);
2671 DUMPREG(i, DISPC_OVL_BA1);
2672 DUMPREG(i, DISPC_OVL_POSITION);
2673 DUMPREG(i, DISPC_OVL_SIZE);
2674 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
2675 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
2676 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
2677 DUMPREG(i, DISPC_OVL_ROW_INC);
2678 DUMPREG(i, DISPC_OVL_PIXEL_INC);
2679 if (dss_has_feature(FEAT_PRELOAD))
2680 DUMPREG(i, DISPC_OVL_PRELOAD);
2682 if (i == OMAP_DSS_GFX) {
2683 DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
2684 DUMPREG(i, DISPC_OVL_TABLE_BA);
2688 DUMPREG(i, DISPC_OVL_FIR);
2689 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
2690 DUMPREG(i, DISPC_OVL_ACCU0);
2691 DUMPREG(i, DISPC_OVL_ACCU1);
2692 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2693 DUMPREG(i, DISPC_OVL_BA0_UV);
2694 DUMPREG(i, DISPC_OVL_BA1_UV);
2695 DUMPREG(i, DISPC_OVL_FIR2);
2696 DUMPREG(i, DISPC_OVL_ACCU2_0);
2697 DUMPREG(i, DISPC_OVL_ACCU2_1);
2699 if (dss_has_feature(FEAT_ATTR2))
2700 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
2701 if (dss_has_feature(FEAT_PRELOAD))
2702 DUMPREG(i, DISPC_OVL_PRELOAD);
2708 #define DISPC_REG(plane, name, i) name(plane, i)
2709 #define DUMPREG(plane, name, i) \
2710 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
2711 46 - strlen(#name) - strlen(p_names[plane]), " ", \
2712 dispc_read_reg(DISPC_REG(plane, name, i)))
2714 /* Video pipeline coefficient registers */
2716 /* start from OMAP_DSS_VIDEO1 */
2717 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
2718 for (j = 0; j < 8; j++)
2719 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
2721 for (j = 0; j < 8; j++)
2722 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
2724 for (j = 0; j < 5; j++)
2725 DUMPREG(i, DISPC_OVL_CONV_COEF, j);
2727 if (dss_has_feature(FEAT_FIR_COEF_V)) {
2728 for (j = 0; j < 8; j++)
2729 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
2732 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2733 for (j = 0; j < 8; j++)
2734 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
2736 for (j = 0; j < 8; j++)
2737 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
2739 for (j = 0; j < 8; j++)
2740 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
2744 dispc_runtime_put();
2750 static void _dispc_mgr_set_pol_freq(enum omap_channel channel, bool onoff,
2751 bool rf, bool ieo, bool ipc, bool ihs, bool ivs, u8 acbi,
2756 DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
2757 onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
2759 l |= FLD_VAL(onoff, 17, 17);
2760 l |= FLD_VAL(rf, 16, 16);
2761 l |= FLD_VAL(ieo, 15, 15);
2762 l |= FLD_VAL(ipc, 14, 14);
2763 l |= FLD_VAL(ihs, 13, 13);
2764 l |= FLD_VAL(ivs, 12, 12);
2765 l |= FLD_VAL(acbi, 11, 8);
2766 l |= FLD_VAL(acb, 7, 0);
2768 dispc_write_reg(DISPC_POL_FREQ(channel), l);
2771 void dispc_mgr_set_pol_freq(enum omap_channel channel,
2772 enum omap_panel_config config, u8 acbi, u8 acb)
2774 _dispc_mgr_set_pol_freq(channel, (config & OMAP_DSS_LCD_ONOFF) != 0,
2775 (config & OMAP_DSS_LCD_RF) != 0,
2776 (config & OMAP_DSS_LCD_IEO) != 0,
2777 (config & OMAP_DSS_LCD_IPC) != 0,
2778 (config & OMAP_DSS_LCD_IHS) != 0,
2779 (config & OMAP_DSS_LCD_IVS) != 0,
2783 /* with fck as input clock rate, find dispc dividers that produce req_pck */
2784 void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
2785 struct dispc_clock_info *cinfo)
2787 u16 pcd_min, pcd_max;
2788 unsigned long best_pck;
2789 u16 best_ld, cur_ld;
2790 u16 best_pd, cur_pd;
2792 pcd_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
2793 pcd_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
2802 for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
2803 unsigned long lck = fck / cur_ld;
2805 for (cur_pd = pcd_min; cur_pd <= pcd_max; ++cur_pd) {
2806 unsigned long pck = lck / cur_pd;
2807 long old_delta = abs(best_pck - req_pck);
2808 long new_delta = abs(pck - req_pck);
2810 if (best_pck == 0 || new_delta < old_delta) {
2823 if (lck / pcd_min < req_pck)
2828 cinfo->lck_div = best_ld;
2829 cinfo->pck_div = best_pd;
2830 cinfo->lck = fck / cinfo->lck_div;
2831 cinfo->pck = cinfo->lck / cinfo->pck_div;
2834 /* calculate clock rates using dividers in cinfo */
2835 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
2836 struct dispc_clock_info *cinfo)
2838 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
2840 if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
2843 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
2844 cinfo->pck = cinfo->lck / cinfo->pck_div;
2849 int dispc_mgr_set_clock_div(enum omap_channel channel,
2850 struct dispc_clock_info *cinfo)
2852 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
2853 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
2855 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
2860 int dispc_mgr_get_clock_div(enum omap_channel channel,
2861 struct dispc_clock_info *cinfo)
2865 fck = dispc_fclk_rate();
2867 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
2868 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
2870 cinfo->lck = fck / cinfo->lck_div;
2871 cinfo->pck = cinfo->lck / cinfo->pck_div;
2876 /* dispc.irq_lock has to be locked by the caller */
2877 static void _omap_dispc_set_irqs(void)
2882 struct omap_dispc_isr_data *isr_data;
2884 mask = dispc.irq_error_mask;
2886 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2887 isr_data = &dispc.registered_isr[i];
2889 if (isr_data->isr == NULL)
2892 mask |= isr_data->mask;
2895 old_mask = dispc_read_reg(DISPC_IRQENABLE);
2896 /* clear the irqstatus for newly enabled irqs */
2897 dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
2899 dispc_write_reg(DISPC_IRQENABLE, mask);
2902 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2906 unsigned long flags;
2907 struct omap_dispc_isr_data *isr_data;
2912 spin_lock_irqsave(&dispc.irq_lock, flags);
2914 /* check for duplicate entry */
2915 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2916 isr_data = &dispc.registered_isr[i];
2917 if (isr_data->isr == isr && isr_data->arg == arg &&
2918 isr_data->mask == mask) {
2927 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2928 isr_data = &dispc.registered_isr[i];
2930 if (isr_data->isr != NULL)
2933 isr_data->isr = isr;
2934 isr_data->arg = arg;
2935 isr_data->mask = mask;
2944 _omap_dispc_set_irqs();
2946 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2950 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2954 EXPORT_SYMBOL(omap_dispc_register_isr);
2956 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2959 unsigned long flags;
2961 struct omap_dispc_isr_data *isr_data;
2963 spin_lock_irqsave(&dispc.irq_lock, flags);
2965 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2966 isr_data = &dispc.registered_isr[i];
2967 if (isr_data->isr != isr || isr_data->arg != arg ||
2968 isr_data->mask != mask)
2971 /* found the correct isr */
2973 isr_data->isr = NULL;
2974 isr_data->arg = NULL;
2982 _omap_dispc_set_irqs();
2984 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2988 EXPORT_SYMBOL(omap_dispc_unregister_isr);
2991 static void print_irq_status(u32 status)
2993 if ((status & dispc.irq_error_mask) == 0)
2996 printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
2999 if (status & DISPC_IRQ_##x) \
3001 PIS(GFX_FIFO_UNDERFLOW);
3003 PIS(VID1_FIFO_UNDERFLOW);
3004 PIS(VID2_FIFO_UNDERFLOW);
3005 if (dss_feat_get_num_ovls() > 3)
3006 PIS(VID3_FIFO_UNDERFLOW);
3008 PIS(SYNC_LOST_DIGIT);
3009 if (dss_has_feature(FEAT_MGR_LCD2))
3017 /* Called from dss.c. Note that we don't touch clocks here,
3018 * but we presume they are on because we got an IRQ. However,
3019 * an irq handler may turn the clocks off, so we may not have
3020 * clock later in the function. */
3021 static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
3024 u32 irqstatus, irqenable;
3025 u32 handledirqs = 0;
3026 u32 unhandled_errors;
3027 struct omap_dispc_isr_data *isr_data;
3028 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
3030 spin_lock(&dispc.irq_lock);
3032 irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
3033 irqenable = dispc_read_reg(DISPC_IRQENABLE);
3035 /* IRQ is not for us */
3036 if (!(irqstatus & irqenable)) {
3037 spin_unlock(&dispc.irq_lock);
3041 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3042 spin_lock(&dispc.irq_stats_lock);
3043 dispc.irq_stats.irq_count++;
3044 dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
3045 spin_unlock(&dispc.irq_stats_lock);
3050 print_irq_status(irqstatus);
3052 /* Ack the interrupt. Do it here before clocks are possibly turned
3054 dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
3055 /* flush posted write */
3056 dispc_read_reg(DISPC_IRQSTATUS);
3058 /* make a copy and unlock, so that isrs can unregister
3060 memcpy(registered_isr, dispc.registered_isr,
3061 sizeof(registered_isr));
3063 spin_unlock(&dispc.irq_lock);
3065 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3066 isr_data = ®istered_isr[i];
3071 if (isr_data->mask & irqstatus) {
3072 isr_data->isr(isr_data->arg, irqstatus);
3073 handledirqs |= isr_data->mask;
3077 spin_lock(&dispc.irq_lock);
3079 unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
3081 if (unhandled_errors) {
3082 dispc.error_irqs |= unhandled_errors;
3084 dispc.irq_error_mask &= ~unhandled_errors;
3085 _omap_dispc_set_irqs();
3087 schedule_work(&dispc.error_work);
3090 spin_unlock(&dispc.irq_lock);
3095 static void dispc_error_worker(struct work_struct *work)
3099 unsigned long flags;
3100 static const unsigned fifo_underflow_bits[] = {
3101 DISPC_IRQ_GFX_FIFO_UNDERFLOW,
3102 DISPC_IRQ_VID1_FIFO_UNDERFLOW,
3103 DISPC_IRQ_VID2_FIFO_UNDERFLOW,
3104 DISPC_IRQ_VID3_FIFO_UNDERFLOW,
3107 static const unsigned sync_lost_bits[] = {
3108 DISPC_IRQ_SYNC_LOST,
3109 DISPC_IRQ_SYNC_LOST_DIGIT,
3110 DISPC_IRQ_SYNC_LOST2,
3113 spin_lock_irqsave(&dispc.irq_lock, flags);
3114 errors = dispc.error_irqs;
3115 dispc.error_irqs = 0;
3116 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3118 dispc_runtime_get();
3120 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3121 struct omap_overlay *ovl;
3124 ovl = omap_dss_get_overlay(i);
3125 bit = fifo_underflow_bits[i];
3128 DSSERR("FIFO UNDERFLOW on %s, disabling the overlay\n",
3130 dispc_ovl_enable(ovl->id, false);
3131 dispc_mgr_go(ovl->manager->id);
3136 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3137 struct omap_overlay_manager *mgr;
3140 mgr = omap_dss_get_overlay_manager(i);
3141 bit = sync_lost_bits[i];
3144 struct omap_dss_device *dssdev = mgr->device;
3147 DSSERR("SYNC_LOST on channel %s, restarting the output "
3148 "with video overlays disabled\n",
3151 enable = dssdev->state == OMAP_DSS_DISPLAY_ACTIVE;
3152 dssdev->driver->disable(dssdev);
3154 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3155 struct omap_overlay *ovl;
3156 ovl = omap_dss_get_overlay(i);
3158 if (ovl->id != OMAP_DSS_GFX &&
3159 ovl->manager == mgr)
3160 dispc_ovl_enable(ovl->id, false);
3163 dispc_mgr_go(mgr->id);
3167 dssdev->driver->enable(dssdev);
3171 if (errors & DISPC_IRQ_OCP_ERR) {
3172 DSSERR("OCP_ERR\n");
3173 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3174 struct omap_overlay_manager *mgr;
3175 mgr = omap_dss_get_overlay_manager(i);
3176 mgr->device->driver->disable(mgr->device);
3180 spin_lock_irqsave(&dispc.irq_lock, flags);
3181 dispc.irq_error_mask |= errors;
3182 _omap_dispc_set_irqs();
3183 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3185 dispc_runtime_put();
3188 int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
3190 void dispc_irq_wait_handler(void *data, u32 mask)
3192 complete((struct completion *)data);
3196 DECLARE_COMPLETION_ONSTACK(completion);
3198 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3204 timeout = wait_for_completion_timeout(&completion, timeout);
3206 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3211 if (timeout == -ERESTARTSYS)
3212 return -ERESTARTSYS;
3217 int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
3218 unsigned long timeout)
3220 void dispc_irq_wait_handler(void *data, u32 mask)
3222 complete((struct completion *)data);
3226 DECLARE_COMPLETION_ONSTACK(completion);
3228 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3234 timeout = wait_for_completion_interruptible_timeout(&completion,
3237 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3242 if (timeout == -ERESTARTSYS)
3243 return -ERESTARTSYS;
3248 #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
3249 void dispc_fake_vsync_irq(void)
3251 u32 irqstatus = DISPC_IRQ_VSYNC;
3254 WARN_ON(!in_interrupt());
3256 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3257 struct omap_dispc_isr_data *isr_data;
3258 isr_data = &dispc.registered_isr[i];
3263 if (isr_data->mask & irqstatus)
3264 isr_data->isr(isr_data->arg, irqstatus);
3269 static void _omap_dispc_initialize_irq(void)
3271 unsigned long flags;
3273 spin_lock_irqsave(&dispc.irq_lock, flags);
3275 memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3277 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
3278 if (dss_has_feature(FEAT_MGR_LCD2))
3279 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
3280 if (dss_feat_get_num_ovls() > 3)
3281 dispc.irq_error_mask |= DISPC_IRQ_VID3_FIFO_UNDERFLOW;
3283 /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3285 dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3287 _omap_dispc_set_irqs();
3289 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3292 void dispc_enable_sidle(void)
3294 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3297 void dispc_disable_sidle(void)
3299 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3302 static void _omap_dispc_initial_config(void)
3306 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3307 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3308 l = dispc_read_reg(DISPC_DIVISOR);
3309 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3310 l = FLD_MOD(l, 1, 0, 0);
3311 l = FLD_MOD(l, 1, 23, 16);
3312 dispc_write_reg(DISPC_DIVISOR, l);
3316 if (dss_has_feature(FEAT_FUNCGATED))
3317 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
3319 /* L3 firewall setting: enable access to OCM RAM */
3320 /* XXX this should be somewhere in plat-omap */
3321 if (cpu_is_omap24xx())
3322 __raw_writel(0x402000b0, OMAP2_L3_IO_ADDRESS(0x680050a0));
3324 _dispc_setup_color_conv_coef();
3326 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3328 dispc_read_plane_fifo_sizes();
3330 dispc_configure_burst_sizes();
3332 dispc_ovl_enable_zorder_planes();
3335 /* DISPC HW IP initialisation */
3336 static int omap_dispchw_probe(struct platform_device *pdev)
3340 struct resource *dispc_mem;
3345 clk = clk_get(&pdev->dev, "fck");
3347 DSSERR("can't get fck\n");
3352 dispc.dss_clk = clk;
3354 spin_lock_init(&dispc.irq_lock);
3356 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3357 spin_lock_init(&dispc.irq_stats_lock);
3358 dispc.irq_stats.last_reset = jiffies;
3361 INIT_WORK(&dispc.error_work, dispc_error_worker);
3363 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3365 DSSERR("can't get IORESOURCE_MEM DISPC\n");
3369 dispc.base = ioremap(dispc_mem->start, resource_size(dispc_mem));
3371 DSSERR("can't ioremap DISPC\n");
3375 dispc.irq = platform_get_irq(dispc.pdev, 0);
3376 if (dispc.irq < 0) {
3377 DSSERR("platform_get_irq failed\n");
3382 r = request_irq(dispc.irq, omap_dispc_irq_handler, IRQF_SHARED,
3383 "OMAP DISPC", dispc.pdev);
3385 DSSERR("request_irq failed\n");
3389 pm_runtime_enable(&pdev->dev);
3391 r = dispc_runtime_get();
3393 goto err_runtime_get;
3395 _omap_dispc_initial_config();
3397 _omap_dispc_initialize_irq();
3399 rev = dispc_read_reg(DISPC_REVISION);
3400 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
3401 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3403 dispc_runtime_put();
3408 pm_runtime_disable(&pdev->dev);
3409 free_irq(dispc.irq, dispc.pdev);
3411 iounmap(dispc.base);
3413 clk_put(dispc.dss_clk);
3418 static int omap_dispchw_remove(struct platform_device *pdev)
3420 pm_runtime_disable(&pdev->dev);
3422 clk_put(dispc.dss_clk);
3424 free_irq(dispc.irq, dispc.pdev);
3425 iounmap(dispc.base);
3429 static int dispc_runtime_suspend(struct device *dev)
3431 dispc_save_context();
3437 static int dispc_runtime_resume(struct device *dev)
3441 r = dss_runtime_get();
3445 dispc_restore_context();
3450 static const struct dev_pm_ops dispc_pm_ops = {
3451 .runtime_suspend = dispc_runtime_suspend,
3452 .runtime_resume = dispc_runtime_resume,
3455 static struct platform_driver omap_dispchw_driver = {
3456 .probe = omap_dispchw_probe,
3457 .remove = omap_dispchw_remove,
3459 .name = "omapdss_dispc",
3460 .owner = THIS_MODULE,
3461 .pm = &dispc_pm_ops,
3465 int dispc_init_platform_driver(void)
3467 return platform_driver_register(&omap_dispchw_driver);
3470 void dispc_uninit_platform_driver(void)
3472 return platform_driver_unregister(&omap_dispchw_driver);