drivers/video/omap2/dss/dispc.c

   1 /*
   2  * linux/drivers/video/omap2/dss/dispc.c
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #define DSS_SUBSYS_NAME "DISPC"
  24
  25 #include <linux/kernel.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/vmalloc.h>
  28 #include <linux/clk.h>
  29 #include <linux/io.h>
  30 #include <linux/jiffies.h>
  31 #include <linux/seq_file.h>
  32 #include <linux/delay.h>
  33 #include <linux/workqueue.h>
  34 #include <linux/hardirq.h>
  35 #include <linux/interrupt.h>
  36 #include <linux/platform_device.h>
  37 #include <linux/pm_runtime.h>
  38
  39 #include <plat/sram.h>
  40 #include <plat/clock.h>
  41
  42 #include <video/omapdss.h>
  43
  44 #include "dss.h"
  45 #include "dss_features.h"
  46 #include "dispc.h"
  47
  48 /* DISPC */
  49 #define DISPC_SZ_REGS                   SZ_4K
  50
  51 #define DISPC_IRQ_MASK_ERROR            (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
  52                                          DISPC_IRQ_OCP_ERR | \
  53                                          DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
  54                                          DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
  55                                          DISPC_IRQ_SYNC_LOST | \
  56                                          DISPC_IRQ_SYNC_LOST_DIGIT)
  57
  58 #define DISPC_MAX_NR_ISRS               8
  59
  60 struct omap_dispc_isr_data {
  61         omap_dispc_isr_t        isr;
  62         void                    *arg;
  63         u32                     mask;
  64 };
  65
  66 struct dispc_h_coef {
  67         s8 hc4;
  68         s8 hc3;
  69         u8 hc2;
  70         s8 hc1;
  71         s8 hc0;
  72 };
  73
  74 struct dispc_v_coef {
  75         s8 vc22;
  76         s8 vc2;
  77         u8 vc1;
  78         s8 vc0;
  79         s8 vc00;
  80 };
  81
  82 enum omap_burst_size {
  83         BURST_SIZE_X2 = 0,
  84         BURST_SIZE_X4 = 1,
  85         BURST_SIZE_X8 = 2,
  86 };
  87
  88 #define REG_GET(idx, start, end) \
  89         FLD_GET(dispc_read_reg(idx), start, end)
  90
  91 #define REG_FLD_MOD(idx, val, start, end)                               \
  92         dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
  93
  94 struct dispc_irq_stats {
  95         unsigned long last_reset;
  96         unsigned irq_count;
  97         unsigned irqs[32];
  98 };
  99
 100 static struct {
 101         struct platform_device *pdev;
 102         void __iomem    *base;
 103
 104         int             ctx_loss_cnt;
 105
 106         int irq;
 107         struct clk *dss_clk;
 108
 109         u32     fifo_size[MAX_DSS_OVERLAYS];
 110
 111         spinlock_t irq_lock;
 112         u32 irq_error_mask;
 113         struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
 114         u32 error_irqs;
 115         struct work_struct error_work;
 116
 117         bool            ctx_valid;
 118         u32             ctx[DISPC_SZ_REGS / sizeof(u32)];
 119
 120 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
 121         spinlock_t irq_stats_lock;
 122         struct dispc_irq_stats irq_stats;
 123 #endif
 124 } dispc;
 125
 126 enum omap_color_component {
 127         /* used for all color formats for OMAP3 and earlier
 128          * and for RGB and Y color component on OMAP4
 129          */
 130         DISPC_COLOR_COMPONENT_RGB_Y             = 1 << 0,
 131         /* used for UV component for
 132          * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
 133          * color formats on OMAP4
 134          */
 135         DISPC_COLOR_COMPONENT_UV                = 1 << 1,
 136 };
 137
 138 static void _omap_dispc_set_irqs(void);
 139
 140 static inline void dispc_write_reg(const u16 idx, u32 val)
 141 {
 142         __raw_writel(val, dispc.base + idx);
 143 }
 144
 145 static inline u32 dispc_read_reg(const u16 idx)
 146 {
 147         return __raw_readl(dispc.base + idx);
 148 }
 149
 150 static int dispc_get_ctx_loss_count(void)
 151 {
 152         struct device *dev = &dispc.pdev->dev;
 153         struct omap_display_platform_data *pdata = dev->platform_data;
 154         struct omap_dss_board_info *board_data = pdata->board_data;
 155         int cnt;
 156
 157         if (!board_data->get_context_loss_count)
 158                 return -ENOENT;
 159
 160         cnt = board_data->get_context_loss_count(dev);
 161
 162         WARN_ONCE(cnt < 0, "get_context_loss_count failed: %d\n", cnt);
 163
 164         return cnt;
 165 }
 166
 167 #define SR(reg) \
 168         dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
 169 #define RR(reg) \
 170         dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
 171
 172 static void dispc_save_context(void)
 173 {
 174         int i, j;
 175
 176         DSSDBG("dispc_save_context\n");
 177
 178         SR(IRQENABLE);
 179         SR(CONTROL);
 180         SR(CONFIG);
 181         SR(LINE_NUMBER);
 182         if (dss_has_feature(FEAT_GLOBAL_ALPHA))
 183                 SR(GLOBAL_ALPHA);
 184         if (dss_has_feature(FEAT_MGR_LCD2)) {
 185                 SR(CONTROL2);
 186                 SR(CONFIG2);
 187         }
 188
 189         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
 190                 SR(DEFAULT_COLOR(i));
 191                 SR(TRANS_COLOR(i));
 192                 SR(SIZE_MGR(i));
 193                 if (i == OMAP_DSS_CHANNEL_DIGIT)
 194                         continue;
 195                 SR(TIMING_H(i));
 196                 SR(TIMING_V(i));
 197                 SR(POL_FREQ(i));
 198                 SR(DIVISORo(i));
 199
 200                 SR(DATA_CYCLE1(i));
 201                 SR(DATA_CYCLE2(i));
 202                 SR(DATA_CYCLE3(i));
 203
 204                 if (dss_has_feature(FEAT_CPR)) {
 205                         SR(CPR_COEF_R(i));
 206                         SR(CPR_COEF_G(i));
 207                         SR(CPR_COEF_B(i));
 208                 }
 209         }
 210
 211         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
 212                 SR(OVL_BA0(i));
 213                 SR(OVL_BA1(i));
 214                 SR(OVL_POSITION(i));
 215                 SR(OVL_SIZE(i));
 216                 SR(OVL_ATTRIBUTES(i));
 217                 SR(OVL_FIFO_THRESHOLD(i));
 218                 SR(OVL_ROW_INC(i));
 219                 SR(OVL_PIXEL_INC(i));
 220                 if (dss_has_feature(FEAT_PRELOAD))
 221                         SR(OVL_PRELOAD(i));
 222                 if (i == OMAP_DSS_GFX) {
 223                         SR(OVL_WINDOW_SKIP(i));
 224                         SR(OVL_TABLE_BA(i));
 225                         continue;
 226                 }
 227                 SR(OVL_FIR(i));
 228                 SR(OVL_PICTURE_SIZE(i));
 229                 SR(OVL_ACCU0(i));
 230                 SR(OVL_ACCU1(i));
 231
 232                 for (j = 0; j < 8; j++)
 233                         SR(OVL_FIR_COEF_H(i, j));
 234
 235                 for (j = 0; j < 8; j++)
 236                         SR(OVL_FIR_COEF_HV(i, j));
 237
 238                 for (j = 0; j < 5; j++)
 239                         SR(OVL_CONV_COEF(i, j));
 240
 241                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
 242                         for (j = 0; j < 8; j++)
 243                                 SR(OVL_FIR_COEF_V(i, j));
 244                 }
 245
 246                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
 247                         SR(OVL_BA0_UV(i));
 248                         SR(OVL_BA1_UV(i));
 249                         SR(OVL_FIR2(i));
 250                         SR(OVL_ACCU2_0(i));
 251                         SR(OVL_ACCU2_1(i));
 252
 253                         for (j = 0; j < 8; j++)
 254                                 SR(OVL_FIR_COEF_H2(i, j));
 255
 256                         for (j = 0; j < 8; j++)
 257                                 SR(OVL_FIR_COEF_HV2(i, j));
 258
 259                         for (j = 0; j < 8; j++)
 260                                 SR(OVL_FIR_COEF_V2(i, j));
 261                 }
 262                 if (dss_has_feature(FEAT_ATTR2))
 263                         SR(OVL_ATTRIBUTES2(i));
 264         }
 265
 266         if (dss_has_feature(FEAT_CORE_CLK_DIV))
 267                 SR(DIVISOR);
 268
 269         dispc.ctx_loss_cnt = dispc_get_ctx_loss_count();
 270         dispc.ctx_valid = true;
 271
 272         DSSDBG("context saved, ctx_loss_count %d\n", dispc.ctx_loss_cnt);
 273 }
 274
 275 static void dispc_restore_context(void)
 276 {
 277         int i, j, ctx;
 278
 279         DSSDBG("dispc_restore_context\n");
 280
 281         if (!dispc.ctx_valid)
 282                 return;
 283
 284         ctx = dispc_get_ctx_loss_count();
 285
 286         if (ctx >= 0 && ctx == dispc.ctx_loss_cnt)
 287                 return;
 288
 289         DSSDBG("ctx_loss_count: saved %d, current %d\n",
 290                         dispc.ctx_loss_cnt, ctx);
 291
 292         /*RR(IRQENABLE);*/
 293         /*RR(CONTROL);*/
 294         RR(CONFIG);
 295         RR(LINE_NUMBER);
 296         if (dss_has_feature(FEAT_GLOBAL_ALPHA))
 297                 RR(GLOBAL_ALPHA);
 298         if (dss_has_feature(FEAT_MGR_LCD2))
 299                 RR(CONFIG2);
 300
 301         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
 302                 RR(DEFAULT_COLOR(i));
 303                 RR(TRANS_COLOR(i));
 304                 RR(SIZE_MGR(i));
 305                 if (i == OMAP_DSS_CHANNEL_DIGIT)
 306                         continue;
 307                 RR(TIMING_H(i));
 308                 RR(TIMING_V(i));
 309                 RR(POL_FREQ(i));
 310                 RR(DIVISORo(i));
 311
 312                 RR(DATA_CYCLE1(i));
 313                 RR(DATA_CYCLE2(i));
 314                 RR(DATA_CYCLE3(i));
 315
 316                 if (dss_has_feature(FEAT_CPR)) {
 317                         RR(CPR_COEF_R(i));
 318                         RR(CPR_COEF_G(i));
 319                         RR(CPR_COEF_B(i));
 320                 }
 321         }
 322
 323         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
 324                 RR(OVL_BA0(i));
 325                 RR(OVL_BA1(i));
 326                 RR(OVL_POSITION(i));
 327                 RR(OVL_SIZE(i));
 328                 RR(OVL_ATTRIBUTES(i));
 329                 RR(OVL_FIFO_THRESHOLD(i));
 330                 RR(OVL_ROW_INC(i));
 331                 RR(OVL_PIXEL_INC(i));
 332                 if (dss_has_feature(FEAT_PRELOAD))
 333                         RR(OVL_PRELOAD(i));
 334                 if (i == OMAP_DSS_GFX) {
 335                         RR(OVL_WINDOW_SKIP(i));
 336                         RR(OVL_TABLE_BA(i));
 337                         continue;
 338                 }
 339                 RR(OVL_FIR(i));
 340                 RR(OVL_PICTURE_SIZE(i));
 341                 RR(OVL_ACCU0(i));
 342                 RR(OVL_ACCU1(i));
 343
 344                 for (j = 0; j < 8; j++)
 345                         RR(OVL_FIR_COEF_H(i, j));
 346
 347                 for (j = 0; j < 8; j++)
 348                         RR(OVL_FIR_COEF_HV(i, j));
 349
 350                 for (j = 0; j < 5; j++)
 351                         RR(OVL_CONV_COEF(i, j));
 352
 353                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
 354                         for (j = 0; j < 8; j++)
 355                                 RR(OVL_FIR_COEF_V(i, j));
 356                 }
 357
 358                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
 359                         RR(OVL_BA0_UV(i));
 360                         RR(OVL_BA1_UV(i));
 361                         RR(OVL_FIR2(i));
 362                         RR(OVL_ACCU2_0(i));
 363                         RR(OVL_ACCU2_1(i));
 364
 365                         for (j = 0; j < 8; j++)
 366                                 RR(OVL_FIR_COEF_H2(i, j));
 367
 368                         for (j = 0; j < 8; j++)
 369                                 RR(OVL_FIR_COEF_HV2(i, j));
 370
 371                         for (j = 0; j < 8; j++)
 372                                 RR(OVL_FIR_COEF_V2(i, j));
 373                 }
 374                 if (dss_has_feature(FEAT_ATTR2))
 375                         RR(OVL_ATTRIBUTES2(i));
 376         }
 377
 378         if (dss_has_feature(FEAT_CORE_CLK_DIV))
 379                 RR(DIVISOR);
 380
 381         /* enable last, because LCD & DIGIT enable are here */
 382         RR(CONTROL);
 383         if (dss_has_feature(FEAT_MGR_LCD2))
 384                 RR(CONTROL2);
 385         /* clear spurious SYNC_LOST_DIGIT interrupts */
 386         dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
 387
 388         /*
 389          * enable last so IRQs won't trigger before
 390          * the context is fully restored
 391          */
 392         RR(IRQENABLE);
 393
 394         DSSDBG("context restored\n");
 395 }
 396
 397 #undef SR
 398 #undef RR
 399
 400 int dispc_runtime_get(void)
 401 {
 402         int r;
 403
 404         DSSDBG("dispc_runtime_get\n");
 405
 406         r = pm_runtime_get_sync(&dispc.pdev->dev);
 407         WARN_ON(r < 0);
 408         return r < 0 ? r : 0;
 409 }
 410
 411 void dispc_runtime_put(void)
 412 {
 413         int r;
 414
 415         DSSDBG("dispc_runtime_put\n");
 416
 417         r = pm_runtime_put(&dispc.pdev->dev);
 418         WARN_ON(r < 0);
 419 }
 420
 421
 422 bool dispc_mgr_go_busy(enum omap_channel channel)
 423 {
 424         int bit;
 425
 426         if (channel == OMAP_DSS_CHANNEL_LCD ||
 427                         channel == OMAP_DSS_CHANNEL_LCD2)
 428                 bit = 5; /* GOLCD */
 429         else
 430                 bit = 6; /* GODIGIT */
 431
 432         if (channel == OMAP_DSS_CHANNEL_LCD2)
 433                 return REG_GET(DISPC_CONTROL2, bit, bit) == 1;
 434         else
 435                 return REG_GET(DISPC_CONTROL, bit, bit) == 1;
 436 }
 437
 438 void dispc_mgr_go(enum omap_channel channel)
 439 {
 440         int bit;
 441         bool enable_bit, go_bit;
 442
 443         if (channel == OMAP_DSS_CHANNEL_LCD ||
 444                         channel == OMAP_DSS_CHANNEL_LCD2)
 445                 bit = 0; /* LCDENABLE */
 446         else
 447                 bit = 1; /* DIGITALENABLE */
 448
 449         /* if the channel is not enabled, we don't need GO */
 450         if (channel == OMAP_DSS_CHANNEL_LCD2)
 451                 enable_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
 452         else
 453                 enable_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
 454
 455         if (!enable_bit)
 456                 return;
 457
 458         if (channel == OMAP_DSS_CHANNEL_LCD ||
 459                         channel == OMAP_DSS_CHANNEL_LCD2)
 460                 bit = 5; /* GOLCD */
 461         else
 462                 bit = 6; /* GODIGIT */
 463
 464         if (channel == OMAP_DSS_CHANNEL_LCD2)
 465                 go_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
 466         else
 467                 go_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
 468
 469         if (go_bit) {
 470                 DSSERR("GO bit not down for channel %d\n", channel);
 471                 return;
 472         }
 473
 474         DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" :
 475                 (channel == OMAP_DSS_CHANNEL_LCD2 ? "LCD2" : "DIGIT"));
 476
 477         if (channel == OMAP_DSS_CHANNEL_LCD2)
 478                 REG_FLD_MOD(DISPC_CONTROL2, 1, bit, bit);
 479         else
 480                 REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
 481 }
 482
 483 static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
 484 {
 485         dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
 486 }
 487
 488 static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
 489 {
 490         dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
 491 }
 492
 493 static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
 494 {
 495         dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
 496 }
 497
 498 static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
 499 {
 500         BUG_ON(plane == OMAP_DSS_GFX);
 501
 502         dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
 503 }
 504
 505 static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
 506                 u32 value)
 507 {
 508         BUG_ON(plane == OMAP_DSS_GFX);
 509
 510         dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
 511 }
 512
 513 static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
 514 {
 515         BUG_ON(plane == OMAP_DSS_GFX);
 516
 517         dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
 518 }
 519
 520 static void dispc_ovl_set_scale_coef(enum omap_plane plane, int hscaleup,
 521                                   int vscaleup, int five_taps,
 522                                   enum omap_color_component color_comp)
 523 {
 524         /* Coefficients for horizontal up-sampling */
 525         static const struct dispc_h_coef coef_hup[8] = {
 526                 {  0,   0, 128,   0,  0 },
 527                 { -1,  13, 124,  -8,  0 },
 528                 { -2,  30, 112, -11, -1 },
 529                 { -5,  51,  95, -11, -2 },
 530                 {  0,  -9,  73,  73, -9 },
 531                 { -2, -11,  95,  51, -5 },
 532                 { -1, -11, 112,  30, -2 },
 533                 {  0,  -8, 124,  13, -1 },
 534         };
 535
 536         /* Coefficients for vertical up-sampling */
 537         static const struct dispc_v_coef coef_vup_3tap[8] = {
 538                 { 0,  0, 128,  0, 0 },
 539                 { 0,  3, 123,  2, 0 },
 540                 { 0, 12, 111,  5, 0 },
 541                 { 0, 32,  89,  7, 0 },
 542                 { 0,  0,  64, 64, 0 },
 543                 { 0,  7,  89, 32, 0 },
 544                 { 0,  5, 111, 12, 0 },
 545                 { 0,  2, 123,  3, 0 },
 546         };
 547
 548         static const struct dispc_v_coef coef_vup_5tap[8] = {
 549                 {  0,   0, 128,   0,  0 },
 550                 { -1,  13, 124,  -8,  0 },
 551                 { -2,  30, 112, -11, -1 },
 552                 { -5,  51,  95, -11, -2 },
 553                 {  0,  -9,  73,  73, -9 },
 554                 { -2, -11,  95,  51, -5 },
 555                 { -1, -11, 112,  30, -2 },
 556                 {  0,  -8, 124,  13, -1 },
 557         };
 558
 559         /* Coefficients for horizontal down-sampling */
 560         static const struct dispc_h_coef coef_hdown[8] = {
 561                 {   0, 36, 56, 36,  0 },
 562                 {   4, 40, 55, 31, -2 },
 563                 {   8, 44, 54, 27, -5 },
 564                 {  12, 48, 53, 22, -7 },
 565                 {  -9, 17, 52, 51, 17 },
 566                 {  -7, 22, 53, 48, 12 },
 567                 {  -5, 27, 54, 44,  8 },
 568                 {  -2, 31, 55, 40,  4 },
 569         };
 570
 571         /* Coefficients for vertical down-sampling */
 572         static const struct dispc_v_coef coef_vdown_3tap[8] = {
 573                 { 0, 36, 56, 36, 0 },
 574                 { 0, 40, 57, 31, 0 },
 575                 { 0, 45, 56, 27, 0 },
 576                 { 0, 50, 55, 23, 0 },
 577                 { 0, 18, 55, 55, 0 },
 578                 { 0, 23, 55, 50, 0 },
 579                 { 0, 27, 56, 45, 0 },
 580                 { 0, 31, 57, 40, 0 },
 581         };
 582
 583         static const struct dispc_v_coef coef_vdown_5tap[8] = {
 584                 {   0, 36, 56, 36,  0 },
 585                 {   4, 40, 55, 31, -2 },
 586                 {   8, 44, 54, 27, -5 },
 587                 {  12, 48, 53, 22, -7 },
 588                 {  -9, 17, 52, 51, 17 },
 589                 {  -7, 22, 53, 48, 12 },
 590                 {  -5, 27, 54, 44,  8 },
 591                 {  -2, 31, 55, 40,  4 },
 592         };
 593
 594         const struct dispc_h_coef *h_coef;
 595         const struct dispc_v_coef *v_coef;
 596         int i;
 597
 598         if (hscaleup)
 599                 h_coef = coef_hup;
 600         else
 601                 h_coef = coef_hdown;
 602
 603         if (vscaleup)
 604                 v_coef = five_taps ? coef_vup_5tap : coef_vup_3tap;
 605         else
 606                 v_coef = five_taps ? coef_vdown_5tap : coef_vdown_3tap;
 607
 608         for (i = 0; i < 8; i++) {
 609                 u32 h, hv;
 610
 611                 h = FLD_VAL(h_coef[i].hc0, 7, 0)
 612                         | FLD_VAL(h_coef[i].hc1, 15, 8)
 613                         | FLD_VAL(h_coef[i].hc2, 23, 16)
 614                         | FLD_VAL(h_coef[i].hc3, 31, 24);
 615                 hv = FLD_VAL(h_coef[i].hc4, 7, 0)
 616                         | FLD_VAL(v_coef[i].vc0, 15, 8)
 617                         | FLD_VAL(v_coef[i].vc1, 23, 16)
 618                         | FLD_VAL(v_coef[i].vc2, 31, 24);
 619
 620                 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
 621                         dispc_ovl_write_firh_reg(plane, i, h);
 622                         dispc_ovl_write_firhv_reg(plane, i, hv);
 623                 } else {
 624                         dispc_ovl_write_firh2_reg(plane, i, h);
 625                         dispc_ovl_write_firhv2_reg(plane, i, hv);
 626                 }
 627
 628         }
 629
 630         if (five_taps) {
 631                 for (i = 0; i < 8; i++) {
 632                         u32 v;
 633                         v = FLD_VAL(v_coef[i].vc00, 7, 0)
 634                                 | FLD_VAL(v_coef[i].vc22, 15, 8);
 635                         if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
 636                                 dispc_ovl_write_firv_reg(plane, i, v);
 637                         else
 638                                 dispc_ovl_write_firv2_reg(plane, i, v);
 639                 }
 640         }
 641 }
 642
 643 static void _dispc_setup_color_conv_coef(void)
 644 {
 645         int i;
 646         const struct color_conv_coef {
 647                 int  ry,  rcr,  rcb,   gy,  gcr,  gcb,   by,  bcr,  bcb;
 648                 int  full_range;
 649         }  ctbl_bt601_5 = {
 650                 298,  409,    0,  298, -208, -100,  298,    0,  517, 0,
 651         };
 652
 653         const struct color_conv_coef *ct;
 654
 655 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
 656
 657         ct = &ctbl_bt601_5;
 658
 659         for (i = 1; i < dss_feat_get_num_ovls(); i++) {
 660                 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 0),
 661                         CVAL(ct->rcr, ct->ry));
 662                 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 1),
 663                         CVAL(ct->gy,  ct->rcb));
 664                 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 2),
 665                         CVAL(ct->gcb, ct->gcr));
 666                 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 3),
 667                         CVAL(ct->bcr, ct->by));
 668                 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 4),
 669                         CVAL(0, ct->bcb));
 670
 671                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), ct->full_range,
 672                         11, 11);
 673         }
 674
 675 #undef CVAL
 676 }
 677
 678
 679 static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
 680 {
 681         dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
 682 }
 683
 684 static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
 685 {
 686         dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
 687 }
 688
 689 static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
 690 {
 691         dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
 692 }
 693
 694 static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
 695 {
 696         dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
 697 }
 698
 699 static void dispc_ovl_set_pos(enum omap_plane plane, int x, int y)
 700 {
 701         u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
 702
 703         dispc_write_reg(DISPC_OVL_POSITION(plane), val);
 704 }
 705
 706 static void dispc_ovl_set_pic_size(enum omap_plane plane, int width, int height)
 707 {
 708         u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 709
 710         if (plane == OMAP_DSS_GFX)
 711                 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
 712         else
 713                 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
 714 }
 715
 716 static void dispc_ovl_set_vid_size(enum omap_plane plane, int width, int height)
 717 {
 718         u32 val;
 719
 720         BUG_ON(plane == OMAP_DSS_GFX);
 721
 722         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 723
 724         dispc_write_reg(DISPC_OVL_SIZE(plane), val);
 725 }
 726
 727 static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane, bool enable)
 728 {
 729         struct omap_overlay *ovl = omap_dss_get_overlay(plane);
 730
 731         if ((ovl->caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
 732                 return;
 733
 734         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
 735 }
 736
 737 static void dispc_ovl_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
 738 {
 739         static const unsigned shifts[] = { 0, 8, 16, };
 740         int shift;
 741         struct omap_overlay *ovl = omap_dss_get_overlay(plane);
 742
 743         if ((ovl->caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
 744                 return;
 745
 746         shift = shifts[plane];
 747         REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
 748 }
 749
 750 static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
 751 {
 752         dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
 753 }
 754
 755 static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
 756 {
 757         dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
 758 }
 759
 760 static void dispc_ovl_set_color_mode(enum omap_plane plane,
 761                 enum omap_color_mode color_mode)
 762 {
 763         u32 m = 0;
 764         if (plane != OMAP_DSS_GFX) {
 765                 switch (color_mode) {
 766                 case OMAP_DSS_COLOR_NV12:
 767                         m = 0x0; break;
 768                 case OMAP_DSS_COLOR_RGB12U:
 769                         m = 0x1; break;
 770                 case OMAP_DSS_COLOR_RGBA16:
 771                         m = 0x2; break;
 772                 case OMAP_DSS_COLOR_RGBX16:
 773                         m = 0x4; break;
 774                 case OMAP_DSS_COLOR_ARGB16:
 775                         m = 0x5; break;
 776                 case OMAP_DSS_COLOR_RGB16:
 777                         m = 0x6; break;
 778                 case OMAP_DSS_COLOR_ARGB16_1555:
 779                         m = 0x7; break;
 780                 case OMAP_DSS_COLOR_RGB24U:
 781                         m = 0x8; break;
 782                 case OMAP_DSS_COLOR_RGB24P:
 783                         m = 0x9; break;
 784                 case OMAP_DSS_COLOR_YUV2:
 785                         m = 0xa; break;
 786                 case OMAP_DSS_COLOR_UYVY:
 787                         m = 0xb; break;
 788                 case OMAP_DSS_COLOR_ARGB32:
 789                         m = 0xc; break;
 790                 case OMAP_DSS_COLOR_RGBA32:
 791                         m = 0xd; break;
 792                 case OMAP_DSS_COLOR_RGBX32:
 793                         m = 0xe; break;
 794                 case OMAP_DSS_COLOR_XRGB16_1555:
 795                         m = 0xf; break;
 796                 default:
 797                         BUG(); break;
 798                 }
 799         } else {
 800                 switch (color_mode) {
 801                 case OMAP_DSS_COLOR_CLUT1:
 802                         m = 0x0; break;
 803                 case OMAP_DSS_COLOR_CLUT2:
 804                         m = 0x1; break;
 805                 case OMAP_DSS_COLOR_CLUT4:
 806                         m = 0x2; break;
 807                 case OMAP_DSS_COLOR_CLUT8:
 808                         m = 0x3; break;
 809                 case OMAP_DSS_COLOR_RGB12U:
 810                         m = 0x4; break;
 811                 case OMAP_DSS_COLOR_ARGB16:
 812                         m = 0x5; break;
 813                 case OMAP_DSS_COLOR_RGB16:
 814                         m = 0x6; break;
 815                 case OMAP_DSS_COLOR_ARGB16_1555:
 816                         m = 0x7; break;
 817                 case OMAP_DSS_COLOR_RGB24U:
 818                         m = 0x8; break;
 819                 case OMAP_DSS_COLOR_RGB24P:
 820                         m = 0x9; break;
 821                 case OMAP_DSS_COLOR_YUV2:
 822                         m = 0xa; break;
 823                 case OMAP_DSS_COLOR_UYVY:
 824                         m = 0xb; break;
 825                 case OMAP_DSS_COLOR_ARGB32:
 826                         m = 0xc; break;
 827                 case OMAP_DSS_COLOR_RGBA32:
 828                         m = 0xd; break;
 829                 case OMAP_DSS_COLOR_RGBX32:
 830                         m = 0xe; break;
 831                 case OMAP_DSS_COLOR_XRGB16_1555:
 832                         m = 0xf; break;
 833                 default:
 834                         BUG(); break;
 835                 }
 836         }
 837
 838         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
 839 }
 840
 841 static void dispc_ovl_set_channel_out(enum omap_plane plane,
 842                 enum omap_channel channel)
 843 {
 844         int shift;
 845         u32 val;
 846         int chan = 0, chan2 = 0;
 847
 848         switch (plane) {
 849         case OMAP_DSS_GFX:
 850                 shift = 8;
 851                 break;
 852         case OMAP_DSS_VIDEO1:
 853         case OMAP_DSS_VIDEO2:
 854                 shift = 16;
 855                 break;
 856         default:
 857                 BUG();
 858                 return;
 859         }
 860
 861         val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
 862         if (dss_has_feature(FEAT_MGR_LCD2)) {
 863                 switch (channel) {
 864                 case OMAP_DSS_CHANNEL_LCD:
 865                         chan = 0;
 866                         chan2 = 0;
 867                         break;
 868                 case OMAP_DSS_CHANNEL_DIGIT:
 869                         chan = 1;
 870                         chan2 = 0;
 871                         break;
 872                 case OMAP_DSS_CHANNEL_LCD2:
 873                         chan = 0;
 874                         chan2 = 1;
 875                         break;
 876                 default:
 877                         BUG();
 878                 }
 879
 880                 val = FLD_MOD(val, chan, shift, shift);
 881                 val = FLD_MOD(val, chan2, 31, 30);
 882         } else {
 883                 val = FLD_MOD(val, channel, shift, shift);
 884         }
 885         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
 886 }
 887
 888 static void dispc_ovl_set_burst_size(enum omap_plane plane,
 889                 enum omap_burst_size burst_size)
 890 {
 891         static const unsigned shifts[] = { 6, 14, 14, };
 892         int shift;
 893
 894         shift = shifts[plane];
 895         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
 896 }
 897
 898 static void dispc_configure_burst_sizes(void)
 899 {
 900         int i;
 901         const int burst_size = BURST_SIZE_X8;
 902
 903         /* Configure burst size always to maximum size */
 904         for (i = 0; i < omap_dss_get_num_overlays(); ++i)
 905                 dispc_ovl_set_burst_size(i, burst_size);
 906 }
 907
 908 u32 dispc_ovl_get_burst_size(enum omap_plane plane)
 909 {
 910         unsigned unit = dss_feat_get_burst_size_unit();
 911         /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
 912         return unit * 8;
 913 }
 914
 915 void dispc_enable_gamma_table(bool enable)
 916 {
 917         /*
 918          * This is partially implemented to support only disabling of
 919          * the gamma table.
 920          */
 921         if (enable) {
 922                 DSSWARN("Gamma table enabling for TV not yet supported");
 923                 return;
 924         }
 925
 926         REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
 927 }
 928
 929 void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
 930 {
 931         u16 reg;
 932
 933         if (channel == OMAP_DSS_CHANNEL_LCD)
 934                 reg = DISPC_CONFIG;
 935         else if (channel == OMAP_DSS_CHANNEL_LCD2)
 936                 reg = DISPC_CONFIG2;
 937         else
 938                 return;
 939
 940         REG_FLD_MOD(reg, enable, 15, 15);
 941 }
 942
 943 void dispc_mgr_set_cpr_coef(enum omap_channel channel,
 944                 struct omap_dss_cpr_coefs *coefs)
 945 {
 946         u32 coef_r, coef_g, coef_b;
 947
 948         if (channel != OMAP_DSS_CHANNEL_LCD && channel != OMAP_DSS_CHANNEL_LCD2)
 949                 return;
 950
 951         coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
 952                 FLD_VAL(coefs->rb, 9, 0);
 953         coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
 954                 FLD_VAL(coefs->gb, 9, 0);
 955         coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
 956                 FLD_VAL(coefs->bb, 9, 0);
 957
 958         dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
 959         dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
 960         dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
 961 }
 962
 963 static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
 964 {
 965         u32 val;
 966
 967         BUG_ON(plane == OMAP_DSS_GFX);
 968
 969         val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
 970         val = FLD_MOD(val, enable, 9, 9);
 971         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
 972 }
 973
 974 void dispc_ovl_enable_replication(enum omap_plane plane, bool enable)
 975 {
 976         static const unsigned shifts[] = { 5, 10, 10 };
 977         int shift;
 978
 979         shift = shifts[plane];
 980         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
 981 }
 982
 983 void dispc_mgr_set_lcd_size(enum omap_channel channel, u16 width, u16 height)
 984 {
 985         u32 val;
 986         BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
 987         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 988         dispc_write_reg(DISPC_SIZE_MGR(channel), val);
 989 }
 990
 991 void dispc_set_digit_size(u16 width, u16 height)
 992 {
 993         u32 val;
 994         BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
 995         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 996         dispc_write_reg(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT), val);
 997 }
 998
 999 static void dispc_read_plane_fifo_sizes(void)
1000 {
1001         u32 size;
1002         int plane;
1003         u8 start, end;
1004         u32 unit;
1005
1006         unit = dss_feat_get_buffer_size_unit();
1007
1008         dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
1009
1010         for (plane = 0; plane < dss_feat_get_num_ovls(); ++plane) {
1011                 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(plane), start, end);
1012                 size *= unit;
1013                 dispc.fifo_size[plane] = size;
1014         }
1015 }
1016
1017 u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
1018 {
1019         return dispc.fifo_size[plane];
1020 }
1021
1022 void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
1023 {
1024         u8 hi_start, hi_end, lo_start, lo_end;
1025         u32 unit;
1026
1027         unit = dss_feat_get_buffer_size_unit();
1028
1029         WARN_ON(low % unit != 0);
1030         WARN_ON(high % unit != 0);
1031
1032         low /= unit;
1033         high /= unit;
1034
1035         dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1036         dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1037
1038         DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n",
1039                         plane,
1040                         REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1041                                 lo_start, lo_end),
1042                         REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1043                                 hi_start, hi_end),
1044                         low, high);
1045
1046         dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
1047                         FLD_VAL(high, hi_start, hi_end) |
1048                         FLD_VAL(low, lo_start, lo_end));
1049 }
1050
1051 void dispc_enable_fifomerge(bool enable)
1052 {
1053         DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1054         REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1055 }
1056
1057 static void dispc_ovl_set_fir(enum omap_plane plane,
1058                                 int hinc, int vinc,
1059                                 enum omap_color_component color_comp)
1060 {
1061         u32 val;
1062
1063         if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1064                 u8 hinc_start, hinc_end, vinc_start, vinc_end;
1065
1066                 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1067                                         &hinc_start, &hinc_end);
1068                 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1069                                         &vinc_start, &vinc_end);
1070                 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1071                                 FLD_VAL(hinc, hinc_start, hinc_end);
1072
1073                 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1074         } else {
1075                 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1076                 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1077         }
1078 }
1079
1080 static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1081 {
1082         u32 val;
1083         u8 hor_start, hor_end, vert_start, vert_end;
1084
1085         dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1086         dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1087
1088         val = FLD_VAL(vaccu, vert_start, vert_end) |
1089                         FLD_VAL(haccu, hor_start, hor_end);
1090
1091         dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
1092 }
1093
1094 static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1095 {
1096         u32 val;
1097         u8 hor_start, hor_end, vert_start, vert_end;
1098
1099         dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1100         dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1101
1102         val = FLD_VAL(vaccu, vert_start, vert_end) |
1103                         FLD_VAL(haccu, hor_start, hor_end);
1104
1105         dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
1106 }
1107
1108 static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1109                 int vaccu)
1110 {
1111         u32 val;
1112
1113         val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1114         dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1115 }
1116
1117 static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1118                 int vaccu)
1119 {
1120         u32 val;
1121
1122         val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1123         dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1124 }
1125
1126 static void dispc_ovl_set_scale_param(enum omap_plane plane,
1127                 u16 orig_width, u16 orig_height,
1128                 u16 out_width, u16 out_height,
1129                 bool five_taps, u8 rotation,
1130                 enum omap_color_component color_comp)
1131 {
1132         int fir_hinc, fir_vinc;
1133         int hscaleup, vscaleup;
1134
1135         hscaleup = orig_width <= out_width;
1136         vscaleup = orig_height <= out_height;
1137
1138         dispc_ovl_set_scale_coef(plane, hscaleup, vscaleup, five_taps,
1139                         color_comp);
1140
1141         fir_hinc = 1024 * orig_width / out_width;
1142         fir_vinc = 1024 * orig_height / out_height;
1143
1144         dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
1145 }
1146
1147 static void dispc_ovl_set_scaling_common(enum omap_plane plane,
1148                 u16 orig_width, u16 orig_height,
1149                 u16 out_width, u16 out_height,
1150                 bool ilace, bool five_taps,
1151                 bool fieldmode, enum omap_color_mode color_mode,
1152                 u8 rotation)
1153 {
1154         int accu0 = 0;
1155         int accu1 = 0;
1156         u32 l;
1157
1158         dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1159                                 out_width, out_height, five_taps,
1160                                 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
1161         l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1162
1163         /* RESIZEENABLE and VERTICALTAPS */
1164         l &= ~((0x3 << 5) | (0x1 << 21));
1165         l |= (orig_width != out_width) ? (1 << 5) : 0;
1166         l |= (orig_height != out_height) ? (1 << 6) : 0;
1167         l |= five_taps ? (1 << 21) : 0;
1168
1169         /* VRESIZECONF and HRESIZECONF */
1170         if (dss_has_feature(FEAT_RESIZECONF)) {
1171                 l &= ~(0x3 << 7);
1172                 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1173                 l |= (orig_height <= out_height) ? 0 : (1 << 8);
1174         }
1175
1176         /* LINEBUFFERSPLIT */
1177         if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1178                 l &= ~(0x1 << 22);
1179                 l |= five_taps ? (1 << 22) : 0;
1180         }
1181
1182         dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
1183
1184         /*
1185          * field 0 = even field = bottom field
1186          * field 1 = odd field = top field
1187          */
1188         if (ilace && !fieldmode) {
1189                 accu1 = 0;
1190                 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
1191                 if (accu0 >= 1024/2) {
1192                         accu1 = 1024/2;
1193                         accu0 -= accu1;
1194                 }
1195         }
1196
1197         dispc_ovl_set_vid_accu0(plane, 0, accu0);
1198         dispc_ovl_set_vid_accu1(plane, 0, accu1);
1199 }
1200
1201 static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
1202                 u16 orig_width, u16 orig_height,
1203                 u16 out_width, u16 out_height,
1204                 bool ilace, bool five_taps,
1205                 bool fieldmode, enum omap_color_mode color_mode,
1206                 u8 rotation)
1207 {
1208         int scale_x = out_width != orig_width;
1209         int scale_y = out_height != orig_height;
1210
1211         if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1212                 return;
1213         if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1214                         color_mode != OMAP_DSS_COLOR_UYVY &&
1215                         color_mode != OMAP_DSS_COLOR_NV12)) {
1216                 /* reset chroma resampling for RGB formats  */
1217                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1218                 return;
1219         }
1220         switch (color_mode) {
1221         case OMAP_DSS_COLOR_NV12:
1222                 /* UV is subsampled by 2 vertically*/
1223                 orig_height >>= 1;
1224                 /* UV is subsampled by 2 horz.*/
1225                 orig_width >>= 1;
1226                 break;
1227         case OMAP_DSS_COLOR_YUV2:
1228         case OMAP_DSS_COLOR_UYVY:
1229                 /*For YUV422 with 90/270 rotation,
1230                  *we don't upsample chroma
1231                  */
1232                 if (rotation == OMAP_DSS_ROT_0 ||
1233                         rotation == OMAP_DSS_ROT_180)
1234                         /* UV is subsampled by 2 hrz*/
1235                         orig_width >>= 1;
1236                 /* must use FIR for YUV422 if rotated */
1237                 if (rotation != OMAP_DSS_ROT_0)
1238                         scale_x = scale_y = true;
1239                 break;
1240         default:
1241                 BUG();
1242         }
1243
1244         if (out_width != orig_width)
1245                 scale_x = true;
1246         if (out_height != orig_height)
1247                 scale_y = true;
1248
1249         dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1250                         out_width, out_height, five_taps,
1251                                 rotation, DISPC_COLOR_COMPONENT_UV);
1252
1253         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1254                 (scale_x || scale_y) ? 1 : 0, 8, 8);
1255         /* set H scaling */
1256         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1257         /* set V scaling */
1258         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1259
1260         dispc_ovl_set_vid_accu2_0(plane, 0x80, 0);
1261         dispc_ovl_set_vid_accu2_1(plane, 0x80, 0);
1262 }
1263
1264 static void dispc_ovl_set_scaling(enum omap_plane plane,
1265                 u16 orig_width, u16 orig_height,
1266                 u16 out_width, u16 out_height,
1267                 bool ilace, bool five_taps,
1268                 bool fieldmode, enum omap_color_mode color_mode,
1269                 u8 rotation)
1270 {
1271         BUG_ON(plane == OMAP_DSS_GFX);
1272
1273         dispc_ovl_set_scaling_common(plane,
1274                         orig_width, orig_height,
1275                         out_width, out_height,
1276                         ilace, five_taps,
1277                         fieldmode, color_mode,
1278                         rotation);
1279
1280         dispc_ovl_set_scaling_uv(plane,
1281                 orig_width, orig_height,
1282                 out_width, out_height,
1283                 ilace, five_taps,
1284                 fieldmode, color_mode,
1285                 rotation);
1286 }
1287
1288 static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1289                 bool mirroring, enum omap_color_mode color_mode)
1290 {
1291         bool row_repeat = false;
1292         int vidrot = 0;
1293
1294         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1295                         color_mode == OMAP_DSS_COLOR_UYVY) {
1296
1297                 if (mirroring) {
1298                         switch (rotation) {
1299                         case OMAP_DSS_ROT_0:
1300                                 vidrot = 2;
1301                                 break;
1302                         case OMAP_DSS_ROT_90:
1303                                 vidrot = 1;
1304                                 break;
1305                         case OMAP_DSS_ROT_180:
1306                                 vidrot = 0;
1307                                 break;
1308                         case OMAP_DSS_ROT_270:
1309                                 vidrot = 3;
1310                                 break;
1311                         }
1312                 } else {
1313                         switch (rotation) {
1314                         case OMAP_DSS_ROT_0:
1315                                 vidrot = 0;
1316                                 break;
1317                         case OMAP_DSS_ROT_90:
1318                                 vidrot = 1;
1319                                 break;
1320                         case OMAP_DSS_ROT_180:
1321                                 vidrot = 2;
1322                                 break;
1323                         case OMAP_DSS_ROT_270:
1324                                 vidrot = 3;
1325                                 break;
1326                         }
1327                 }
1328
1329                 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
1330                         row_repeat = true;
1331                 else
1332                         row_repeat = false;
1333         }
1334
1335         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
1336         if (dss_has_feature(FEAT_ROWREPEATENABLE))
1337                 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1338                         row_repeat ? 1 : 0, 18, 18);
1339 }
1340
1341 static int color_mode_to_bpp(enum omap_color_mode color_mode)
1342 {
1343         switch (color_mode) {
1344         case OMAP_DSS_COLOR_CLUT1:
1345                 return 1;
1346         case OMAP_DSS_COLOR_CLUT2:
1347                 return 2;
1348         case OMAP_DSS_COLOR_CLUT4:
1349                 return 4;
1350         case OMAP_DSS_COLOR_CLUT8:
1351         case OMAP_DSS_COLOR_NV12:
1352                 return 8;
1353         case OMAP_DSS_COLOR_RGB12U:
1354         case OMAP_DSS_COLOR_RGB16:
1355         case OMAP_DSS_COLOR_ARGB16:
1356         case OMAP_DSS_COLOR_YUV2:
1357         case OMAP_DSS_COLOR_UYVY:
1358         case OMAP_DSS_COLOR_RGBA16:
1359         case OMAP_DSS_COLOR_RGBX16:
1360         case OMAP_DSS_COLOR_ARGB16_1555:
1361         case OMAP_DSS_COLOR_XRGB16_1555:
1362                 return 16;
1363         case OMAP_DSS_COLOR_RGB24P:
1364                 return 24;
1365         case OMAP_DSS_COLOR_RGB24U:
1366         case OMAP_DSS_COLOR_ARGB32:
1367         case OMAP_DSS_COLOR_RGBA32:
1368         case OMAP_DSS_COLOR_RGBX32:
1369                 return 32;
1370         default:
1371                 BUG();
1372         }
1373 }
1374
1375 static s32 pixinc(int pixels, u8 ps)
1376 {
1377         if (pixels == 1)
1378                 return 1;
1379         else if (pixels > 1)
1380                 return 1 + (pixels - 1) * ps;
1381         else if (pixels < 0)
1382                 return 1 - (-pixels + 1) * ps;
1383         else
1384                 BUG();
1385 }
1386
1387 static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1388                 u16 screen_width,
1389                 u16 width, u16 height,
1390                 enum omap_color_mode color_mode, bool fieldmode,
1391                 unsigned int field_offset,
1392                 unsigned *offset0, unsigned *offset1,
1393                 s32 *row_inc, s32 *pix_inc)
1394 {
1395         u8 ps;
1396
1397         /* FIXME CLUT formats */
1398         switch (color_mode) {
1399         case OMAP_DSS_COLOR_CLUT1:
1400         case OMAP_DSS_COLOR_CLUT2:
1401         case OMAP_DSS_COLOR_CLUT4:
1402         case OMAP_DSS_COLOR_CLUT8:
1403                 BUG();
1404                 return;
1405         case OMAP_DSS_COLOR_YUV2:
1406         case OMAP_DSS_COLOR_UYVY:
1407                 ps = 4;
1408                 break;
1409         default:
1410                 ps = color_mode_to_bpp(color_mode) / 8;
1411                 break;
1412         }
1413
1414         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1415                         width, height);
1416
1417         /*
1418          * field 0 = even field = bottom field
1419          * field 1 = odd field = top field
1420          */
1421         switch (rotation + mirror * 4) {
1422         case OMAP_DSS_ROT_0:
1423         case OMAP_DSS_ROT_180:
1424                 /*
1425                  * If the pixel format is YUV or UYVY divide the width
1426                  * of the image by 2 for 0 and 180 degree rotation.
1427                  */
1428                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1429                         color_mode == OMAP_DSS_COLOR_UYVY)
1430                         width = width >> 1;
1431         case OMAP_DSS_ROT_90:
1432         case OMAP_DSS_ROT_270:
1433                 *offset1 = 0;
1434                 if (field_offset)
1435                         *offset0 = field_offset * screen_width * ps;
1436                 else
1437                         *offset0 = 0;
1438
1439                 *row_inc = pixinc(1 + (screen_width - width) +
1440                                 (fieldmode ? screen_width : 0),
1441                                 ps);
1442                 *pix_inc = pixinc(1, ps);
1443                 break;
1444
1445         case OMAP_DSS_ROT_0 + 4:
1446         case OMAP_DSS_ROT_180 + 4:
1447                 /* If the pixel format is YUV or UYVY divide the width
1448                  * of the image by 2  for 0 degree and 180 degree
1449                  */
1450                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1451                         color_mode == OMAP_DSS_COLOR_UYVY)
1452                         width = width >> 1;
1453         case OMAP_DSS_ROT_90 + 4:
1454         case OMAP_DSS_ROT_270 + 4:
1455                 *offset1 = 0;
1456                 if (field_offset)
1457                         *offset0 = field_offset * screen_width * ps;
1458                 else
1459                         *offset0 = 0;
1460                 *row_inc = pixinc(1 - (screen_width + width) -
1461                                 (fieldmode ? screen_width : 0),
1462                                 ps);
1463                 *pix_inc = pixinc(1, ps);
1464                 break;
1465
1466         default:
1467                 BUG();
1468         }
1469 }
1470
1471 static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1472                 u16 screen_width,
1473                 u16 width, u16 height,
1474                 enum omap_color_mode color_mode, bool fieldmode,
1475                 unsigned int field_offset,
1476                 unsigned *offset0, unsigned *offset1,
1477                 s32 *row_inc, s32 *pix_inc)
1478 {
1479         u8 ps;
1480         u16 fbw, fbh;
1481
1482         /* FIXME CLUT formats */
1483         switch (color_mode) {
1484         case OMAP_DSS_COLOR_CLUT1:
1485         case OMAP_DSS_COLOR_CLUT2:
1486         case OMAP_DSS_COLOR_CLUT4:
1487         case OMAP_DSS_COLOR_CLUT8:
1488                 BUG();
1489                 return;
1490         default:
1491                 ps = color_mode_to_bpp(color_mode) / 8;
1492                 break;
1493         }
1494
1495         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1496                         width, height);
1497
1498         /* width & height are overlay sizes, convert to fb sizes */
1499
1500         if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1501                 fbw = width;
1502                 fbh = height;
1503         } else {
1504                 fbw = height;
1505                 fbh = width;
1506         }
1507
1508         /*
1509          * field 0 = even field = bottom field
1510          * field 1 = odd field = top field
1511          */
1512         switch (rotation + mirror * 4) {
1513         case OMAP_DSS_ROT_0:
1514                 *offset1 = 0;
1515                 if (field_offset)
1516                         *offset0 = *offset1 + field_offset * screen_width * ps;
1517                 else
1518                         *offset0 = *offset1;
1519                 *row_inc = pixinc(1 + (screen_width - fbw) +
1520                                 (fieldmode ? screen_width : 0),
1521                                 ps);
1522                 *pix_inc = pixinc(1, ps);
1523                 break;
1524         case OMAP_DSS_ROT_90:
1525                 *offset1 = screen_width * (fbh - 1) * ps;
1526                 if (field_offset)
1527                         *offset0 = *offset1 + field_offset * ps;
1528                 else
1529                         *offset0 = *offset1;
1530                 *row_inc = pixinc(screen_width * (fbh - 1) + 1 +
1531                                 (fieldmode ? 1 : 0), ps);
1532                 *pix_inc = pixinc(-screen_width, ps);
1533                 break;
1534         case OMAP_DSS_ROT_180:
1535                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1536                 if (field_offset)
1537                         *offset0 = *offset1 - field_offset * screen_width * ps;
1538                 else
1539                         *offset0 = *offset1;
1540                 *row_inc = pixinc(-1 -
1541                                 (screen_width - fbw) -
1542                                 (fieldmode ? screen_width : 0),
1543                                 ps);
1544                 *pix_inc = pixinc(-1, ps);
1545                 break;
1546         case OMAP_DSS_ROT_270:
1547                 *offset1 = (fbw - 1) * ps;
1548                 if (field_offset)
1549                         *offset0 = *offset1 - field_offset * ps;
1550                 else
1551                         *offset0 = *offset1;
1552                 *row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
1553                                 (fieldmode ? 1 : 0), ps);
1554                 *pix_inc = pixinc(screen_width, ps);
1555                 break;
1556
1557         /* mirroring */
1558         case OMAP_DSS_ROT_0 + 4:
1559                 *offset1 = (fbw - 1) * ps;
1560                 if (field_offset)
1561                         *offset0 = *offset1 + field_offset * screen_width * ps;
1562                 else
1563                         *offset0 = *offset1;
1564                 *row_inc = pixinc(screen_width * 2 - 1 +
1565                                 (fieldmode ? screen_width : 0),
1566                                 ps);
1567                 *pix_inc = pixinc(-1, ps);
1568                 break;
1569
1570         case OMAP_DSS_ROT_90 + 4:
1571                 *offset1 = 0;
1572                 if (field_offset)
1573                         *offset0 = *offset1 + field_offset * ps;
1574                 else
1575                         *offset0 = *offset1;
1576                 *row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
1577                                 (fieldmode ? 1 : 0),
1578                                 ps);
1579                 *pix_inc = pixinc(screen_width, ps);
1580                 break;
1581
1582         case OMAP_DSS_ROT_180 + 4:
1583                 *offset1 = screen_width * (fbh - 1) * ps;
1584                 if (field_offset)
1585                         *offset0 = *offset1 - field_offset * screen_width * ps;
1586                 else
1587                         *offset0 = *offset1;
1588                 *row_inc = pixinc(1 - screen_width * 2 -
1589                                 (fieldmode ? screen_width : 0),
1590                                 ps);
1591                 *pix_inc = pixinc(1, ps);
1592                 break;
1593
1594         case OMAP_DSS_ROT_270 + 4:
1595                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1596                 if (field_offset)
1597                         *offset0 = *offset1 - field_offset * ps;
1598                 else
1599                         *offset0 = *offset1;
1600                 *row_inc = pixinc(screen_width * (fbh - 1) - 1 -
1601                                 (fieldmode ? 1 : 0),
1602                                 ps);
1603                 *pix_inc = pixinc(-screen_width, ps);
1604                 break;
1605
1606         default:
1607                 BUG();
1608         }
1609 }
1610
1611 static unsigned long calc_fclk_five_taps(enum omap_channel channel, u16 width,
1612                 u16 height, u16 out_width, u16 out_height,
1613                 enum omap_color_mode color_mode)
1614 {
1615         u32 fclk = 0;
1616         /* FIXME venc pclk? */
1617         u64 tmp, pclk = dispc_mgr_pclk_rate(channel);
1618
1619         if (height > out_height) {
1620                 /* FIXME get real display PPL */
1621                 unsigned int ppl = 800;
1622
1623                 tmp = pclk * height * out_width;
1624                 do_div(tmp, 2 * out_height * ppl);
1625                 fclk = tmp;
1626
1627                 if (height > 2 * out_height) {
1628                         if (ppl == out_width)
1629                                 return 0;
1630
1631                         tmp = pclk * (height - 2 * out_height) * out_width;
1632                         do_div(tmp, 2 * out_height * (ppl - out_width));
1633                         fclk = max(fclk, (u32) tmp);
1634                 }
1635         }
1636
1637         if (width > out_width) {
1638                 tmp = pclk * width;
1639                 do_div(tmp, out_width);
1640                 fclk = max(fclk, (u32) tmp);
1641
1642                 if (color_mode == OMAP_DSS_COLOR_RGB24U)
1643                         fclk <<= 1;
1644         }
1645
1646         return fclk;
1647 }
1648
1649 static unsigned long calc_fclk(enum omap_channel channel, u16 width,
1650                 u16 height, u16 out_width, u16 out_height)
1651 {
1652         unsigned int hf, vf;
1653
1654         /*
1655          * FIXME how to determine the 'A' factor
1656          * for the no downscaling case ?
1657          */
1658
1659         if (width > 3 * out_width)
1660                 hf = 4;
1661         else if (width > 2 * out_width)
1662                 hf = 3;
1663         else if (width > out_width)
1664                 hf = 2;
1665         else
1666                 hf = 1;
1667
1668         if (height > out_height)
1669                 vf = 2;
1670         else
1671                 vf = 1;
1672
1673         /* FIXME venc pclk? */
1674         return dispc_mgr_pclk_rate(channel) * vf * hf;
1675 }
1676
1677 int dispc_ovl_setup(enum omap_plane plane,
1678                 u32 paddr, u16 screen_width,
1679                 u16 pos_x, u16 pos_y,
1680                 u16 width, u16 height,
1681                 u16 out_width, u16 out_height,
1682                 enum omap_color_mode color_mode,
1683                 bool ilace,
1684                 enum omap_dss_rotation_type rotation_type,
1685                 u8 rotation, bool mirror,
1686                 u8 global_alpha, u8 pre_mult_alpha,
1687                 enum omap_channel channel, u32 puv_addr)
1688 {
1689         const int maxdownscale = cpu_is_omap34xx() ? 4 : 2;
1690         bool five_taps = 0;
1691         bool fieldmode = 0;
1692         int cconv = 0;
1693         unsigned offset0, offset1;
1694         s32 row_inc;
1695         s32 pix_inc;
1696         u16 frame_height = height;
1697         unsigned int field_offset = 0;
1698
1699         DSSDBG("dispc_ovl_setup %d, pa %x, sw %d, %d,%d, %dx%d -> "
1700                "%dx%d, ilace %d, cmode %x, rot %d, mir %d chan %d\n",
1701                plane, paddr, screen_width, pos_x, pos_y,
1702                width, height,
1703                out_width, out_height,
1704                ilace, color_mode,
1705                rotation, mirror, channel);
1706
1707         if (paddr == 0)
1708                 return -EINVAL;
1709
1710         if (ilace && height == out_height)
1711                 fieldmode = 1;
1712
1713         if (ilace) {
1714                 if (fieldmode)
1715                         height /= 2;
1716                 pos_y /= 2;
1717                 out_height /= 2;
1718
1719                 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
1720                                 "out_height %d\n",
1721                                 height, pos_y, out_height);
1722         }
1723
1724         if (!dss_feat_color_mode_supported(plane, color_mode))
1725                 return -EINVAL;
1726
1727         if (plane == OMAP_DSS_GFX) {
1728                 if (width != out_width || height != out_height)
1729                         return -EINVAL;
1730         } else {
1731                 /* video plane */
1732
1733                 unsigned long fclk = 0;
1734
1735                 if (out_width < width / maxdownscale ||
1736                    out_width > width * 8)
1737                         return -EINVAL;
1738
1739                 if (out_height < height / maxdownscale ||
1740                    out_height > height * 8)
1741                         return -EINVAL;
1742
1743                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1744                         color_mode == OMAP_DSS_COLOR_UYVY ||
1745                         color_mode == OMAP_DSS_COLOR_NV12)
1746                         cconv = 1;
1747
1748                 /* Must use 5-tap filter? */
1749                 five_taps = height > out_height * 2;
1750
1751                 if (!five_taps) {
1752                         fclk = calc_fclk(channel, width, height, out_width,
1753                                         out_height);
1754
1755                         /* Try 5-tap filter if 3-tap fclk is too high */
1756                         if (cpu_is_omap34xx() && height > out_height &&
1757                                         fclk > dispc_fclk_rate())
1758                                 five_taps = true;
1759                 }
1760
1761                 if (width > (2048 >> five_taps)) {
1762                         DSSERR("failed to set up scaling, fclk too low\n");
1763                         return -EINVAL;
1764                 }
1765
1766                 if (five_taps)
1767                         fclk = calc_fclk_five_taps(channel, width, height,
1768                                         out_width, out_height, color_mode);
1769
1770                 DSSDBG("required fclk rate = %lu Hz\n", fclk);
1771                 DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
1772
1773                 if (!fclk || fclk > dispc_fclk_rate()) {
1774                         DSSERR("failed to set up scaling, "
1775                                         "required fclk rate = %lu Hz, "
1776                                         "current fclk rate = %lu Hz\n",
1777                                         fclk, dispc_fclk_rate());
1778                         return -EINVAL;
1779                 }
1780         }
1781
1782         if (ilace && !fieldmode) {
1783                 /*
1784                  * when downscaling the bottom field may have to start several
1785                  * source lines below the top field. Unfortunately ACCUI
1786                  * registers will only hold the fractional part of the offset
1787                  * so the integer part must be added to the base address of the
1788                  * bottom field.
1789                  */
1790                 if (!height || height == out_height)
1791                         field_offset = 0;
1792                 else
1793                         field_offset = height / out_height / 2;
1794         }
1795
1796         /* Fields are independent but interleaved in memory. */
1797         if (fieldmode)
1798                 field_offset = 1;
1799
1800         if (rotation_type == OMAP_DSS_ROT_DMA)
1801                 calc_dma_rotation_offset(rotation, mirror,
1802                                 screen_width, width, frame_height, color_mode,
1803                                 fieldmode, field_offset,
1804                                 &offset0, &offset1, &row_inc, &pix_inc);
1805         else
1806                 calc_vrfb_rotation_offset(rotation, mirror,
1807                                 screen_width, width, frame_height, color_mode,
1808                                 fieldmode, field_offset,
1809                                 &offset0, &offset1, &row_inc, &pix_inc);
1810
1811         DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
1812                         offset0, offset1, row_inc, pix_inc);
1813
1814         dispc_ovl_set_color_mode(plane, color_mode);
1815
1816         dispc_ovl_set_ba0(plane, paddr + offset0);
1817         dispc_ovl_set_ba1(plane, paddr + offset1);
1818
1819         if (OMAP_DSS_COLOR_NV12 == color_mode) {
1820                 dispc_ovl_set_ba0_uv(plane, puv_addr + offset0);
1821                 dispc_ovl_set_ba1_uv(plane, puv_addr + offset1);
1822         }
1823
1824
1825         dispc_ovl_set_row_inc(plane, row_inc);
1826         dispc_ovl_set_pix_inc(plane, pix_inc);
1827
1828         DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, width, height,
1829                         out_width, out_height);
1830
1831         dispc_ovl_set_pos(plane, pos_x, pos_y);
1832
1833         dispc_ovl_set_pic_size(plane, width, height);
1834
1835         if (plane != OMAP_DSS_GFX) {
1836                 dispc_ovl_set_scaling(plane, width, height,
1837                                    out_width, out_height,
1838                                    ilace, five_taps, fieldmode,
1839                                    color_mode, rotation);
1840                 dispc_ovl_set_vid_size(plane, out_width, out_height);
1841                 dispc_ovl_set_vid_color_conv(plane, cconv);
1842         }
1843
1844         dispc_ovl_set_rotation_attrs(plane, rotation, mirror, color_mode);
1845
1846         dispc_ovl_set_pre_mult_alpha(plane, pre_mult_alpha);
1847         dispc_ovl_setup_global_alpha(plane, global_alpha);
1848
1849         dispc_ovl_set_channel_out(plane, channel);
1850
1851         return 0;
1852 }
1853
1854 int dispc_ovl_enable(enum omap_plane plane, bool enable)
1855 {
1856         DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
1857
1858         REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
1859
1860         return 0;
1861 }
1862
1863 static void dispc_disable_isr(void *data, u32 mask)
1864 {
1865         struct completion *compl = data;
1866         complete(compl);
1867 }
1868
1869 static void _enable_lcd_out(enum omap_channel channel, bool enable)
1870 {
1871         if (channel == OMAP_DSS_CHANNEL_LCD2)
1872                 REG_FLD_MOD(DISPC_CONTROL2, enable ? 1 : 0, 0, 0);
1873         else
1874                 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
1875 }
1876
1877 static void dispc_mgr_enable_lcd_out(enum omap_channel channel, bool enable)
1878 {
1879         struct completion frame_done_completion;
1880         bool is_on;
1881         int r;
1882         u32 irq;
1883
1884         /* When we disable LCD output, we need to wait until frame is done.
1885          * Otherwise the DSS is still working, and turning off the clocks
1886          * prevents DSS from going to OFF mode */
1887         is_on = channel == OMAP_DSS_CHANNEL_LCD2 ?
1888                         REG_GET(DISPC_CONTROL2, 0, 0) :
1889                         REG_GET(DISPC_CONTROL, 0, 0);
1890
1891         irq = channel == OMAP_DSS_CHANNEL_LCD2 ? DISPC_IRQ_FRAMEDONE2 :
1892                         DISPC_IRQ_FRAMEDONE;
1893
1894         if (!enable && is_on) {
1895                 init_completion(&frame_done_completion);
1896
1897                 r = omap_dispc_register_isr(dispc_disable_isr,
1898                                 &frame_done_completion, irq);
1899
1900                 if (r)
1901                         DSSERR("failed to register FRAMEDONE isr\n");
1902         }
1903
1904         _enable_lcd_out(channel, enable);
1905
1906         if (!enable && is_on) {
1907                 if (!wait_for_completion_timeout(&frame_done_completion,
1908                                         msecs_to_jiffies(100)))
1909                         DSSERR("timeout waiting for FRAME DONE\n");
1910
1911                 r = omap_dispc_unregister_isr(dispc_disable_isr,
1912                                 &frame_done_completion, irq);
1913
1914                 if (r)
1915                         DSSERR("failed to unregister FRAMEDONE isr\n");
1916         }
1917 }
1918
1919 static void _enable_digit_out(bool enable)
1920 {
1921         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
1922 }
1923
1924 static void dispc_mgr_enable_digit_out(bool enable)
1925 {
1926         struct completion frame_done_completion;
1927         enum dss_hdmi_venc_clk_source_select src;
1928         int r, i;
1929         u32 irq_mask;
1930         int num_irqs;
1931
1932         if (REG_GET(DISPC_CONTROL, 1, 1) == enable)
1933                 return;
1934
1935         src = dss_get_hdmi_venc_clk_source();
1936
1937         if (enable) {
1938                 unsigned long flags;
1939                 /* When we enable digit output, we'll get an extra digit
1940                  * sync lost interrupt, that we need to ignore */
1941                 spin_lock_irqsave(&dispc.irq_lock, flags);
1942                 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
1943                 _omap_dispc_set_irqs();
1944                 spin_unlock_irqrestore(&dispc.irq_lock, flags);
1945         }
1946
1947         /* When we disable digit output, we need to wait until fields are done.
1948          * Otherwise the DSS is still working, and turning off the clocks
1949          * prevents DSS from going to OFF mode. And when enabling, we need to
1950          * wait for the extra sync losts */
1951         init_completion(&frame_done_completion);
1952
1953         if (src == DSS_HDMI_M_PCLK && enable == false) {
1954                 irq_mask = DISPC_IRQ_FRAMEDONETV;
1955                 num_irqs = 1;
1956         } else {
1957                 irq_mask = DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD;
1958                 /* XXX I understand from TRM that we should only wait for the
1959                  * current field to complete. But it seems we have to wait for
1960                  * both fields */
1961                 num_irqs = 2;
1962         }
1963
1964         r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
1965                         irq_mask);
1966         if (r)
1967                 DSSERR("failed to register %x isr\n", irq_mask);
1968
1969         _enable_digit_out(enable);
1970
1971         for (i = 0; i < num_irqs; ++i) {
1972                 if (!wait_for_completion_timeout(&frame_done_completion,
1973                                         msecs_to_jiffies(100)))
1974                         DSSERR("timeout waiting for digit out to %s\n",
1975                                         enable ? "start" : "stop");
1976         }
1977
1978         r = omap_dispc_unregister_isr(dispc_disable_isr, &frame_done_completion,
1979                         irq_mask);
1980         if (r)
1981                 DSSERR("failed to unregister %x isr\n", irq_mask);
1982
1983         if (enable) {
1984                 unsigned long flags;
1985                 spin_lock_irqsave(&dispc.irq_lock, flags);
1986                 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST_DIGIT;
1987                 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
1988                 _omap_dispc_set_irqs();
1989                 spin_unlock_irqrestore(&dispc.irq_lock, flags);
1990         }
1991 }
1992
1993 bool dispc_mgr_is_enabled(enum omap_channel channel)
1994 {
1995         if (channel == OMAP_DSS_CHANNEL_LCD)
1996                 return !!REG_GET(DISPC_CONTROL, 0, 0);
1997         else if (channel == OMAP_DSS_CHANNEL_DIGIT)
1998                 return !!REG_GET(DISPC_CONTROL, 1, 1);
1999         else if (channel == OMAP_DSS_CHANNEL_LCD2)
2000                 return !!REG_GET(DISPC_CONTROL2, 0, 0);
2001         else
2002                 BUG();
2003 }
2004
2005 void dispc_mgr_enable(enum omap_channel channel, bool enable)
2006 {
2007         if (channel == OMAP_DSS_CHANNEL_LCD ||
2008                         channel == OMAP_DSS_CHANNEL_LCD2)
2009                 dispc_mgr_enable_lcd_out(channel, enable);
2010         else if (channel == OMAP_DSS_CHANNEL_DIGIT)
2011                 dispc_mgr_enable_digit_out(enable);
2012         else
2013                 BUG();
2014 }
2015
2016 void dispc_lcd_enable_signal_polarity(bool act_high)
2017 {
2018         if (!dss_has_feature(FEAT_LCDENABLEPOL))
2019                 return;
2020
2021         REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
2022 }
2023
2024 void dispc_lcd_enable_signal(bool enable)
2025 {
2026         if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2027                 return;
2028
2029         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
2030 }
2031
2032 void dispc_pck_free_enable(bool enable)
2033 {
2034         if (!dss_has_feature(FEAT_PCKFREEENABLE))
2035                 return;
2036
2037         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
2038 }
2039
2040 void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
2041 {
2042         if (channel == OMAP_DSS_CHANNEL_LCD2)
2043                 REG_FLD_MOD(DISPC_CONFIG2, enable ? 1 : 0, 16, 16);
2044         else
2045                 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
2046 }
2047
2048
2049 void dispc_mgr_set_lcd_display_type(enum omap_channel channel,
2050                 enum omap_lcd_display_type type)
2051 {
2052         int mode;
2053
2054         switch (type) {
2055         case OMAP_DSS_LCD_DISPLAY_STN:
2056                 mode = 0;
2057                 break;
2058
2059         case OMAP_DSS_LCD_DISPLAY_TFT:
2060                 mode = 1;
2061                 break;
2062
2063         default:
2064                 BUG();
2065                 return;
2066         }
2067
2068         if (channel == OMAP_DSS_CHANNEL_LCD2)
2069                 REG_FLD_MOD(DISPC_CONTROL2, mode, 3, 3);
2070         else
2071                 REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
2072 }
2073
2074 void dispc_set_loadmode(enum omap_dss_load_mode mode)
2075 {
2076         REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
2077 }
2078
2079
2080 void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
2081 {
2082         dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
2083 }
2084
2085 u32 dispc_mgr_get_default_color(enum omap_channel channel)
2086 {
2087         u32 l;
2088
2089         BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT &&
2090                 channel != OMAP_DSS_CHANNEL_LCD &&
2091                 channel != OMAP_DSS_CHANNEL_LCD2);
2092
2093         l = dispc_read_reg(DISPC_DEFAULT_COLOR(channel));
2094
2095         return l;
2096 }
2097
2098 void dispc_mgr_set_trans_key(enum omap_channel ch,
2099                 enum omap_dss_trans_key_type type,
2100                 u32 trans_key)
2101 {
2102         if (ch == OMAP_DSS_CHANNEL_LCD)
2103                 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
2104         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2105                 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
2106         else /* OMAP_DSS_CHANNEL_LCD2 */
2107                 REG_FLD_MOD(DISPC_CONFIG2, type, 11, 11);
2108
2109         dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
2110 }
2111
2112 void dispc_mgr_get_trans_key(enum omap_channel ch,
2113                 enum omap_dss_trans_key_type *type,
2114                 u32 *trans_key)
2115 {
2116         if (type) {
2117                 if (ch == OMAP_DSS_CHANNEL_LCD)
2118                         *type = REG_GET(DISPC_CONFIG, 11, 11);
2119                 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2120                         *type = REG_GET(DISPC_CONFIG, 13, 13);
2121                 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2122                         *type = REG_GET(DISPC_CONFIG2, 11, 11);
2123                 else
2124                         BUG();
2125         }
2126
2127         if (trans_key)
2128                 *trans_key = dispc_read_reg(DISPC_TRANS_COLOR(ch));
2129 }
2130
2131 void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
2132 {
2133         if (ch == OMAP_DSS_CHANNEL_LCD)
2134                 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
2135         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2136                 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
2137         else /* OMAP_DSS_CHANNEL_LCD2 */
2138                 REG_FLD_MOD(DISPC_CONFIG2, enable, 10, 10);
2139 }
2140 void dispc_mgr_enable_alpha_blending(enum omap_channel ch, bool enable)
2141 {
2142         if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
2143                 return;
2144
2145         if (ch == OMAP_DSS_CHANNEL_LCD)
2146                 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2147         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2148                 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2149         else /* OMAP_DSS_CHANNEL_LCD2 */
2150                 REG_FLD_MOD(DISPC_CONFIG2, enable, 18, 18);
2151 }
2152 bool dispc_mgr_alpha_blending_enabled(enum omap_channel ch)
2153 {
2154         bool enabled;
2155
2156         if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
2157                 return false;
2158
2159         if (ch == OMAP_DSS_CHANNEL_LCD)
2160                 enabled = REG_GET(DISPC_CONFIG, 18, 18);
2161         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2162                 enabled = REG_GET(DISPC_CONFIG, 19, 19);
2163         else if (ch == OMAP_DSS_CHANNEL_LCD2)
2164                 enabled = REG_GET(DISPC_CONFIG2, 18, 18);
2165         else
2166                 BUG();
2167
2168         return enabled;
2169 }
2170
2171
2172 bool dispc_mgr_trans_key_enabled(enum omap_channel ch)
2173 {
2174         bool enabled;
2175
2176         if (ch == OMAP_DSS_CHANNEL_LCD)
2177                 enabled = REG_GET(DISPC_CONFIG, 10, 10);
2178         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2179                 enabled = REG_GET(DISPC_CONFIG, 12, 12);
2180         else if (ch == OMAP_DSS_CHANNEL_LCD2)
2181                 enabled = REG_GET(DISPC_CONFIG2, 10, 10);
2182         else
2183                 BUG();
2184
2185         return enabled;
2186 }
2187
2188
2189 void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
2190 {
2191         int code;
2192
2193         switch (data_lines) {
2194         case 12:
2195                 code = 0;
2196                 break;
2197         case 16:
2198                 code = 1;
2199                 break;
2200         case 18:
2201                 code = 2;
2202                 break;
2203         case 24:
2204                 code = 3;
2205                 break;
2206         default:
2207                 BUG();
2208                 return;
2209         }
2210
2211         if (channel == OMAP_DSS_CHANNEL_LCD2)
2212                 REG_FLD_MOD(DISPC_CONTROL2, code, 9, 8);
2213         else
2214                 REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
2215 }
2216
2217 void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
2218 {
2219         u32 l;
2220         int gpout0, gpout1;
2221
2222         switch (mode) {
2223         case DSS_IO_PAD_MODE_RESET:
2224                 gpout0 = 0;
2225                 gpout1 = 0;
2226                 break;
2227         case DSS_IO_PAD_MODE_RFBI:
2228                 gpout0 = 1;
2229                 gpout1 = 0;
2230                 break;
2231         case DSS_IO_PAD_MODE_BYPASS:
2232                 gpout0 = 1;
2233                 gpout1 = 1;
2234                 break;
2235         default:
2236                 BUG();
2237                 return;
2238         }
2239
2240         l = dispc_read_reg(DISPC_CONTROL);
2241         l = FLD_MOD(l, gpout0, 15, 15);
2242         l = FLD_MOD(l, gpout1, 16, 16);
2243         dispc_write_reg(DISPC_CONTROL, l);
2244 }
2245
2246 void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
2247 {
2248         if (channel == OMAP_DSS_CHANNEL_LCD2)
2249                 REG_FLD_MOD(DISPC_CONTROL2, enable, 11, 11);
2250         else
2251                 REG_FLD_MOD(DISPC_CONTROL, enable, 11, 11);
2252 }
2253
2254 static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2255                 int vsw, int vfp, int vbp)
2256 {
2257         if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2258                 if (hsw < 1 || hsw > 64 ||
2259                                 hfp < 1 || hfp > 256 ||
2260                                 hbp < 1 || hbp > 256 ||
2261                                 vsw < 1 || vsw > 64 ||
2262                                 vfp < 0 || vfp > 255 ||
2263                                 vbp < 0 || vbp > 255)
2264                         return false;
2265         } else {
2266                 if (hsw < 1 || hsw > 256 ||
2267                                 hfp < 1 || hfp > 4096 ||
2268                                 hbp < 1 || hbp > 4096 ||
2269                                 vsw < 1 || vsw > 256 ||
2270                                 vfp < 0 || vfp > 4095 ||
2271                                 vbp < 0 || vbp > 4095)
2272                         return false;
2273         }
2274
2275         return true;
2276 }
2277
2278 bool dispc_lcd_timings_ok(struct omap_video_timings *timings)
2279 {
2280         return _dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2281                         timings->hbp, timings->vsw,
2282                         timings->vfp, timings->vbp);
2283 }
2284
2285 static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
2286                 int hfp, int hbp, int vsw, int vfp, int vbp)
2287 {
2288         u32 timing_h, timing_v;
2289
2290         if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2291                 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
2292                         FLD_VAL(hbp-1, 27, 20);
2293
2294                 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
2295                         FLD_VAL(vbp, 27, 20);
2296         } else {
2297                 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
2298                         FLD_VAL(hbp-1, 31, 20);
2299
2300                 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
2301                         FLD_VAL(vbp, 31, 20);
2302         }
2303
2304         dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2305         dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
2306 }
2307
2308 /* change name to mode? */
2309 void dispc_mgr_set_lcd_timings(enum omap_channel channel,
2310                 struct omap_video_timings *timings)
2311 {
2312         unsigned xtot, ytot;
2313         unsigned long ht, vt;
2314
2315         if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2316                                 timings->hbp, timings->vsw,
2317                                 timings->vfp, timings->vbp))
2318                 BUG();
2319
2320         _dispc_mgr_set_lcd_timings(channel, timings->hsw, timings->hfp,
2321                         timings->hbp, timings->vsw, timings->vfp,
2322                         timings->vbp);
2323
2324         dispc_mgr_set_lcd_size(channel, timings->x_res, timings->y_res);
2325
2326         xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
2327         ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
2328
2329         ht = (timings->pixel_clock * 1000) / xtot;
2330         vt = (timings->pixel_clock * 1000) / xtot / ytot;
2331
2332         DSSDBG("channel %d xres %u yres %u\n", channel, timings->x_res,
2333                         timings->y_res);
2334         DSSDBG("pck %u\n", timings->pixel_clock);
2335         DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2336                         timings->hsw, timings->hfp, timings->hbp,
2337                         timings->vsw, timings->vfp, timings->vbp);
2338
2339         DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2340 }
2341
2342 static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
2343                 u16 pck_div)
2344 {
2345         BUG_ON(lck_div < 1);
2346         BUG_ON(pck_div < 1);
2347
2348         dispc_write_reg(DISPC_DIVISORo(channel),
2349                         FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
2350 }
2351
2352 static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2353                 int *pck_div)
2354 {
2355         u32 l;
2356         l = dispc_read_reg(DISPC_DIVISORo(channel));
2357         *lck_div = FLD_GET(l, 23, 16);
2358         *pck_div = FLD_GET(l, 7, 0);
2359 }
2360
2361 unsigned long dispc_fclk_rate(void)
2362 {
2363         struct platform_device *dsidev;
2364         unsigned long r = 0;
2365
2366         switch (dss_get_dispc_clk_source()) {
2367         case OMAP_DSS_CLK_SRC_FCK:
2368                 r = clk_get_rate(dispc.dss_clk);
2369                 break;
2370         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
2371                 dsidev = dsi_get_dsidev_from_id(0);
2372                 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2373                 break;
2374         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2375                 dsidev = dsi_get_dsidev_from_id(1);
2376                 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2377                 break;
2378         default:
2379                 BUG();
2380         }
2381
2382         return r;
2383 }
2384
2385 unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
2386 {
2387         struct platform_device *dsidev;
2388         int lcd;
2389         unsigned long r;
2390         u32 l;
2391
2392         l = dispc_read_reg(DISPC_DIVISORo(channel));
2393
2394         lcd = FLD_GET(l, 23, 16);
2395
2396         switch (dss_get_lcd_clk_source(channel)) {
2397         case OMAP_DSS_CLK_SRC_FCK:
2398                 r = clk_get_rate(dispc.dss_clk);
2399                 break;
2400         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
2401                 dsidev = dsi_get_dsidev_from_id(0);
2402                 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2403                 break;
2404         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2405                 dsidev = dsi_get_dsidev_from_id(1);
2406                 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2407                 break;
2408         default:
2409                 BUG();
2410         }
2411
2412         return r / lcd;
2413 }
2414
2415 unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
2416 {
2417         int pcd;
2418         unsigned long r;
2419         u32 l;
2420
2421         l = dispc_read_reg(DISPC_DIVISORo(channel));
2422
2423         pcd = FLD_GET(l, 7, 0);
2424
2425         r = dispc_mgr_lclk_rate(channel);
2426
2427         return r / pcd;
2428 }
2429
2430 void dispc_dump_clocks(struct seq_file *s)
2431 {
2432         int lcd, pcd;
2433         u32 l;
2434         enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
2435         enum omap_dss_clk_source lcd_clk_src;
2436
2437         if (dispc_runtime_get())
2438                 return;
2439
2440         seq_printf(s, "- DISPC -\n");
2441
2442         seq_printf(s, "dispc fclk source = %s (%s)\n",
2443                         dss_get_generic_clk_source_name(dispc_clk_src),
2444                         dss_feat_get_clk_source_name(dispc_clk_src));
2445
2446         seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2447
2448         if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
2449                 seq_printf(s, "- DISPC-CORE-CLK -\n");
2450                 l = dispc_read_reg(DISPC_DIVISOR);
2451                 lcd = FLD_GET(l, 23, 16);
2452
2453                 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2454                                 (dispc_fclk_rate()/lcd), lcd);
2455         }
2456         seq_printf(s, "- LCD1 -\n");
2457
2458         lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD);
2459
2460         seq_printf(s, "lcd1_clk source = %s (%s)\n",
2461                 dss_get_generic_clk_source_name(lcd_clk_src),
2462                 dss_feat_get_clk_source_name(lcd_clk_src));
2463
2464         dispc_mgr_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD, &lcd, &pcd);
2465
2466         seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2467                         dispc_mgr_lclk_rate(OMAP_DSS_CHANNEL_LCD), lcd);
2468         seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2469                         dispc_mgr_pclk_rate(OMAP_DSS_CHANNEL_LCD), pcd);
2470         if (dss_has_feature(FEAT_MGR_LCD2)) {
2471                 seq_printf(s, "- LCD2 -\n");
2472
2473                 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD2);
2474
2475                 seq_printf(s, "lcd2_clk source = %s (%s)\n",
2476                         dss_get_generic_clk_source_name(lcd_clk_src),
2477                         dss_feat_get_clk_source_name(lcd_clk_src));
2478
2479                 dispc_mgr_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD2, &lcd, &pcd);
2480
2481                 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2482                                 dispc_mgr_lclk_rate(OMAP_DSS_CHANNEL_LCD2), lcd);
2483                 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2484                                 dispc_mgr_pclk_rate(OMAP_DSS_CHANNEL_LCD2), pcd);
2485         }
2486
2487         dispc_runtime_put();
2488 }
2489
2490 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2491 void dispc_dump_irqs(struct seq_file *s)
2492 {
2493         unsigned long flags;
2494         struct dispc_irq_stats stats;
2495
2496         spin_lock_irqsave(&dispc.irq_stats_lock, flags);
2497
2498         stats = dispc.irq_stats;
2499         memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
2500         dispc.irq_stats.last_reset = jiffies;
2501
2502         spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
2503
2504         seq_printf(s, "period %u ms\n",
2505                         jiffies_to_msecs(jiffies - stats.last_reset));
2506
2507         seq_printf(s, "irqs %d\n", stats.irq_count);
2508 #define PIS(x) \
2509         seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
2510
2511         PIS(FRAMEDONE);
2512         PIS(VSYNC);
2513         PIS(EVSYNC_EVEN);
2514         PIS(EVSYNC_ODD);
2515         PIS(ACBIAS_COUNT_STAT);
2516         PIS(PROG_LINE_NUM);
2517         PIS(GFX_FIFO_UNDERFLOW);
2518         PIS(GFX_END_WIN);
2519         PIS(PAL_GAMMA_MASK);
2520         PIS(OCP_ERR);
2521         PIS(VID1_FIFO_UNDERFLOW);
2522         PIS(VID1_END_WIN);
2523         PIS(VID2_FIFO_UNDERFLOW);
2524         PIS(VID2_END_WIN);
2525         PIS(SYNC_LOST);
2526         PIS(SYNC_LOST_DIGIT);
2527         PIS(WAKEUP);
2528         if (dss_has_feature(FEAT_MGR_LCD2)) {
2529                 PIS(FRAMEDONE2);
2530                 PIS(VSYNC2);
2531                 PIS(ACBIAS_COUNT_STAT2);
2532                 PIS(SYNC_LOST2);
2533         }
2534 #undef PIS
2535 }
2536 #endif
2537
2538 void dispc_dump_regs(struct seq_file *s)
2539 {
2540         int i, j;
2541         const char *mgr_names[] = {
2542                 [OMAP_DSS_CHANNEL_LCD]          = "LCD",
2543                 [OMAP_DSS_CHANNEL_DIGIT]        = "TV",
2544                 [OMAP_DSS_CHANNEL_LCD2]         = "LCD2",
2545         };
2546         const char *ovl_names[] = {
2547                 [OMAP_DSS_GFX]          = "GFX",
2548                 [OMAP_DSS_VIDEO1]       = "VID1",
2549                 [OMAP_DSS_VIDEO2]       = "VID2",
2550         };
2551         const char **p_names;
2552
2553 #define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
2554
2555         if (dispc_runtime_get())
2556                 return;
2557
2558         /* DISPC common registers */
2559         DUMPREG(DISPC_REVISION);
2560         DUMPREG(DISPC_SYSCONFIG);
2561         DUMPREG(DISPC_SYSSTATUS);
2562         DUMPREG(DISPC_IRQSTATUS);
2563         DUMPREG(DISPC_IRQENABLE);
2564         DUMPREG(DISPC_CONTROL);
2565         DUMPREG(DISPC_CONFIG);
2566         DUMPREG(DISPC_CAPABLE);
2567         DUMPREG(DISPC_LINE_STATUS);
2568         DUMPREG(DISPC_LINE_NUMBER);
2569         if (dss_has_feature(FEAT_GLOBAL_ALPHA))
2570                 DUMPREG(DISPC_GLOBAL_ALPHA);
2571         if (dss_has_feature(FEAT_MGR_LCD2)) {
2572                 DUMPREG(DISPC_CONTROL2);
2573                 DUMPREG(DISPC_CONFIG2);
2574         }
2575
2576 #undef DUMPREG
2577
2578 #define DISPC_REG(i, name) name(i)
2579 #define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
2580         48 - strlen(#r) - strlen(p_names[i]), " ", \
2581         dispc_read_reg(DISPC_REG(i, r)))
2582
2583         p_names = mgr_names;
2584
2585         /* DISPC channel specific registers */
2586         for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
2587                 DUMPREG(i, DISPC_DEFAULT_COLOR);
2588                 DUMPREG(i, DISPC_TRANS_COLOR);
2589                 DUMPREG(i, DISPC_SIZE_MGR);
2590
2591                 if (i == OMAP_DSS_CHANNEL_DIGIT)
2592                         continue;
2593
2594                 DUMPREG(i, DISPC_DEFAULT_COLOR);
2595                 DUMPREG(i, DISPC_TRANS_COLOR);
2596                 DUMPREG(i, DISPC_TIMING_H);
2597                 DUMPREG(i, DISPC_TIMING_V);
2598                 DUMPREG(i, DISPC_POL_FREQ);
2599                 DUMPREG(i, DISPC_DIVISORo);
2600                 DUMPREG(i, DISPC_SIZE_MGR);
2601
2602                 DUMPREG(i, DISPC_DATA_CYCLE1);
2603                 DUMPREG(i, DISPC_DATA_CYCLE2);
2604                 DUMPREG(i, DISPC_DATA_CYCLE3);
2605
2606                 if (dss_has_feature(FEAT_CPR)) {
2607                         DUMPREG(i, DISPC_CPR_COEF_R);
2608                         DUMPREG(i, DISPC_CPR_COEF_G);
2609                         DUMPREG(i, DISPC_CPR_COEF_B);
2610                 }
2611         }
2612
2613         p_names = ovl_names;
2614
2615         for (i = 0; i < dss_feat_get_num_ovls(); i++) {
2616                 DUMPREG(i, DISPC_OVL_BA0);
2617                 DUMPREG(i, DISPC_OVL_BA1);
2618                 DUMPREG(i, DISPC_OVL_POSITION);
2619                 DUMPREG(i, DISPC_OVL_SIZE);
2620                 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
2621                 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
2622                 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
2623                 DUMPREG(i, DISPC_OVL_ROW_INC);
2624                 DUMPREG(i, DISPC_OVL_PIXEL_INC);
2625                 if (dss_has_feature(FEAT_PRELOAD))
2626                         DUMPREG(i, DISPC_OVL_PRELOAD);
2627
2628                 if (i == OMAP_DSS_GFX) {
2629                         DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
2630                         DUMPREG(i, DISPC_OVL_TABLE_BA);
2631                         continue;
2632                 }
2633
2634                 DUMPREG(i, DISPC_OVL_FIR);
2635                 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
2636                 DUMPREG(i, DISPC_OVL_ACCU0);
2637                 DUMPREG(i, DISPC_OVL_ACCU1);
2638                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2639                         DUMPREG(i, DISPC_OVL_BA0_UV);
2640                         DUMPREG(i, DISPC_OVL_BA1_UV);
2641                         DUMPREG(i, DISPC_OVL_FIR2);
2642                         DUMPREG(i, DISPC_OVL_ACCU2_0);
2643                         DUMPREG(i, DISPC_OVL_ACCU2_1);
2644                 }
2645                 if (dss_has_feature(FEAT_ATTR2))
2646                         DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
2647                 if (dss_has_feature(FEAT_PRELOAD))
2648                         DUMPREG(i, DISPC_OVL_PRELOAD);
2649         }
2650
2651 #undef DISPC_REG
2652 #undef DUMPREG
2653
2654 #define DISPC_REG(plane, name, i) name(plane, i)
2655 #define DUMPREG(plane, name, i) \
2656         seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
2657         46 - strlen(#name) - strlen(p_names[plane]), " ", \
2658         dispc_read_reg(DISPC_REG(plane, name, i)))
2659
2660         /* Video pipeline coefficient registers */
2661
2662         /* start from OMAP_DSS_VIDEO1 */
2663         for (i = 1; i < dss_feat_get_num_ovls(); i++) {
2664                 for (j = 0; j < 8; j++)
2665                         DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
2666
2667                 for (j = 0; j < 8; j++)
2668                         DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
2669
2670                 for (j = 0; j < 5; j++)
2671                         DUMPREG(i, DISPC_OVL_CONV_COEF, j);
2672
2673                 if (dss_has_feature(FEAT_FIR_COEF_V)) {
2674                         for (j = 0; j < 8; j++)
2675                                 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
2676                 }
2677
2678                 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2679                         for (j = 0; j < 8; j++)
2680                                 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
2681
2682                         for (j = 0; j < 8; j++)
2683                                 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
2684
2685                         for (j = 0; j < 8; j++)
2686                                 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
2687                 }
2688         }
2689
2690         dispc_runtime_put();
2691
2692 #undef DISPC_REG
2693 #undef DUMPREG
2694 }
2695
2696 static void _dispc_mgr_set_pol_freq(enum omap_channel channel, bool onoff,
2697                 bool rf, bool ieo, bool ipc, bool ihs, bool ivs, u8 acbi,
2698                 u8 acb)
2699 {
2700         u32 l = 0;
2701
2702         DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
2703                         onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
2704
2705         l |= FLD_VAL(onoff, 17, 17);
2706         l |= FLD_VAL(rf, 16, 16);
2707         l |= FLD_VAL(ieo, 15, 15);
2708         l |= FLD_VAL(ipc, 14, 14);
2709         l |= FLD_VAL(ihs, 13, 13);
2710         l |= FLD_VAL(ivs, 12, 12);
2711         l |= FLD_VAL(acbi, 11, 8);
2712         l |= FLD_VAL(acb, 7, 0);
2713
2714         dispc_write_reg(DISPC_POL_FREQ(channel), l);
2715 }
2716
2717 void dispc_mgr_set_pol_freq(enum omap_channel channel,
2718                 enum omap_panel_config config, u8 acbi, u8 acb)
2719 {
2720         _dispc_mgr_set_pol_freq(channel, (config & OMAP_DSS_LCD_ONOFF) != 0,
2721                         (config & OMAP_DSS_LCD_RF) != 0,
2722                         (config & OMAP_DSS_LCD_IEO) != 0,
2723                         (config & OMAP_DSS_LCD_IPC) != 0,
2724                         (config & OMAP_DSS_LCD_IHS) != 0,
2725                         (config & OMAP_DSS_LCD_IVS) != 0,
2726                         acbi, acb);
2727 }
2728
2729 /* with fck as input clock rate, find dispc dividers that produce req_pck */
2730 void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
2731                 struct dispc_clock_info *cinfo)
2732 {
2733         u16 pcd_min, pcd_max;
2734         unsigned long best_pck;
2735         u16 best_ld, cur_ld;
2736         u16 best_pd, cur_pd;
2737
2738         pcd_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
2739         pcd_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
2740
2741         if (!is_tft)
2742                 pcd_min = 3;
2743
2744         best_pck = 0;
2745         best_ld = 0;
2746         best_pd = 0;
2747
2748         for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
2749                 unsigned long lck = fck / cur_ld;
2750
2751                 for (cur_pd = pcd_min; cur_pd <= pcd_max; ++cur_pd) {
2752                         unsigned long pck = lck / cur_pd;
2753                         long old_delta = abs(best_pck - req_pck);
2754                         long new_delta = abs(pck - req_pck);
2755
2756                         if (best_pck == 0 || new_delta < old_delta) {
2757                                 best_pck = pck;
2758                                 best_ld = cur_ld;
2759                                 best_pd = cur_pd;
2760
2761                                 if (pck == req_pck)
2762                                         goto found;
2763                         }
2764
2765                         if (pck < req_pck)
2766                                 break;
2767                 }
2768
2769                 if (lck / pcd_min < req_pck)
2770                         break;
2771         }
2772
2773 found:
2774         cinfo->lck_div = best_ld;
2775         cinfo->pck_div = best_pd;
2776         cinfo->lck = fck / cinfo->lck_div;
2777         cinfo->pck = cinfo->lck / cinfo->pck_div;
2778 }
2779
2780 /* calculate clock rates using dividers in cinfo */
2781 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
2782                 struct dispc_clock_info *cinfo)
2783 {
2784         if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
2785                 return -EINVAL;
2786         if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
2787                 return -EINVAL;
2788
2789         cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
2790         cinfo->pck = cinfo->lck / cinfo->pck_div;
2791
2792         return 0;
2793 }
2794
2795 int dispc_mgr_set_clock_div(enum omap_channel channel,
2796                 struct dispc_clock_info *cinfo)
2797 {
2798         DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
2799         DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
2800
2801         dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
2802
2803         return 0;
2804 }
2805
2806 int dispc_mgr_get_clock_div(enum omap_channel channel,
2807                 struct dispc_clock_info *cinfo)
2808 {
2809         unsigned long fck;
2810
2811         fck = dispc_fclk_rate();
2812
2813         cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
2814         cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
2815
2816         cinfo->lck = fck / cinfo->lck_div;
2817         cinfo->pck = cinfo->lck / cinfo->pck_div;
2818
2819         return 0;
2820 }
2821
2822 /* dispc.irq_lock has to be locked by the caller */
2823 static void _omap_dispc_set_irqs(void)
2824 {
2825         u32 mask;
2826         u32 old_mask;
2827         int i;
2828         struct omap_dispc_isr_data *isr_data;
2829
2830         mask = dispc.irq_error_mask;
2831
2832         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2833                 isr_data = &dispc.registered_isr[i];
2834
2835                 if (isr_data->isr == NULL)
2836                         continue;
2837
2838                 mask |= isr_data->mask;
2839         }
2840
2841         old_mask = dispc_read_reg(DISPC_IRQENABLE);
2842         /* clear the irqstatus for newly enabled irqs */
2843         dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
2844
2845         dispc_write_reg(DISPC_IRQENABLE, mask);
2846 }
2847
2848 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2849 {
2850         int i;
2851         int ret;
2852         unsigned long flags;
2853         struct omap_dispc_isr_data *isr_data;
2854
2855         if (isr == NULL)
2856                 return -EINVAL;
2857
2858         spin_lock_irqsave(&dispc.irq_lock, flags);
2859
2860         /* check for duplicate entry */
2861         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2862                 isr_data = &dispc.registered_isr[i];
2863                 if (isr_data->isr == isr && isr_data->arg == arg &&
2864                                 isr_data->mask == mask) {
2865                         ret = -EINVAL;
2866                         goto err;
2867                 }
2868         }
2869
2870         isr_data = NULL;
2871         ret = -EBUSY;
2872
2873         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2874                 isr_data = &dispc.registered_isr[i];
2875
2876                 if (isr_data->isr != NULL)
2877                         continue;
2878
2879                 isr_data->isr = isr;
2880                 isr_data->arg = arg;
2881                 isr_data->mask = mask;
2882                 ret = 0;
2883
2884                 break;
2885         }
2886
2887         if (ret)
2888                 goto err;
2889
2890         _omap_dispc_set_irqs();
2891
2892         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2893
2894         return 0;
2895 err:
2896         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2897
2898         return ret;
2899 }
2900 EXPORT_SYMBOL(omap_dispc_register_isr);
2901
2902 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2903 {
2904         int i;
2905         unsigned long flags;
2906         int ret = -EINVAL;
2907         struct omap_dispc_isr_data *isr_data;
2908
2909         spin_lock_irqsave(&dispc.irq_lock, flags);
2910
2911         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2912                 isr_data = &dispc.registered_isr[i];
2913                 if (isr_data->isr != isr || isr_data->arg != arg ||
2914                                 isr_data->mask != mask)
2915                         continue;
2916
2917                 /* found the correct isr */
2918
2919                 isr_data->isr = NULL;
2920                 isr_data->arg = NULL;
2921                 isr_data->mask = 0;
2922
2923                 ret = 0;
2924                 break;
2925         }
2926
2927         if (ret == 0)
2928                 _omap_dispc_set_irqs();
2929
2930         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2931
2932         return ret;
2933 }
2934 EXPORT_SYMBOL(omap_dispc_unregister_isr);
2935
2936 #ifdef DEBUG
2937 static void print_irq_status(u32 status)
2938 {
2939         if ((status & dispc.irq_error_mask) == 0)
2940                 return;
2941
2942         printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
2943
2944 #define PIS(x) \
2945         if (status & DISPC_IRQ_##x) \
2946                 printk(#x " ");
2947         PIS(GFX_FIFO_UNDERFLOW);
2948         PIS(OCP_ERR);
2949         PIS(VID1_FIFO_UNDERFLOW);
2950         PIS(VID2_FIFO_UNDERFLOW);
2951         PIS(SYNC_LOST);
2952         PIS(SYNC_LOST_DIGIT);
2953         if (dss_has_feature(FEAT_MGR_LCD2))
2954                 PIS(SYNC_LOST2);
2955 #undef PIS
2956
2957         printk("\n");
2958 }
2959 #endif
2960
2961 /* Called from dss.c. Note that we don't touch clocks here,
2962  * but we presume they are on because we got an IRQ. However,
2963  * an irq handler may turn the clocks off, so we may not have
2964  * clock later in the function. */
2965 static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
2966 {
2967         int i;
2968         u32 irqstatus, irqenable;
2969         u32 handledirqs = 0;
2970         u32 unhandled_errors;
2971         struct omap_dispc_isr_data *isr_data;
2972         struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
2973
2974         spin_lock(&dispc.irq_lock);
2975
2976         irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
2977         irqenable = dispc_read_reg(DISPC_IRQENABLE);
2978
2979         /* IRQ is not for us */
2980         if (!(irqstatus & irqenable)) {
2981                 spin_unlock(&dispc.irq_lock);
2982                 return IRQ_NONE;
2983         }
2984
2985 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2986         spin_lock(&dispc.irq_stats_lock);
2987         dispc.irq_stats.irq_count++;
2988         dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
2989         spin_unlock(&dispc.irq_stats_lock);
2990 #endif
2991
2992 #ifdef DEBUG
2993         if (dss_debug)
2994                 print_irq_status(irqstatus);
2995 #endif
2996         /* Ack the interrupt. Do it here before clocks are possibly turned
2997          * off */
2998         dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
2999         /* flush posted write */
3000         dispc_read_reg(DISPC_IRQSTATUS);
3001
3002         /* make a copy and unlock, so that isrs can unregister
3003          * themselves */
3004         memcpy(registered_isr, dispc.registered_isr,
3005                         sizeof(registered_isr));
3006
3007         spin_unlock(&dispc.irq_lock);
3008
3009         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3010                 isr_data = &registered_isr[i];
3011
3012                 if (!isr_data->isr)
3013                         continue;
3014
3015                 if (isr_data->mask & irqstatus) {
3016                         isr_data->isr(isr_data->arg, irqstatus);
3017                         handledirqs |= isr_data->mask;
3018                 }
3019         }
3020
3021         spin_lock(&dispc.irq_lock);
3022
3023         unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
3024
3025         if (unhandled_errors) {
3026                 dispc.error_irqs |= unhandled_errors;
3027
3028                 dispc.irq_error_mask &= ~unhandled_errors;
3029                 _omap_dispc_set_irqs();
3030
3031                 schedule_work(&dispc.error_work);
3032         }
3033
3034         spin_unlock(&dispc.irq_lock);
3035
3036         return IRQ_HANDLED;
3037 }
3038
3039 static void dispc_error_worker(struct work_struct *work)
3040 {
3041         int i;
3042         u32 errors;
3043         unsigned long flags;
3044         static const unsigned fifo_underflow_bits[] = {
3045                 DISPC_IRQ_GFX_FIFO_UNDERFLOW,
3046                 DISPC_IRQ_VID1_FIFO_UNDERFLOW,
3047                 DISPC_IRQ_VID2_FIFO_UNDERFLOW,
3048         };
3049
3050         static const unsigned sync_lost_bits[] = {
3051                 DISPC_IRQ_SYNC_LOST,
3052                 DISPC_IRQ_SYNC_LOST_DIGIT,
3053                 DISPC_IRQ_SYNC_LOST2,
3054         };
3055
3056         spin_lock_irqsave(&dispc.irq_lock, flags);
3057         errors = dispc.error_irqs;
3058         dispc.error_irqs = 0;
3059         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3060
3061         dispc_runtime_get();
3062
3063         for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3064                 struct omap_overlay *ovl;
3065                 unsigned bit;
3066
3067                 ovl = omap_dss_get_overlay(i);
3068                 bit = fifo_underflow_bits[i];
3069
3070                 if (bit & errors) {
3071                         DSSERR("FIFO UNDERFLOW on %s, disabling the overlay\n",
3072                                         ovl->name);
3073                         dispc_ovl_enable(ovl->id, false);
3074                         dispc_mgr_go(ovl->manager->id);
3075                         mdelay(50);
3076                 }
3077         }
3078
3079         for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3080                 struct omap_overlay_manager *mgr;
3081                 unsigned bit;
3082
3083                 mgr = omap_dss_get_overlay_manager(i);
3084                 bit = sync_lost_bits[i];
3085
3086                 if (bit & errors) {
3087                         struct omap_dss_device *dssdev = mgr->device;
3088                         bool enable;
3089
3090                         DSSERR("SYNC_LOST on channel %s, restarting the output "
3091                                         "with video overlays disabled\n",
3092                                         mgr->name);
3093
3094                         enable = dssdev->state == OMAP_DSS_DISPLAY_ACTIVE;
3095                         dssdev->driver->disable(dssdev);
3096
3097                         for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3098                                 struct omap_overlay *ovl;
3099                                 ovl = omap_dss_get_overlay(i);
3100
3101                                 if (ovl->id != OMAP_DSS_GFX &&
3102                                                 ovl->manager == mgr)
3103                                         dispc_ovl_enable(ovl->id, false);
3104                         }
3105
3106                         dispc_mgr_go(mgr->id);
3107                         mdelay(50);
3108
3109                         if (enable)
3110                                 dssdev->driver->enable(dssdev);
3111                 }
3112         }
3113
3114         if (errors & DISPC_IRQ_OCP_ERR) {
3115                 DSSERR("OCP_ERR\n");
3116                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3117                         struct omap_overlay_manager *mgr;
3118                         mgr = omap_dss_get_overlay_manager(i);
3119                         mgr->device->driver->disable(mgr->device);
3120                 }
3121         }
3122
3123         spin_lock_irqsave(&dispc.irq_lock, flags);
3124         dispc.irq_error_mask |= errors;
3125         _omap_dispc_set_irqs();
3126         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3127
3128         dispc_runtime_put();
3129 }
3130
3131 int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
3132 {
3133         void dispc_irq_wait_handler(void *data, u32 mask)
3134         {
3135                 complete((struct completion *)data);
3136         }
3137
3138         int r;
3139         DECLARE_COMPLETION_ONSTACK(completion);
3140
3141         r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3142                         irqmask);
3143
3144         if (r)
3145                 return r;
3146
3147         timeout = wait_for_completion_timeout(&completion, timeout);
3148
3149         omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3150
3151         if (timeout == 0)
3152                 return -ETIMEDOUT;
3153
3154         if (timeout == -ERESTARTSYS)
3155                 return -ERESTARTSYS;
3156
3157         return 0;
3158 }
3159
3160 int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
3161                 unsigned long timeout)
3162 {
3163         void dispc_irq_wait_handler(void *data, u32 mask)
3164         {
3165                 complete((struct completion *)data);
3166         }
3167
3168         int r;
3169         DECLARE_COMPLETION_ONSTACK(completion);
3170
3171         r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3172                         irqmask);
3173
3174         if (r)
3175                 return r;
3176
3177         timeout = wait_for_completion_interruptible_timeout(&completion,
3178                         timeout);
3179
3180         omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3181
3182         if (timeout == 0)
3183                 return -ETIMEDOUT;
3184
3185         if (timeout == -ERESTARTSYS)
3186                 return -ERESTARTSYS;
3187
3188         return 0;
3189 }
3190
3191 #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
3192 void dispc_fake_vsync_irq(void)
3193 {
3194         u32 irqstatus = DISPC_IRQ_VSYNC;
3195         int i;
3196
3197         WARN_ON(!in_interrupt());
3198
3199         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3200                 struct omap_dispc_isr_data *isr_data;
3201                 isr_data = &dispc.registered_isr[i];
3202
3203                 if (!isr_data->isr)
3204                         continue;
3205
3206                 if (isr_data->mask & irqstatus)
3207                         isr_data->isr(isr_data->arg, irqstatus);
3208         }
3209 }
3210 #endif
3211
3212 static void _omap_dispc_initialize_irq(void)
3213 {
3214         unsigned long flags;
3215
3216         spin_lock_irqsave(&dispc.irq_lock, flags);
3217
3218         memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3219
3220         dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
3221         if (dss_has_feature(FEAT_MGR_LCD2))
3222                 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
3223
3224         /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3225          * so clear it */
3226         dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3227
3228         _omap_dispc_set_irqs();
3229
3230         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3231 }
3232
3233 void dispc_enable_sidle(void)
3234 {
3235         REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3);  /* SIDLEMODE: smart idle */
3236 }
3237
3238 void dispc_disable_sidle(void)
3239 {
3240         REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3);  /* SIDLEMODE: no idle */
3241 }
3242
3243 static void _omap_dispc_initial_config(void)
3244 {
3245         u32 l;
3246
3247         /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3248         if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3249                 l = dispc_read_reg(DISPC_DIVISOR);
3250                 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3251                 l = FLD_MOD(l, 1, 0, 0);
3252                 l = FLD_MOD(l, 1, 23, 16);
3253                 dispc_write_reg(DISPC_DIVISOR, l);
3254         }
3255
3256         /* FUNCGATED */
3257         if (dss_has_feature(FEAT_FUNCGATED))
3258                 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
3259
3260         /* L3 firewall setting: enable access to OCM RAM */
3261         /* XXX this should be somewhere in plat-omap */
3262         if (cpu_is_omap24xx())
3263                 __raw_writel(0x402000b0, OMAP2_L3_IO_ADDRESS(0x680050a0));
3264
3265         _dispc_setup_color_conv_coef();
3266
3267         dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3268
3269         dispc_read_plane_fifo_sizes();
3270
3271         dispc_configure_burst_sizes();
3272 }
3273
3274 /* DISPC HW IP initialisation */
3275 static int omap_dispchw_probe(struct platform_device *pdev)
3276 {
3277         u32 rev;
3278         int r = 0;
3279         struct resource *dispc_mem;
3280         struct clk *clk;
3281
3282         dispc.pdev = pdev;
3283
3284         clk = clk_get(&pdev->dev, "fck");
3285         if (IS_ERR(clk)) {
3286                 DSSERR("can't get fck\n");
3287                 r = PTR_ERR(clk);
3288                 goto err_get_clk;
3289         }
3290
3291         dispc.dss_clk = clk;
3292
3293         spin_lock_init(&dispc.irq_lock);
3294
3295 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3296         spin_lock_init(&dispc.irq_stats_lock);
3297         dispc.irq_stats.last_reset = jiffies;
3298 #endif
3299
3300         INIT_WORK(&dispc.error_work, dispc_error_worker);
3301
3302         dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3303         if (!dispc_mem) {
3304                 DSSERR("can't get IORESOURCE_MEM DISPC\n");
3305                 r = -EINVAL;
3306                 goto err_ioremap;
3307         }
3308         dispc.base = ioremap(dispc_mem->start, resource_size(dispc_mem));
3309         if (!dispc.base) {
3310                 DSSERR("can't ioremap DISPC\n");
3311                 r = -ENOMEM;
3312                 goto err_ioremap;
3313         }
3314         dispc.irq = platform_get_irq(dispc.pdev, 0);
3315         if (dispc.irq < 0) {
3316                 DSSERR("platform_get_irq failed\n");
3317                 r = -ENODEV;
3318                 goto err_irq;
3319         }
3320
3321         r = request_irq(dispc.irq, omap_dispc_irq_handler, IRQF_SHARED,
3322                 "OMAP DISPC", dispc.pdev);
3323         if (r < 0) {
3324                 DSSERR("request_irq failed\n");
3325                 goto err_irq;
3326         }
3327
3328         pm_runtime_enable(&pdev->dev);
3329
3330         r = dispc_runtime_get();
3331         if (r)
3332                 goto err_runtime_get;
3333
3334         _omap_dispc_initial_config();
3335
3336         _omap_dispc_initialize_irq();
3337
3338         rev = dispc_read_reg(DISPC_REVISION);
3339         dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
3340                FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3341
3342         dispc_runtime_put();
3343
3344         return 0;
3345
3346 err_runtime_get:
3347         pm_runtime_disable(&pdev->dev);
3348         free_irq(dispc.irq, dispc.pdev);
3349 err_irq:
3350         iounmap(dispc.base);
3351 err_ioremap:
3352         clk_put(dispc.dss_clk);
3353 err_get_clk:
3354         return r;
3355 }
3356
3357 static int omap_dispchw_remove(struct platform_device *pdev)
3358 {
3359         pm_runtime_disable(&pdev->dev);
3360
3361         clk_put(dispc.dss_clk);
3362
3363         free_irq(dispc.irq, dispc.pdev);
3364         iounmap(dispc.base);
3365         return 0;
3366 }
3367
3368 static int dispc_runtime_suspend(struct device *dev)
3369 {
3370         dispc_save_context();
3371         dss_runtime_put();
3372
3373         return 0;
3374 }
3375
3376 static int dispc_runtime_resume(struct device *dev)
3377 {
3378         int r;
3379
3380         r = dss_runtime_get();
3381         if (r < 0)
3382                 return r;
3383
3384         dispc_restore_context();
3385
3386         return 0;
3387 }
3388
3389 static const struct dev_pm_ops dispc_pm_ops = {
3390         .runtime_suspend = dispc_runtime_suspend,
3391         .runtime_resume = dispc_runtime_resume,
3392 };
3393
3394 static struct platform_driver omap_dispchw_driver = {
3395         .probe          = omap_dispchw_probe,
3396         .remove         = omap_dispchw_remove,
3397         .driver         = {
3398                 .name   = "omapdss_dispc",
3399                 .owner  = THIS_MODULE,
3400                 .pm     = &dispc_pm_ops,
3401         },
3402 };
3403
3404 int dispc_init_platform_driver(void)
3405 {
3406         return platform_driver_register(&omap_dispchw_driver);
3407 }
3408
3409 void dispc_uninit_platform_driver(void)
3410 {
3411         return platform_driver_unregister(&omap_dispchw_driver);
3412 }