drivers/video/omap2/dss/dispc.c

   1 /*
   2  * linux/drivers/video/omap2/dss/dispc.c
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #define DSS_SUBSYS_NAME "DISPC"
  24
  25 #include <linux/kernel.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/vmalloc.h>
  28 #include <linux/clk.h>
  29 #include <linux/io.h>
  30 #include <linux/jiffies.h>
  31 #include <linux/seq_file.h>
  32 #include <linux/delay.h>
  33 #include <linux/workqueue.h>
  34 #include <linux/hardirq.h>
  35
  36 #include <plat/sram.h>
  37 #include <plat/clock.h>
  38
  39 #include <plat/display.h>
  40
  41 #include "dss.h"
  42
  43 /* DISPC */
  44 #define DISPC_BASE                      0x48050400
  45
  46 #define DISPC_SZ_REGS                   SZ_1K
  47
  48 struct dispc_reg { u16 idx; };
  49
  50 #define DISPC_REG(idx)                  ((const struct dispc_reg) { idx })
  51
  52 /* DISPC common */
  53 #define DISPC_REVISION                  DISPC_REG(0x0000)
  54 #define DISPC_SYSCONFIG                 DISPC_REG(0x0010)
  55 #define DISPC_SYSSTATUS                 DISPC_REG(0x0014)
  56 #define DISPC_IRQSTATUS                 DISPC_REG(0x0018)
  57 #define DISPC_IRQENABLE                 DISPC_REG(0x001C)
  58 #define DISPC_CONTROL                   DISPC_REG(0x0040)
  59 #define DISPC_CONFIG                    DISPC_REG(0x0044)
  60 #define DISPC_CAPABLE                   DISPC_REG(0x0048)
  61 #define DISPC_DEFAULT_COLOR0            DISPC_REG(0x004C)
  62 #define DISPC_DEFAULT_COLOR1            DISPC_REG(0x0050)
  63 #define DISPC_TRANS_COLOR0              DISPC_REG(0x0054)
  64 #define DISPC_TRANS_COLOR1              DISPC_REG(0x0058)
  65 #define DISPC_LINE_STATUS               DISPC_REG(0x005C)
  66 #define DISPC_LINE_NUMBER               DISPC_REG(0x0060)
  67 #define DISPC_TIMING_H                  DISPC_REG(0x0064)
  68 #define DISPC_TIMING_V                  DISPC_REG(0x0068)
  69 #define DISPC_POL_FREQ                  DISPC_REG(0x006C)
  70 #define DISPC_DIVISOR                   DISPC_REG(0x0070)
  71 #define DISPC_GLOBAL_ALPHA              DISPC_REG(0x0074)
  72 #define DISPC_SIZE_DIG                  DISPC_REG(0x0078)
  73 #define DISPC_SIZE_LCD                  DISPC_REG(0x007C)
  74
  75 /* DISPC GFX plane */
  76 #define DISPC_GFX_BA0                   DISPC_REG(0x0080)
  77 #define DISPC_GFX_BA1                   DISPC_REG(0x0084)
  78 #define DISPC_GFX_POSITION              DISPC_REG(0x0088)
  79 #define DISPC_GFX_SIZE                  DISPC_REG(0x008C)
  80 #define DISPC_GFX_ATTRIBUTES            DISPC_REG(0x00A0)
  81 #define DISPC_GFX_FIFO_THRESHOLD        DISPC_REG(0x00A4)
  82 #define DISPC_GFX_FIFO_SIZE_STATUS      DISPC_REG(0x00A8)
  83 #define DISPC_GFX_ROW_INC               DISPC_REG(0x00AC)
  84 #define DISPC_GFX_PIXEL_INC             DISPC_REG(0x00B0)
  85 #define DISPC_GFX_WINDOW_SKIP           DISPC_REG(0x00B4)
  86 #define DISPC_GFX_TABLE_BA              DISPC_REG(0x00B8)
  87
  88 #define DISPC_DATA_CYCLE1               DISPC_REG(0x01D4)
  89 #define DISPC_DATA_CYCLE2               DISPC_REG(0x01D8)
  90 #define DISPC_DATA_CYCLE3               DISPC_REG(0x01DC)
  91
  92 #define DISPC_CPR_COEF_R                DISPC_REG(0x0220)
  93 #define DISPC_CPR_COEF_G                DISPC_REG(0x0224)
  94 #define DISPC_CPR_COEF_B                DISPC_REG(0x0228)
  95
  96 #define DISPC_GFX_PRELOAD               DISPC_REG(0x022C)
  97
  98 /* DISPC Video plane, n = 0 for VID1 and n = 1 for VID2 */
  99 #define DISPC_VID_REG(n, idx)           DISPC_REG(0x00BC + (n)*0x90 + idx)
 100
 101 #define DISPC_VID_BA0(n)                DISPC_VID_REG(n, 0x0000)
 102 #define DISPC_VID_BA1(n)                DISPC_VID_REG(n, 0x0004)
 103 #define DISPC_VID_POSITION(n)           DISPC_VID_REG(n, 0x0008)
 104 #define DISPC_VID_SIZE(n)               DISPC_VID_REG(n, 0x000C)
 105 #define DISPC_VID_ATTRIBUTES(n)         DISPC_VID_REG(n, 0x0010)
 106 #define DISPC_VID_FIFO_THRESHOLD(n)     DISPC_VID_REG(n, 0x0014)
 107 #define DISPC_VID_FIFO_SIZE_STATUS(n)   DISPC_VID_REG(n, 0x0018)
 108 #define DISPC_VID_ROW_INC(n)            DISPC_VID_REG(n, 0x001C)
 109 #define DISPC_VID_PIXEL_INC(n)          DISPC_VID_REG(n, 0x0020)
 110 #define DISPC_VID_FIR(n)                DISPC_VID_REG(n, 0x0024)
 111 #define DISPC_VID_PICTURE_SIZE(n)       DISPC_VID_REG(n, 0x0028)
 112 #define DISPC_VID_ACCU0(n)              DISPC_VID_REG(n, 0x002C)
 113 #define DISPC_VID_ACCU1(n)              DISPC_VID_REG(n, 0x0030)
 114
 115 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 116 #define DISPC_VID_FIR_COEF_H(n, i)      DISPC_REG(0x00F0 + (n)*0x90 + (i)*0x8)
 117 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 118 #define DISPC_VID_FIR_COEF_HV(n, i)     DISPC_REG(0x00F4 + (n)*0x90 + (i)*0x8)
 119 /* coef index i = {0, 1, 2, 3, 4} */
 120 #define DISPC_VID_CONV_COEF(n, i)       DISPC_REG(0x0130 + (n)*0x90 + (i)*0x4)
 121 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 122 #define DISPC_VID_FIR_COEF_V(n, i)      DISPC_REG(0x01E0 + (n)*0x20 + (i)*0x4)
 123
 124 #define DISPC_VID_PRELOAD(n)            DISPC_REG(0x230 + (n)*0x04)
 125
 126
 127 #define DISPC_IRQ_MASK_ERROR            (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
 128                                          DISPC_IRQ_OCP_ERR | \
 129                                          DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
 130                                          DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
 131                                          DISPC_IRQ_SYNC_LOST | \
 132                                          DISPC_IRQ_SYNC_LOST_DIGIT)
 133
 134 #define DISPC_MAX_NR_ISRS               8
 135
 136 struct omap_dispc_isr_data {
 137         omap_dispc_isr_t        isr;
 138         void                    *arg;
 139         u32                     mask;
 140 };
 141
 142 struct dispc_h_coef {
 143         s8 hc4;
 144         s8 hc3;
 145         u8 hc2;
 146         s8 hc1;
 147         s8 hc0;
 148 };
 149
 150 struct dispc_v_coef {
 151         s8 vc22;
 152         s8 vc2;
 153         u8 vc1;
 154         s8 vc0;
 155         s8 vc00;
 156 };
 157
 158 #define REG_GET(idx, start, end) \
 159         FLD_GET(dispc_read_reg(idx), start, end)
 160
 161 #define REG_FLD_MOD(idx, val, start, end)                               \
 162         dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
 163
 164 static const struct dispc_reg dispc_reg_att[] = { DISPC_GFX_ATTRIBUTES,
 165         DISPC_VID_ATTRIBUTES(0),
 166         DISPC_VID_ATTRIBUTES(1) };
 167
 168 struct dispc_irq_stats {
 169         unsigned long last_reset;
 170         unsigned irq_count;
 171         unsigned irqs[32];
 172 };
 173
 174 static struct {
 175         void __iomem    *base;
 176
 177         u32     fifo_size[3];
 178
 179         spinlock_t irq_lock;
 180         u32 irq_error_mask;
 181         struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
 182         u32 error_irqs;
 183         struct work_struct error_work;
 184
 185         u32             ctx[DISPC_SZ_REGS / sizeof(u32)];
 186
 187 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
 188         spinlock_t irq_stats_lock;
 189         struct dispc_irq_stats irq_stats;
 190 #endif
 191 } dispc;
 192
 193 static void _omap_dispc_set_irqs(void);
 194
 195 static inline void dispc_write_reg(const struct dispc_reg idx, u32 val)
 196 {
 197         __raw_writel(val, dispc.base + idx.idx);
 198 }
 199
 200 static inline u32 dispc_read_reg(const struct dispc_reg idx)
 201 {
 202         return __raw_readl(dispc.base + idx.idx);
 203 }
 204
 205 #define SR(reg) \
 206         dispc.ctx[(DISPC_##reg).idx / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
 207 #define RR(reg) \
 208         dispc_write_reg(DISPC_##reg, dispc.ctx[(DISPC_##reg).idx / sizeof(u32)])
 209
 210 void dispc_save_context(void)
 211 {
 212         if (cpu_is_omap24xx())
 213                 return;
 214
 215         SR(SYSCONFIG);
 216         SR(IRQENABLE);
 217         SR(CONTROL);
 218         SR(CONFIG);
 219         SR(DEFAULT_COLOR0);
 220         SR(DEFAULT_COLOR1);
 221         SR(TRANS_COLOR0);
 222         SR(TRANS_COLOR1);
 223         SR(LINE_NUMBER);
 224         SR(TIMING_H);
 225         SR(TIMING_V);
 226         SR(POL_FREQ);
 227         SR(DIVISOR);
 228         SR(GLOBAL_ALPHA);
 229         SR(SIZE_DIG);
 230         SR(SIZE_LCD);
 231
 232         SR(GFX_BA0);
 233         SR(GFX_BA1);
 234         SR(GFX_POSITION);
 235         SR(GFX_SIZE);
 236         SR(GFX_ATTRIBUTES);
 237         SR(GFX_FIFO_THRESHOLD);
 238         SR(GFX_ROW_INC);
 239         SR(GFX_PIXEL_INC);
 240         SR(GFX_WINDOW_SKIP);
 241         SR(GFX_TABLE_BA);
 242
 243         SR(DATA_CYCLE1);
 244         SR(DATA_CYCLE2);
 245         SR(DATA_CYCLE3);
 246
 247         SR(CPR_COEF_R);
 248         SR(CPR_COEF_G);
 249         SR(CPR_COEF_B);
 250
 251         SR(GFX_PRELOAD);
 252
 253         /* VID1 */
 254         SR(VID_BA0(0));
 255         SR(VID_BA1(0));
 256         SR(VID_POSITION(0));
 257         SR(VID_SIZE(0));
 258         SR(VID_ATTRIBUTES(0));
 259         SR(VID_FIFO_THRESHOLD(0));
 260         SR(VID_ROW_INC(0));
 261         SR(VID_PIXEL_INC(0));
 262         SR(VID_FIR(0));
 263         SR(VID_PICTURE_SIZE(0));
 264         SR(VID_ACCU0(0));
 265         SR(VID_ACCU1(0));
 266
 267         SR(VID_FIR_COEF_H(0, 0));
 268         SR(VID_FIR_COEF_H(0, 1));
 269         SR(VID_FIR_COEF_H(0, 2));
 270         SR(VID_FIR_COEF_H(0, 3));
 271         SR(VID_FIR_COEF_H(0, 4));
 272         SR(VID_FIR_COEF_H(0, 5));
 273         SR(VID_FIR_COEF_H(0, 6));
 274         SR(VID_FIR_COEF_H(0, 7));
 275
 276         SR(VID_FIR_COEF_HV(0, 0));
 277         SR(VID_FIR_COEF_HV(0, 1));
 278         SR(VID_FIR_COEF_HV(0, 2));
 279         SR(VID_FIR_COEF_HV(0, 3));
 280         SR(VID_FIR_COEF_HV(0, 4));
 281         SR(VID_FIR_COEF_HV(0, 5));
 282         SR(VID_FIR_COEF_HV(0, 6));
 283         SR(VID_FIR_COEF_HV(0, 7));
 284
 285         SR(VID_CONV_COEF(0, 0));
 286         SR(VID_CONV_COEF(0, 1));
 287         SR(VID_CONV_COEF(0, 2));
 288         SR(VID_CONV_COEF(0, 3));
 289         SR(VID_CONV_COEF(0, 4));
 290
 291         SR(VID_FIR_COEF_V(0, 0));
 292         SR(VID_FIR_COEF_V(0, 1));
 293         SR(VID_FIR_COEF_V(0, 2));
 294         SR(VID_FIR_COEF_V(0, 3));
 295         SR(VID_FIR_COEF_V(0, 4));
 296         SR(VID_FIR_COEF_V(0, 5));
 297         SR(VID_FIR_COEF_V(0, 6));
 298         SR(VID_FIR_COEF_V(0, 7));
 299
 300         SR(VID_PRELOAD(0));
 301
 302         /* VID2 */
 303         SR(VID_BA0(1));
 304         SR(VID_BA1(1));
 305         SR(VID_POSITION(1));
 306         SR(VID_SIZE(1));
 307         SR(VID_ATTRIBUTES(1));
 308         SR(VID_FIFO_THRESHOLD(1));
 309         SR(VID_ROW_INC(1));
 310         SR(VID_PIXEL_INC(1));
 311         SR(VID_FIR(1));
 312         SR(VID_PICTURE_SIZE(1));
 313         SR(VID_ACCU0(1));
 314         SR(VID_ACCU1(1));
 315
 316         SR(VID_FIR_COEF_H(1, 0));
 317         SR(VID_FIR_COEF_H(1, 1));
 318         SR(VID_FIR_COEF_H(1, 2));
 319         SR(VID_FIR_COEF_H(1, 3));
 320         SR(VID_FIR_COEF_H(1, 4));
 321         SR(VID_FIR_COEF_H(1, 5));
 322         SR(VID_FIR_COEF_H(1, 6));
 323         SR(VID_FIR_COEF_H(1, 7));
 324
 325         SR(VID_FIR_COEF_HV(1, 0));
 326         SR(VID_FIR_COEF_HV(1, 1));
 327         SR(VID_FIR_COEF_HV(1, 2));
 328         SR(VID_FIR_COEF_HV(1, 3));
 329         SR(VID_FIR_COEF_HV(1, 4));
 330         SR(VID_FIR_COEF_HV(1, 5));
 331         SR(VID_FIR_COEF_HV(1, 6));
 332         SR(VID_FIR_COEF_HV(1, 7));
 333
 334         SR(VID_CONV_COEF(1, 0));
 335         SR(VID_CONV_COEF(1, 1));
 336         SR(VID_CONV_COEF(1, 2));
 337         SR(VID_CONV_COEF(1, 3));
 338         SR(VID_CONV_COEF(1, 4));
 339
 340         SR(VID_FIR_COEF_V(1, 0));
 341         SR(VID_FIR_COEF_V(1, 1));
 342         SR(VID_FIR_COEF_V(1, 2));
 343         SR(VID_FIR_COEF_V(1, 3));
 344         SR(VID_FIR_COEF_V(1, 4));
 345         SR(VID_FIR_COEF_V(1, 5));
 346         SR(VID_FIR_COEF_V(1, 6));
 347         SR(VID_FIR_COEF_V(1, 7));
 348
 349         SR(VID_PRELOAD(1));
 350 }
 351
 352 void dispc_restore_context(void)
 353 {
 354         RR(SYSCONFIG);
 355         /*RR(IRQENABLE);*/
 356         /*RR(CONTROL);*/
 357         RR(CONFIG);
 358         RR(DEFAULT_COLOR0);
 359         RR(DEFAULT_COLOR1);
 360         RR(TRANS_COLOR0);
 361         RR(TRANS_COLOR1);
 362         RR(LINE_NUMBER);
 363         RR(TIMING_H);
 364         RR(TIMING_V);
 365         RR(POL_FREQ);
 366         RR(DIVISOR);
 367         RR(GLOBAL_ALPHA);
 368         RR(SIZE_DIG);
 369         RR(SIZE_LCD);
 370
 371         RR(GFX_BA0);
 372         RR(GFX_BA1);
 373         RR(GFX_POSITION);
 374         RR(GFX_SIZE);
 375         RR(GFX_ATTRIBUTES);
 376         RR(GFX_FIFO_THRESHOLD);
 377         RR(GFX_ROW_INC);
 378         RR(GFX_PIXEL_INC);
 379         RR(GFX_WINDOW_SKIP);
 380         RR(GFX_TABLE_BA);
 381
 382         RR(DATA_CYCLE1);
 383         RR(DATA_CYCLE2);
 384         RR(DATA_CYCLE3);
 385
 386         RR(CPR_COEF_R);
 387         RR(CPR_COEF_G);
 388         RR(CPR_COEF_B);
 389
 390         RR(GFX_PRELOAD);
 391
 392         /* VID1 */
 393         RR(VID_BA0(0));
 394         RR(VID_BA1(0));
 395         RR(VID_POSITION(0));
 396         RR(VID_SIZE(0));
 397         RR(VID_ATTRIBUTES(0));
 398         RR(VID_FIFO_THRESHOLD(0));
 399         RR(VID_ROW_INC(0));
 400         RR(VID_PIXEL_INC(0));
 401         RR(VID_FIR(0));
 402         RR(VID_PICTURE_SIZE(0));
 403         RR(VID_ACCU0(0));
 404         RR(VID_ACCU1(0));
 405
 406         RR(VID_FIR_COEF_H(0, 0));
 407         RR(VID_FIR_COEF_H(0, 1));
 408         RR(VID_FIR_COEF_H(0, 2));
 409         RR(VID_FIR_COEF_H(0, 3));
 410         RR(VID_FIR_COEF_H(0, 4));
 411         RR(VID_FIR_COEF_H(0, 5));
 412         RR(VID_FIR_COEF_H(0, 6));
 413         RR(VID_FIR_COEF_H(0, 7));
 414
 415         RR(VID_FIR_COEF_HV(0, 0));
 416         RR(VID_FIR_COEF_HV(0, 1));
 417         RR(VID_FIR_COEF_HV(0, 2));
 418         RR(VID_FIR_COEF_HV(0, 3));
 419         RR(VID_FIR_COEF_HV(0, 4));
 420         RR(VID_FIR_COEF_HV(0, 5));
 421         RR(VID_FIR_COEF_HV(0, 6));
 422         RR(VID_FIR_COEF_HV(0, 7));
 423
 424         RR(VID_CONV_COEF(0, 0));
 425         RR(VID_CONV_COEF(0, 1));
 426         RR(VID_CONV_COEF(0, 2));
 427         RR(VID_CONV_COEF(0, 3));
 428         RR(VID_CONV_COEF(0, 4));
 429
 430         RR(VID_FIR_COEF_V(0, 0));
 431         RR(VID_FIR_COEF_V(0, 1));
 432         RR(VID_FIR_COEF_V(0, 2));
 433         RR(VID_FIR_COEF_V(0, 3));
 434         RR(VID_FIR_COEF_V(0, 4));
 435         RR(VID_FIR_COEF_V(0, 5));
 436         RR(VID_FIR_COEF_V(0, 6));
 437         RR(VID_FIR_COEF_V(0, 7));
 438
 439         RR(VID_PRELOAD(0));
 440
 441         /* VID2 */
 442         RR(VID_BA0(1));
 443         RR(VID_BA1(1));
 444         RR(VID_POSITION(1));
 445         RR(VID_SIZE(1));
 446         RR(VID_ATTRIBUTES(1));
 447         RR(VID_FIFO_THRESHOLD(1));
 448         RR(VID_ROW_INC(1));
 449         RR(VID_PIXEL_INC(1));
 450         RR(VID_FIR(1));
 451         RR(VID_PICTURE_SIZE(1));
 452         RR(VID_ACCU0(1));
 453         RR(VID_ACCU1(1));
 454
 455         RR(VID_FIR_COEF_H(1, 0));
 456         RR(VID_FIR_COEF_H(1, 1));
 457         RR(VID_FIR_COEF_H(1, 2));
 458         RR(VID_FIR_COEF_H(1, 3));
 459         RR(VID_FIR_COEF_H(1, 4));
 460         RR(VID_FIR_COEF_H(1, 5));
 461         RR(VID_FIR_COEF_H(1, 6));
 462         RR(VID_FIR_COEF_H(1, 7));
 463
 464         RR(VID_FIR_COEF_HV(1, 0));
 465         RR(VID_FIR_COEF_HV(1, 1));
 466         RR(VID_FIR_COEF_HV(1, 2));
 467         RR(VID_FIR_COEF_HV(1, 3));
 468         RR(VID_FIR_COEF_HV(1, 4));
 469         RR(VID_FIR_COEF_HV(1, 5));
 470         RR(VID_FIR_COEF_HV(1, 6));
 471         RR(VID_FIR_COEF_HV(1, 7));
 472
 473         RR(VID_CONV_COEF(1, 0));
 474         RR(VID_CONV_COEF(1, 1));
 475         RR(VID_CONV_COEF(1, 2));
 476         RR(VID_CONV_COEF(1, 3));
 477         RR(VID_CONV_COEF(1, 4));
 478
 479         RR(VID_FIR_COEF_V(1, 0));
 480         RR(VID_FIR_COEF_V(1, 1));
 481         RR(VID_FIR_COEF_V(1, 2));
 482         RR(VID_FIR_COEF_V(1, 3));
 483         RR(VID_FIR_COEF_V(1, 4));
 484         RR(VID_FIR_COEF_V(1, 5));
 485         RR(VID_FIR_COEF_V(1, 6));
 486         RR(VID_FIR_COEF_V(1, 7));
 487
 488         RR(VID_PRELOAD(1));
 489
 490         /* enable last, because LCD & DIGIT enable are here */
 491         RR(CONTROL);
 492
 493         /* clear spurious SYNC_LOST_DIGIT interrupts */
 494         dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
 495
 496         /*
 497          * enable last so IRQs won't trigger before
 498          * the context is fully restored
 499          */
 500         RR(IRQENABLE);
 501 }
 502
 503 #undef SR
 504 #undef RR
 505
 506 static inline void enable_clocks(bool enable)
 507 {
 508         if (enable)
 509                 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
 510         else
 511                 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
 512 }
 513
 514 bool dispc_go_busy(enum omap_channel channel)
 515 {
 516         int bit;
 517
 518         if (channel == OMAP_DSS_CHANNEL_LCD)
 519                 bit = 5; /* GOLCD */
 520         else
 521                 bit = 6; /* GODIGIT */
 522
 523         return REG_GET(DISPC_CONTROL, bit, bit) == 1;
 524 }
 525
 526 void dispc_go(enum omap_channel channel)
 527 {
 528         int bit;
 529
 530         enable_clocks(1);
 531
 532         if (channel == OMAP_DSS_CHANNEL_LCD)
 533                 bit = 0; /* LCDENABLE */
 534         else
 535                 bit = 1; /* DIGITALENABLE */
 536
 537         /* if the channel is not enabled, we don't need GO */
 538         if (REG_GET(DISPC_CONTROL, bit, bit) == 0)
 539                 goto end;
 540
 541         if (channel == OMAP_DSS_CHANNEL_LCD)
 542                 bit = 5; /* GOLCD */
 543         else
 544                 bit = 6; /* GODIGIT */
 545
 546         if (REG_GET(DISPC_CONTROL, bit, bit) == 1) {
 547                 DSSERR("GO bit not down for channel %d\n", channel);
 548                 goto end;
 549         }
 550
 551         DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" : "DIGIT");
 552
 553         REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
 554 end:
 555         enable_clocks(0);
 556 }
 557
 558 static void _dispc_write_firh_reg(enum omap_plane plane, int reg, u32 value)
 559 {
 560         BUG_ON(plane == OMAP_DSS_GFX);
 561
 562         dispc_write_reg(DISPC_VID_FIR_COEF_H(plane-1, reg), value);
 563 }
 564
 565 static void _dispc_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
 566 {
 567         BUG_ON(plane == OMAP_DSS_GFX);
 568
 569         dispc_write_reg(DISPC_VID_FIR_COEF_HV(plane-1, reg), value);
 570 }
 571
 572 static void _dispc_write_firv_reg(enum omap_plane plane, int reg, u32 value)
 573 {
 574         BUG_ON(plane == OMAP_DSS_GFX);
 575
 576         dispc_write_reg(DISPC_VID_FIR_COEF_V(plane-1, reg), value);
 577 }
 578
 579 static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup,
 580                 int vscaleup, int five_taps)
 581 {
 582         /* Coefficients for horizontal up-sampling */
 583         static const struct dispc_h_coef coef_hup[8] = {
 584                 {  0,   0, 128,   0,  0 },
 585                 { -1,  13, 124,  -8,  0 },
 586                 { -2,  30, 112, -11, -1 },
 587                 { -5,  51,  95, -11, -2 },
 588                 {  0,  -9,  73,  73, -9 },
 589                 { -2, -11,  95,  51, -5 },
 590                 { -1, -11, 112,  30, -2 },
 591                 {  0,  -8, 124,  13, -1 },
 592         };
 593
 594         /* Coefficients for vertical up-sampling */
 595         static const struct dispc_v_coef coef_vup_3tap[8] = {
 596                 { 0,  0, 128,  0, 0 },
 597                 { 0,  3, 123,  2, 0 },
 598                 { 0, 12, 111,  5, 0 },
 599                 { 0, 32,  89,  7, 0 },
 600                 { 0,  0,  64, 64, 0 },
 601                 { 0,  7,  89, 32, 0 },
 602                 { 0,  5, 111, 12, 0 },
 603                 { 0,  2, 123,  3, 0 },
 604         };
 605
 606         static const struct dispc_v_coef coef_vup_5tap[8] = {
 607                 {  0,   0, 128,   0,  0 },
 608                 { -1,  13, 124,  -8,  0 },
 609                 { -2,  30, 112, -11, -1 },
 610                 { -5,  51,  95, -11, -2 },
 611                 {  0,  -9,  73,  73, -9 },
 612                 { -2, -11,  95,  51, -5 },
 613                 { -1, -11, 112,  30, -2 },
 614                 {  0,  -8, 124,  13, -1 },
 615         };
 616
 617         /* Coefficients for horizontal down-sampling */
 618         static const struct dispc_h_coef coef_hdown[8] = {
 619                 {   0, 36, 56, 36,  0 },
 620                 {   4, 40, 55, 31, -2 },
 621                 {   8, 44, 54, 27, -5 },
 622                 {  12, 48, 53, 22, -7 },
 623                 {  -9, 17, 52, 51, 17 },
 624                 {  -7, 22, 53, 48, 12 },
 625                 {  -5, 27, 54, 44,  8 },
 626                 {  -2, 31, 55, 40,  4 },
 627         };
 628
 629         /* Coefficients for vertical down-sampling */
 630         static const struct dispc_v_coef coef_vdown_3tap[8] = {
 631                 { 0, 36, 56, 36, 0 },
 632                 { 0, 40, 57, 31, 0 },
 633                 { 0, 45, 56, 27, 0 },
 634                 { 0, 50, 55, 23, 0 },
 635                 { 0, 18, 55, 55, 0 },
 636                 { 0, 23, 55, 50, 0 },
 637                 { 0, 27, 56, 45, 0 },
 638                 { 0, 31, 57, 40, 0 },
 639         };
 640
 641         static const struct dispc_v_coef coef_vdown_5tap[8] = {
 642                 {   0, 36, 56, 36,  0 },
 643                 {   4, 40, 55, 31, -2 },
 644                 {   8, 44, 54, 27, -5 },
 645                 {  12, 48, 53, 22, -7 },
 646                 {  -9, 17, 52, 51, 17 },
 647                 {  -7, 22, 53, 48, 12 },
 648                 {  -5, 27, 54, 44,  8 },
 649                 {  -2, 31, 55, 40,  4 },
 650         };
 651
 652         const struct dispc_h_coef *h_coef;
 653         const struct dispc_v_coef *v_coef;
 654         int i;
 655
 656         if (hscaleup)
 657                 h_coef = coef_hup;
 658         else
 659                 h_coef = coef_hdown;
 660
 661         if (vscaleup)
 662                 v_coef = five_taps ? coef_vup_5tap : coef_vup_3tap;
 663         else
 664                 v_coef = five_taps ? coef_vdown_5tap : coef_vdown_3tap;
 665
 666         for (i = 0; i < 8; i++) {
 667                 u32 h, hv;
 668
 669                 h = FLD_VAL(h_coef[i].hc0, 7, 0)
 670                         | FLD_VAL(h_coef[i].hc1, 15, 8)
 671                         | FLD_VAL(h_coef[i].hc2, 23, 16)
 672                         | FLD_VAL(h_coef[i].hc3, 31, 24);
 673                 hv = FLD_VAL(h_coef[i].hc4, 7, 0)
 674                         | FLD_VAL(v_coef[i].vc0, 15, 8)
 675                         | FLD_VAL(v_coef[i].vc1, 23, 16)
 676                         | FLD_VAL(v_coef[i].vc2, 31, 24);
 677
 678                 _dispc_write_firh_reg(plane, i, h);
 679                 _dispc_write_firhv_reg(plane, i, hv);
 680         }
 681
 682         if (five_taps) {
 683                 for (i = 0; i < 8; i++) {
 684                         u32 v;
 685                         v = FLD_VAL(v_coef[i].vc00, 7, 0)
 686                                 | FLD_VAL(v_coef[i].vc22, 15, 8);
 687                         _dispc_write_firv_reg(plane, i, v);
 688                 }
 689         }
 690 }
 691
 692 static void _dispc_setup_color_conv_coef(void)
 693 {
 694         const struct color_conv_coef {
 695                 int  ry,  rcr,  rcb,   gy,  gcr,  gcb,   by,  bcr,  bcb;
 696                 int  full_range;
 697         }  ctbl_bt601_5 = {
 698                 298,  409,    0,  298, -208, -100,  298,    0,  517, 0,
 699         };
 700
 701         const struct color_conv_coef *ct;
 702
 703 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
 704
 705         ct = &ctbl_bt601_5;
 706
 707         dispc_write_reg(DISPC_VID_CONV_COEF(0, 0), CVAL(ct->rcr, ct->ry));
 708         dispc_write_reg(DISPC_VID_CONV_COEF(0, 1), CVAL(ct->gy,  ct->rcb));
 709         dispc_write_reg(DISPC_VID_CONV_COEF(0, 2), CVAL(ct->gcb, ct->gcr));
 710         dispc_write_reg(DISPC_VID_CONV_COEF(0, 3), CVAL(ct->bcr, ct->by));
 711         dispc_write_reg(DISPC_VID_CONV_COEF(0, 4), CVAL(0,       ct->bcb));
 712
 713         dispc_write_reg(DISPC_VID_CONV_COEF(1, 0), CVAL(ct->rcr, ct->ry));
 714         dispc_write_reg(DISPC_VID_CONV_COEF(1, 1), CVAL(ct->gy,  ct->rcb));
 715         dispc_write_reg(DISPC_VID_CONV_COEF(1, 2), CVAL(ct->gcb, ct->gcr));
 716         dispc_write_reg(DISPC_VID_CONV_COEF(1, 3), CVAL(ct->bcr, ct->by));
 717         dispc_write_reg(DISPC_VID_CONV_COEF(1, 4), CVAL(0,       ct->bcb));
 718
 719 #undef CVAL
 720
 721         REG_FLD_MOD(DISPC_VID_ATTRIBUTES(0), ct->full_range, 11, 11);
 722         REG_FLD_MOD(DISPC_VID_ATTRIBUTES(1), ct->full_range, 11, 11);
 723 }
 724
 725
 726 static void _dispc_set_plane_ba0(enum omap_plane plane, u32 paddr)
 727 {
 728         const struct dispc_reg ba0_reg[] = { DISPC_GFX_BA0,
 729                 DISPC_VID_BA0(0),
 730                 DISPC_VID_BA0(1) };
 731
 732         dispc_write_reg(ba0_reg[plane], paddr);
 733 }
 734
 735 static void _dispc_set_plane_ba1(enum omap_plane plane, u32 paddr)
 736 {
 737         const struct dispc_reg ba1_reg[] = { DISPC_GFX_BA1,
 738                                       DISPC_VID_BA1(0),
 739                                       DISPC_VID_BA1(1) };
 740
 741         dispc_write_reg(ba1_reg[plane], paddr);
 742 }
 743
 744 static void _dispc_set_plane_pos(enum omap_plane plane, int x, int y)
 745 {
 746         const struct dispc_reg pos_reg[] = { DISPC_GFX_POSITION,
 747                                       DISPC_VID_POSITION(0),
 748                                       DISPC_VID_POSITION(1) };
 749
 750         u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
 751         dispc_write_reg(pos_reg[plane], val);
 752 }
 753
 754 static void _dispc_set_pic_size(enum omap_plane plane, int width, int height)
 755 {
 756         const struct dispc_reg siz_reg[] = { DISPC_GFX_SIZE,
 757                                       DISPC_VID_PICTURE_SIZE(0),
 758                                       DISPC_VID_PICTURE_SIZE(1) };
 759         u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 760         dispc_write_reg(siz_reg[plane], val);
 761 }
 762
 763 static void _dispc_set_vid_size(enum omap_plane plane, int width, int height)
 764 {
 765         u32 val;
 766         const struct dispc_reg vsi_reg[] = { DISPC_VID_SIZE(0),
 767                                       DISPC_VID_SIZE(1) };
 768
 769         BUG_ON(plane == OMAP_DSS_GFX);
 770
 771         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 772         dispc_write_reg(vsi_reg[plane-1], val);
 773 }
 774
 775 static void _dispc_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
 776 {
 777
 778         BUG_ON(plane == OMAP_DSS_VIDEO1);
 779
 780         if (cpu_is_omap24xx())
 781                 return;
 782
 783         if (plane == OMAP_DSS_GFX)
 784                 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 7, 0);
 785         else if (plane == OMAP_DSS_VIDEO2)
 786                 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 23, 16);
 787 }
 788
 789 static void _dispc_set_pix_inc(enum omap_plane plane, s32 inc)
 790 {
 791         const struct dispc_reg ri_reg[] = { DISPC_GFX_PIXEL_INC,
 792                                      DISPC_VID_PIXEL_INC(0),
 793                                      DISPC_VID_PIXEL_INC(1) };
 794
 795         dispc_write_reg(ri_reg[plane], inc);
 796 }
 797
 798 static void _dispc_set_row_inc(enum omap_plane plane, s32 inc)
 799 {
 800         const struct dispc_reg ri_reg[] = { DISPC_GFX_ROW_INC,
 801                                      DISPC_VID_ROW_INC(0),
 802                                      DISPC_VID_ROW_INC(1) };
 803
 804         dispc_write_reg(ri_reg[plane], inc);
 805 }
 806
 807 static void _dispc_set_color_mode(enum omap_plane plane,
 808                 enum omap_color_mode color_mode)
 809 {
 810         u32 m = 0;
 811
 812         switch (color_mode) {
 813         case OMAP_DSS_COLOR_CLUT1:
 814                 m = 0x0; break;
 815         case OMAP_DSS_COLOR_CLUT2:
 816                 m = 0x1; break;
 817         case OMAP_DSS_COLOR_CLUT4:
 818                 m = 0x2; break;
 819         case OMAP_DSS_COLOR_CLUT8:
 820                 m = 0x3; break;
 821         case OMAP_DSS_COLOR_RGB12U:
 822                 m = 0x4; break;
 823         case OMAP_DSS_COLOR_ARGB16:
 824                 m = 0x5; break;
 825         case OMAP_DSS_COLOR_RGB16:
 826                 m = 0x6; break;
 827         case OMAP_DSS_COLOR_RGB24U:
 828                 m = 0x8; break;
 829         case OMAP_DSS_COLOR_RGB24P:
 830                 m = 0x9; break;
 831         case OMAP_DSS_COLOR_YUV2:
 832                 m = 0xa; break;
 833         case OMAP_DSS_COLOR_UYVY:
 834                 m = 0xb; break;
 835         case OMAP_DSS_COLOR_ARGB32:
 836                 m = 0xc; break;
 837         case OMAP_DSS_COLOR_RGBA32:
 838                 m = 0xd; break;
 839         case OMAP_DSS_COLOR_RGBX32:
 840                 m = 0xe; break;
 841         default:
 842                 BUG(); break;
 843         }
 844
 845         REG_FLD_MOD(dispc_reg_att[plane], m, 4, 1);
 846 }
 847
 848 static void _dispc_set_channel_out(enum omap_plane plane,
 849                 enum omap_channel channel)
 850 {
 851         int shift;
 852         u32 val;
 853
 854         switch (plane) {
 855         case OMAP_DSS_GFX:
 856                 shift = 8;
 857                 break;
 858         case OMAP_DSS_VIDEO1:
 859         case OMAP_DSS_VIDEO2:
 860                 shift = 16;
 861                 break;
 862         default:
 863                 BUG();
 864                 return;
 865         }
 866
 867         val = dispc_read_reg(dispc_reg_att[plane]);
 868         val = FLD_MOD(val, channel, shift, shift);
 869         dispc_write_reg(dispc_reg_att[plane], val);
 870 }
 871
 872 void dispc_set_burst_size(enum omap_plane plane,
 873                 enum omap_burst_size burst_size)
 874 {
 875         int shift;
 876         u32 val;
 877
 878         enable_clocks(1);
 879
 880         switch (plane) {
 881         case OMAP_DSS_GFX:
 882                 shift = 6;
 883                 break;
 884         case OMAP_DSS_VIDEO1:
 885         case OMAP_DSS_VIDEO2:
 886                 shift = 14;
 887                 break;
 888         default:
 889                 BUG();
 890                 return;
 891         }
 892
 893         val = dispc_read_reg(dispc_reg_att[plane]);
 894         val = FLD_MOD(val, burst_size, shift+1, shift);
 895         dispc_write_reg(dispc_reg_att[plane], val);
 896
 897         enable_clocks(0);
 898 }
 899
 900 static void _dispc_set_vid_color_conv(enum omap_plane plane, bool enable)
 901 {
 902         u32 val;
 903
 904         BUG_ON(plane == OMAP_DSS_GFX);
 905
 906         val = dispc_read_reg(dispc_reg_att[plane]);
 907         val = FLD_MOD(val, enable, 9, 9);
 908         dispc_write_reg(dispc_reg_att[plane], val);
 909 }
 910
 911 void dispc_enable_replication(enum omap_plane plane, bool enable)
 912 {
 913         int bit;
 914
 915         if (plane == OMAP_DSS_GFX)
 916                 bit = 5;
 917         else
 918                 bit = 10;
 919
 920         enable_clocks(1);
 921         REG_FLD_MOD(dispc_reg_att[plane], enable, bit, bit);
 922         enable_clocks(0);
 923 }
 924
 925 void dispc_set_lcd_size(u16 width, u16 height)
 926 {
 927         u32 val;
 928         BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
 929         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 930         enable_clocks(1);
 931         dispc_write_reg(DISPC_SIZE_LCD, val);
 932         enable_clocks(0);
 933 }
 934
 935 void dispc_set_digit_size(u16 width, u16 height)
 936 {
 937         u32 val;
 938         BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
 939         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 940         enable_clocks(1);
 941         dispc_write_reg(DISPC_SIZE_DIG, val);
 942         enable_clocks(0);
 943 }
 944
 945 static void dispc_read_plane_fifo_sizes(void)
 946 {
 947         const struct dispc_reg fsz_reg[] = { DISPC_GFX_FIFO_SIZE_STATUS,
 948                                       DISPC_VID_FIFO_SIZE_STATUS(0),
 949                                       DISPC_VID_FIFO_SIZE_STATUS(1) };
 950         u32 size;
 951         int plane;
 952
 953         enable_clocks(1);
 954
 955         for (plane = 0; plane < ARRAY_SIZE(dispc.fifo_size); ++plane) {
 956                 if (cpu_is_omap24xx())
 957                         size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 8, 0);
 958                 else if (cpu_is_omap34xx())
 959                         size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 10, 0);
 960                 else
 961                         BUG();
 962
 963                 dispc.fifo_size[plane] = size;
 964         }
 965
 966         enable_clocks(0);
 967 }
 968
 969 u32 dispc_get_plane_fifo_size(enum omap_plane plane)
 970 {
 971         return dispc.fifo_size[plane];
 972 }
 973
 974 void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high)
 975 {
 976         const struct dispc_reg ftrs_reg[] = { DISPC_GFX_FIFO_THRESHOLD,
 977                                        DISPC_VID_FIFO_THRESHOLD(0),
 978                                        DISPC_VID_FIFO_THRESHOLD(1) };
 979         enable_clocks(1);
 980
 981         DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n",
 982                         plane,
 983                         REG_GET(ftrs_reg[plane], 11, 0),
 984                         REG_GET(ftrs_reg[plane], 27, 16),
 985                         low, high);
 986
 987         if (cpu_is_omap24xx())
 988                 dispc_write_reg(ftrs_reg[plane],
 989                                 FLD_VAL(high, 24, 16) | FLD_VAL(low, 8, 0));
 990         else
 991                 dispc_write_reg(ftrs_reg[plane],
 992                                 FLD_VAL(high, 27, 16) | FLD_VAL(low, 11, 0));
 993
 994         enable_clocks(0);
 995 }
 996
 997 void dispc_enable_fifomerge(bool enable)
 998 {
 999         enable_clocks(1);
1000
1001         DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1002         REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1003
1004         enable_clocks(0);
1005 }
1006
1007 static void _dispc_set_fir(enum omap_plane plane, int hinc, int vinc)
1008 {
1009         u32 val;
1010         const struct dispc_reg fir_reg[] = { DISPC_VID_FIR(0),
1011                                       DISPC_VID_FIR(1) };
1012
1013         BUG_ON(plane == OMAP_DSS_GFX);
1014
1015         if (cpu_is_omap24xx())
1016                 val = FLD_VAL(vinc, 27, 16) | FLD_VAL(hinc, 11, 0);
1017         else
1018                 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1019         dispc_write_reg(fir_reg[plane-1], val);
1020 }
1021
1022 static void _dispc_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1023 {
1024         u32 val;
1025         const struct dispc_reg ac0_reg[] = { DISPC_VID_ACCU0(0),
1026                                       DISPC_VID_ACCU0(1) };
1027
1028         BUG_ON(plane == OMAP_DSS_GFX);
1029
1030         val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0);
1031         dispc_write_reg(ac0_reg[plane-1], val);
1032 }
1033
1034 static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1035 {
1036         u32 val;
1037         const struct dispc_reg ac1_reg[] = { DISPC_VID_ACCU1(0),
1038                                       DISPC_VID_ACCU1(1) };
1039
1040         BUG_ON(plane == OMAP_DSS_GFX);
1041
1042         val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0);
1043         dispc_write_reg(ac1_reg[plane-1], val);
1044 }
1045
1046
1047 static void _dispc_set_scaling(enum omap_plane plane,
1048                 u16 orig_width, u16 orig_height,
1049                 u16 out_width, u16 out_height,
1050                 bool ilace, bool five_taps,
1051                 bool fieldmode)
1052 {
1053         int fir_hinc;
1054         int fir_vinc;
1055         int hscaleup, vscaleup;
1056         int accu0 = 0;
1057         int accu1 = 0;
1058         u32 l;
1059
1060         BUG_ON(plane == OMAP_DSS_GFX);
1061
1062         hscaleup = orig_width <= out_width;
1063         vscaleup = orig_height <= out_height;
1064
1065         _dispc_set_scale_coef(plane, hscaleup, vscaleup, five_taps);
1066
1067         if (!orig_width || orig_width == out_width)
1068                 fir_hinc = 0;
1069         else
1070                 fir_hinc = 1024 * orig_width / out_width;
1071
1072         if (!orig_height || orig_height == out_height)
1073                 fir_vinc = 0;
1074         else
1075                 fir_vinc = 1024 * orig_height / out_height;
1076
1077         _dispc_set_fir(plane, fir_hinc, fir_vinc);
1078
1079         l = dispc_read_reg(dispc_reg_att[plane]);
1080         l &= ~((0x0f << 5) | (0x3 << 21));
1081
1082         l |= fir_hinc ? (1 << 5) : 0;
1083         l |= fir_vinc ? (1 << 6) : 0;
1084
1085         l |= hscaleup ? 0 : (1 << 7);
1086         l |= vscaleup ? 0 : (1 << 8);
1087
1088         l |= five_taps ? (1 << 21) : 0;
1089         l |= five_taps ? (1 << 22) : 0;
1090
1091         dispc_write_reg(dispc_reg_att[plane], l);
1092
1093         /*
1094          * field 0 = even field = bottom field
1095          * field 1 = odd field = top field
1096          */
1097         if (ilace && !fieldmode) {
1098                 accu1 = 0;
1099                 accu0 = (fir_vinc / 2) & 0x3ff;
1100                 if (accu0 >= 1024/2) {
1101                         accu1 = 1024/2;
1102                         accu0 -= accu1;
1103                 }
1104         }
1105
1106         _dispc_set_vid_accu0(plane, 0, accu0);
1107         _dispc_set_vid_accu1(plane, 0, accu1);
1108 }
1109
1110 static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1111                 bool mirroring, enum omap_color_mode color_mode)
1112 {
1113         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1114                         color_mode == OMAP_DSS_COLOR_UYVY) {
1115                 int vidrot = 0;
1116
1117                 if (mirroring) {
1118                         switch (rotation) {
1119                         case OMAP_DSS_ROT_0:
1120                                 vidrot = 2;
1121                                 break;
1122                         case OMAP_DSS_ROT_90:
1123                                 vidrot = 1;
1124                                 break;
1125                         case OMAP_DSS_ROT_180:
1126                                 vidrot = 0;
1127                                 break;
1128                         case OMAP_DSS_ROT_270:
1129                                 vidrot = 3;
1130                                 break;
1131                         }
1132                 } else {
1133                         switch (rotation) {
1134                         case OMAP_DSS_ROT_0:
1135                                 vidrot = 0;
1136                                 break;
1137                         case OMAP_DSS_ROT_90:
1138                                 vidrot = 1;
1139                                 break;
1140                         case OMAP_DSS_ROT_180:
1141                                 vidrot = 2;
1142                                 break;
1143                         case OMAP_DSS_ROT_270:
1144                                 vidrot = 3;
1145                                 break;
1146                         }
1147                 }
1148
1149                 REG_FLD_MOD(dispc_reg_att[plane], vidrot, 13, 12);
1150
1151                 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
1152                         REG_FLD_MOD(dispc_reg_att[plane], 0x1, 18, 18);
1153                 else
1154                         REG_FLD_MOD(dispc_reg_att[plane], 0x0, 18, 18);
1155         } else {
1156                 REG_FLD_MOD(dispc_reg_att[plane], 0, 13, 12);
1157                 REG_FLD_MOD(dispc_reg_att[plane], 0, 18, 18);
1158         }
1159 }
1160
1161 static int color_mode_to_bpp(enum omap_color_mode color_mode)
1162 {
1163         switch (color_mode) {
1164         case OMAP_DSS_COLOR_CLUT1:
1165                 return 1;
1166         case OMAP_DSS_COLOR_CLUT2:
1167                 return 2;
1168         case OMAP_DSS_COLOR_CLUT4:
1169                 return 4;
1170         case OMAP_DSS_COLOR_CLUT8:
1171                 return 8;
1172         case OMAP_DSS_COLOR_RGB12U:
1173         case OMAP_DSS_COLOR_RGB16:
1174         case OMAP_DSS_COLOR_ARGB16:
1175         case OMAP_DSS_COLOR_YUV2:
1176         case OMAP_DSS_COLOR_UYVY:
1177                 return 16;
1178         case OMAP_DSS_COLOR_RGB24P:
1179                 return 24;
1180         case OMAP_DSS_COLOR_RGB24U:
1181         case OMAP_DSS_COLOR_ARGB32:
1182         case OMAP_DSS_COLOR_RGBA32:
1183         case OMAP_DSS_COLOR_RGBX32:
1184                 return 32;
1185         default:
1186                 BUG();
1187         }
1188 }
1189
1190 static s32 pixinc(int pixels, u8 ps)
1191 {
1192         if (pixels == 1)
1193                 return 1;
1194         else if (pixels > 1)
1195                 return 1 + (pixels - 1) * ps;
1196         else if (pixels < 0)
1197                 return 1 - (-pixels + 1) * ps;
1198         else
1199                 BUG();
1200 }
1201
1202 static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1203                 u16 screen_width,
1204                 u16 width, u16 height,
1205                 enum omap_color_mode color_mode, bool fieldmode,
1206                 unsigned int field_offset,
1207                 unsigned *offset0, unsigned *offset1,
1208                 s32 *row_inc, s32 *pix_inc)
1209 {
1210         u8 ps;
1211
1212         /* FIXME CLUT formats */
1213         switch (color_mode) {
1214         case OMAP_DSS_COLOR_CLUT1:
1215         case OMAP_DSS_COLOR_CLUT2:
1216         case OMAP_DSS_COLOR_CLUT4:
1217         case OMAP_DSS_COLOR_CLUT8:
1218                 BUG();
1219                 return;
1220         case OMAP_DSS_COLOR_YUV2:
1221         case OMAP_DSS_COLOR_UYVY:
1222                 ps = 4;
1223                 break;
1224         default:
1225                 ps = color_mode_to_bpp(color_mode) / 8;
1226                 break;
1227         }
1228
1229         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1230                         width, height);
1231
1232         /*
1233          * field 0 = even field = bottom field
1234          * field 1 = odd field = top field
1235          */
1236         switch (rotation + mirror * 4) {
1237         case OMAP_DSS_ROT_0:
1238         case OMAP_DSS_ROT_180:
1239                 /*
1240                  * If the pixel format is YUV or UYVY divide the width
1241                  * of the image by 2 for 0 and 180 degree rotation.
1242                  */
1243                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1244                         color_mode == OMAP_DSS_COLOR_UYVY)
1245                         width = width >> 1;
1246         case OMAP_DSS_ROT_90:
1247         case OMAP_DSS_ROT_270:
1248                 *offset1 = 0;
1249                 if (field_offset)
1250                         *offset0 = field_offset * screen_width * ps;
1251                 else
1252                         *offset0 = 0;
1253
1254                 *row_inc = pixinc(1 + (screen_width - width) +
1255                                 (fieldmode ? screen_width : 0),
1256                                 ps);
1257                 *pix_inc = pixinc(1, ps);
1258                 break;
1259
1260         case OMAP_DSS_ROT_0 + 4:
1261         case OMAP_DSS_ROT_180 + 4:
1262                 /* If the pixel format is YUV or UYVY divide the width
1263                  * of the image by 2  for 0 degree and 180 degree
1264                  */
1265                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1266                         color_mode == OMAP_DSS_COLOR_UYVY)
1267                         width = width >> 1;
1268         case OMAP_DSS_ROT_90 + 4:
1269         case OMAP_DSS_ROT_270 + 4:
1270                 *offset1 = 0;
1271                 if (field_offset)
1272                         *offset0 = field_offset * screen_width * ps;
1273                 else
1274                         *offset0 = 0;
1275                 *row_inc = pixinc(1 - (screen_width + width) -
1276                                 (fieldmode ? screen_width : 0),
1277                                 ps);
1278                 *pix_inc = pixinc(1, ps);
1279                 break;
1280
1281         default:
1282                 BUG();
1283         }
1284 }
1285
1286 static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1287                 u16 screen_width,
1288                 u16 width, u16 height,
1289                 enum omap_color_mode color_mode, bool fieldmode,
1290                 unsigned int field_offset,
1291                 unsigned *offset0, unsigned *offset1,
1292                 s32 *row_inc, s32 *pix_inc)
1293 {
1294         u8 ps;
1295         u16 fbw, fbh;
1296
1297         /* FIXME CLUT formats */
1298         switch (color_mode) {
1299         case OMAP_DSS_COLOR_CLUT1:
1300         case OMAP_DSS_COLOR_CLUT2:
1301         case OMAP_DSS_COLOR_CLUT4:
1302         case OMAP_DSS_COLOR_CLUT8:
1303                 BUG();
1304                 return;
1305         default:
1306                 ps = color_mode_to_bpp(color_mode) / 8;
1307                 break;
1308         }
1309
1310         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1311                         width, height);
1312
1313         /* width & height are overlay sizes, convert to fb sizes */
1314
1315         if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1316                 fbw = width;
1317                 fbh = height;
1318         } else {
1319                 fbw = height;
1320                 fbh = width;
1321         }
1322
1323         /*
1324          * field 0 = even field = bottom field
1325          * field 1 = odd field = top field
1326          */
1327         switch (rotation + mirror * 4) {
1328         case OMAP_DSS_ROT_0:
1329                 *offset1 = 0;
1330                 if (field_offset)
1331                         *offset0 = *offset1 + field_offset * screen_width * ps;
1332                 else
1333                         *offset0 = *offset1;
1334                 *row_inc = pixinc(1 + (screen_width - fbw) +
1335                                 (fieldmode ? screen_width : 0),
1336                                 ps);
1337                 *pix_inc = pixinc(1, ps);
1338                 break;
1339         case OMAP_DSS_ROT_90:
1340                 *offset1 = screen_width * (fbh - 1) * ps;
1341                 if (field_offset)
1342                         *offset0 = *offset1 + field_offset * ps;
1343                 else
1344                         *offset0 = *offset1;
1345                 *row_inc = pixinc(screen_width * (fbh - 1) + 1 +
1346                                 (fieldmode ? 1 : 0), ps);
1347                 *pix_inc = pixinc(-screen_width, ps);
1348                 break;
1349         case OMAP_DSS_ROT_180:
1350                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1351                 if (field_offset)
1352                         *offset0 = *offset1 - field_offset * screen_width * ps;
1353                 else
1354                         *offset0 = *offset1;
1355                 *row_inc = pixinc(-1 -
1356                                 (screen_width - fbw) -
1357                                 (fieldmode ? screen_width : 0),
1358                                 ps);
1359                 *pix_inc = pixinc(-1, ps);
1360                 break;
1361         case OMAP_DSS_ROT_270:
1362                 *offset1 = (fbw - 1) * ps;
1363                 if (field_offset)
1364                         *offset0 = *offset1 - field_offset * ps;
1365                 else
1366                         *offset0 = *offset1;
1367                 *row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
1368                                 (fieldmode ? 1 : 0), ps);
1369                 *pix_inc = pixinc(screen_width, ps);
1370                 break;
1371
1372         /* mirroring */
1373         case OMAP_DSS_ROT_0 + 4:
1374                 *offset1 = (fbw - 1) * ps;
1375                 if (field_offset)
1376                         *offset0 = *offset1 + field_offset * screen_width * ps;
1377                 else
1378                         *offset0 = *offset1;
1379                 *row_inc = pixinc(screen_width * 2 - 1 +
1380                                 (fieldmode ? screen_width : 0),
1381                                 ps);
1382                 *pix_inc = pixinc(-1, ps);
1383                 break;
1384
1385         case OMAP_DSS_ROT_90 + 4:
1386                 *offset1 = 0;
1387                 if (field_offset)
1388                         *offset0 = *offset1 + field_offset * ps;
1389                 else
1390                         *offset0 = *offset1;
1391                 *row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
1392                                 (fieldmode ? 1 : 0),
1393                                 ps);
1394                 *pix_inc = pixinc(screen_width, ps);
1395                 break;
1396
1397         case OMAP_DSS_ROT_180 + 4:
1398                 *offset1 = screen_width * (fbh - 1) * ps;
1399                 if (field_offset)
1400                         *offset0 = *offset1 - field_offset * screen_width * ps;
1401                 else
1402                         *offset0 = *offset1;
1403                 *row_inc = pixinc(1 - screen_width * 2 -
1404                                 (fieldmode ? screen_width : 0),
1405                                 ps);
1406                 *pix_inc = pixinc(1, ps);
1407                 break;
1408
1409         case OMAP_DSS_ROT_270 + 4:
1410                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1411                 if (field_offset)
1412                         *offset0 = *offset1 - field_offset * ps;
1413                 else
1414                         *offset0 = *offset1;
1415                 *row_inc = pixinc(screen_width * (fbh - 1) - 1 -
1416                                 (fieldmode ? 1 : 0),
1417                                 ps);
1418                 *pix_inc = pixinc(-screen_width, ps);
1419                 break;
1420
1421         default:
1422                 BUG();
1423         }
1424 }
1425
1426 static unsigned long calc_fclk_five_taps(u16 width, u16 height,
1427                 u16 out_width, u16 out_height, enum omap_color_mode color_mode)
1428 {
1429         u32 fclk = 0;
1430         /* FIXME venc pclk? */
1431         u64 tmp, pclk = dispc_pclk_rate();
1432
1433         if (height > out_height) {
1434                 /* FIXME get real display PPL */
1435                 unsigned int ppl = 800;
1436
1437                 tmp = pclk * height * out_width;
1438                 do_div(tmp, 2 * out_height * ppl);
1439                 fclk = tmp;
1440
1441                 if (height > 2 * out_height) {
1442                         if (ppl == out_width)
1443                                 return 0;
1444
1445                         tmp = pclk * (height - 2 * out_height) * out_width;
1446                         do_div(tmp, 2 * out_height * (ppl - out_width));
1447                         fclk = max(fclk, (u32) tmp);
1448                 }
1449         }
1450
1451         if (width > out_width) {
1452                 tmp = pclk * width;
1453                 do_div(tmp, out_width);
1454                 fclk = max(fclk, (u32) tmp);
1455
1456                 if (color_mode == OMAP_DSS_COLOR_RGB24U)
1457                         fclk <<= 1;
1458         }
1459
1460         return fclk;
1461 }
1462
1463 static unsigned long calc_fclk(u16 width, u16 height,
1464                 u16 out_width, u16 out_height)
1465 {
1466         unsigned int hf, vf;
1467
1468         /*
1469          * FIXME how to determine the 'A' factor
1470          * for the no downscaling case ?
1471          */
1472
1473         if (width > 3 * out_width)
1474                 hf = 4;
1475         else if (width > 2 * out_width)
1476                 hf = 3;
1477         else if (width > out_width)
1478                 hf = 2;
1479         else
1480                 hf = 1;
1481
1482         if (height > out_height)
1483                 vf = 2;
1484         else
1485                 vf = 1;
1486
1487         /* FIXME venc pclk? */
1488         return dispc_pclk_rate() * vf * hf;
1489 }
1490
1491 void dispc_set_channel_out(enum omap_plane plane, enum omap_channel channel_out)
1492 {
1493         enable_clocks(1);
1494         _dispc_set_channel_out(plane, channel_out);
1495         enable_clocks(0);
1496 }
1497
1498 static int _dispc_setup_plane(enum omap_plane plane,
1499                 u32 paddr, u16 screen_width,
1500                 u16 pos_x, u16 pos_y,
1501                 u16 width, u16 height,
1502                 u16 out_width, u16 out_height,
1503                 enum omap_color_mode color_mode,
1504                 bool ilace,
1505                 enum omap_dss_rotation_type rotation_type,
1506                 u8 rotation, int mirror,
1507                 u8 global_alpha)
1508 {
1509         const int maxdownscale = cpu_is_omap34xx() ? 4 : 2;
1510         bool five_taps = 0;
1511         bool fieldmode = 0;
1512         int cconv = 0;
1513         unsigned offset0, offset1;
1514         s32 row_inc;
1515         s32 pix_inc;
1516         u16 frame_height = height;
1517         unsigned int field_offset = 0;
1518
1519         if (paddr == 0)
1520                 return -EINVAL;
1521
1522         if (ilace && height == out_height)
1523                 fieldmode = 1;
1524
1525         if (ilace) {
1526                 if (fieldmode)
1527                         height /= 2;
1528                 pos_y /= 2;
1529                 out_height /= 2;
1530
1531                 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
1532                                 "out_height %d\n",
1533                                 height, pos_y, out_height);
1534         }
1535
1536         if (plane == OMAP_DSS_GFX) {
1537                 if (width != out_width || height != out_height)
1538                         return -EINVAL;
1539
1540                 switch (color_mode) {
1541                 case OMAP_DSS_COLOR_ARGB16:
1542                 case OMAP_DSS_COLOR_ARGB32:
1543                 case OMAP_DSS_COLOR_RGBA32:
1544                 case OMAP_DSS_COLOR_RGBX32:
1545                         if (cpu_is_omap24xx())
1546                                 return -EINVAL;
1547                         /* fall through */
1548                 case OMAP_DSS_COLOR_RGB12U:
1549                 case OMAP_DSS_COLOR_RGB16:
1550                 case OMAP_DSS_COLOR_RGB24P:
1551                 case OMAP_DSS_COLOR_RGB24U:
1552                         break;
1553
1554                 default:
1555                         return -EINVAL;
1556                 }
1557         } else {
1558                 /* video plane */
1559
1560                 unsigned long fclk = 0;
1561
1562                 if (out_width < width / maxdownscale ||
1563                    out_width > width * 8)
1564                         return -EINVAL;
1565
1566                 if (out_height < height / maxdownscale ||
1567                    out_height > height * 8)
1568                         return -EINVAL;
1569
1570                 switch (color_mode) {
1571                 case OMAP_DSS_COLOR_RGBX32:
1572                 case OMAP_DSS_COLOR_RGB12U:
1573                         if (cpu_is_omap24xx())
1574                                 return -EINVAL;
1575                         /* fall through */
1576                 case OMAP_DSS_COLOR_RGB16:
1577                 case OMAP_DSS_COLOR_RGB24P:
1578                 case OMAP_DSS_COLOR_RGB24U:
1579                         break;
1580
1581                 case OMAP_DSS_COLOR_ARGB16:
1582                 case OMAP_DSS_COLOR_ARGB32:
1583                 case OMAP_DSS_COLOR_RGBA32:
1584                         if (cpu_is_omap24xx())
1585                                 return -EINVAL;
1586                         if (plane == OMAP_DSS_VIDEO1)
1587                                 return -EINVAL;
1588                         break;
1589
1590                 case OMAP_DSS_COLOR_YUV2:
1591                 case OMAP_DSS_COLOR_UYVY:
1592                         cconv = 1;
1593                         break;
1594
1595                 default:
1596                         return -EINVAL;
1597                 }
1598
1599                 /* Must use 5-tap filter? */
1600                 five_taps = height > out_height * 2;
1601
1602                 if (!five_taps) {
1603                         fclk = calc_fclk(width, height,
1604                                         out_width, out_height);
1605
1606                         /* Try 5-tap filter if 3-tap fclk is too high */
1607                         if (cpu_is_omap34xx() && height > out_height &&
1608                                         fclk > dispc_fclk_rate())
1609                                 five_taps = true;
1610                 }
1611
1612                 if (width > (2048 >> five_taps)) {
1613                         DSSERR("failed to set up scaling, fclk too low\n");
1614                         return -EINVAL;
1615                 }
1616
1617                 if (five_taps)
1618                         fclk = calc_fclk_five_taps(width, height,
1619                                         out_width, out_height, color_mode);
1620
1621                 DSSDBG("required fclk rate = %lu Hz\n", fclk);
1622                 DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
1623
1624                 if (!fclk || fclk > dispc_fclk_rate()) {
1625                         DSSERR("failed to set up scaling, "
1626                                         "required fclk rate = %lu Hz, "
1627                                         "current fclk rate = %lu Hz\n",
1628                                         fclk, dispc_fclk_rate());
1629                         return -EINVAL;
1630                 }
1631         }
1632
1633         if (ilace && !fieldmode) {
1634                 /*
1635                  * when downscaling the bottom field may have to start several
1636                  * source lines below the top field. Unfortunately ACCUI
1637                  * registers will only hold the fractional part of the offset
1638                  * so the integer part must be added to the base address of the
1639                  * bottom field.
1640                  */
1641                 if (!height || height == out_height)
1642                         field_offset = 0;
1643                 else
1644                         field_offset = height / out_height / 2;
1645         }
1646
1647         /* Fields are independent but interleaved in memory. */
1648         if (fieldmode)
1649                 field_offset = 1;
1650
1651         if (rotation_type == OMAP_DSS_ROT_DMA)
1652                 calc_dma_rotation_offset(rotation, mirror,
1653                                 screen_width, width, frame_height, color_mode,
1654                                 fieldmode, field_offset,
1655                                 &offset0, &offset1, &row_inc, &pix_inc);
1656         else
1657                 calc_vrfb_rotation_offset(rotation, mirror,
1658                                 screen_width, width, frame_height, color_mode,
1659                                 fieldmode, field_offset,
1660                                 &offset0, &offset1, &row_inc, &pix_inc);
1661
1662         DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
1663                         offset0, offset1, row_inc, pix_inc);
1664
1665         _dispc_set_color_mode(plane, color_mode);
1666
1667         _dispc_set_plane_ba0(plane, paddr + offset0);
1668         _dispc_set_plane_ba1(plane, paddr + offset1);
1669
1670         _dispc_set_row_inc(plane, row_inc);
1671         _dispc_set_pix_inc(plane, pix_inc);
1672
1673         DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, width, height,
1674                         out_width, out_height);
1675
1676         _dispc_set_plane_pos(plane, pos_x, pos_y);
1677
1678         _dispc_set_pic_size(plane, width, height);
1679
1680         if (plane != OMAP_DSS_GFX) {
1681                 _dispc_set_scaling(plane, width, height,
1682                                    out_width, out_height,
1683                                    ilace, five_taps, fieldmode);
1684                 _dispc_set_vid_size(plane, out_width, out_height);
1685                 _dispc_set_vid_color_conv(plane, cconv);
1686         }
1687
1688         _dispc_set_rotation_attrs(plane, rotation, mirror, color_mode);
1689
1690         if (plane != OMAP_DSS_VIDEO1)
1691                 _dispc_setup_global_alpha(plane, global_alpha);
1692
1693         return 0;
1694 }
1695
1696 static void _dispc_enable_plane(enum omap_plane plane, bool enable)
1697 {
1698         REG_FLD_MOD(dispc_reg_att[plane], enable ? 1 : 0, 0, 0);
1699 }
1700
1701 static void dispc_disable_isr(void *data, u32 mask)
1702 {
1703         struct completion *compl = data;
1704         complete(compl);
1705 }
1706
1707 static void _enable_lcd_out(bool enable)
1708 {
1709         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
1710 }
1711
1712 static void dispc_enable_lcd_out(bool enable)
1713 {
1714         struct completion frame_done_completion;
1715         bool is_on;
1716         int r;
1717
1718         enable_clocks(1);
1719
1720         /* When we disable LCD output, we need to wait until frame is done.
1721          * Otherwise the DSS is still working, and turning off the clocks
1722          * prevents DSS from going to OFF mode */
1723         is_on = REG_GET(DISPC_CONTROL, 0, 0);
1724
1725         if (!enable && is_on) {
1726                 init_completion(&frame_done_completion);
1727
1728                 r = omap_dispc_register_isr(dispc_disable_isr,
1729                                 &frame_done_completion,
1730                                 DISPC_IRQ_FRAMEDONE);
1731
1732                 if (r)
1733                         DSSERR("failed to register FRAMEDONE isr\n");
1734         }
1735
1736         _enable_lcd_out(enable);
1737
1738         if (!enable && is_on) {
1739                 if (!wait_for_completion_timeout(&frame_done_completion,
1740                                         msecs_to_jiffies(100)))
1741                         DSSERR("timeout waiting for FRAME DONE\n");
1742
1743                 r = omap_dispc_unregister_isr(dispc_disable_isr,
1744                                 &frame_done_completion,
1745                                 DISPC_IRQ_FRAMEDONE);
1746
1747                 if (r)
1748                         DSSERR("failed to unregister FRAMEDONE isr\n");
1749         }
1750
1751         enable_clocks(0);
1752 }
1753
1754 static void _enable_digit_out(bool enable)
1755 {
1756         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
1757 }
1758
1759 static void dispc_enable_digit_out(bool enable)
1760 {
1761         struct completion frame_done_completion;
1762         int r;
1763
1764         enable_clocks(1);
1765
1766         if (REG_GET(DISPC_CONTROL, 1, 1) == enable) {
1767                 enable_clocks(0);
1768                 return;
1769         }
1770
1771         if (enable) {
1772                 unsigned long flags;
1773                 /* When we enable digit output, we'll get an extra digit
1774                  * sync lost interrupt, that we need to ignore */
1775                 spin_lock_irqsave(&dispc.irq_lock, flags);
1776                 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
1777                 _omap_dispc_set_irqs();
1778                 spin_unlock_irqrestore(&dispc.irq_lock, flags);
1779         }
1780
1781         /* When we disable digit output, we need to wait until fields are done.
1782          * Otherwise the DSS is still working, and turning off the clocks
1783          * prevents DSS from going to OFF mode. And when enabling, we need to
1784          * wait for the extra sync losts */
1785         init_completion(&frame_done_completion);
1786
1787         r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
1788                         DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1789         if (r)
1790                 DSSERR("failed to register EVSYNC isr\n");
1791
1792         _enable_digit_out(enable);
1793
1794         /* XXX I understand from TRM that we should only wait for the
1795          * current field to complete. But it seems we have to wait
1796          * for both fields */
1797         if (!wait_for_completion_timeout(&frame_done_completion,
1798                                 msecs_to_jiffies(100)))
1799                 DSSERR("timeout waiting for EVSYNC\n");
1800
1801         if (!wait_for_completion_timeout(&frame_done_completion,
1802                                 msecs_to_jiffies(100)))
1803                 DSSERR("timeout waiting for EVSYNC\n");
1804
1805         r = omap_dispc_unregister_isr(dispc_disable_isr,
1806                         &frame_done_completion,
1807                         DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1808         if (r)
1809                 DSSERR("failed to unregister EVSYNC isr\n");
1810
1811         if (enable) {
1812                 unsigned long flags;
1813                 spin_lock_irqsave(&dispc.irq_lock, flags);
1814                 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
1815                 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
1816                 _omap_dispc_set_irqs();
1817                 spin_unlock_irqrestore(&dispc.irq_lock, flags);
1818         }
1819
1820         enable_clocks(0);
1821 }
1822
1823 bool dispc_is_channel_enabled(enum omap_channel channel)
1824 {
1825         if (channel == OMAP_DSS_CHANNEL_LCD)
1826                 return !!REG_GET(DISPC_CONTROL, 0, 0);
1827         else if (channel == OMAP_DSS_CHANNEL_DIGIT)
1828                 return !!REG_GET(DISPC_CONTROL, 1, 1);
1829         else
1830                 BUG();
1831 }
1832
1833 void dispc_enable_channel(enum omap_channel channel, bool enable)
1834 {
1835         if (channel == OMAP_DSS_CHANNEL_LCD)
1836                 dispc_enable_lcd_out(enable);
1837         else if (channel == OMAP_DSS_CHANNEL_DIGIT)
1838                 dispc_enable_digit_out(enable);
1839         else
1840                 BUG();
1841 }
1842
1843 void dispc_lcd_enable_signal_polarity(bool act_high)
1844 {
1845         enable_clocks(1);
1846         REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
1847         enable_clocks(0);
1848 }
1849
1850 void dispc_lcd_enable_signal(bool enable)
1851 {
1852         enable_clocks(1);
1853         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
1854         enable_clocks(0);
1855 }
1856
1857 void dispc_pck_free_enable(bool enable)
1858 {
1859         enable_clocks(1);
1860         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
1861         enable_clocks(0);
1862 }
1863
1864 void dispc_enable_fifohandcheck(bool enable)
1865 {
1866         enable_clocks(1);
1867         REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
1868         enable_clocks(0);
1869 }
1870
1871
1872 void dispc_set_lcd_display_type(enum omap_lcd_display_type type)
1873 {
1874         int mode;
1875
1876         switch (type) {
1877         case OMAP_DSS_LCD_DISPLAY_STN:
1878                 mode = 0;
1879                 break;
1880
1881         case OMAP_DSS_LCD_DISPLAY_TFT:
1882                 mode = 1;
1883                 break;
1884
1885         default:
1886                 BUG();
1887                 return;
1888         }
1889
1890         enable_clocks(1);
1891         REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
1892         enable_clocks(0);
1893 }
1894
1895 void dispc_set_loadmode(enum omap_dss_load_mode mode)
1896 {
1897         enable_clocks(1);
1898         REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
1899         enable_clocks(0);
1900 }
1901
1902
1903 void dispc_set_default_color(enum omap_channel channel, u32 color)
1904 {
1905         const struct dispc_reg def_reg[] = { DISPC_DEFAULT_COLOR0,
1906                                 DISPC_DEFAULT_COLOR1 };
1907
1908         enable_clocks(1);
1909         dispc_write_reg(def_reg[channel], color);
1910         enable_clocks(0);
1911 }
1912
1913 u32 dispc_get_default_color(enum omap_channel channel)
1914 {
1915         const struct dispc_reg def_reg[] = { DISPC_DEFAULT_COLOR0,
1916                                 DISPC_DEFAULT_COLOR1 };
1917         u32 l;
1918
1919         BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT &&
1920                channel != OMAP_DSS_CHANNEL_LCD);
1921
1922         enable_clocks(1);
1923         l = dispc_read_reg(def_reg[channel]);
1924         enable_clocks(0);
1925
1926         return l;
1927 }
1928
1929 void dispc_set_trans_key(enum omap_channel ch,
1930                 enum omap_dss_trans_key_type type,
1931                 u32 trans_key)
1932 {
1933         const struct dispc_reg tr_reg[] = {
1934                 DISPC_TRANS_COLOR0, DISPC_TRANS_COLOR1 };
1935
1936         enable_clocks(1);
1937         if (ch == OMAP_DSS_CHANNEL_LCD)
1938                 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
1939         else /* OMAP_DSS_CHANNEL_DIGIT */
1940                 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
1941
1942         dispc_write_reg(tr_reg[ch], trans_key);
1943         enable_clocks(0);
1944 }
1945
1946 void dispc_get_trans_key(enum omap_channel ch,
1947                 enum omap_dss_trans_key_type *type,
1948                 u32 *trans_key)
1949 {
1950         const struct dispc_reg tr_reg[] = {
1951                 DISPC_TRANS_COLOR0, DISPC_TRANS_COLOR1 };
1952
1953         enable_clocks(1);
1954         if (type) {
1955                 if (ch == OMAP_DSS_CHANNEL_LCD)
1956                         *type = REG_GET(DISPC_CONFIG, 11, 11);
1957                 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
1958                         *type = REG_GET(DISPC_CONFIG, 13, 13);
1959                 else
1960                         BUG();
1961         }
1962
1963         if (trans_key)
1964                 *trans_key = dispc_read_reg(tr_reg[ch]);
1965         enable_clocks(0);
1966 }
1967
1968 void dispc_enable_trans_key(enum omap_channel ch, bool enable)
1969 {
1970         enable_clocks(1);
1971         if (ch == OMAP_DSS_CHANNEL_LCD)
1972                 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
1973         else /* OMAP_DSS_CHANNEL_DIGIT */
1974                 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
1975         enable_clocks(0);
1976 }
1977 void dispc_enable_alpha_blending(enum omap_channel ch, bool enable)
1978 {
1979         if (cpu_is_omap24xx())
1980                 return;
1981
1982         enable_clocks(1);
1983         if (ch == OMAP_DSS_CHANNEL_LCD)
1984                 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
1985         else /* OMAP_DSS_CHANNEL_DIGIT */
1986                 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
1987         enable_clocks(0);
1988 }
1989 bool dispc_alpha_blending_enabled(enum omap_channel ch)
1990 {
1991         bool enabled;
1992
1993         if (cpu_is_omap24xx())
1994                 return false;
1995
1996         enable_clocks(1);
1997         if (ch == OMAP_DSS_CHANNEL_LCD)
1998                 enabled = REG_GET(DISPC_CONFIG, 18, 18);
1999         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2000                 enabled = REG_GET(DISPC_CONFIG, 18, 18);
2001         else
2002                 BUG();
2003         enable_clocks(0);
2004
2005         return enabled;
2006
2007 }
2008
2009
2010 bool dispc_trans_key_enabled(enum omap_channel ch)
2011 {
2012         bool enabled;
2013
2014         enable_clocks(1);
2015         if (ch == OMAP_DSS_CHANNEL_LCD)
2016                 enabled = REG_GET(DISPC_CONFIG, 10, 10);
2017         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2018                 enabled = REG_GET(DISPC_CONFIG, 12, 12);
2019         else
2020                 BUG();
2021         enable_clocks(0);
2022
2023         return enabled;
2024 }
2025
2026
2027 void dispc_set_tft_data_lines(u8 data_lines)
2028 {
2029         int code;
2030
2031         switch (data_lines) {
2032         case 12:
2033                 code = 0;
2034                 break;
2035         case 16:
2036                 code = 1;
2037                 break;
2038         case 18:
2039                 code = 2;
2040                 break;
2041         case 24:
2042                 code = 3;
2043                 break;
2044         default:
2045                 BUG();
2046                 return;
2047         }
2048
2049         enable_clocks(1);
2050         REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
2051         enable_clocks(0);
2052 }
2053
2054 void dispc_set_parallel_interface_mode(enum omap_parallel_interface_mode mode)
2055 {
2056         u32 l;
2057         int stallmode;
2058         int gpout0 = 1;
2059         int gpout1;
2060
2061         switch (mode) {
2062         case OMAP_DSS_PARALLELMODE_BYPASS:
2063                 stallmode = 0;
2064                 gpout1 = 1;
2065                 break;
2066
2067         case OMAP_DSS_PARALLELMODE_RFBI:
2068                 stallmode = 1;
2069                 gpout1 = 0;
2070                 break;
2071
2072         case OMAP_DSS_PARALLELMODE_DSI:
2073                 stallmode = 1;
2074                 gpout1 = 1;
2075                 break;
2076
2077         default:
2078                 BUG();
2079                 return;
2080         }
2081
2082         enable_clocks(1);
2083
2084         l = dispc_read_reg(DISPC_CONTROL);
2085
2086         l = FLD_MOD(l, stallmode, 11, 11);
2087         l = FLD_MOD(l, gpout0, 15, 15);
2088         l = FLD_MOD(l, gpout1, 16, 16);
2089
2090         dispc_write_reg(DISPC_CONTROL, l);
2091
2092         enable_clocks(0);
2093 }
2094
2095 static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2096                 int vsw, int vfp, int vbp)
2097 {
2098         if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2099                 if (hsw < 1 || hsw > 64 ||
2100                                 hfp < 1 || hfp > 256 ||
2101                                 hbp < 1 || hbp > 256 ||
2102                                 vsw < 1 || vsw > 64 ||
2103                                 vfp < 0 || vfp > 255 ||
2104                                 vbp < 0 || vbp > 255)
2105                         return false;
2106         } else {
2107                 if (hsw < 1 || hsw > 256 ||
2108                                 hfp < 1 || hfp > 4096 ||
2109                                 hbp < 1 || hbp > 4096 ||
2110                                 vsw < 1 || vsw > 256 ||
2111                                 vfp < 0 || vfp > 4095 ||
2112                                 vbp < 0 || vbp > 4095)
2113                         return false;
2114         }
2115
2116         return true;
2117 }
2118
2119 bool dispc_lcd_timings_ok(struct omap_video_timings *timings)
2120 {
2121         return _dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2122                         timings->hbp, timings->vsw,
2123                         timings->vfp, timings->vbp);
2124 }
2125
2126 static void _dispc_set_lcd_timings(int hsw, int hfp, int hbp,
2127                                    int vsw, int vfp, int vbp)
2128 {
2129         u32 timing_h, timing_v;
2130
2131         if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2132                 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
2133                         FLD_VAL(hbp-1, 27, 20);
2134
2135                 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
2136                         FLD_VAL(vbp, 27, 20);
2137         } else {
2138                 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
2139                         FLD_VAL(hbp-1, 31, 20);
2140
2141                 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
2142                         FLD_VAL(vbp, 31, 20);
2143         }
2144
2145         enable_clocks(1);
2146         dispc_write_reg(DISPC_TIMING_H, timing_h);
2147         dispc_write_reg(DISPC_TIMING_V, timing_v);
2148         enable_clocks(0);
2149 }
2150
2151 /* change name to mode? */
2152 void dispc_set_lcd_timings(struct omap_video_timings *timings)
2153 {
2154         unsigned xtot, ytot;
2155         unsigned long ht, vt;
2156
2157         if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2158                                 timings->hbp, timings->vsw,
2159                                 timings->vfp, timings->vbp))
2160                 BUG();
2161
2162         _dispc_set_lcd_timings(timings->hsw, timings->hfp, timings->hbp,
2163                         timings->vsw, timings->vfp, timings->vbp);
2164
2165         dispc_set_lcd_size(timings->x_res, timings->y_res);
2166
2167         xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
2168         ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
2169
2170         ht = (timings->pixel_clock * 1000) / xtot;
2171         vt = (timings->pixel_clock * 1000) / xtot / ytot;
2172
2173         DSSDBG("xres %u yres %u\n", timings->x_res, timings->y_res);
2174         DSSDBG("pck %u\n", timings->pixel_clock);
2175         DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2176                         timings->hsw, timings->hfp, timings->hbp,
2177                         timings->vsw, timings->vfp, timings->vbp);
2178
2179         DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2180 }
2181
2182 static void dispc_set_lcd_divisor(u16 lck_div, u16 pck_div)
2183 {
2184         BUG_ON(lck_div < 1);
2185         BUG_ON(pck_div < 2);
2186
2187         enable_clocks(1);
2188         dispc_write_reg(DISPC_DIVISOR,
2189                         FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
2190         enable_clocks(0);
2191 }
2192
2193 static void dispc_get_lcd_divisor(int *lck_div, int *pck_div)
2194 {
2195         u32 l;
2196         l = dispc_read_reg(DISPC_DIVISOR);
2197         *lck_div = FLD_GET(l, 23, 16);
2198         *pck_div = FLD_GET(l, 7, 0);
2199 }
2200
2201 unsigned long dispc_fclk_rate(void)
2202 {
2203         unsigned long r = 0;
2204
2205         if (dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK)
2206                 r = dss_clk_get_rate(DSS_CLK_FCK1);
2207         else
2208 #ifdef CONFIG_OMAP2_DSS_DSI
2209                 r = dsi_get_dsi1_pll_rate();
2210 #else
2211         BUG();
2212 #endif
2213         return r;
2214 }
2215
2216 unsigned long dispc_lclk_rate(void)
2217 {
2218         int lcd;
2219         unsigned long r;
2220         u32 l;
2221
2222         l = dispc_read_reg(DISPC_DIVISOR);
2223
2224         lcd = FLD_GET(l, 23, 16);
2225
2226         r = dispc_fclk_rate();
2227
2228         return r / lcd;
2229 }
2230
2231 unsigned long dispc_pclk_rate(void)
2232 {
2233         int lcd, pcd;
2234         unsigned long r;
2235         u32 l;
2236
2237         l = dispc_read_reg(DISPC_DIVISOR);
2238
2239         lcd = FLD_GET(l, 23, 16);
2240         pcd = FLD_GET(l, 7, 0);
2241
2242         r = dispc_fclk_rate();
2243
2244         return r / lcd / pcd;
2245 }
2246
2247 void dispc_dump_clocks(struct seq_file *s)
2248 {
2249         int lcd, pcd;
2250
2251         enable_clocks(1);
2252
2253         dispc_get_lcd_divisor(&lcd, &pcd);
2254
2255         seq_printf(s, "- DISPC -\n");
2256
2257         seq_printf(s, "dispc fclk source = %s\n",
2258                         dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ?
2259                         "dss1_alwon_fclk" : "dsi1_pll_fclk");
2260
2261         seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2262         seq_printf(s, "lck\t\t%-16lulck div\t%u\n", dispc_lclk_rate(), lcd);
2263         seq_printf(s, "pck\t\t%-16lupck div\t%u\n", dispc_pclk_rate(), pcd);
2264
2265         enable_clocks(0);
2266 }
2267
2268 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2269 void dispc_dump_irqs(struct seq_file *s)
2270 {
2271         unsigned long flags;
2272         struct dispc_irq_stats stats;
2273
2274         spin_lock_irqsave(&dispc.irq_stats_lock, flags);
2275
2276         stats = dispc.irq_stats;
2277         memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
2278         dispc.irq_stats.last_reset = jiffies;
2279
2280         spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
2281
2282         seq_printf(s, "period %u ms\n",
2283                         jiffies_to_msecs(jiffies - stats.last_reset));
2284
2285         seq_printf(s, "irqs %d\n", stats.irq_count);
2286 #define PIS(x) \
2287         seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
2288
2289         PIS(FRAMEDONE);
2290         PIS(VSYNC);
2291         PIS(EVSYNC_EVEN);
2292         PIS(EVSYNC_ODD);
2293         PIS(ACBIAS_COUNT_STAT);
2294         PIS(PROG_LINE_NUM);
2295         PIS(GFX_FIFO_UNDERFLOW);
2296         PIS(GFX_END_WIN);
2297         PIS(PAL_GAMMA_MASK);
2298         PIS(OCP_ERR);
2299         PIS(VID1_FIFO_UNDERFLOW);
2300         PIS(VID1_END_WIN);
2301         PIS(VID2_FIFO_UNDERFLOW);
2302         PIS(VID2_END_WIN);
2303         PIS(SYNC_LOST);
2304         PIS(SYNC_LOST_DIGIT);
2305         PIS(WAKEUP);
2306 #undef PIS
2307 }
2308 #endif
2309
2310 void dispc_dump_regs(struct seq_file *s)
2311 {
2312 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dispc_read_reg(r))
2313
2314         dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
2315
2316         DUMPREG(DISPC_REVISION);
2317         DUMPREG(DISPC_SYSCONFIG);
2318         DUMPREG(DISPC_SYSSTATUS);
2319         DUMPREG(DISPC_IRQSTATUS);
2320         DUMPREG(DISPC_IRQENABLE);
2321         DUMPREG(DISPC_CONTROL);
2322         DUMPREG(DISPC_CONFIG);
2323         DUMPREG(DISPC_CAPABLE);
2324         DUMPREG(DISPC_DEFAULT_COLOR0);
2325         DUMPREG(DISPC_DEFAULT_COLOR1);
2326         DUMPREG(DISPC_TRANS_COLOR0);
2327         DUMPREG(DISPC_TRANS_COLOR1);
2328         DUMPREG(DISPC_LINE_STATUS);
2329         DUMPREG(DISPC_LINE_NUMBER);
2330         DUMPREG(DISPC_TIMING_H);
2331         DUMPREG(DISPC_TIMING_V);
2332         DUMPREG(DISPC_POL_FREQ);
2333         DUMPREG(DISPC_DIVISOR);
2334         DUMPREG(DISPC_GLOBAL_ALPHA);
2335         DUMPREG(DISPC_SIZE_DIG);
2336         DUMPREG(DISPC_SIZE_LCD);
2337
2338         DUMPREG(DISPC_GFX_BA0);
2339         DUMPREG(DISPC_GFX_BA1);
2340         DUMPREG(DISPC_GFX_POSITION);
2341         DUMPREG(DISPC_GFX_SIZE);
2342         DUMPREG(DISPC_GFX_ATTRIBUTES);
2343         DUMPREG(DISPC_GFX_FIFO_THRESHOLD);
2344         DUMPREG(DISPC_GFX_FIFO_SIZE_STATUS);
2345         DUMPREG(DISPC_GFX_ROW_INC);
2346         DUMPREG(DISPC_GFX_PIXEL_INC);
2347         DUMPREG(DISPC_GFX_WINDOW_SKIP);
2348         DUMPREG(DISPC_GFX_TABLE_BA);
2349
2350         DUMPREG(DISPC_DATA_CYCLE1);
2351         DUMPREG(DISPC_DATA_CYCLE2);
2352         DUMPREG(DISPC_DATA_CYCLE3);
2353
2354         DUMPREG(DISPC_CPR_COEF_R);
2355         DUMPREG(DISPC_CPR_COEF_G);
2356         DUMPREG(DISPC_CPR_COEF_B);
2357
2358         DUMPREG(DISPC_GFX_PRELOAD);
2359
2360         DUMPREG(DISPC_VID_BA0(0));
2361         DUMPREG(DISPC_VID_BA1(0));
2362         DUMPREG(DISPC_VID_POSITION(0));
2363         DUMPREG(DISPC_VID_SIZE(0));
2364         DUMPREG(DISPC_VID_ATTRIBUTES(0));
2365         DUMPREG(DISPC_VID_FIFO_THRESHOLD(0));
2366         DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(0));
2367         DUMPREG(DISPC_VID_ROW_INC(0));
2368         DUMPREG(DISPC_VID_PIXEL_INC(0));
2369         DUMPREG(DISPC_VID_FIR(0));
2370         DUMPREG(DISPC_VID_PICTURE_SIZE(0));
2371         DUMPREG(DISPC_VID_ACCU0(0));
2372         DUMPREG(DISPC_VID_ACCU1(0));
2373
2374         DUMPREG(DISPC_VID_BA0(1));
2375         DUMPREG(DISPC_VID_BA1(1));
2376         DUMPREG(DISPC_VID_POSITION(1));
2377         DUMPREG(DISPC_VID_SIZE(1));
2378         DUMPREG(DISPC_VID_ATTRIBUTES(1));
2379         DUMPREG(DISPC_VID_FIFO_THRESHOLD(1));
2380         DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(1));
2381         DUMPREG(DISPC_VID_ROW_INC(1));
2382         DUMPREG(DISPC_VID_PIXEL_INC(1));
2383         DUMPREG(DISPC_VID_FIR(1));
2384         DUMPREG(DISPC_VID_PICTURE_SIZE(1));
2385         DUMPREG(DISPC_VID_ACCU0(1));
2386         DUMPREG(DISPC_VID_ACCU1(1));
2387
2388         DUMPREG(DISPC_VID_FIR_COEF_H(0, 0));
2389         DUMPREG(DISPC_VID_FIR_COEF_H(0, 1));
2390         DUMPREG(DISPC_VID_FIR_COEF_H(0, 2));
2391         DUMPREG(DISPC_VID_FIR_COEF_H(0, 3));
2392         DUMPREG(DISPC_VID_FIR_COEF_H(0, 4));
2393         DUMPREG(DISPC_VID_FIR_COEF_H(0, 5));
2394         DUMPREG(DISPC_VID_FIR_COEF_H(0, 6));
2395         DUMPREG(DISPC_VID_FIR_COEF_H(0, 7));
2396         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 0));
2397         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 1));
2398         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 2));
2399         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 3));
2400         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 4));
2401         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 5));
2402         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 6));
2403         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 7));
2404         DUMPREG(DISPC_VID_CONV_COEF(0, 0));
2405         DUMPREG(DISPC_VID_CONV_COEF(0, 1));
2406         DUMPREG(DISPC_VID_CONV_COEF(0, 2));
2407         DUMPREG(DISPC_VID_CONV_COEF(0, 3));
2408         DUMPREG(DISPC_VID_CONV_COEF(0, 4));
2409         DUMPREG(DISPC_VID_FIR_COEF_V(0, 0));
2410         DUMPREG(DISPC_VID_FIR_COEF_V(0, 1));
2411         DUMPREG(DISPC_VID_FIR_COEF_V(0, 2));
2412         DUMPREG(DISPC_VID_FIR_COEF_V(0, 3));
2413         DUMPREG(DISPC_VID_FIR_COEF_V(0, 4));
2414         DUMPREG(DISPC_VID_FIR_COEF_V(0, 5));
2415         DUMPREG(DISPC_VID_FIR_COEF_V(0, 6));
2416         DUMPREG(DISPC_VID_FIR_COEF_V(0, 7));
2417
2418         DUMPREG(DISPC_VID_FIR_COEF_H(1, 0));
2419         DUMPREG(DISPC_VID_FIR_COEF_H(1, 1));
2420         DUMPREG(DISPC_VID_FIR_COEF_H(1, 2));
2421         DUMPREG(DISPC_VID_FIR_COEF_H(1, 3));
2422         DUMPREG(DISPC_VID_FIR_COEF_H(1, 4));
2423         DUMPREG(DISPC_VID_FIR_COEF_H(1, 5));
2424         DUMPREG(DISPC_VID_FIR_COEF_H(1, 6));
2425         DUMPREG(DISPC_VID_FIR_COEF_H(1, 7));
2426         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 0));
2427         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 1));
2428         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 2));
2429         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 3));
2430         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 4));
2431         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 5));
2432         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 6));
2433         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 7));
2434         DUMPREG(DISPC_VID_CONV_COEF(1, 0));
2435         DUMPREG(DISPC_VID_CONV_COEF(1, 1));
2436         DUMPREG(DISPC_VID_CONV_COEF(1, 2));
2437         DUMPREG(DISPC_VID_CONV_COEF(1, 3));
2438         DUMPREG(DISPC_VID_CONV_COEF(1, 4));
2439         DUMPREG(DISPC_VID_FIR_COEF_V(1, 0));
2440         DUMPREG(DISPC_VID_FIR_COEF_V(1, 1));
2441         DUMPREG(DISPC_VID_FIR_COEF_V(1, 2));
2442         DUMPREG(DISPC_VID_FIR_COEF_V(1, 3));
2443         DUMPREG(DISPC_VID_FIR_COEF_V(1, 4));
2444         DUMPREG(DISPC_VID_FIR_COEF_V(1, 5));
2445         DUMPREG(DISPC_VID_FIR_COEF_V(1, 6));
2446         DUMPREG(DISPC_VID_FIR_COEF_V(1, 7));
2447
2448         DUMPREG(DISPC_VID_PRELOAD(0));
2449         DUMPREG(DISPC_VID_PRELOAD(1));
2450
2451         dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
2452 #undef DUMPREG
2453 }
2454
2455 static void _dispc_set_pol_freq(bool onoff, bool rf, bool ieo, bool ipc,
2456                                 bool ihs, bool ivs, u8 acbi, u8 acb)
2457 {
2458         u32 l = 0;
2459
2460         DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
2461                         onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
2462
2463         l |= FLD_VAL(onoff, 17, 17);
2464         l |= FLD_VAL(rf, 16, 16);
2465         l |= FLD_VAL(ieo, 15, 15);
2466         l |= FLD_VAL(ipc, 14, 14);
2467         l |= FLD_VAL(ihs, 13, 13);
2468         l |= FLD_VAL(ivs, 12, 12);
2469         l |= FLD_VAL(acbi, 11, 8);
2470         l |= FLD_VAL(acb, 7, 0);
2471
2472         enable_clocks(1);
2473         dispc_write_reg(DISPC_POL_FREQ, l);
2474         enable_clocks(0);
2475 }
2476
2477 void dispc_set_pol_freq(enum omap_panel_config config, u8 acbi, u8 acb)
2478 {
2479         _dispc_set_pol_freq((config & OMAP_DSS_LCD_ONOFF) != 0,
2480                         (config & OMAP_DSS_LCD_RF) != 0,
2481                         (config & OMAP_DSS_LCD_IEO) != 0,
2482                         (config & OMAP_DSS_LCD_IPC) != 0,
2483                         (config & OMAP_DSS_LCD_IHS) != 0,
2484                         (config & OMAP_DSS_LCD_IVS) != 0,
2485                         acbi, acb);
2486 }
2487
2488 /* with fck as input clock rate, find dispc dividers that produce req_pck */
2489 void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
2490                 struct dispc_clock_info *cinfo)
2491 {
2492         u16 pcd_min = is_tft ? 2 : 3;
2493         unsigned long best_pck;
2494         u16 best_ld, cur_ld;
2495         u16 best_pd, cur_pd;
2496
2497         best_pck = 0;
2498         best_ld = 0;
2499         best_pd = 0;
2500
2501         for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
2502                 unsigned long lck = fck / cur_ld;
2503
2504                 for (cur_pd = pcd_min; cur_pd <= 255; ++cur_pd) {
2505                         unsigned long pck = lck / cur_pd;
2506                         long old_delta = abs(best_pck - req_pck);
2507                         long new_delta = abs(pck - req_pck);
2508
2509                         if (best_pck == 0 || new_delta < old_delta) {
2510                                 best_pck = pck;
2511                                 best_ld = cur_ld;
2512                                 best_pd = cur_pd;
2513
2514                                 if (pck == req_pck)
2515                                         goto found;
2516                         }
2517
2518                         if (pck < req_pck)
2519                                 break;
2520                 }
2521
2522                 if (lck / pcd_min < req_pck)
2523                         break;
2524         }
2525
2526 found:
2527         cinfo->lck_div = best_ld;
2528         cinfo->pck_div = best_pd;
2529         cinfo->lck = fck / cinfo->lck_div;
2530         cinfo->pck = cinfo->lck / cinfo->pck_div;
2531 }
2532
2533 /* calculate clock rates using dividers in cinfo */
2534 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
2535                 struct dispc_clock_info *cinfo)
2536 {
2537         if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
2538                 return -EINVAL;
2539         if (cinfo->pck_div < 2 || cinfo->pck_div > 255)
2540                 return -EINVAL;
2541
2542         cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
2543         cinfo->pck = cinfo->lck / cinfo->pck_div;
2544
2545         return 0;
2546 }
2547
2548 int dispc_set_clock_div(struct dispc_clock_info *cinfo)
2549 {
2550         DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
2551         DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
2552
2553         dispc_set_lcd_divisor(cinfo->lck_div, cinfo->pck_div);
2554
2555         return 0;
2556 }
2557
2558 int dispc_get_clock_div(struct dispc_clock_info *cinfo)
2559 {
2560         unsigned long fck;
2561
2562         fck = dispc_fclk_rate();
2563
2564         cinfo->lck_div = REG_GET(DISPC_DIVISOR, 23, 16);
2565         cinfo->pck_div = REG_GET(DISPC_DIVISOR, 7, 0);
2566
2567         cinfo->lck = fck / cinfo->lck_div;
2568         cinfo->pck = cinfo->lck / cinfo->pck_div;
2569
2570         return 0;
2571 }
2572
2573 /* dispc.irq_lock has to be locked by the caller */
2574 static void _omap_dispc_set_irqs(void)
2575 {
2576         u32 mask;
2577         u32 old_mask;
2578         int i;
2579         struct omap_dispc_isr_data *isr_data;
2580
2581         mask = dispc.irq_error_mask;
2582
2583         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2584                 isr_data = &dispc.registered_isr[i];
2585
2586                 if (isr_data->isr == NULL)
2587                         continue;
2588
2589                 mask |= isr_data->mask;
2590         }
2591
2592         enable_clocks(1);
2593
2594         old_mask = dispc_read_reg(DISPC_IRQENABLE);
2595         /* clear the irqstatus for newly enabled irqs */
2596         dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
2597
2598         dispc_write_reg(DISPC_IRQENABLE, mask);
2599
2600         enable_clocks(0);
2601 }
2602
2603 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2604 {
2605         int i;
2606         int ret;
2607         unsigned long flags;
2608         struct omap_dispc_isr_data *isr_data;
2609
2610         if (isr == NULL)
2611                 return -EINVAL;
2612
2613         spin_lock_irqsave(&dispc.irq_lock, flags);
2614
2615         /* check for duplicate entry */
2616         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2617                 isr_data = &dispc.registered_isr[i];
2618                 if (isr_data->isr == isr && isr_data->arg == arg &&
2619                                 isr_data->mask == mask) {
2620                         ret = -EINVAL;
2621                         goto err;
2622                 }
2623         }
2624
2625         isr_data = NULL;
2626         ret = -EBUSY;
2627
2628         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2629                 isr_data = &dispc.registered_isr[i];
2630
2631                 if (isr_data->isr != NULL)
2632                         continue;
2633
2634                 isr_data->isr = isr;
2635                 isr_data->arg = arg;
2636                 isr_data->mask = mask;
2637                 ret = 0;
2638
2639                 break;
2640         }
2641
2642         _omap_dispc_set_irqs();
2643
2644         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2645
2646         return 0;
2647 err:
2648         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2649
2650         return ret;
2651 }
2652 EXPORT_SYMBOL(omap_dispc_register_isr);
2653
2654 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2655 {
2656         int i;
2657         unsigned long flags;
2658         int ret = -EINVAL;
2659         struct omap_dispc_isr_data *isr_data;
2660
2661         spin_lock_irqsave(&dispc.irq_lock, flags);
2662
2663         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2664                 isr_data = &dispc.registered_isr[i];
2665                 if (isr_data->isr != isr || isr_data->arg != arg ||
2666                                 isr_data->mask != mask)
2667                         continue;
2668
2669                 /* found the correct isr */
2670
2671                 isr_data->isr = NULL;
2672                 isr_data->arg = NULL;
2673                 isr_data->mask = 0;
2674
2675                 ret = 0;
2676                 break;
2677         }
2678
2679         if (ret == 0)
2680                 _omap_dispc_set_irqs();
2681
2682         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2683
2684         return ret;
2685 }
2686 EXPORT_SYMBOL(omap_dispc_unregister_isr);
2687
2688 #ifdef DEBUG
2689 static void print_irq_status(u32 status)
2690 {
2691         if ((status & dispc.irq_error_mask) == 0)
2692                 return;
2693
2694         printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
2695
2696 #define PIS(x) \
2697         if (status & DISPC_IRQ_##x) \
2698                 printk(#x " ");
2699         PIS(GFX_FIFO_UNDERFLOW);
2700         PIS(OCP_ERR);
2701         PIS(VID1_FIFO_UNDERFLOW);
2702         PIS(VID2_FIFO_UNDERFLOW);
2703         PIS(SYNC_LOST);
2704         PIS(SYNC_LOST_DIGIT);
2705 #undef PIS
2706
2707         printk("\n");
2708 }
2709 #endif
2710
2711 /* Called from dss.c. Note that we don't touch clocks here,
2712  * but we presume they are on because we got an IRQ. However,
2713  * an irq handler may turn the clocks off, so we may not have
2714  * clock later in the function. */
2715 void dispc_irq_handler(void)
2716 {
2717         int i;
2718         u32 irqstatus;
2719         u32 handledirqs = 0;
2720         u32 unhandled_errors;
2721         struct omap_dispc_isr_data *isr_data;
2722         struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
2723
2724         spin_lock(&dispc.irq_lock);
2725
2726         irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
2727
2728 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2729         spin_lock(&dispc.irq_stats_lock);
2730         dispc.irq_stats.irq_count++;
2731         dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
2732         spin_unlock(&dispc.irq_stats_lock);
2733 #endif
2734
2735 #ifdef DEBUG
2736         if (dss_debug)
2737                 print_irq_status(irqstatus);
2738 #endif
2739         /* Ack the interrupt. Do it here before clocks are possibly turned
2740          * off */
2741         dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
2742         /* flush posted write */
2743         dispc_read_reg(DISPC_IRQSTATUS);
2744
2745         /* make a copy and unlock, so that isrs can unregister
2746          * themselves */
2747         memcpy(registered_isr, dispc.registered_isr,
2748                         sizeof(registered_isr));
2749
2750         spin_unlock(&dispc.irq_lock);
2751
2752         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2753                 isr_data = &registered_isr[i];
2754
2755                 if (!isr_data->isr)
2756                         continue;
2757
2758                 if (isr_data->mask & irqstatus) {
2759                         isr_data->isr(isr_data->arg, irqstatus);
2760                         handledirqs |= isr_data->mask;
2761                 }
2762         }
2763
2764         spin_lock(&dispc.irq_lock);
2765
2766         unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
2767
2768         if (unhandled_errors) {
2769                 dispc.error_irqs |= unhandled_errors;
2770
2771                 dispc.irq_error_mask &= ~unhandled_errors;
2772                 _omap_dispc_set_irqs();
2773
2774                 schedule_work(&dispc.error_work);
2775         }
2776
2777         spin_unlock(&dispc.irq_lock);
2778 }
2779
2780 static void dispc_error_worker(struct work_struct *work)
2781 {
2782         int i;
2783         u32 errors;
2784         unsigned long flags;
2785
2786         spin_lock_irqsave(&dispc.irq_lock, flags);
2787         errors = dispc.error_irqs;
2788         dispc.error_irqs = 0;
2789         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2790
2791         if (errors & DISPC_IRQ_GFX_FIFO_UNDERFLOW) {
2792                 DSSERR("GFX_FIFO_UNDERFLOW, disabling GFX\n");
2793                 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2794                         struct omap_overlay *ovl;
2795                         ovl = omap_dss_get_overlay(i);
2796
2797                         if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2798                                 continue;
2799
2800                         if (ovl->id == 0) {
2801                                 dispc_enable_plane(ovl->id, 0);
2802                                 dispc_go(ovl->manager->id);
2803                                 mdelay(50);
2804                                 break;
2805                         }
2806                 }
2807         }
2808
2809         if (errors & DISPC_IRQ_VID1_FIFO_UNDERFLOW) {
2810                 DSSERR("VID1_FIFO_UNDERFLOW, disabling VID1\n");
2811                 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2812                         struct omap_overlay *ovl;
2813                         ovl = omap_dss_get_overlay(i);
2814
2815                         if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2816                                 continue;
2817
2818                         if (ovl->id == 1) {
2819                                 dispc_enable_plane(ovl->id, 0);
2820                                 dispc_go(ovl->manager->id);
2821                                 mdelay(50);
2822                                 break;
2823                         }
2824                 }
2825         }
2826
2827         if (errors & DISPC_IRQ_VID2_FIFO_UNDERFLOW) {
2828                 DSSERR("VID2_FIFO_UNDERFLOW, disabling VID2\n");
2829                 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2830                         struct omap_overlay *ovl;
2831                         ovl = omap_dss_get_overlay(i);
2832
2833                         if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2834                                 continue;
2835
2836                         if (ovl->id == 2) {
2837                                 dispc_enable_plane(ovl->id, 0);
2838                                 dispc_go(ovl->manager->id);
2839                                 mdelay(50);
2840                                 break;
2841                         }
2842                 }
2843         }
2844
2845         if (errors & DISPC_IRQ_SYNC_LOST) {
2846                 struct omap_overlay_manager *manager = NULL;
2847                 bool enable = false;
2848
2849                 DSSERR("SYNC_LOST, disabling LCD\n");
2850
2851                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
2852                         struct omap_overlay_manager *mgr;
2853                         mgr = omap_dss_get_overlay_manager(i);
2854
2855                         if (mgr->id == OMAP_DSS_CHANNEL_LCD) {
2856                                 manager = mgr;
2857                                 enable = mgr->device->state ==
2858                                                 OMAP_DSS_DISPLAY_ACTIVE;
2859                                 mgr->device->driver->disable(mgr->device);
2860                                 break;
2861                         }
2862                 }
2863
2864                 if (manager) {
2865                         struct omap_dss_device *dssdev = manager->device;
2866                         for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2867                                 struct omap_overlay *ovl;
2868                                 ovl = omap_dss_get_overlay(i);
2869
2870                                 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2871                                         continue;
2872
2873                                 if (ovl->id != 0 && ovl->manager == manager)
2874                                         dispc_enable_plane(ovl->id, 0);
2875                         }
2876
2877                         dispc_go(manager->id);
2878                         mdelay(50);
2879                         if (enable)
2880                                 dssdev->driver->enable(dssdev);
2881                 }
2882         }
2883
2884         if (errors & DISPC_IRQ_SYNC_LOST_DIGIT) {
2885                 struct omap_overlay_manager *manager = NULL;
2886                 bool enable = false;
2887
2888                 DSSERR("SYNC_LOST_DIGIT, disabling TV\n");
2889
2890                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
2891                         struct omap_overlay_manager *mgr;
2892                         mgr = omap_dss_get_overlay_manager(i);
2893
2894                         if (mgr->id == OMAP_DSS_CHANNEL_DIGIT) {
2895                                 manager = mgr;
2896                                 enable = mgr->device->state ==
2897                                                 OMAP_DSS_DISPLAY_ACTIVE;
2898                                 mgr->device->driver->disable(mgr->device);
2899                                 break;
2900                         }
2901                 }
2902
2903                 if (manager) {
2904                         struct omap_dss_device *dssdev = manager->device;
2905                         for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2906                                 struct omap_overlay *ovl;
2907                                 ovl = omap_dss_get_overlay(i);
2908
2909                                 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2910                                         continue;
2911
2912                                 if (ovl->id != 0 && ovl->manager == manager)
2913                                         dispc_enable_plane(ovl->id, 0);
2914                         }
2915
2916                         dispc_go(manager->id);
2917                         mdelay(50);
2918                         if (enable)
2919                                 dssdev->driver->enable(dssdev);
2920                 }
2921         }
2922
2923         if (errors & DISPC_IRQ_OCP_ERR) {
2924                 DSSERR("OCP_ERR\n");
2925                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
2926                         struct omap_overlay_manager *mgr;
2927                         mgr = omap_dss_get_overlay_manager(i);
2928
2929                         if (mgr->caps & OMAP_DSS_OVL_CAP_DISPC)
2930                                 mgr->device->driver->disable(mgr->device);
2931                 }
2932         }
2933
2934         spin_lock_irqsave(&dispc.irq_lock, flags);
2935         dispc.irq_error_mask |= errors;
2936         _omap_dispc_set_irqs();
2937         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2938 }
2939
2940 int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
2941 {
2942         void dispc_irq_wait_handler(void *data, u32 mask)
2943         {
2944                 complete((struct completion *)data);
2945         }
2946
2947         int r;
2948         DECLARE_COMPLETION_ONSTACK(completion);
2949
2950         r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
2951                         irqmask);
2952
2953         if (r)
2954                 return r;
2955
2956         timeout = wait_for_completion_timeout(&completion, timeout);
2957
2958         omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
2959
2960         if (timeout == 0)
2961                 return -ETIMEDOUT;
2962
2963         if (timeout == -ERESTARTSYS)
2964                 return -ERESTARTSYS;
2965
2966         return 0;
2967 }
2968
2969 int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
2970                 unsigned long timeout)
2971 {
2972         void dispc_irq_wait_handler(void *data, u32 mask)
2973         {
2974                 complete((struct completion *)data);
2975         }
2976
2977         int r;
2978         DECLARE_COMPLETION_ONSTACK(completion);
2979
2980         r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
2981                         irqmask);
2982
2983         if (r)
2984                 return r;
2985
2986         timeout = wait_for_completion_interruptible_timeout(&completion,
2987                         timeout);
2988
2989         omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
2990
2991         if (timeout == 0)
2992                 return -ETIMEDOUT;
2993
2994         if (timeout == -ERESTARTSYS)
2995                 return -ERESTARTSYS;
2996
2997         return 0;
2998 }
2999
3000 #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
3001 void dispc_fake_vsync_irq(void)
3002 {
3003         u32 irqstatus = DISPC_IRQ_VSYNC;
3004         int i;
3005
3006         WARN_ON(!in_interrupt());
3007
3008         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3009                 struct omap_dispc_isr_data *isr_data;
3010                 isr_data = &dispc.registered_isr[i];
3011
3012                 if (!isr_data->isr)
3013                         continue;
3014
3015                 if (isr_data->mask & irqstatus)
3016                         isr_data->isr(isr_data->arg, irqstatus);
3017         }
3018 }
3019 #endif
3020
3021 static void _omap_dispc_initialize_irq(void)
3022 {
3023         unsigned long flags;
3024
3025         spin_lock_irqsave(&dispc.irq_lock, flags);
3026
3027         memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3028
3029         dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
3030
3031         /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3032          * so clear it */
3033         dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3034
3035         _omap_dispc_set_irqs();
3036
3037         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3038 }
3039
3040 void dispc_enable_sidle(void)
3041 {
3042         REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3);  /* SIDLEMODE: smart idle */
3043 }
3044
3045 void dispc_disable_sidle(void)
3046 {
3047         REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3);  /* SIDLEMODE: no idle */
3048 }
3049
3050 static void _omap_dispc_initial_config(void)
3051 {
3052         u32 l;
3053
3054         l = dispc_read_reg(DISPC_SYSCONFIG);
3055         l = FLD_MOD(l, 2, 13, 12);      /* MIDLEMODE: smart standby */
3056         l = FLD_MOD(l, 2, 4, 3);        /* SIDLEMODE: smart idle */
3057         l = FLD_MOD(l, 1, 2, 2);        /* ENWAKEUP */
3058         l = FLD_MOD(l, 1, 0, 0);        /* AUTOIDLE */
3059         dispc_write_reg(DISPC_SYSCONFIG, l);
3060
3061         /* FUNCGATED */
3062         REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
3063
3064         /* L3 firewall setting: enable access to OCM RAM */
3065         /* XXX this should be somewhere in plat-omap */
3066         if (cpu_is_omap24xx())
3067                 __raw_writel(0x402000b0, OMAP2_L3_IO_ADDRESS(0x680050a0));
3068
3069         _dispc_setup_color_conv_coef();
3070
3071         dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3072
3073         dispc_read_plane_fifo_sizes();
3074 }
3075
3076 int dispc_init(void)
3077 {
3078         u32 rev;
3079
3080         spin_lock_init(&dispc.irq_lock);
3081
3082 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3083         spin_lock_init(&dispc.irq_stats_lock);
3084         dispc.irq_stats.last_reset = jiffies;
3085 #endif
3086
3087         INIT_WORK(&dispc.error_work, dispc_error_worker);
3088
3089         dispc.base = ioremap(DISPC_BASE, DISPC_SZ_REGS);
3090         if (!dispc.base) {
3091                 DSSERR("can't ioremap DISPC\n");
3092                 return -ENOMEM;
3093         }
3094
3095         enable_clocks(1);
3096
3097         _omap_dispc_initial_config();
3098
3099         _omap_dispc_initialize_irq();
3100
3101         dispc_save_context();
3102
3103         rev = dispc_read_reg(DISPC_REVISION);
3104         printk(KERN_INFO "OMAP DISPC rev %d.%d\n",
3105                FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3106
3107         enable_clocks(0);
3108
3109         return 0;
3110 }
3111
3112 void dispc_exit(void)
3113 {
3114         iounmap(dispc.base);
3115 }
3116
3117 int dispc_enable_plane(enum omap_plane plane, bool enable)
3118 {
3119         DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
3120
3121         enable_clocks(1);
3122         _dispc_enable_plane(plane, enable);
3123         enable_clocks(0);
3124
3125         return 0;
3126 }
3127
3128 int dispc_setup_plane(enum omap_plane plane,
3129                        u32 paddr, u16 screen_width,
3130                        u16 pos_x, u16 pos_y,
3131                        u16 width, u16 height,
3132                        u16 out_width, u16 out_height,
3133                        enum omap_color_mode color_mode,
3134                        bool ilace,
3135                        enum omap_dss_rotation_type rotation_type,
3136                        u8 rotation, bool mirror, u8 global_alpha)
3137 {
3138         int r = 0;
3139
3140         DSSDBG("dispc_setup_plane %d, pa %x, sw %d, %d,%d, %dx%d -> "
3141                "%dx%d, ilace %d, cmode %x, rot %d, mir %d\n",
3142                plane, paddr, screen_width, pos_x, pos_y,
3143                width, height,
3144                out_width, out_height,
3145                ilace, color_mode,
3146                rotation, mirror);
3147
3148         enable_clocks(1);
3149
3150         r = _dispc_setup_plane(plane,
3151                            paddr, screen_width,
3152                            pos_x, pos_y,
3153                            width, height,
3154                            out_width, out_height,
3155                            color_mode, ilace,
3156                            rotation_type,
3157                            rotation, mirror,
3158                            global_alpha);
3159
3160         enable_clocks(0);
3161
3162         return r;
3163 }