drivers/video/omap2/dss/dispc.c

   1 /*
   2  * linux/drivers/video/omap2/dss/dispc.c
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #define DSS_SUBSYS_NAME "DISPC"
  24
  25 #include <linux/kernel.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/vmalloc.h>
  28 #include <linux/clk.h>
  29 #include <linux/io.h>
  30 #include <linux/jiffies.h>
  31 #include <linux/seq_file.h>
  32 #include <linux/delay.h>
  33 #include <linux/workqueue.h>
  34 #include <linux/hardirq.h>
  35
  36 #include <plat/sram.h>
  37 #include <plat/clock.h>
  38
  39 #include <plat/display.h>
  40
  41 #include "dss.h"
  42 #include "dss_features.h"
  43
  44 /* DISPC */
  45 #define DISPC_BASE                      0x48050400
  46
  47 #define DISPC_SZ_REGS                   SZ_4K
  48
  49 struct dispc_reg { u16 idx; };
  50
  51 #define DISPC_REG(idx)                  ((const struct dispc_reg) { idx })
  52
  53 /*
  54  * DISPC common registers and
  55  * DISPC channel registers , ch = 0 for LCD, ch = 1 for
  56  * DIGIT, and ch = 2 for LCD2
  57  */
  58 #define DISPC_REVISION                  DISPC_REG(0x0000)
  59 #define DISPC_SYSCONFIG                 DISPC_REG(0x0010)
  60 #define DISPC_SYSSTATUS                 DISPC_REG(0x0014)
  61 #define DISPC_IRQSTATUS                 DISPC_REG(0x0018)
  62 #define DISPC_IRQENABLE                 DISPC_REG(0x001C)
  63 #define DISPC_CONTROL                   DISPC_REG(0x0040)
  64 #define DISPC_CONTROL2                  DISPC_REG(0x0238)
  65 #define DISPC_CONFIG                    DISPC_REG(0x0044)
  66 #define DISPC_CONFIG2                   DISPC_REG(0x0620)
  67 #define DISPC_CAPABLE                   DISPC_REG(0x0048)
  68 #define DISPC_DEFAULT_COLOR(ch)         DISPC_REG(ch == 0 ? 0x004C : \
  69                                         (ch == 1 ? 0x0050 : 0x03AC))
  70 #define DISPC_TRANS_COLOR(ch)           DISPC_REG(ch == 0 ? 0x0054 : \
  71                                         (ch == 1 ? 0x0058 : 0x03B0))
  72 #define DISPC_LINE_STATUS               DISPC_REG(0x005C)
  73 #define DISPC_LINE_NUMBER               DISPC_REG(0x0060)
  74 #define DISPC_TIMING_H(ch)              DISPC_REG(ch != 2 ? 0x0064 : 0x0400)
  75 #define DISPC_TIMING_V(ch)              DISPC_REG(ch != 2 ? 0x0068 : 0x0404)
  76 #define DISPC_POL_FREQ(ch)              DISPC_REG(ch != 2 ? 0x006C : 0x0408)
  77 #define DISPC_DIVISOR(ch)               DISPC_REG(ch != 2 ? 0x0070 : 0x040C)
  78 #define DISPC_GLOBAL_ALPHA              DISPC_REG(0x0074)
  79 #define DISPC_SIZE_DIG                  DISPC_REG(0x0078)
  80 #define DISPC_SIZE_LCD(ch)              DISPC_REG(ch != 2 ? 0x007C : 0x03CC)
  81
  82 /* DISPC GFX plane */
  83 #define DISPC_GFX_BA0                   DISPC_REG(0x0080)
  84 #define DISPC_GFX_BA1                   DISPC_REG(0x0084)
  85 #define DISPC_GFX_POSITION              DISPC_REG(0x0088)
  86 #define DISPC_GFX_SIZE                  DISPC_REG(0x008C)
  87 #define DISPC_GFX_ATTRIBUTES            DISPC_REG(0x00A0)
  88 #define DISPC_GFX_FIFO_THRESHOLD        DISPC_REG(0x00A4)
  89 #define DISPC_GFX_FIFO_SIZE_STATUS      DISPC_REG(0x00A8)
  90 #define DISPC_GFX_ROW_INC               DISPC_REG(0x00AC)
  91 #define DISPC_GFX_PIXEL_INC             DISPC_REG(0x00B0)
  92 #define DISPC_GFX_WINDOW_SKIP           DISPC_REG(0x00B4)
  93 #define DISPC_GFX_TABLE_BA              DISPC_REG(0x00B8)
  94
  95 #define DISPC_DATA_CYCLE1(ch)           DISPC_REG(ch != 2 ? 0x01D4 : 0x03C0)
  96 #define DISPC_DATA_CYCLE2(ch)           DISPC_REG(ch != 2 ? 0x01D8 : 0x03C4)
  97 #define DISPC_DATA_CYCLE3(ch)           DISPC_REG(ch != 2 ? 0x01DC : 0x03C8)
  98 #define DISPC_CPR_COEF_R(ch)            DISPC_REG(ch != 2 ? 0x0220 : 0x03BC)
  99 #define DISPC_CPR_COEF_G(ch)            DISPC_REG(ch != 2 ? 0x0224 : 0x03B8)
 100 #define DISPC_CPR_COEF_B(ch)            DISPC_REG(ch != 2 ? 0x0228 : 0x03B4)
 101
 102 #define DISPC_GFX_PRELOAD               DISPC_REG(0x022C)
 103
 104 /* DISPC Video plane, n = 0 for VID1 and n = 1 for VID2 */
 105 #define DISPC_VID_REG(n, idx)           DISPC_REG(0x00BC + (n)*0x90 + idx)
 106
 107 #define DISPC_VID_BA0(n)                DISPC_VID_REG(n, 0x0000)
 108 #define DISPC_VID_BA1(n)                DISPC_VID_REG(n, 0x0004)
 109 #define DISPC_VID_POSITION(n)           DISPC_VID_REG(n, 0x0008)
 110 #define DISPC_VID_SIZE(n)               DISPC_VID_REG(n, 0x000C)
 111 #define DISPC_VID_ATTRIBUTES(n)         DISPC_VID_REG(n, 0x0010)
 112 #define DISPC_VID_FIFO_THRESHOLD(n)     DISPC_VID_REG(n, 0x0014)
 113 #define DISPC_VID_FIFO_SIZE_STATUS(n)   DISPC_VID_REG(n, 0x0018)
 114 #define DISPC_VID_ROW_INC(n)            DISPC_VID_REG(n, 0x001C)
 115 #define DISPC_VID_PIXEL_INC(n)          DISPC_VID_REG(n, 0x0020)
 116 #define DISPC_VID_FIR(n)                DISPC_VID_REG(n, 0x0024)
 117 #define DISPC_VID_PICTURE_SIZE(n)       DISPC_VID_REG(n, 0x0028)
 118 #define DISPC_VID_ACCU0(n)              DISPC_VID_REG(n, 0x002C)
 119 #define DISPC_VID_ACCU1(n)              DISPC_VID_REG(n, 0x0030)
 120
 121 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 122 #define DISPC_VID_FIR_COEF_H(n, i)      DISPC_REG(0x00F0 + (n)*0x90 + (i)*0x8)
 123 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 124 #define DISPC_VID_FIR_COEF_HV(n, i)     DISPC_REG(0x00F4 + (n)*0x90 + (i)*0x8)
 125 /* coef index i = {0, 1, 2, 3, 4} */
 126 #define DISPC_VID_CONV_COEF(n, i)       DISPC_REG(0x0130 + (n)*0x90 + (i)*0x4)
 127 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
 128 #define DISPC_VID_FIR_COEF_V(n, i)      DISPC_REG(0x01E0 + (n)*0x20 + (i)*0x4)
 129
 130 #define DISPC_VID_PRELOAD(n)            DISPC_REG(0x230 + (n)*0x04)
 131
 132
 133 #define DISPC_IRQ_MASK_ERROR            (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
 134                                          DISPC_IRQ_OCP_ERR | \
 135                                          DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
 136                                          DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
 137                                          DISPC_IRQ_SYNC_LOST | \
 138                                          DISPC_IRQ_SYNC_LOST_DIGIT)
 139
 140 #define DISPC_MAX_NR_ISRS               8
 141
 142 struct omap_dispc_isr_data {
 143         omap_dispc_isr_t        isr;
 144         void                    *arg;
 145         u32                     mask;
 146 };
 147
 148 struct dispc_h_coef {
 149         s8 hc4;
 150         s8 hc3;
 151         u8 hc2;
 152         s8 hc1;
 153         s8 hc0;
 154 };
 155
 156 struct dispc_v_coef {
 157         s8 vc22;
 158         s8 vc2;
 159         u8 vc1;
 160         s8 vc0;
 161         s8 vc00;
 162 };
 163
 164 #define REG_GET(idx, start, end) \
 165         FLD_GET(dispc_read_reg(idx), start, end)
 166
 167 #define REG_FLD_MOD(idx, val, start, end)                               \
 168         dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
 169
 170 static const struct dispc_reg dispc_reg_att[] = { DISPC_GFX_ATTRIBUTES,
 171         DISPC_VID_ATTRIBUTES(0),
 172         DISPC_VID_ATTRIBUTES(1) };
 173
 174 struct dispc_irq_stats {
 175         unsigned long last_reset;
 176         unsigned irq_count;
 177         unsigned irqs[32];
 178 };
 179
 180 static struct {
 181         void __iomem    *base;
 182
 183         u32     fifo_size[3];
 184
 185         spinlock_t irq_lock;
 186         u32 irq_error_mask;
 187         struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
 188         u32 error_irqs;
 189         struct work_struct error_work;
 190
 191         u32             ctx[DISPC_SZ_REGS / sizeof(u32)];
 192
 193 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
 194         spinlock_t irq_stats_lock;
 195         struct dispc_irq_stats irq_stats;
 196 #endif
 197 } dispc;
 198
 199 static void _omap_dispc_set_irqs(void);
 200
 201 static inline void dispc_write_reg(const struct dispc_reg idx, u32 val)
 202 {
 203         __raw_writel(val, dispc.base + idx.idx);
 204 }
 205
 206 static inline u32 dispc_read_reg(const struct dispc_reg idx)
 207 {
 208         return __raw_readl(dispc.base + idx.idx);
 209 }
 210
 211 #define SR(reg) \
 212         dispc.ctx[(DISPC_##reg).idx / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
 213 #define RR(reg) \
 214         dispc_write_reg(DISPC_##reg, dispc.ctx[(DISPC_##reg).idx / sizeof(u32)])
 215
 216 void dispc_save_context(void)
 217 {
 218         if (cpu_is_omap24xx())
 219                 return;
 220
 221         SR(SYSCONFIG);
 222         SR(IRQENABLE);
 223         SR(CONTROL);
 224         SR(CONFIG);
 225         SR(DEFAULT_COLOR(0));
 226         SR(DEFAULT_COLOR(1));
 227         SR(TRANS_COLOR(0));
 228         SR(TRANS_COLOR(1));
 229         SR(LINE_NUMBER);
 230         SR(TIMING_H(0));
 231         SR(TIMING_V(0));
 232         SR(POL_FREQ(0));
 233         SR(DIVISOR(0));
 234         SR(GLOBAL_ALPHA);
 235         SR(SIZE_DIG);
 236         SR(SIZE_LCD(0));
 237
 238         SR(GFX_BA0);
 239         SR(GFX_BA1);
 240         SR(GFX_POSITION);
 241         SR(GFX_SIZE);
 242         SR(GFX_ATTRIBUTES);
 243         SR(GFX_FIFO_THRESHOLD);
 244         SR(GFX_ROW_INC);
 245         SR(GFX_PIXEL_INC);
 246         SR(GFX_WINDOW_SKIP);
 247         SR(GFX_TABLE_BA);
 248
 249         SR(DATA_CYCLE1(0));
 250         SR(DATA_CYCLE2(0));
 251         SR(DATA_CYCLE3(0));
 252
 253         SR(CPR_COEF_R(0));
 254         SR(CPR_COEF_G(0));
 255         SR(CPR_COEF_B(0));
 256
 257         SR(GFX_PRELOAD);
 258
 259         /* VID1 */
 260         SR(VID_BA0(0));
 261         SR(VID_BA1(0));
 262         SR(VID_POSITION(0));
 263         SR(VID_SIZE(0));
 264         SR(VID_ATTRIBUTES(0));
 265         SR(VID_FIFO_THRESHOLD(0));
 266         SR(VID_ROW_INC(0));
 267         SR(VID_PIXEL_INC(0));
 268         SR(VID_FIR(0));
 269         SR(VID_PICTURE_SIZE(0));
 270         SR(VID_ACCU0(0));
 271         SR(VID_ACCU1(0));
 272
 273         SR(VID_FIR_COEF_H(0, 0));
 274         SR(VID_FIR_COEF_H(0, 1));
 275         SR(VID_FIR_COEF_H(0, 2));
 276         SR(VID_FIR_COEF_H(0, 3));
 277         SR(VID_FIR_COEF_H(0, 4));
 278         SR(VID_FIR_COEF_H(0, 5));
 279         SR(VID_FIR_COEF_H(0, 6));
 280         SR(VID_FIR_COEF_H(0, 7));
 281
 282         SR(VID_FIR_COEF_HV(0, 0));
 283         SR(VID_FIR_COEF_HV(0, 1));
 284         SR(VID_FIR_COEF_HV(0, 2));
 285         SR(VID_FIR_COEF_HV(0, 3));
 286         SR(VID_FIR_COEF_HV(0, 4));
 287         SR(VID_FIR_COEF_HV(0, 5));
 288         SR(VID_FIR_COEF_HV(0, 6));
 289         SR(VID_FIR_COEF_HV(0, 7));
 290
 291         SR(VID_CONV_COEF(0, 0));
 292         SR(VID_CONV_COEF(0, 1));
 293         SR(VID_CONV_COEF(0, 2));
 294         SR(VID_CONV_COEF(0, 3));
 295         SR(VID_CONV_COEF(0, 4));
 296
 297         SR(VID_FIR_COEF_V(0, 0));
 298         SR(VID_FIR_COEF_V(0, 1));
 299         SR(VID_FIR_COEF_V(0, 2));
 300         SR(VID_FIR_COEF_V(0, 3));
 301         SR(VID_FIR_COEF_V(0, 4));
 302         SR(VID_FIR_COEF_V(0, 5));
 303         SR(VID_FIR_COEF_V(0, 6));
 304         SR(VID_FIR_COEF_V(0, 7));
 305
 306         SR(VID_PRELOAD(0));
 307
 308         /* VID2 */
 309         SR(VID_BA0(1));
 310         SR(VID_BA1(1));
 311         SR(VID_POSITION(1));
 312         SR(VID_SIZE(1));
 313         SR(VID_ATTRIBUTES(1));
 314         SR(VID_FIFO_THRESHOLD(1));
 315         SR(VID_ROW_INC(1));
 316         SR(VID_PIXEL_INC(1));
 317         SR(VID_FIR(1));
 318         SR(VID_PICTURE_SIZE(1));
 319         SR(VID_ACCU0(1));
 320         SR(VID_ACCU1(1));
 321
 322         SR(VID_FIR_COEF_H(1, 0));
 323         SR(VID_FIR_COEF_H(1, 1));
 324         SR(VID_FIR_COEF_H(1, 2));
 325         SR(VID_FIR_COEF_H(1, 3));
 326         SR(VID_FIR_COEF_H(1, 4));
 327         SR(VID_FIR_COEF_H(1, 5));
 328         SR(VID_FIR_COEF_H(1, 6));
 329         SR(VID_FIR_COEF_H(1, 7));
 330
 331         SR(VID_FIR_COEF_HV(1, 0));
 332         SR(VID_FIR_COEF_HV(1, 1));
 333         SR(VID_FIR_COEF_HV(1, 2));
 334         SR(VID_FIR_COEF_HV(1, 3));
 335         SR(VID_FIR_COEF_HV(1, 4));
 336         SR(VID_FIR_COEF_HV(1, 5));
 337         SR(VID_FIR_COEF_HV(1, 6));
 338         SR(VID_FIR_COEF_HV(1, 7));
 339
 340         SR(VID_CONV_COEF(1, 0));
 341         SR(VID_CONV_COEF(1, 1));
 342         SR(VID_CONV_COEF(1, 2));
 343         SR(VID_CONV_COEF(1, 3));
 344         SR(VID_CONV_COEF(1, 4));
 345
 346         SR(VID_FIR_COEF_V(1, 0));
 347         SR(VID_FIR_COEF_V(1, 1));
 348         SR(VID_FIR_COEF_V(1, 2));
 349         SR(VID_FIR_COEF_V(1, 3));
 350         SR(VID_FIR_COEF_V(1, 4));
 351         SR(VID_FIR_COEF_V(1, 5));
 352         SR(VID_FIR_COEF_V(1, 6));
 353         SR(VID_FIR_COEF_V(1, 7));
 354
 355         SR(VID_PRELOAD(1));
 356 }
 357
 358 void dispc_restore_context(void)
 359 {
 360         RR(SYSCONFIG);
 361         /*RR(IRQENABLE);*/
 362         /*RR(CONTROL);*/
 363         RR(CONFIG);
 364         RR(DEFAULT_COLOR(0));
 365         RR(DEFAULT_COLOR(1));
 366         RR(TRANS_COLOR(0));
 367         RR(TRANS_COLOR(1));
 368         RR(LINE_NUMBER);
 369         RR(TIMING_H(0));
 370         RR(TIMING_V(0));
 371         RR(POL_FREQ(0));
 372         RR(DIVISOR(0));
 373         RR(GLOBAL_ALPHA);
 374         RR(SIZE_DIG);
 375         RR(SIZE_LCD(0));
 376
 377         RR(GFX_BA0);
 378         RR(GFX_BA1);
 379         RR(GFX_POSITION);
 380         RR(GFX_SIZE);
 381         RR(GFX_ATTRIBUTES);
 382         RR(GFX_FIFO_THRESHOLD);
 383         RR(GFX_ROW_INC);
 384         RR(GFX_PIXEL_INC);
 385         RR(GFX_WINDOW_SKIP);
 386         RR(GFX_TABLE_BA);
 387
 388         RR(DATA_CYCLE1(0));
 389         RR(DATA_CYCLE2(0));
 390         RR(DATA_CYCLE3(0));
 391
 392         RR(CPR_COEF_R(0));
 393         RR(CPR_COEF_G(0));
 394         RR(CPR_COEF_B(0));
 395
 396         RR(GFX_PRELOAD);
 397
 398         /* VID1 */
 399         RR(VID_BA0(0));
 400         RR(VID_BA1(0));
 401         RR(VID_POSITION(0));
 402         RR(VID_SIZE(0));
 403         RR(VID_ATTRIBUTES(0));
 404         RR(VID_FIFO_THRESHOLD(0));
 405         RR(VID_ROW_INC(0));
 406         RR(VID_PIXEL_INC(0));
 407         RR(VID_FIR(0));
 408         RR(VID_PICTURE_SIZE(0));
 409         RR(VID_ACCU0(0));
 410         RR(VID_ACCU1(0));
 411
 412         RR(VID_FIR_COEF_H(0, 0));
 413         RR(VID_FIR_COEF_H(0, 1));
 414         RR(VID_FIR_COEF_H(0, 2));
 415         RR(VID_FIR_COEF_H(0, 3));
 416         RR(VID_FIR_COEF_H(0, 4));
 417         RR(VID_FIR_COEF_H(0, 5));
 418         RR(VID_FIR_COEF_H(0, 6));
 419         RR(VID_FIR_COEF_H(0, 7));
 420
 421         RR(VID_FIR_COEF_HV(0, 0));
 422         RR(VID_FIR_COEF_HV(0, 1));
 423         RR(VID_FIR_COEF_HV(0, 2));
 424         RR(VID_FIR_COEF_HV(0, 3));
 425         RR(VID_FIR_COEF_HV(0, 4));
 426         RR(VID_FIR_COEF_HV(0, 5));
 427         RR(VID_FIR_COEF_HV(0, 6));
 428         RR(VID_FIR_COEF_HV(0, 7));
 429
 430         RR(VID_CONV_COEF(0, 0));
 431         RR(VID_CONV_COEF(0, 1));
 432         RR(VID_CONV_COEF(0, 2));
 433         RR(VID_CONV_COEF(0, 3));
 434         RR(VID_CONV_COEF(0, 4));
 435
 436         RR(VID_FIR_COEF_V(0, 0));
 437         RR(VID_FIR_COEF_V(0, 1));
 438         RR(VID_FIR_COEF_V(0, 2));
 439         RR(VID_FIR_COEF_V(0, 3));
 440         RR(VID_FIR_COEF_V(0, 4));
 441         RR(VID_FIR_COEF_V(0, 5));
 442         RR(VID_FIR_COEF_V(0, 6));
 443         RR(VID_FIR_COEF_V(0, 7));
 444
 445         RR(VID_PRELOAD(0));
 446
 447         /* VID2 */
 448         RR(VID_BA0(1));
 449         RR(VID_BA1(1));
 450         RR(VID_POSITION(1));
 451         RR(VID_SIZE(1));
 452         RR(VID_ATTRIBUTES(1));
 453         RR(VID_FIFO_THRESHOLD(1));
 454         RR(VID_ROW_INC(1));
 455         RR(VID_PIXEL_INC(1));
 456         RR(VID_FIR(1));
 457         RR(VID_PICTURE_SIZE(1));
 458         RR(VID_ACCU0(1));
 459         RR(VID_ACCU1(1));
 460
 461         RR(VID_FIR_COEF_H(1, 0));
 462         RR(VID_FIR_COEF_H(1, 1));
 463         RR(VID_FIR_COEF_H(1, 2));
 464         RR(VID_FIR_COEF_H(1, 3));
 465         RR(VID_FIR_COEF_H(1, 4));
 466         RR(VID_FIR_COEF_H(1, 5));
 467         RR(VID_FIR_COEF_H(1, 6));
 468         RR(VID_FIR_COEF_H(1, 7));
 469
 470         RR(VID_FIR_COEF_HV(1, 0));
 471         RR(VID_FIR_COEF_HV(1, 1));
 472         RR(VID_FIR_COEF_HV(1, 2));
 473         RR(VID_FIR_COEF_HV(1, 3));
 474         RR(VID_FIR_COEF_HV(1, 4));
 475         RR(VID_FIR_COEF_HV(1, 5));
 476         RR(VID_FIR_COEF_HV(1, 6));
 477         RR(VID_FIR_COEF_HV(1, 7));
 478
 479         RR(VID_CONV_COEF(1, 0));
 480         RR(VID_CONV_COEF(1, 1));
 481         RR(VID_CONV_COEF(1, 2));
 482         RR(VID_CONV_COEF(1, 3));
 483         RR(VID_CONV_COEF(1, 4));
 484
 485         RR(VID_FIR_COEF_V(1, 0));
 486         RR(VID_FIR_COEF_V(1, 1));
 487         RR(VID_FIR_COEF_V(1, 2));
 488         RR(VID_FIR_COEF_V(1, 3));
 489         RR(VID_FIR_COEF_V(1, 4));
 490         RR(VID_FIR_COEF_V(1, 5));
 491         RR(VID_FIR_COEF_V(1, 6));
 492         RR(VID_FIR_COEF_V(1, 7));
 493
 494         RR(VID_PRELOAD(1));
 495
 496         /* enable last, because LCD & DIGIT enable are here */
 497         RR(CONTROL);
 498
 499         /* clear spurious SYNC_LOST_DIGIT interrupts */
 500         dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
 501
 502         /*
 503          * enable last so IRQs won't trigger before
 504          * the context is fully restored
 505          */
 506         RR(IRQENABLE);
 507 }
 508
 509 #undef SR
 510 #undef RR
 511
 512 static inline void enable_clocks(bool enable)
 513 {
 514         if (enable)
 515                 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
 516         else
 517                 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
 518 }
 519
 520 bool dispc_go_busy(enum omap_channel channel)
 521 {
 522         int bit;
 523
 524         if (channel == OMAP_DSS_CHANNEL_LCD)
 525                 bit = 5; /* GOLCD */
 526         else
 527                 bit = 6; /* GODIGIT */
 528
 529         return REG_GET(DISPC_CONTROL, bit, bit) == 1;
 530 }
 531
 532 void dispc_go(enum omap_channel channel)
 533 {
 534         int bit;
 535
 536         enable_clocks(1);
 537
 538         if (channel == OMAP_DSS_CHANNEL_LCD)
 539                 bit = 0; /* LCDENABLE */
 540         else
 541                 bit = 1; /* DIGITALENABLE */
 542
 543         /* if the channel is not enabled, we don't need GO */
 544         if (REG_GET(DISPC_CONTROL, bit, bit) == 0)
 545                 goto end;
 546
 547         if (channel == OMAP_DSS_CHANNEL_LCD)
 548                 bit = 5; /* GOLCD */
 549         else
 550                 bit = 6; /* GODIGIT */
 551
 552         if (REG_GET(DISPC_CONTROL, bit, bit) == 1) {
 553                 DSSERR("GO bit not down for channel %d\n", channel);
 554                 goto end;
 555         }
 556
 557         DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" : "DIGIT");
 558
 559         REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
 560 end:
 561         enable_clocks(0);
 562 }
 563
 564 static void _dispc_write_firh_reg(enum omap_plane plane, int reg, u32 value)
 565 {
 566         BUG_ON(plane == OMAP_DSS_GFX);
 567
 568         dispc_write_reg(DISPC_VID_FIR_COEF_H(plane-1, reg), value);
 569 }
 570
 571 static void _dispc_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
 572 {
 573         BUG_ON(plane == OMAP_DSS_GFX);
 574
 575         dispc_write_reg(DISPC_VID_FIR_COEF_HV(plane-1, reg), value);
 576 }
 577
 578 static void _dispc_write_firv_reg(enum omap_plane plane, int reg, u32 value)
 579 {
 580         BUG_ON(plane == OMAP_DSS_GFX);
 581
 582         dispc_write_reg(DISPC_VID_FIR_COEF_V(plane-1, reg), value);
 583 }
 584
 585 static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup,
 586                 int vscaleup, int five_taps)
 587 {
 588         /* Coefficients for horizontal up-sampling */
 589         static const struct dispc_h_coef coef_hup[8] = {
 590                 {  0,   0, 128,   0,  0 },
 591                 { -1,  13, 124,  -8,  0 },
 592                 { -2,  30, 112, -11, -1 },
 593                 { -5,  51,  95, -11, -2 },
 594                 {  0,  -9,  73,  73, -9 },
 595                 { -2, -11,  95,  51, -5 },
 596                 { -1, -11, 112,  30, -2 },
 597                 {  0,  -8, 124,  13, -1 },
 598         };
 599
 600         /* Coefficients for vertical up-sampling */
 601         static const struct dispc_v_coef coef_vup_3tap[8] = {
 602                 { 0,  0, 128,  0, 0 },
 603                 { 0,  3, 123,  2, 0 },
 604                 { 0, 12, 111,  5, 0 },
 605                 { 0, 32,  89,  7, 0 },
 606                 { 0,  0,  64, 64, 0 },
 607                 { 0,  7,  89, 32, 0 },
 608                 { 0,  5, 111, 12, 0 },
 609                 { 0,  2, 123,  3, 0 },
 610         };
 611
 612         static const struct dispc_v_coef coef_vup_5tap[8] = {
 613                 {  0,   0, 128,   0,  0 },
 614                 { -1,  13, 124,  -8,  0 },
 615                 { -2,  30, 112, -11, -1 },
 616                 { -5,  51,  95, -11, -2 },
 617                 {  0,  -9,  73,  73, -9 },
 618                 { -2, -11,  95,  51, -5 },
 619                 { -1, -11, 112,  30, -2 },
 620                 {  0,  -8, 124,  13, -1 },
 621         };
 622
 623         /* Coefficients for horizontal down-sampling */
 624         static const struct dispc_h_coef coef_hdown[8] = {
 625                 {   0, 36, 56, 36,  0 },
 626                 {   4, 40, 55, 31, -2 },
 627                 {   8, 44, 54, 27, -5 },
 628                 {  12, 48, 53, 22, -7 },
 629                 {  -9, 17, 52, 51, 17 },
 630                 {  -7, 22, 53, 48, 12 },
 631                 {  -5, 27, 54, 44,  8 },
 632                 {  -2, 31, 55, 40,  4 },
 633         };
 634
 635         /* Coefficients for vertical down-sampling */
 636         static const struct dispc_v_coef coef_vdown_3tap[8] = {
 637                 { 0, 36, 56, 36, 0 },
 638                 { 0, 40, 57, 31, 0 },
 639                 { 0, 45, 56, 27, 0 },
 640                 { 0, 50, 55, 23, 0 },
 641                 { 0, 18, 55, 55, 0 },
 642                 { 0, 23, 55, 50, 0 },
 643                 { 0, 27, 56, 45, 0 },
 644                 { 0, 31, 57, 40, 0 },
 645         };
 646
 647         static const struct dispc_v_coef coef_vdown_5tap[8] = {
 648                 {   0, 36, 56, 36,  0 },
 649                 {   4, 40, 55, 31, -2 },
 650                 {   8, 44, 54, 27, -5 },
 651                 {  12, 48, 53, 22, -7 },
 652                 {  -9, 17, 52, 51, 17 },
 653                 {  -7, 22, 53, 48, 12 },
 654                 {  -5, 27, 54, 44,  8 },
 655                 {  -2, 31, 55, 40,  4 },
 656         };
 657
 658         const struct dispc_h_coef *h_coef;
 659         const struct dispc_v_coef *v_coef;
 660         int i;
 661
 662         if (hscaleup)
 663                 h_coef = coef_hup;
 664         else
 665                 h_coef = coef_hdown;
 666
 667         if (vscaleup)
 668                 v_coef = five_taps ? coef_vup_5tap : coef_vup_3tap;
 669         else
 670                 v_coef = five_taps ? coef_vdown_5tap : coef_vdown_3tap;
 671
 672         for (i = 0; i < 8; i++) {
 673                 u32 h, hv;
 674
 675                 h = FLD_VAL(h_coef[i].hc0, 7, 0)
 676                         | FLD_VAL(h_coef[i].hc1, 15, 8)
 677                         | FLD_VAL(h_coef[i].hc2, 23, 16)
 678                         | FLD_VAL(h_coef[i].hc3, 31, 24);
 679                 hv = FLD_VAL(h_coef[i].hc4, 7, 0)
 680                         | FLD_VAL(v_coef[i].vc0, 15, 8)
 681                         | FLD_VAL(v_coef[i].vc1, 23, 16)
 682                         | FLD_VAL(v_coef[i].vc2, 31, 24);
 683
 684                 _dispc_write_firh_reg(plane, i, h);
 685                 _dispc_write_firhv_reg(plane, i, hv);
 686         }
 687
 688         if (five_taps) {
 689                 for (i = 0; i < 8; i++) {
 690                         u32 v;
 691                         v = FLD_VAL(v_coef[i].vc00, 7, 0)
 692                                 | FLD_VAL(v_coef[i].vc22, 15, 8);
 693                         _dispc_write_firv_reg(plane, i, v);
 694                 }
 695         }
 696 }
 697
 698 static void _dispc_setup_color_conv_coef(void)
 699 {
 700         const struct color_conv_coef {
 701                 int  ry,  rcr,  rcb,   gy,  gcr,  gcb,   by,  bcr,  bcb;
 702                 int  full_range;
 703         }  ctbl_bt601_5 = {
 704                 298,  409,    0,  298, -208, -100,  298,    0,  517, 0,
 705         };
 706
 707         const struct color_conv_coef *ct;
 708
 709 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
 710
 711         ct = &ctbl_bt601_5;
 712
 713         dispc_write_reg(DISPC_VID_CONV_COEF(0, 0), CVAL(ct->rcr, ct->ry));
 714         dispc_write_reg(DISPC_VID_CONV_COEF(0, 1), CVAL(ct->gy,  ct->rcb));
 715         dispc_write_reg(DISPC_VID_CONV_COEF(0, 2), CVAL(ct->gcb, ct->gcr));
 716         dispc_write_reg(DISPC_VID_CONV_COEF(0, 3), CVAL(ct->bcr, ct->by));
 717         dispc_write_reg(DISPC_VID_CONV_COEF(0, 4), CVAL(0,       ct->bcb));
 718
 719         dispc_write_reg(DISPC_VID_CONV_COEF(1, 0), CVAL(ct->rcr, ct->ry));
 720         dispc_write_reg(DISPC_VID_CONV_COEF(1, 1), CVAL(ct->gy,  ct->rcb));
 721         dispc_write_reg(DISPC_VID_CONV_COEF(1, 2), CVAL(ct->gcb, ct->gcr));
 722         dispc_write_reg(DISPC_VID_CONV_COEF(1, 3), CVAL(ct->bcr, ct->by));
 723         dispc_write_reg(DISPC_VID_CONV_COEF(1, 4), CVAL(0,       ct->bcb));
 724
 725 #undef CVAL
 726
 727         REG_FLD_MOD(DISPC_VID_ATTRIBUTES(0), ct->full_range, 11, 11);
 728         REG_FLD_MOD(DISPC_VID_ATTRIBUTES(1), ct->full_range, 11, 11);
 729 }
 730
 731
 732 static void _dispc_set_plane_ba0(enum omap_plane plane, u32 paddr)
 733 {
 734         const struct dispc_reg ba0_reg[] = { DISPC_GFX_BA0,
 735                 DISPC_VID_BA0(0),
 736                 DISPC_VID_BA0(1) };
 737
 738         dispc_write_reg(ba0_reg[plane], paddr);
 739 }
 740
 741 static void _dispc_set_plane_ba1(enum omap_plane plane, u32 paddr)
 742 {
 743         const struct dispc_reg ba1_reg[] = { DISPC_GFX_BA1,
 744                                       DISPC_VID_BA1(0),
 745                                       DISPC_VID_BA1(1) };
 746
 747         dispc_write_reg(ba1_reg[plane], paddr);
 748 }
 749
 750 static void _dispc_set_plane_pos(enum omap_plane plane, int x, int y)
 751 {
 752         const struct dispc_reg pos_reg[] = { DISPC_GFX_POSITION,
 753                                       DISPC_VID_POSITION(0),
 754                                       DISPC_VID_POSITION(1) };
 755
 756         u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
 757         dispc_write_reg(pos_reg[plane], val);
 758 }
 759
 760 static void _dispc_set_pic_size(enum omap_plane plane, int width, int height)
 761 {
 762         const struct dispc_reg siz_reg[] = { DISPC_GFX_SIZE,
 763                                       DISPC_VID_PICTURE_SIZE(0),
 764                                       DISPC_VID_PICTURE_SIZE(1) };
 765         u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 766         dispc_write_reg(siz_reg[plane], val);
 767 }
 768
 769 static void _dispc_set_vid_size(enum omap_plane plane, int width, int height)
 770 {
 771         u32 val;
 772         const struct dispc_reg vsi_reg[] = { DISPC_VID_SIZE(0),
 773                                       DISPC_VID_SIZE(1) };
 774
 775         BUG_ON(plane == OMAP_DSS_GFX);
 776
 777         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 778         dispc_write_reg(vsi_reg[plane-1], val);
 779 }
 780
 781 static void _dispc_set_pre_mult_alpha(enum omap_plane plane, bool enable)
 782 {
 783         if (!dss_has_feature(FEAT_PRE_MULT_ALPHA))
 784                 return;
 785
 786         if (!dss_has_feature(FEAT_GLOBAL_ALPHA_VID1) &&
 787                 plane == OMAP_DSS_VIDEO1)
 788                 return;
 789
 790         REG_FLD_MOD(dispc_reg_att[plane], enable ? 1 : 0, 28, 28);
 791 }
 792
 793 static void _dispc_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
 794 {
 795         if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
 796                 return;
 797
 798         if (!dss_has_feature(FEAT_GLOBAL_ALPHA_VID1) &&
 799                 plane == OMAP_DSS_VIDEO1)
 800                 return;
 801
 802         if (plane == OMAP_DSS_GFX)
 803                 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 7, 0);
 804         else if (plane == OMAP_DSS_VIDEO2)
 805                 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 23, 16);
 806 }
 807
 808 static void _dispc_set_pix_inc(enum omap_plane plane, s32 inc)
 809 {
 810         const struct dispc_reg ri_reg[] = { DISPC_GFX_PIXEL_INC,
 811                                      DISPC_VID_PIXEL_INC(0),
 812                                      DISPC_VID_PIXEL_INC(1) };
 813
 814         dispc_write_reg(ri_reg[plane], inc);
 815 }
 816
 817 static void _dispc_set_row_inc(enum omap_plane plane, s32 inc)
 818 {
 819         const struct dispc_reg ri_reg[] = { DISPC_GFX_ROW_INC,
 820                                      DISPC_VID_ROW_INC(0),
 821                                      DISPC_VID_ROW_INC(1) };
 822
 823         dispc_write_reg(ri_reg[plane], inc);
 824 }
 825
 826 static void _dispc_set_color_mode(enum omap_plane plane,
 827                 enum omap_color_mode color_mode)
 828 {
 829         u32 m = 0;
 830
 831         switch (color_mode) {
 832         case OMAP_DSS_COLOR_CLUT1:
 833                 m = 0x0; break;
 834         case OMAP_DSS_COLOR_CLUT2:
 835                 m = 0x1; break;
 836         case OMAP_DSS_COLOR_CLUT4:
 837                 m = 0x2; break;
 838         case OMAP_DSS_COLOR_CLUT8:
 839                 m = 0x3; break;
 840         case OMAP_DSS_COLOR_RGB12U:
 841                 m = 0x4; break;
 842         case OMAP_DSS_COLOR_ARGB16:
 843                 m = 0x5; break;
 844         case OMAP_DSS_COLOR_RGB16:
 845                 m = 0x6; break;
 846         case OMAP_DSS_COLOR_RGB24U:
 847                 m = 0x8; break;
 848         case OMAP_DSS_COLOR_RGB24P:
 849                 m = 0x9; break;
 850         case OMAP_DSS_COLOR_YUV2:
 851                 m = 0xa; break;
 852         case OMAP_DSS_COLOR_UYVY:
 853                 m = 0xb; break;
 854         case OMAP_DSS_COLOR_ARGB32:
 855                 m = 0xc; break;
 856         case OMAP_DSS_COLOR_RGBA32:
 857                 m = 0xd; break;
 858         case OMAP_DSS_COLOR_RGBX32:
 859                 m = 0xe; break;
 860         default:
 861                 BUG(); break;
 862         }
 863
 864         REG_FLD_MOD(dispc_reg_att[plane], m, 4, 1);
 865 }
 866
 867 static void _dispc_set_channel_out(enum omap_plane plane,
 868                 enum omap_channel channel)
 869 {
 870         int shift;
 871         u32 val;
 872
 873         switch (plane) {
 874         case OMAP_DSS_GFX:
 875                 shift = 8;
 876                 break;
 877         case OMAP_DSS_VIDEO1:
 878         case OMAP_DSS_VIDEO2:
 879                 shift = 16;
 880                 break;
 881         default:
 882                 BUG();
 883                 return;
 884         }
 885
 886         val = dispc_read_reg(dispc_reg_att[plane]);
 887         val = FLD_MOD(val, channel, shift, shift);
 888         dispc_write_reg(dispc_reg_att[plane], val);
 889 }
 890
 891 void dispc_set_burst_size(enum omap_plane plane,
 892                 enum omap_burst_size burst_size)
 893 {
 894         int shift;
 895         u32 val;
 896
 897         enable_clocks(1);
 898
 899         switch (plane) {
 900         case OMAP_DSS_GFX:
 901                 shift = 6;
 902                 break;
 903         case OMAP_DSS_VIDEO1:
 904         case OMAP_DSS_VIDEO2:
 905                 shift = 14;
 906                 break;
 907         default:
 908                 BUG();
 909                 return;
 910         }
 911
 912         val = dispc_read_reg(dispc_reg_att[plane]);
 913         val = FLD_MOD(val, burst_size, shift+1, shift);
 914         dispc_write_reg(dispc_reg_att[plane], val);
 915
 916         enable_clocks(0);
 917 }
 918
 919 static void _dispc_set_vid_color_conv(enum omap_plane plane, bool enable)
 920 {
 921         u32 val;
 922
 923         BUG_ON(plane == OMAP_DSS_GFX);
 924
 925         val = dispc_read_reg(dispc_reg_att[plane]);
 926         val = FLD_MOD(val, enable, 9, 9);
 927         dispc_write_reg(dispc_reg_att[plane], val);
 928 }
 929
 930 void dispc_enable_replication(enum omap_plane plane, bool enable)
 931 {
 932         int bit;
 933
 934         if (plane == OMAP_DSS_GFX)
 935                 bit = 5;
 936         else
 937                 bit = 10;
 938
 939         enable_clocks(1);
 940         REG_FLD_MOD(dispc_reg_att[plane], enable, bit, bit);
 941         enable_clocks(0);
 942 }
 943
 944 void dispc_set_lcd_size(enum omap_channel channel, u16 width, u16 height)
 945 {
 946         u32 val;
 947         BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
 948         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 949         enable_clocks(1);
 950         dispc_write_reg(DISPC_SIZE_LCD(channel), val);
 951         enable_clocks(0);
 952 }
 953
 954 void dispc_set_digit_size(u16 width, u16 height)
 955 {
 956         u32 val;
 957         BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
 958         val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
 959         enable_clocks(1);
 960         dispc_write_reg(DISPC_SIZE_DIG, val);
 961         enable_clocks(0);
 962 }
 963
 964 static void dispc_read_plane_fifo_sizes(void)
 965 {
 966         const struct dispc_reg fsz_reg[] = { DISPC_GFX_FIFO_SIZE_STATUS,
 967                                       DISPC_VID_FIFO_SIZE_STATUS(0),
 968                                       DISPC_VID_FIFO_SIZE_STATUS(1) };
 969         u32 size;
 970         int plane;
 971         u8 start, end;
 972
 973         enable_clocks(1);
 974
 975         dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
 976
 977         for (plane = 0; plane < ARRAY_SIZE(dispc.fifo_size); ++plane) {
 978                 size = FLD_GET(dispc_read_reg(fsz_reg[plane]), start, end);
 979                 dispc.fifo_size[plane] = size;
 980         }
 981
 982         enable_clocks(0);
 983 }
 984
 985 u32 dispc_get_plane_fifo_size(enum omap_plane plane)
 986 {
 987         return dispc.fifo_size[plane];
 988 }
 989
 990 void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high)
 991 {
 992         const struct dispc_reg ftrs_reg[] = { DISPC_GFX_FIFO_THRESHOLD,
 993                                        DISPC_VID_FIFO_THRESHOLD(0),
 994                                        DISPC_VID_FIFO_THRESHOLD(1) };
 995         u8 hi_start, hi_end, lo_start, lo_end;
 996
 997         enable_clocks(1);
 998
 999         DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n",
1000                         plane,
1001                         REG_GET(ftrs_reg[plane], 11, 0),
1002                         REG_GET(ftrs_reg[plane], 27, 16),
1003                         low, high);
1004
1005         dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1006         dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1007
1008         dispc_write_reg(ftrs_reg[plane],
1009                         FLD_VAL(high, hi_start, hi_end) |
1010                         FLD_VAL(low, lo_start, lo_end));
1011
1012         enable_clocks(0);
1013 }
1014
1015 void dispc_enable_fifomerge(bool enable)
1016 {
1017         enable_clocks(1);
1018
1019         DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1020         REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1021
1022         enable_clocks(0);
1023 }
1024
1025 static void _dispc_set_fir(enum omap_plane plane, int hinc, int vinc)
1026 {
1027         u32 val;
1028         const struct dispc_reg fir_reg[] = { DISPC_VID_FIR(0),
1029                                       DISPC_VID_FIR(1) };
1030         u8 hinc_start, hinc_end, vinc_start, vinc_end;
1031
1032         BUG_ON(plane == OMAP_DSS_GFX);
1033
1034         dss_feat_get_reg_field(FEAT_REG_FIRHINC, &hinc_start, &hinc_end);
1035         dss_feat_get_reg_field(FEAT_REG_FIRVINC, &vinc_start, &vinc_end);
1036
1037         val = FLD_VAL(vinc, vinc_start, vinc_end) |
1038                         FLD_VAL(hinc, hinc_start, hinc_end);
1039
1040         dispc_write_reg(fir_reg[plane-1], val);
1041 }
1042
1043 static void _dispc_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1044 {
1045         u32 val;
1046         const struct dispc_reg ac0_reg[] = { DISPC_VID_ACCU0(0),
1047                                       DISPC_VID_ACCU0(1) };
1048
1049         BUG_ON(plane == OMAP_DSS_GFX);
1050
1051         val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0);
1052         dispc_write_reg(ac0_reg[plane-1], val);
1053 }
1054
1055 static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1056 {
1057         u32 val;
1058         const struct dispc_reg ac1_reg[] = { DISPC_VID_ACCU1(0),
1059                                       DISPC_VID_ACCU1(1) };
1060
1061         BUG_ON(plane == OMAP_DSS_GFX);
1062
1063         val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0);
1064         dispc_write_reg(ac1_reg[plane-1], val);
1065 }
1066
1067
1068 static void _dispc_set_scaling(enum omap_plane plane,
1069                 u16 orig_width, u16 orig_height,
1070                 u16 out_width, u16 out_height,
1071                 bool ilace, bool five_taps,
1072                 bool fieldmode)
1073 {
1074         int fir_hinc;
1075         int fir_vinc;
1076         int hscaleup, vscaleup;
1077         int accu0 = 0;
1078         int accu1 = 0;
1079         u32 l;
1080
1081         BUG_ON(plane == OMAP_DSS_GFX);
1082
1083         hscaleup = orig_width <= out_width;
1084         vscaleup = orig_height <= out_height;
1085
1086         _dispc_set_scale_coef(plane, hscaleup, vscaleup, five_taps);
1087
1088         if (!orig_width || orig_width == out_width)
1089                 fir_hinc = 0;
1090         else
1091                 fir_hinc = 1024 * orig_width / out_width;
1092
1093         if (!orig_height || orig_height == out_height)
1094                 fir_vinc = 0;
1095         else
1096                 fir_vinc = 1024 * orig_height / out_height;
1097
1098         _dispc_set_fir(plane, fir_hinc, fir_vinc);
1099
1100         l = dispc_read_reg(dispc_reg_att[plane]);
1101         l &= ~((0x0f << 5) | (0x3 << 21));
1102
1103         l |= fir_hinc ? (1 << 5) : 0;
1104         l |= fir_vinc ? (1 << 6) : 0;
1105
1106         l |= hscaleup ? 0 : (1 << 7);
1107         l |= vscaleup ? 0 : (1 << 8);
1108
1109         l |= five_taps ? (1 << 21) : 0;
1110         l |= five_taps ? (1 << 22) : 0;
1111
1112         dispc_write_reg(dispc_reg_att[plane], l);
1113
1114         /*
1115          * field 0 = even field = bottom field
1116          * field 1 = odd field = top field
1117          */
1118         if (ilace && !fieldmode) {
1119                 accu1 = 0;
1120                 accu0 = (fir_vinc / 2) & 0x3ff;
1121                 if (accu0 >= 1024/2) {
1122                         accu1 = 1024/2;
1123                         accu0 -= accu1;
1124                 }
1125         }
1126
1127         _dispc_set_vid_accu0(plane, 0, accu0);
1128         _dispc_set_vid_accu1(plane, 0, accu1);
1129 }
1130
1131 static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1132                 bool mirroring, enum omap_color_mode color_mode)
1133 {
1134         if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1135                         color_mode == OMAP_DSS_COLOR_UYVY) {
1136                 int vidrot = 0;
1137
1138                 if (mirroring) {
1139                         switch (rotation) {
1140                         case OMAP_DSS_ROT_0:
1141                                 vidrot = 2;
1142                                 break;
1143                         case OMAP_DSS_ROT_90:
1144                                 vidrot = 1;
1145                                 break;
1146                         case OMAP_DSS_ROT_180:
1147                                 vidrot = 0;
1148                                 break;
1149                         case OMAP_DSS_ROT_270:
1150                                 vidrot = 3;
1151                                 break;
1152                         }
1153                 } else {
1154                         switch (rotation) {
1155                         case OMAP_DSS_ROT_0:
1156                                 vidrot = 0;
1157                                 break;
1158                         case OMAP_DSS_ROT_90:
1159                                 vidrot = 1;
1160                                 break;
1161                         case OMAP_DSS_ROT_180:
1162                                 vidrot = 2;
1163                                 break;
1164                         case OMAP_DSS_ROT_270:
1165                                 vidrot = 3;
1166                                 break;
1167                         }
1168                 }
1169
1170                 REG_FLD_MOD(dispc_reg_att[plane], vidrot, 13, 12);
1171
1172                 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
1173                         REG_FLD_MOD(dispc_reg_att[plane], 0x1, 18, 18);
1174                 else
1175                         REG_FLD_MOD(dispc_reg_att[plane], 0x0, 18, 18);
1176         } else {
1177                 REG_FLD_MOD(dispc_reg_att[plane], 0, 13, 12);
1178                 REG_FLD_MOD(dispc_reg_att[plane], 0, 18, 18);
1179         }
1180 }
1181
1182 static int color_mode_to_bpp(enum omap_color_mode color_mode)
1183 {
1184         switch (color_mode) {
1185         case OMAP_DSS_COLOR_CLUT1:
1186                 return 1;
1187         case OMAP_DSS_COLOR_CLUT2:
1188                 return 2;
1189         case OMAP_DSS_COLOR_CLUT4:
1190                 return 4;
1191         case OMAP_DSS_COLOR_CLUT8:
1192                 return 8;
1193         case OMAP_DSS_COLOR_RGB12U:
1194         case OMAP_DSS_COLOR_RGB16:
1195         case OMAP_DSS_COLOR_ARGB16:
1196         case OMAP_DSS_COLOR_YUV2:
1197         case OMAP_DSS_COLOR_UYVY:
1198                 return 16;
1199         case OMAP_DSS_COLOR_RGB24P:
1200                 return 24;
1201         case OMAP_DSS_COLOR_RGB24U:
1202         case OMAP_DSS_COLOR_ARGB32:
1203         case OMAP_DSS_COLOR_RGBA32:
1204         case OMAP_DSS_COLOR_RGBX32:
1205                 return 32;
1206         default:
1207                 BUG();
1208         }
1209 }
1210
1211 static s32 pixinc(int pixels, u8 ps)
1212 {
1213         if (pixels == 1)
1214                 return 1;
1215         else if (pixels > 1)
1216                 return 1 + (pixels - 1) * ps;
1217         else if (pixels < 0)
1218                 return 1 - (-pixels + 1) * ps;
1219         else
1220                 BUG();
1221 }
1222
1223 static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1224                 u16 screen_width,
1225                 u16 width, u16 height,
1226                 enum omap_color_mode color_mode, bool fieldmode,
1227                 unsigned int field_offset,
1228                 unsigned *offset0, unsigned *offset1,
1229                 s32 *row_inc, s32 *pix_inc)
1230 {
1231         u8 ps;
1232
1233         /* FIXME CLUT formats */
1234         switch (color_mode) {
1235         case OMAP_DSS_COLOR_CLUT1:
1236         case OMAP_DSS_COLOR_CLUT2:
1237         case OMAP_DSS_COLOR_CLUT4:
1238         case OMAP_DSS_COLOR_CLUT8:
1239                 BUG();
1240                 return;
1241         case OMAP_DSS_COLOR_YUV2:
1242         case OMAP_DSS_COLOR_UYVY:
1243                 ps = 4;
1244                 break;
1245         default:
1246                 ps = color_mode_to_bpp(color_mode) / 8;
1247                 break;
1248         }
1249
1250         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1251                         width, height);
1252
1253         /*
1254          * field 0 = even field = bottom field
1255          * field 1 = odd field = top field
1256          */
1257         switch (rotation + mirror * 4) {
1258         case OMAP_DSS_ROT_0:
1259         case OMAP_DSS_ROT_180:
1260                 /*
1261                  * If the pixel format is YUV or UYVY divide the width
1262                  * of the image by 2 for 0 and 180 degree rotation.
1263                  */
1264                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1265                         color_mode == OMAP_DSS_COLOR_UYVY)
1266                         width = width >> 1;
1267         case OMAP_DSS_ROT_90:
1268         case OMAP_DSS_ROT_270:
1269                 *offset1 = 0;
1270                 if (field_offset)
1271                         *offset0 = field_offset * screen_width * ps;
1272                 else
1273                         *offset0 = 0;
1274
1275                 *row_inc = pixinc(1 + (screen_width - width) +
1276                                 (fieldmode ? screen_width : 0),
1277                                 ps);
1278                 *pix_inc = pixinc(1, ps);
1279                 break;
1280
1281         case OMAP_DSS_ROT_0 + 4:
1282         case OMAP_DSS_ROT_180 + 4:
1283                 /* If the pixel format is YUV or UYVY divide the width
1284                  * of the image by 2  for 0 degree and 180 degree
1285                  */
1286                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1287                         color_mode == OMAP_DSS_COLOR_UYVY)
1288                         width = width >> 1;
1289         case OMAP_DSS_ROT_90 + 4:
1290         case OMAP_DSS_ROT_270 + 4:
1291                 *offset1 = 0;
1292                 if (field_offset)
1293                         *offset0 = field_offset * screen_width * ps;
1294                 else
1295                         *offset0 = 0;
1296                 *row_inc = pixinc(1 - (screen_width + width) -
1297                                 (fieldmode ? screen_width : 0),
1298                                 ps);
1299                 *pix_inc = pixinc(1, ps);
1300                 break;
1301
1302         default:
1303                 BUG();
1304         }
1305 }
1306
1307 static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1308                 u16 screen_width,
1309                 u16 width, u16 height,
1310                 enum omap_color_mode color_mode, bool fieldmode,
1311                 unsigned int field_offset,
1312                 unsigned *offset0, unsigned *offset1,
1313                 s32 *row_inc, s32 *pix_inc)
1314 {
1315         u8 ps;
1316         u16 fbw, fbh;
1317
1318         /* FIXME CLUT formats */
1319         switch (color_mode) {
1320         case OMAP_DSS_COLOR_CLUT1:
1321         case OMAP_DSS_COLOR_CLUT2:
1322         case OMAP_DSS_COLOR_CLUT4:
1323         case OMAP_DSS_COLOR_CLUT8:
1324                 BUG();
1325                 return;
1326         default:
1327                 ps = color_mode_to_bpp(color_mode) / 8;
1328                 break;
1329         }
1330
1331         DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1332                         width, height);
1333
1334         /* width & height are overlay sizes, convert to fb sizes */
1335
1336         if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1337                 fbw = width;
1338                 fbh = height;
1339         } else {
1340                 fbw = height;
1341                 fbh = width;
1342         }
1343
1344         /*
1345          * field 0 = even field = bottom field
1346          * field 1 = odd field = top field
1347          */
1348         switch (rotation + mirror * 4) {
1349         case OMAP_DSS_ROT_0:
1350                 *offset1 = 0;
1351                 if (field_offset)
1352                         *offset0 = *offset1 + field_offset * screen_width * ps;
1353                 else
1354                         *offset0 = *offset1;
1355                 *row_inc = pixinc(1 + (screen_width - fbw) +
1356                                 (fieldmode ? screen_width : 0),
1357                                 ps);
1358                 *pix_inc = pixinc(1, ps);
1359                 break;
1360         case OMAP_DSS_ROT_90:
1361                 *offset1 = screen_width * (fbh - 1) * ps;
1362                 if (field_offset)
1363                         *offset0 = *offset1 + field_offset * ps;
1364                 else
1365                         *offset0 = *offset1;
1366                 *row_inc = pixinc(screen_width * (fbh - 1) + 1 +
1367                                 (fieldmode ? 1 : 0), ps);
1368                 *pix_inc = pixinc(-screen_width, ps);
1369                 break;
1370         case OMAP_DSS_ROT_180:
1371                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1372                 if (field_offset)
1373                         *offset0 = *offset1 - field_offset * screen_width * ps;
1374                 else
1375                         *offset0 = *offset1;
1376                 *row_inc = pixinc(-1 -
1377                                 (screen_width - fbw) -
1378                                 (fieldmode ? screen_width : 0),
1379                                 ps);
1380                 *pix_inc = pixinc(-1, ps);
1381                 break;
1382         case OMAP_DSS_ROT_270:
1383                 *offset1 = (fbw - 1) * ps;
1384                 if (field_offset)
1385                         *offset0 = *offset1 - field_offset * ps;
1386                 else
1387                         *offset0 = *offset1;
1388                 *row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
1389                                 (fieldmode ? 1 : 0), ps);
1390                 *pix_inc = pixinc(screen_width, ps);
1391                 break;
1392
1393         /* mirroring */
1394         case OMAP_DSS_ROT_0 + 4:
1395                 *offset1 = (fbw - 1) * ps;
1396                 if (field_offset)
1397                         *offset0 = *offset1 + field_offset * screen_width * ps;
1398                 else
1399                         *offset0 = *offset1;
1400                 *row_inc = pixinc(screen_width * 2 - 1 +
1401                                 (fieldmode ? screen_width : 0),
1402                                 ps);
1403                 *pix_inc = pixinc(-1, ps);
1404                 break;
1405
1406         case OMAP_DSS_ROT_90 + 4:
1407                 *offset1 = 0;
1408                 if (field_offset)
1409                         *offset0 = *offset1 + field_offset * ps;
1410                 else
1411                         *offset0 = *offset1;
1412                 *row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
1413                                 (fieldmode ? 1 : 0),
1414                                 ps);
1415                 *pix_inc = pixinc(screen_width, ps);
1416                 break;
1417
1418         case OMAP_DSS_ROT_180 + 4:
1419                 *offset1 = screen_width * (fbh - 1) * ps;
1420                 if (field_offset)
1421                         *offset0 = *offset1 - field_offset * screen_width * ps;
1422                 else
1423                         *offset0 = *offset1;
1424                 *row_inc = pixinc(1 - screen_width * 2 -
1425                                 (fieldmode ? screen_width : 0),
1426                                 ps);
1427                 *pix_inc = pixinc(1, ps);
1428                 break;
1429
1430         case OMAP_DSS_ROT_270 + 4:
1431                 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1432                 if (field_offset)
1433                         *offset0 = *offset1 - field_offset * ps;
1434                 else
1435                         *offset0 = *offset1;
1436                 *row_inc = pixinc(screen_width * (fbh - 1) - 1 -
1437                                 (fieldmode ? 1 : 0),
1438                                 ps);
1439                 *pix_inc = pixinc(-screen_width, ps);
1440                 break;
1441
1442         default:
1443                 BUG();
1444         }
1445 }
1446
1447 static unsigned long calc_fclk_five_taps(u16 width, u16 height,
1448                 u16 out_width, u16 out_height, enum omap_color_mode color_mode)
1449 {
1450         u32 fclk = 0;
1451         /* FIXME venc pclk? */
1452         u64 tmp, pclk = dispc_pclk_rate();
1453
1454         if (height > out_height) {
1455                 /* FIXME get real display PPL */
1456                 unsigned int ppl = 800;
1457
1458                 tmp = pclk * height * out_width;
1459                 do_div(tmp, 2 * out_height * ppl);
1460                 fclk = tmp;
1461
1462                 if (height > 2 * out_height) {
1463                         if (ppl == out_width)
1464                                 return 0;
1465
1466                         tmp = pclk * (height - 2 * out_height) * out_width;
1467                         do_div(tmp, 2 * out_height * (ppl - out_width));
1468                         fclk = max(fclk, (u32) tmp);
1469                 }
1470         }
1471
1472         if (width > out_width) {
1473                 tmp = pclk * width;
1474                 do_div(tmp, out_width);
1475                 fclk = max(fclk, (u32) tmp);
1476
1477                 if (color_mode == OMAP_DSS_COLOR_RGB24U)
1478                         fclk <<= 1;
1479         }
1480
1481         return fclk;
1482 }
1483
1484 static unsigned long calc_fclk(u16 width, u16 height,
1485                 u16 out_width, u16 out_height)
1486 {
1487         unsigned int hf, vf;
1488
1489         /*
1490          * FIXME how to determine the 'A' factor
1491          * for the no downscaling case ?
1492          */
1493
1494         if (width > 3 * out_width)
1495                 hf = 4;
1496         else if (width > 2 * out_width)
1497                 hf = 3;
1498         else if (width > out_width)
1499                 hf = 2;
1500         else
1501                 hf = 1;
1502
1503         if (height > out_height)
1504                 vf = 2;
1505         else
1506                 vf = 1;
1507
1508         /* FIXME venc pclk? */
1509         return dispc_pclk_rate() * vf * hf;
1510 }
1511
1512 void dispc_set_channel_out(enum omap_plane plane, enum omap_channel channel_out)
1513 {
1514         enable_clocks(1);
1515         _dispc_set_channel_out(plane, channel_out);
1516         enable_clocks(0);
1517 }
1518
1519 static int _dispc_setup_plane(enum omap_plane plane,
1520                 u32 paddr, u16 screen_width,
1521                 u16 pos_x, u16 pos_y,
1522                 u16 width, u16 height,
1523                 u16 out_width, u16 out_height,
1524                 enum omap_color_mode color_mode,
1525                 bool ilace,
1526                 enum omap_dss_rotation_type rotation_type,
1527                 u8 rotation, int mirror,
1528                 u8 global_alpha,
1529                 u8 pre_mult_alpha)
1530 {
1531         const int maxdownscale = cpu_is_omap34xx() ? 4 : 2;
1532         bool five_taps = 0;
1533         bool fieldmode = 0;
1534         int cconv = 0;
1535         unsigned offset0, offset1;
1536         s32 row_inc;
1537         s32 pix_inc;
1538         u16 frame_height = height;
1539         unsigned int field_offset = 0;
1540
1541         if (paddr == 0)
1542                 return -EINVAL;
1543
1544         if (ilace && height == out_height)
1545                 fieldmode = 1;
1546
1547         if (ilace) {
1548                 if (fieldmode)
1549                         height /= 2;
1550                 pos_y /= 2;
1551                 out_height /= 2;
1552
1553                 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
1554                                 "out_height %d\n",
1555                                 height, pos_y, out_height);
1556         }
1557
1558         if (!dss_feat_color_mode_supported(plane, color_mode))
1559                 return -EINVAL;
1560
1561         if (plane == OMAP_DSS_GFX) {
1562                 if (width != out_width || height != out_height)
1563                         return -EINVAL;
1564         } else {
1565                 /* video plane */
1566
1567                 unsigned long fclk = 0;
1568
1569                 if (out_width < width / maxdownscale ||
1570                    out_width > width * 8)
1571                         return -EINVAL;
1572
1573                 if (out_height < height / maxdownscale ||
1574                    out_height > height * 8)
1575                         return -EINVAL;
1576
1577                 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1578                         color_mode == OMAP_DSS_COLOR_UYVY)
1579                         cconv = 1;
1580
1581                 /* Must use 5-tap filter? */
1582                 five_taps = height > out_height * 2;
1583
1584                 if (!five_taps) {
1585                         fclk = calc_fclk(width, height,
1586                                         out_width, out_height);
1587
1588                         /* Try 5-tap filter if 3-tap fclk is too high */
1589                         if (cpu_is_omap34xx() && height > out_height &&
1590                                         fclk > dispc_fclk_rate())
1591                                 five_taps = true;
1592                 }
1593
1594                 if (width > (2048 >> five_taps)) {
1595                         DSSERR("failed to set up scaling, fclk too low\n");
1596                         return -EINVAL;
1597                 }
1598
1599                 if (five_taps)
1600                         fclk = calc_fclk_five_taps(width, height,
1601                                         out_width, out_height, color_mode);
1602
1603                 DSSDBG("required fclk rate = %lu Hz\n", fclk);
1604                 DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
1605
1606                 if (!fclk || fclk > dispc_fclk_rate()) {
1607                         DSSERR("failed to set up scaling, "
1608                                         "required fclk rate = %lu Hz, "
1609                                         "current fclk rate = %lu Hz\n",
1610                                         fclk, dispc_fclk_rate());
1611                         return -EINVAL;
1612                 }
1613         }
1614
1615         if (ilace && !fieldmode) {
1616                 /*
1617                  * when downscaling the bottom field may have to start several
1618                  * source lines below the top field. Unfortunately ACCUI
1619                  * registers will only hold the fractional part of the offset
1620                  * so the integer part must be added to the base address of the
1621                  * bottom field.
1622                  */
1623                 if (!height || height == out_height)
1624                         field_offset = 0;
1625                 else
1626                         field_offset = height / out_height / 2;
1627         }
1628
1629         /* Fields are independent but interleaved in memory. */
1630         if (fieldmode)
1631                 field_offset = 1;
1632
1633         if (rotation_type == OMAP_DSS_ROT_DMA)
1634                 calc_dma_rotation_offset(rotation, mirror,
1635                                 screen_width, width, frame_height, color_mode,
1636                                 fieldmode, field_offset,
1637                                 &offset0, &offset1, &row_inc, &pix_inc);
1638         else
1639                 calc_vrfb_rotation_offset(rotation, mirror,
1640                                 screen_width, width, frame_height, color_mode,
1641                                 fieldmode, field_offset,
1642                                 &offset0, &offset1, &row_inc, &pix_inc);
1643
1644         DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
1645                         offset0, offset1, row_inc, pix_inc);
1646
1647         _dispc_set_color_mode(plane, color_mode);
1648
1649         _dispc_set_plane_ba0(plane, paddr + offset0);
1650         _dispc_set_plane_ba1(plane, paddr + offset1);
1651
1652         _dispc_set_row_inc(plane, row_inc);
1653         _dispc_set_pix_inc(plane, pix_inc);
1654
1655         DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, width, height,
1656                         out_width, out_height);
1657
1658         _dispc_set_plane_pos(plane, pos_x, pos_y);
1659
1660         _dispc_set_pic_size(plane, width, height);
1661
1662         if (plane != OMAP_DSS_GFX) {
1663                 _dispc_set_scaling(plane, width, height,
1664                                    out_width, out_height,
1665                                    ilace, five_taps, fieldmode);
1666                 _dispc_set_vid_size(plane, out_width, out_height);
1667                 _dispc_set_vid_color_conv(plane, cconv);
1668         }
1669
1670         _dispc_set_rotation_attrs(plane, rotation, mirror, color_mode);
1671
1672         _dispc_set_pre_mult_alpha(plane, pre_mult_alpha);
1673         _dispc_setup_global_alpha(plane, global_alpha);
1674
1675         return 0;
1676 }
1677
1678 static void _dispc_enable_plane(enum omap_plane plane, bool enable)
1679 {
1680         REG_FLD_MOD(dispc_reg_att[plane], enable ? 1 : 0, 0, 0);
1681 }
1682
1683 static void dispc_disable_isr(void *data, u32 mask)
1684 {
1685         struct completion *compl = data;
1686         complete(compl);
1687 }
1688
1689 static void _enable_lcd_out(bool enable)
1690 {
1691         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
1692 }
1693
1694 static void dispc_enable_lcd_out(bool enable)
1695 {
1696         struct completion frame_done_completion;
1697         bool is_on;
1698         int r;
1699
1700         enable_clocks(1);
1701
1702         /* When we disable LCD output, we need to wait until frame is done.
1703          * Otherwise the DSS is still working, and turning off the clocks
1704          * prevents DSS from going to OFF mode */
1705         is_on = REG_GET(DISPC_CONTROL, 0, 0);
1706
1707         if (!enable && is_on) {
1708                 init_completion(&frame_done_completion);
1709
1710                 r = omap_dispc_register_isr(dispc_disable_isr,
1711                                 &frame_done_completion,
1712                                 DISPC_IRQ_FRAMEDONE);
1713
1714                 if (r)
1715                         DSSERR("failed to register FRAMEDONE isr\n");
1716         }
1717
1718         _enable_lcd_out(enable);
1719
1720         if (!enable && is_on) {
1721                 if (!wait_for_completion_timeout(&frame_done_completion,
1722                                         msecs_to_jiffies(100)))
1723                         DSSERR("timeout waiting for FRAME DONE\n");
1724
1725                 r = omap_dispc_unregister_isr(dispc_disable_isr,
1726                                 &frame_done_completion,
1727                                 DISPC_IRQ_FRAMEDONE);
1728
1729                 if (r)
1730                         DSSERR("failed to unregister FRAMEDONE isr\n");
1731         }
1732
1733         enable_clocks(0);
1734 }
1735
1736 static void _enable_digit_out(bool enable)
1737 {
1738         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
1739 }
1740
1741 static void dispc_enable_digit_out(bool enable)
1742 {
1743         struct completion frame_done_completion;
1744         int r;
1745
1746         enable_clocks(1);
1747
1748         if (REG_GET(DISPC_CONTROL, 1, 1) == enable) {
1749                 enable_clocks(0);
1750                 return;
1751         }
1752
1753         if (enable) {
1754                 unsigned long flags;
1755                 /* When we enable digit output, we'll get an extra digit
1756                  * sync lost interrupt, that we need to ignore */
1757                 spin_lock_irqsave(&dispc.irq_lock, flags);
1758                 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
1759                 _omap_dispc_set_irqs();
1760                 spin_unlock_irqrestore(&dispc.irq_lock, flags);
1761         }
1762
1763         /* When we disable digit output, we need to wait until fields are done.
1764          * Otherwise the DSS is still working, and turning off the clocks
1765          * prevents DSS from going to OFF mode. And when enabling, we need to
1766          * wait for the extra sync losts */
1767         init_completion(&frame_done_completion);
1768
1769         r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
1770                         DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1771         if (r)
1772                 DSSERR("failed to register EVSYNC isr\n");
1773
1774         _enable_digit_out(enable);
1775
1776         /* XXX I understand from TRM that we should only wait for the
1777          * current field to complete. But it seems we have to wait
1778          * for both fields */
1779         if (!wait_for_completion_timeout(&frame_done_completion,
1780                                 msecs_to_jiffies(100)))
1781                 DSSERR("timeout waiting for EVSYNC\n");
1782
1783         if (!wait_for_completion_timeout(&frame_done_completion,
1784                                 msecs_to_jiffies(100)))
1785                 DSSERR("timeout waiting for EVSYNC\n");
1786
1787         r = omap_dispc_unregister_isr(dispc_disable_isr,
1788                         &frame_done_completion,
1789                         DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1790         if (r)
1791                 DSSERR("failed to unregister EVSYNC isr\n");
1792
1793         if (enable) {
1794                 unsigned long flags;
1795                 spin_lock_irqsave(&dispc.irq_lock, flags);
1796                 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
1797                 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
1798                 _omap_dispc_set_irqs();
1799                 spin_unlock_irqrestore(&dispc.irq_lock, flags);
1800         }
1801
1802         enable_clocks(0);
1803 }
1804
1805 bool dispc_is_channel_enabled(enum omap_channel channel)
1806 {
1807         if (channel == OMAP_DSS_CHANNEL_LCD)
1808                 return !!REG_GET(DISPC_CONTROL, 0, 0);
1809         else if (channel == OMAP_DSS_CHANNEL_DIGIT)
1810                 return !!REG_GET(DISPC_CONTROL, 1, 1);
1811         else
1812                 BUG();
1813 }
1814
1815 void dispc_enable_channel(enum omap_channel channel, bool enable)
1816 {
1817         if (channel == OMAP_DSS_CHANNEL_LCD)
1818                 dispc_enable_lcd_out(enable);
1819         else if (channel == OMAP_DSS_CHANNEL_DIGIT)
1820                 dispc_enable_digit_out(enable);
1821         else
1822                 BUG();
1823 }
1824
1825 void dispc_lcd_enable_signal_polarity(bool act_high)
1826 {
1827         enable_clocks(1);
1828         REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
1829         enable_clocks(0);
1830 }
1831
1832 void dispc_lcd_enable_signal(bool enable)
1833 {
1834         enable_clocks(1);
1835         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
1836         enable_clocks(0);
1837 }
1838
1839 void dispc_pck_free_enable(bool enable)
1840 {
1841         enable_clocks(1);
1842         REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
1843         enable_clocks(0);
1844 }
1845
1846 void dispc_enable_fifohandcheck(enum omap_channel channel, bool enable)
1847 {
1848         enable_clocks(1);
1849         REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
1850         enable_clocks(0);
1851 }
1852
1853
1854 void dispc_set_lcd_display_type(enum omap_channel channel,
1855                 enum omap_lcd_display_type type)
1856 {
1857         int mode;
1858
1859         switch (type) {
1860         case OMAP_DSS_LCD_DISPLAY_STN:
1861                 mode = 0;
1862                 break;
1863
1864         case OMAP_DSS_LCD_DISPLAY_TFT:
1865                 mode = 1;
1866                 break;
1867
1868         default:
1869                 BUG();
1870                 return;
1871         }
1872
1873         enable_clocks(1);
1874         REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
1875         enable_clocks(0);
1876 }
1877
1878 void dispc_set_loadmode(enum omap_dss_load_mode mode)
1879 {
1880         enable_clocks(1);
1881         REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
1882         enable_clocks(0);
1883 }
1884
1885
1886 void dispc_set_default_color(enum omap_channel channel, u32 color)
1887 {
1888         enable_clocks(1);
1889         dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
1890         enable_clocks(0);
1891 }
1892
1893 u32 dispc_get_default_color(enum omap_channel channel)
1894 {
1895         u32 l;
1896
1897         BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT &&
1898                channel != OMAP_DSS_CHANNEL_LCD);
1899
1900         enable_clocks(1);
1901         l = dispc_read_reg(DISPC_DEFAULT_COLOR(channel));
1902         enable_clocks(0);
1903
1904         return l;
1905 }
1906
1907 void dispc_set_trans_key(enum omap_channel ch,
1908                 enum omap_dss_trans_key_type type,
1909                 u32 trans_key)
1910 {
1911         enable_clocks(1);
1912         if (ch == OMAP_DSS_CHANNEL_LCD)
1913                 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
1914         else /* OMAP_DSS_CHANNEL_DIGIT */
1915                 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
1916
1917         dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
1918         enable_clocks(0);
1919 }
1920
1921 void dispc_get_trans_key(enum omap_channel ch,
1922                 enum omap_dss_trans_key_type *type,
1923                 u32 *trans_key)
1924 {
1925         enable_clocks(1);
1926         if (type) {
1927                 if (ch == OMAP_DSS_CHANNEL_LCD)
1928                         *type = REG_GET(DISPC_CONFIG, 11, 11);
1929                 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
1930                         *type = REG_GET(DISPC_CONFIG, 13, 13);
1931                 else
1932                         BUG();
1933         }
1934
1935         if (trans_key)
1936                 *trans_key = dispc_read_reg(DISPC_TRANS_COLOR(ch));
1937         enable_clocks(0);
1938 }
1939
1940 void dispc_enable_trans_key(enum omap_channel ch, bool enable)
1941 {
1942         enable_clocks(1);
1943         if (ch == OMAP_DSS_CHANNEL_LCD)
1944                 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
1945         else /* OMAP_DSS_CHANNEL_DIGIT */
1946                 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
1947         enable_clocks(0);
1948 }
1949 void dispc_enable_alpha_blending(enum omap_channel ch, bool enable)
1950 {
1951         if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
1952                 return;
1953
1954         enable_clocks(1);
1955         if (ch == OMAP_DSS_CHANNEL_LCD)
1956                 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
1957         else /* OMAP_DSS_CHANNEL_DIGIT */
1958                 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
1959         enable_clocks(0);
1960 }
1961 bool dispc_alpha_blending_enabled(enum omap_channel ch)
1962 {
1963         bool enabled;
1964
1965         if (!dss_has_feature(FEAT_GLOBAL_ALPHA))
1966                 return false;
1967
1968         enable_clocks(1);
1969         if (ch == OMAP_DSS_CHANNEL_LCD)
1970                 enabled = REG_GET(DISPC_CONFIG, 18, 18);
1971         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
1972                 enabled = REG_GET(DISPC_CONFIG, 19, 19);
1973         else
1974                 BUG();
1975         enable_clocks(0);
1976
1977         return enabled;
1978 }
1979
1980
1981 bool dispc_trans_key_enabled(enum omap_channel ch)
1982 {
1983         bool enabled;
1984
1985         enable_clocks(1);
1986         if (ch == OMAP_DSS_CHANNEL_LCD)
1987                 enabled = REG_GET(DISPC_CONFIG, 10, 10);
1988         else if (ch == OMAP_DSS_CHANNEL_DIGIT)
1989                 enabled = REG_GET(DISPC_CONFIG, 12, 12);
1990         else
1991                 BUG();
1992         enable_clocks(0);
1993
1994         return enabled;
1995 }
1996
1997
1998 void dispc_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
1999 {
2000         int code;
2001
2002         switch (data_lines) {
2003         case 12:
2004                 code = 0;
2005                 break;
2006         case 16:
2007                 code = 1;
2008                 break;
2009         case 18:
2010                 code = 2;
2011                 break;
2012         case 24:
2013                 code = 3;
2014                 break;
2015         default:
2016                 BUG();
2017                 return;
2018         }
2019
2020         enable_clocks(1);
2021         REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
2022         enable_clocks(0);
2023 }
2024
2025 void dispc_set_parallel_interface_mode(enum omap_channel channel,
2026                 enum omap_parallel_interface_mode mode)
2027 {
2028         u32 l;
2029         int stallmode;
2030         int gpout0 = 1;
2031         int gpout1;
2032
2033         switch (mode) {
2034         case OMAP_DSS_PARALLELMODE_BYPASS:
2035                 stallmode = 0;
2036                 gpout1 = 1;
2037                 break;
2038
2039         case OMAP_DSS_PARALLELMODE_RFBI:
2040                 stallmode = 1;
2041                 gpout1 = 0;
2042                 break;
2043
2044         case OMAP_DSS_PARALLELMODE_DSI:
2045                 stallmode = 1;
2046                 gpout1 = 1;
2047                 break;
2048
2049         default:
2050                 BUG();
2051                 return;
2052         }
2053
2054         enable_clocks(1);
2055
2056         l = dispc_read_reg(DISPC_CONTROL);
2057
2058         l = FLD_MOD(l, stallmode, 11, 11);
2059
2060         if (channel == OMAP_DSS_CHANNEL_LCD) {
2061                 l = FLD_MOD(l, gpout0, 15, 15);
2062                 l = FLD_MOD(l, gpout1, 16, 16);
2063         }
2064         dispc_write_reg(DISPC_CONTROL, l);
2065
2066         enable_clocks(0);
2067 }
2068
2069 static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2070                 int vsw, int vfp, int vbp)
2071 {
2072         if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2073                 if (hsw < 1 || hsw > 64 ||
2074                                 hfp < 1 || hfp > 256 ||
2075                                 hbp < 1 || hbp > 256 ||
2076                                 vsw < 1 || vsw > 64 ||
2077                                 vfp < 0 || vfp > 255 ||
2078                                 vbp < 0 || vbp > 255)
2079                         return false;
2080         } else {
2081                 if (hsw < 1 || hsw > 256 ||
2082                                 hfp < 1 || hfp > 4096 ||
2083                                 hbp < 1 || hbp > 4096 ||
2084                                 vsw < 1 || vsw > 256 ||
2085                                 vfp < 0 || vfp > 4095 ||
2086                                 vbp < 0 || vbp > 4095)
2087                         return false;
2088         }
2089
2090         return true;
2091 }
2092
2093 bool dispc_lcd_timings_ok(struct omap_video_timings *timings)
2094 {
2095         return _dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2096                         timings->hbp, timings->vsw,
2097                         timings->vfp, timings->vbp);
2098 }
2099
2100 static void _dispc_set_lcd_timings(enum omap_channel channel, int hsw,
2101                 int hfp, int hbp, int vsw, int vfp, int vbp)
2102 {
2103         u32 timing_h, timing_v;
2104
2105         if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2106                 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
2107                         FLD_VAL(hbp-1, 27, 20);
2108
2109                 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
2110                         FLD_VAL(vbp, 27, 20);
2111         } else {
2112                 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
2113                         FLD_VAL(hbp-1, 31, 20);
2114
2115                 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
2116                         FLD_VAL(vbp, 31, 20);
2117         }
2118
2119         enable_clocks(1);
2120         dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2121         dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
2122         enable_clocks(0);
2123 }
2124
2125 /* change name to mode? */
2126 void dispc_set_lcd_timings(enum omap_channel channel,
2127                 struct omap_video_timings *timings)
2128 {
2129         unsigned xtot, ytot;
2130         unsigned long ht, vt;
2131
2132         if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2133                                 timings->hbp, timings->vsw,
2134                                 timings->vfp, timings->vbp))
2135                 BUG();
2136
2137         _dispc_set_lcd_timings(channel, timings->hsw, timings->hfp,
2138                         timings->hbp, timings->vsw, timings->vfp,
2139                         timings->vbp);
2140
2141         dispc_set_lcd_size(channel, timings->x_res, timings->y_res);
2142
2143         xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
2144         ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
2145
2146         ht = (timings->pixel_clock * 1000) / xtot;
2147         vt = (timings->pixel_clock * 1000) / xtot / ytot;
2148
2149         DSSDBG("xres %u yres %u\n", timings->x_res, timings->y_res);
2150         DSSDBG("pck %u\n", timings->pixel_clock);
2151         DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2152                         timings->hsw, timings->hfp, timings->hbp,
2153                         timings->vsw, timings->vfp, timings->vbp);
2154
2155         DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2156 }
2157
2158 static void dispc_set_lcd_divisor(u16 lck_div, u16 pck_div)
2159 {
2160         BUG_ON(lck_div < 1);
2161         BUG_ON(pck_div < 2);
2162
2163         enable_clocks(1);
2164         dispc_write_reg(DISPC_DIVISOR(OMAP_DSS_CHANNEL_LCD),
2165                         FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
2166         enable_clocks(0);
2167 }
2168
2169 static void dispc_get_lcd_divisor(int *lck_div, int *pck_div)
2170 {
2171         u32 l;
2172         l = dispc_read_reg(DISPC_DIVISOR(OMAP_DSS_CHANNEL_LCD));
2173         *lck_div = FLD_GET(l, 23, 16);
2174         *pck_div = FLD_GET(l, 7, 0);
2175 }
2176
2177 unsigned long dispc_fclk_rate(void)
2178 {
2179         unsigned long r = 0;
2180
2181         if (dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK)
2182                 r = dss_clk_get_rate(DSS_CLK_FCK1);
2183         else
2184 #ifdef CONFIG_OMAP2_DSS_DSI
2185                 r = dsi_get_dsi1_pll_rate();
2186 #else
2187         BUG();
2188 #endif
2189         return r;
2190 }
2191
2192 unsigned long dispc_lclk_rate(void)
2193 {
2194         int lcd;
2195         unsigned long r;
2196         u32 l;
2197
2198         l = dispc_read_reg(DISPC_DIVISOR(OMAP_DSS_CHANNEL_LCD));
2199
2200         lcd = FLD_GET(l, 23, 16);
2201
2202         r = dispc_fclk_rate();
2203
2204         return r / lcd;
2205 }
2206
2207 unsigned long dispc_pclk_rate(void)
2208 {
2209         int lcd, pcd;
2210         unsigned long r;
2211         u32 l;
2212
2213         l = dispc_read_reg(DISPC_DIVISOR(OMAP_DSS_CHANNEL_LCD));
2214
2215         lcd = FLD_GET(l, 23, 16);
2216         pcd = FLD_GET(l, 7, 0);
2217
2218         r = dispc_fclk_rate();
2219
2220         return r / lcd / pcd;
2221 }
2222
2223 void dispc_dump_clocks(struct seq_file *s)
2224 {
2225         int lcd, pcd;
2226
2227         enable_clocks(1);
2228
2229         dispc_get_lcd_divisor(&lcd, &pcd);
2230
2231         seq_printf(s, "- DISPC -\n");
2232
2233         seq_printf(s, "dispc fclk source = %s\n",
2234                         dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ?
2235                         "dss1_alwon_fclk" : "dsi1_pll_fclk");
2236
2237         seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2238         seq_printf(s, "lck\t\t%-16lulck div\t%u\n", dispc_lclk_rate(), lcd);
2239         seq_printf(s, "pck\t\t%-16lupck div\t%u\n", dispc_pclk_rate(), pcd);
2240
2241         enable_clocks(0);
2242 }
2243
2244 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2245 void dispc_dump_irqs(struct seq_file *s)
2246 {
2247         unsigned long flags;
2248         struct dispc_irq_stats stats;
2249
2250         spin_lock_irqsave(&dispc.irq_stats_lock, flags);
2251
2252         stats = dispc.irq_stats;
2253         memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
2254         dispc.irq_stats.last_reset = jiffies;
2255
2256         spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
2257
2258         seq_printf(s, "period %u ms\n",
2259                         jiffies_to_msecs(jiffies - stats.last_reset));
2260
2261         seq_printf(s, "irqs %d\n", stats.irq_count);
2262 #define PIS(x) \
2263         seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
2264
2265         PIS(FRAMEDONE);
2266         PIS(VSYNC);
2267         PIS(EVSYNC_EVEN);
2268         PIS(EVSYNC_ODD);
2269         PIS(ACBIAS_COUNT_STAT);
2270         PIS(PROG_LINE_NUM);
2271         PIS(GFX_FIFO_UNDERFLOW);
2272         PIS(GFX_END_WIN);
2273         PIS(PAL_GAMMA_MASK);
2274         PIS(OCP_ERR);
2275         PIS(VID1_FIFO_UNDERFLOW);
2276         PIS(VID1_END_WIN);
2277         PIS(VID2_FIFO_UNDERFLOW);
2278         PIS(VID2_END_WIN);
2279         PIS(SYNC_LOST);
2280         PIS(SYNC_LOST_DIGIT);
2281         PIS(WAKEUP);
2282 #undef PIS
2283 }
2284 #endif
2285
2286 void dispc_dump_regs(struct seq_file *s)
2287 {
2288 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dispc_read_reg(r))
2289
2290         dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
2291
2292         DUMPREG(DISPC_REVISION);
2293         DUMPREG(DISPC_SYSCONFIG);
2294         DUMPREG(DISPC_SYSSTATUS);
2295         DUMPREG(DISPC_IRQSTATUS);
2296         DUMPREG(DISPC_IRQENABLE);
2297         DUMPREG(DISPC_CONTROL);
2298         DUMPREG(DISPC_CONFIG);
2299         DUMPREG(DISPC_CAPABLE);
2300         DUMPREG(DISPC_DEFAULT_COLOR(0));
2301         DUMPREG(DISPC_DEFAULT_COLOR(1));
2302         DUMPREG(DISPC_TRANS_COLOR(0));
2303         DUMPREG(DISPC_TRANS_COLOR(1));
2304         DUMPREG(DISPC_LINE_STATUS);
2305         DUMPREG(DISPC_LINE_NUMBER);
2306         DUMPREG(DISPC_TIMING_H(0));
2307         DUMPREG(DISPC_TIMING_V(0));
2308         DUMPREG(DISPC_POL_FREQ(0));
2309         DUMPREG(DISPC_DIVISOR(0));
2310         DUMPREG(DISPC_GLOBAL_ALPHA);
2311         DUMPREG(DISPC_SIZE_DIG);
2312         DUMPREG(DISPC_SIZE_LCD(0));
2313
2314         DUMPREG(DISPC_GFX_BA0);
2315         DUMPREG(DISPC_GFX_BA1);
2316         DUMPREG(DISPC_GFX_POSITION);
2317         DUMPREG(DISPC_GFX_SIZE);
2318         DUMPREG(DISPC_GFX_ATTRIBUTES);
2319         DUMPREG(DISPC_GFX_FIFO_THRESHOLD);
2320         DUMPREG(DISPC_GFX_FIFO_SIZE_STATUS);
2321         DUMPREG(DISPC_GFX_ROW_INC);
2322         DUMPREG(DISPC_GFX_PIXEL_INC);
2323         DUMPREG(DISPC_GFX_WINDOW_SKIP);
2324         DUMPREG(DISPC_GFX_TABLE_BA);
2325
2326         DUMPREG(DISPC_DATA_CYCLE1(0));
2327         DUMPREG(DISPC_DATA_CYCLE2(0));
2328         DUMPREG(DISPC_DATA_CYCLE3(0));
2329
2330         DUMPREG(DISPC_CPR_COEF_R(0));
2331         DUMPREG(DISPC_CPR_COEF_G(0));
2332         DUMPREG(DISPC_CPR_COEF_B(0));
2333
2334         DUMPREG(DISPC_GFX_PRELOAD);
2335
2336         DUMPREG(DISPC_VID_BA0(0));
2337         DUMPREG(DISPC_VID_BA1(0));
2338         DUMPREG(DISPC_VID_POSITION(0));
2339         DUMPREG(DISPC_VID_SIZE(0));
2340         DUMPREG(DISPC_VID_ATTRIBUTES(0));
2341         DUMPREG(DISPC_VID_FIFO_THRESHOLD(0));
2342         DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(0));
2343         DUMPREG(DISPC_VID_ROW_INC(0));
2344         DUMPREG(DISPC_VID_PIXEL_INC(0));
2345         DUMPREG(DISPC_VID_FIR(0));
2346         DUMPREG(DISPC_VID_PICTURE_SIZE(0));
2347         DUMPREG(DISPC_VID_ACCU0(0));
2348         DUMPREG(DISPC_VID_ACCU1(0));
2349
2350         DUMPREG(DISPC_VID_BA0(1));
2351         DUMPREG(DISPC_VID_BA1(1));
2352         DUMPREG(DISPC_VID_POSITION(1));
2353         DUMPREG(DISPC_VID_SIZE(1));
2354         DUMPREG(DISPC_VID_ATTRIBUTES(1));
2355         DUMPREG(DISPC_VID_FIFO_THRESHOLD(1));
2356         DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(1));
2357         DUMPREG(DISPC_VID_ROW_INC(1));
2358         DUMPREG(DISPC_VID_PIXEL_INC(1));
2359         DUMPREG(DISPC_VID_FIR(1));
2360         DUMPREG(DISPC_VID_PICTURE_SIZE(1));
2361         DUMPREG(DISPC_VID_ACCU0(1));
2362         DUMPREG(DISPC_VID_ACCU1(1));
2363
2364         DUMPREG(DISPC_VID_FIR_COEF_H(0, 0));
2365         DUMPREG(DISPC_VID_FIR_COEF_H(0, 1));
2366         DUMPREG(DISPC_VID_FIR_COEF_H(0, 2));
2367         DUMPREG(DISPC_VID_FIR_COEF_H(0, 3));
2368         DUMPREG(DISPC_VID_FIR_COEF_H(0, 4));
2369         DUMPREG(DISPC_VID_FIR_COEF_H(0, 5));
2370         DUMPREG(DISPC_VID_FIR_COEF_H(0, 6));
2371         DUMPREG(DISPC_VID_FIR_COEF_H(0, 7));
2372         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 0));
2373         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 1));
2374         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 2));
2375         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 3));
2376         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 4));
2377         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 5));
2378         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 6));
2379         DUMPREG(DISPC_VID_FIR_COEF_HV(0, 7));
2380         DUMPREG(DISPC_VID_CONV_COEF(0, 0));
2381         DUMPREG(DISPC_VID_CONV_COEF(0, 1));
2382         DUMPREG(DISPC_VID_CONV_COEF(0, 2));
2383         DUMPREG(DISPC_VID_CONV_COEF(0, 3));
2384         DUMPREG(DISPC_VID_CONV_COEF(0, 4));
2385         DUMPREG(DISPC_VID_FIR_COEF_V(0, 0));
2386         DUMPREG(DISPC_VID_FIR_COEF_V(0, 1));
2387         DUMPREG(DISPC_VID_FIR_COEF_V(0, 2));
2388         DUMPREG(DISPC_VID_FIR_COEF_V(0, 3));
2389         DUMPREG(DISPC_VID_FIR_COEF_V(0, 4));
2390         DUMPREG(DISPC_VID_FIR_COEF_V(0, 5));
2391         DUMPREG(DISPC_VID_FIR_COEF_V(0, 6));
2392         DUMPREG(DISPC_VID_FIR_COEF_V(0, 7));
2393
2394         DUMPREG(DISPC_VID_FIR_COEF_H(1, 0));
2395         DUMPREG(DISPC_VID_FIR_COEF_H(1, 1));
2396         DUMPREG(DISPC_VID_FIR_COEF_H(1, 2));
2397         DUMPREG(DISPC_VID_FIR_COEF_H(1, 3));
2398         DUMPREG(DISPC_VID_FIR_COEF_H(1, 4));
2399         DUMPREG(DISPC_VID_FIR_COEF_H(1, 5));
2400         DUMPREG(DISPC_VID_FIR_COEF_H(1, 6));
2401         DUMPREG(DISPC_VID_FIR_COEF_H(1, 7));
2402         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 0));
2403         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 1));
2404         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 2));
2405         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 3));
2406         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 4));
2407         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 5));
2408         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 6));
2409         DUMPREG(DISPC_VID_FIR_COEF_HV(1, 7));
2410         DUMPREG(DISPC_VID_CONV_COEF(1, 0));
2411         DUMPREG(DISPC_VID_CONV_COEF(1, 1));
2412         DUMPREG(DISPC_VID_CONV_COEF(1, 2));
2413         DUMPREG(DISPC_VID_CONV_COEF(1, 3));
2414         DUMPREG(DISPC_VID_CONV_COEF(1, 4));
2415         DUMPREG(DISPC_VID_FIR_COEF_V(1, 0));
2416         DUMPREG(DISPC_VID_FIR_COEF_V(1, 1));
2417         DUMPREG(DISPC_VID_FIR_COEF_V(1, 2));
2418         DUMPREG(DISPC_VID_FIR_COEF_V(1, 3));
2419         DUMPREG(DISPC_VID_FIR_COEF_V(1, 4));
2420         DUMPREG(DISPC_VID_FIR_COEF_V(1, 5));
2421         DUMPREG(DISPC_VID_FIR_COEF_V(1, 6));
2422         DUMPREG(DISPC_VID_FIR_COEF_V(1, 7));
2423
2424         DUMPREG(DISPC_VID_PRELOAD(0));
2425         DUMPREG(DISPC_VID_PRELOAD(1));
2426
2427         dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
2428 #undef DUMPREG
2429 }
2430
2431 static void _dispc_set_pol_freq(bool onoff, bool rf, bool ieo, bool ipc,
2432                                 bool ihs, bool ivs, u8 acbi, u8 acb)
2433 {
2434         u32 l = 0;
2435
2436         DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
2437                         onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
2438
2439         l |= FLD_VAL(onoff, 17, 17);
2440         l |= FLD_VAL(rf, 16, 16);
2441         l |= FLD_VAL(ieo, 15, 15);
2442         l |= FLD_VAL(ipc, 14, 14);
2443         l |= FLD_VAL(ihs, 13, 13);
2444         l |= FLD_VAL(ivs, 12, 12);
2445         l |= FLD_VAL(acbi, 11, 8);
2446         l |= FLD_VAL(acb, 7, 0);
2447
2448         enable_clocks(1);
2449         dispc_write_reg(DISPC_POL_FREQ(OMAP_DSS_CHANNEL_LCD), l);
2450         enable_clocks(0);
2451 }
2452
2453 void dispc_set_pol_freq(enum omap_panel_config config, u8 acbi, u8 acb)
2454 {
2455         _dispc_set_pol_freq((config & OMAP_DSS_LCD_ONOFF) != 0,
2456                         (config & OMAP_DSS_LCD_RF) != 0,
2457                         (config & OMAP_DSS_LCD_IEO) != 0,
2458                         (config & OMAP_DSS_LCD_IPC) != 0,
2459                         (config & OMAP_DSS_LCD_IHS) != 0,
2460                         (config & OMAP_DSS_LCD_IVS) != 0,
2461                         acbi, acb);
2462 }
2463
2464 /* with fck as input clock rate, find dispc dividers that produce req_pck */
2465 void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
2466                 struct dispc_clock_info *cinfo)
2467 {
2468         u16 pcd_min = is_tft ? 2 : 3;
2469         unsigned long best_pck;
2470         u16 best_ld, cur_ld;
2471         u16 best_pd, cur_pd;
2472
2473         best_pck = 0;
2474         best_ld = 0;
2475         best_pd = 0;
2476
2477         for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
2478                 unsigned long lck = fck / cur_ld;
2479
2480                 for (cur_pd = pcd_min; cur_pd <= 255; ++cur_pd) {
2481                         unsigned long pck = lck / cur_pd;
2482                         long old_delta = abs(best_pck - req_pck);
2483                         long new_delta = abs(pck - req_pck);
2484
2485                         if (best_pck == 0 || new_delta < old_delta) {
2486                                 best_pck = pck;
2487                                 best_ld = cur_ld;
2488                                 best_pd = cur_pd;
2489
2490                                 if (pck == req_pck)
2491                                         goto found;
2492                         }
2493
2494                         if (pck < req_pck)
2495                                 break;
2496                 }
2497
2498                 if (lck / pcd_min < req_pck)
2499                         break;
2500         }
2501
2502 found:
2503         cinfo->lck_div = best_ld;
2504         cinfo->pck_div = best_pd;
2505         cinfo->lck = fck / cinfo->lck_div;
2506         cinfo->pck = cinfo->lck / cinfo->pck_div;
2507 }
2508
2509 /* calculate clock rates using dividers in cinfo */
2510 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
2511                 struct dispc_clock_info *cinfo)
2512 {
2513         if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
2514                 return -EINVAL;
2515         if (cinfo->pck_div < 2 || cinfo->pck_div > 255)
2516                 return -EINVAL;
2517
2518         cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
2519         cinfo->pck = cinfo->lck / cinfo->pck_div;
2520
2521         return 0;
2522 }
2523
2524 int dispc_set_clock_div(struct dispc_clock_info *cinfo)
2525 {
2526         DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
2527         DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
2528
2529         dispc_set_lcd_divisor(cinfo->lck_div, cinfo->pck_div);
2530
2531         return 0;
2532 }
2533
2534 int dispc_get_clock_div(struct dispc_clock_info *cinfo)
2535 {
2536         unsigned long fck;
2537
2538         fck = dispc_fclk_rate();
2539
2540         cinfo->lck_div = REG_GET(DISPC_DIVISOR(OMAP_DSS_CHANNEL_LCD), 23, 16);
2541         cinfo->pck_div = REG_GET(DISPC_DIVISOR(OMAP_DSS_CHANNEL_LCD), 7, 0);
2542
2543         cinfo->lck = fck / cinfo->lck_div;
2544         cinfo->pck = cinfo->lck / cinfo->pck_div;
2545
2546         return 0;
2547 }
2548
2549 /* dispc.irq_lock has to be locked by the caller */
2550 static void _omap_dispc_set_irqs(void)
2551 {
2552         u32 mask;
2553         u32 old_mask;
2554         int i;
2555         struct omap_dispc_isr_data *isr_data;
2556
2557         mask = dispc.irq_error_mask;
2558
2559         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2560                 isr_data = &dispc.registered_isr[i];
2561
2562                 if (isr_data->isr == NULL)
2563                         continue;
2564
2565                 mask |= isr_data->mask;
2566         }
2567
2568         enable_clocks(1);
2569
2570         old_mask = dispc_read_reg(DISPC_IRQENABLE);
2571         /* clear the irqstatus for newly enabled irqs */
2572         dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
2573
2574         dispc_write_reg(DISPC_IRQENABLE, mask);
2575
2576         enable_clocks(0);
2577 }
2578
2579 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2580 {
2581         int i;
2582         int ret;
2583         unsigned long flags;
2584         struct omap_dispc_isr_data *isr_data;
2585
2586         if (isr == NULL)
2587                 return -EINVAL;
2588
2589         spin_lock_irqsave(&dispc.irq_lock, flags);
2590
2591         /* check for duplicate entry */
2592         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2593                 isr_data = &dispc.registered_isr[i];
2594                 if (isr_data->isr == isr && isr_data->arg == arg &&
2595                                 isr_data->mask == mask) {
2596                         ret = -EINVAL;
2597                         goto err;
2598                 }
2599         }
2600
2601         isr_data = NULL;
2602         ret = -EBUSY;
2603
2604         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2605                 isr_data = &dispc.registered_isr[i];
2606
2607                 if (isr_data->isr != NULL)
2608                         continue;
2609
2610                 isr_data->isr = isr;
2611                 isr_data->arg = arg;
2612                 isr_data->mask = mask;
2613                 ret = 0;
2614
2615                 break;
2616         }
2617
2618         _omap_dispc_set_irqs();
2619
2620         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2621
2622         return 0;
2623 err:
2624         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2625
2626         return ret;
2627 }
2628 EXPORT_SYMBOL(omap_dispc_register_isr);
2629
2630 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2631 {
2632         int i;
2633         unsigned long flags;
2634         int ret = -EINVAL;
2635         struct omap_dispc_isr_data *isr_data;
2636
2637         spin_lock_irqsave(&dispc.irq_lock, flags);
2638
2639         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2640                 isr_data = &dispc.registered_isr[i];
2641                 if (isr_data->isr != isr || isr_data->arg != arg ||
2642                                 isr_data->mask != mask)
2643                         continue;
2644
2645                 /* found the correct isr */
2646
2647                 isr_data->isr = NULL;
2648                 isr_data->arg = NULL;
2649                 isr_data->mask = 0;
2650
2651                 ret = 0;
2652                 break;
2653         }
2654
2655         if (ret == 0)
2656                 _omap_dispc_set_irqs();
2657
2658         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2659
2660         return ret;
2661 }
2662 EXPORT_SYMBOL(omap_dispc_unregister_isr);
2663
2664 #ifdef DEBUG
2665 static void print_irq_status(u32 status)
2666 {
2667         if ((status & dispc.irq_error_mask) == 0)
2668                 return;
2669
2670         printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
2671
2672 #define PIS(x) \
2673         if (status & DISPC_IRQ_##x) \
2674                 printk(#x " ");
2675         PIS(GFX_FIFO_UNDERFLOW);
2676         PIS(OCP_ERR);
2677         PIS(VID1_FIFO_UNDERFLOW);
2678         PIS(VID2_FIFO_UNDERFLOW);
2679         PIS(SYNC_LOST);
2680         PIS(SYNC_LOST_DIGIT);
2681 #undef PIS
2682
2683         printk("\n");
2684 }
2685 #endif
2686
2687 /* Called from dss.c. Note that we don't touch clocks here,
2688  * but we presume they are on because we got an IRQ. However,
2689  * an irq handler may turn the clocks off, so we may not have
2690  * clock later in the function. */
2691 void dispc_irq_handler(void)
2692 {
2693         int i;
2694         u32 irqstatus;
2695         u32 handledirqs = 0;
2696         u32 unhandled_errors;
2697         struct omap_dispc_isr_data *isr_data;
2698         struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
2699
2700         spin_lock(&dispc.irq_lock);
2701
2702         irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
2703
2704 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2705         spin_lock(&dispc.irq_stats_lock);
2706         dispc.irq_stats.irq_count++;
2707         dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
2708         spin_unlock(&dispc.irq_stats_lock);
2709 #endif
2710
2711 #ifdef DEBUG
2712         if (dss_debug)
2713                 print_irq_status(irqstatus);
2714 #endif
2715         /* Ack the interrupt. Do it here before clocks are possibly turned
2716          * off */
2717         dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
2718         /* flush posted write */
2719         dispc_read_reg(DISPC_IRQSTATUS);
2720
2721         /* make a copy and unlock, so that isrs can unregister
2722          * themselves */
2723         memcpy(registered_isr, dispc.registered_isr,
2724                         sizeof(registered_isr));
2725
2726         spin_unlock(&dispc.irq_lock);
2727
2728         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2729                 isr_data = &registered_isr[i];
2730
2731                 if (!isr_data->isr)
2732                         continue;
2733
2734                 if (isr_data->mask & irqstatus) {
2735                         isr_data->isr(isr_data->arg, irqstatus);
2736                         handledirqs |= isr_data->mask;
2737                 }
2738         }
2739
2740         spin_lock(&dispc.irq_lock);
2741
2742         unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
2743
2744         if (unhandled_errors) {
2745                 dispc.error_irqs |= unhandled_errors;
2746
2747                 dispc.irq_error_mask &= ~unhandled_errors;
2748                 _omap_dispc_set_irqs();
2749
2750                 schedule_work(&dispc.error_work);
2751         }
2752
2753         spin_unlock(&dispc.irq_lock);
2754 }
2755
2756 static void dispc_error_worker(struct work_struct *work)
2757 {
2758         int i;
2759         u32 errors;
2760         unsigned long flags;
2761
2762         spin_lock_irqsave(&dispc.irq_lock, flags);
2763         errors = dispc.error_irqs;
2764         dispc.error_irqs = 0;
2765         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2766
2767         if (errors & DISPC_IRQ_GFX_FIFO_UNDERFLOW) {
2768                 DSSERR("GFX_FIFO_UNDERFLOW, disabling GFX\n");
2769                 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2770                         struct omap_overlay *ovl;
2771                         ovl = omap_dss_get_overlay(i);
2772
2773                         if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2774                                 continue;
2775
2776                         if (ovl->id == 0) {
2777                                 dispc_enable_plane(ovl->id, 0);
2778                                 dispc_go(ovl->manager->id);
2779                                 mdelay(50);
2780                                 break;
2781                         }
2782                 }
2783         }
2784
2785         if (errors & DISPC_IRQ_VID1_FIFO_UNDERFLOW) {
2786                 DSSERR("VID1_FIFO_UNDERFLOW, disabling VID1\n");
2787                 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2788                         struct omap_overlay *ovl;
2789                         ovl = omap_dss_get_overlay(i);
2790
2791                         if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2792                                 continue;
2793
2794                         if (ovl->id == 1) {
2795                                 dispc_enable_plane(ovl->id, 0);
2796                                 dispc_go(ovl->manager->id);
2797                                 mdelay(50);
2798                                 break;
2799                         }
2800                 }
2801         }
2802
2803         if (errors & DISPC_IRQ_VID2_FIFO_UNDERFLOW) {
2804                 DSSERR("VID2_FIFO_UNDERFLOW, disabling VID2\n");
2805                 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2806                         struct omap_overlay *ovl;
2807                         ovl = omap_dss_get_overlay(i);
2808
2809                         if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2810                                 continue;
2811
2812                         if (ovl->id == 2) {
2813                                 dispc_enable_plane(ovl->id, 0);
2814                                 dispc_go(ovl->manager->id);
2815                                 mdelay(50);
2816                                 break;
2817                         }
2818                 }
2819         }
2820
2821         if (errors & DISPC_IRQ_SYNC_LOST) {
2822                 struct omap_overlay_manager *manager = NULL;
2823                 bool enable = false;
2824
2825                 DSSERR("SYNC_LOST, disabling LCD\n");
2826
2827                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
2828                         struct omap_overlay_manager *mgr;
2829                         mgr = omap_dss_get_overlay_manager(i);
2830
2831                         if (mgr->id == OMAP_DSS_CHANNEL_LCD) {
2832                                 manager = mgr;
2833                                 enable = mgr->device->state ==
2834                                                 OMAP_DSS_DISPLAY_ACTIVE;
2835                                 mgr->device->driver->disable(mgr->device);
2836                                 break;
2837                         }
2838                 }
2839
2840                 if (manager) {
2841                         struct omap_dss_device *dssdev = manager->device;
2842                         for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2843                                 struct omap_overlay *ovl;
2844                                 ovl = omap_dss_get_overlay(i);
2845
2846                                 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2847                                         continue;
2848
2849                                 if (ovl->id != 0 && ovl->manager == manager)
2850                                         dispc_enable_plane(ovl->id, 0);
2851                         }
2852
2853                         dispc_go(manager->id);
2854                         mdelay(50);
2855                         if (enable)
2856                                 dssdev->driver->enable(dssdev);
2857                 }
2858         }
2859
2860         if (errors & DISPC_IRQ_SYNC_LOST_DIGIT) {
2861                 struct omap_overlay_manager *manager = NULL;
2862                 bool enable = false;
2863
2864                 DSSERR("SYNC_LOST_DIGIT, disabling TV\n");
2865
2866                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
2867                         struct omap_overlay_manager *mgr;
2868                         mgr = omap_dss_get_overlay_manager(i);
2869
2870                         if (mgr->id == OMAP_DSS_CHANNEL_DIGIT) {
2871                                 manager = mgr;
2872                                 enable = mgr->device->state ==
2873                                                 OMAP_DSS_DISPLAY_ACTIVE;
2874                                 mgr->device->driver->disable(mgr->device);
2875                                 break;
2876                         }
2877                 }
2878
2879                 if (manager) {
2880                         struct omap_dss_device *dssdev = manager->device;
2881                         for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2882                                 struct omap_overlay *ovl;
2883                                 ovl = omap_dss_get_overlay(i);
2884
2885                                 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2886                                         continue;
2887
2888                                 if (ovl->id != 0 && ovl->manager == manager)
2889                                         dispc_enable_plane(ovl->id, 0);
2890                         }
2891
2892                         dispc_go(manager->id);
2893                         mdelay(50);
2894                         if (enable)
2895                                 dssdev->driver->enable(dssdev);
2896                 }
2897         }
2898
2899         if (errors & DISPC_IRQ_OCP_ERR) {
2900                 DSSERR("OCP_ERR\n");
2901                 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
2902                         struct omap_overlay_manager *mgr;
2903                         mgr = omap_dss_get_overlay_manager(i);
2904
2905                         if (mgr->caps & OMAP_DSS_OVL_CAP_DISPC)
2906                                 mgr->device->driver->disable(mgr->device);
2907                 }
2908         }
2909
2910         spin_lock_irqsave(&dispc.irq_lock, flags);
2911         dispc.irq_error_mask |= errors;
2912         _omap_dispc_set_irqs();
2913         spin_unlock_irqrestore(&dispc.irq_lock, flags);
2914 }
2915
2916 int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
2917 {
2918         void dispc_irq_wait_handler(void *data, u32 mask)
2919         {
2920                 complete((struct completion *)data);
2921         }
2922
2923         int r;
2924         DECLARE_COMPLETION_ONSTACK(completion);
2925
2926         r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
2927                         irqmask);
2928
2929         if (r)
2930                 return r;
2931
2932         timeout = wait_for_completion_timeout(&completion, timeout);
2933
2934         omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
2935
2936         if (timeout == 0)
2937                 return -ETIMEDOUT;
2938
2939         if (timeout == -ERESTARTSYS)
2940                 return -ERESTARTSYS;
2941
2942         return 0;
2943 }
2944
2945 int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
2946                 unsigned long timeout)
2947 {
2948         void dispc_irq_wait_handler(void *data, u32 mask)
2949         {
2950                 complete((struct completion *)data);
2951         }
2952
2953         int r;
2954         DECLARE_COMPLETION_ONSTACK(completion);
2955
2956         r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
2957                         irqmask);
2958
2959         if (r)
2960                 return r;
2961
2962         timeout = wait_for_completion_interruptible_timeout(&completion,
2963                         timeout);
2964
2965         omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
2966
2967         if (timeout == 0)
2968                 return -ETIMEDOUT;
2969
2970         if (timeout == -ERESTARTSYS)
2971                 return -ERESTARTSYS;
2972
2973         return 0;
2974 }
2975
2976 #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
2977 void dispc_fake_vsync_irq(void)
2978 {
2979         u32 irqstatus = DISPC_IRQ_VSYNC;
2980         int i;
2981
2982         WARN_ON(!in_interrupt());
2983
2984         for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2985                 struct omap_dispc_isr_data *isr_data;
2986                 isr_data = &dispc.registered_isr[i];
2987
2988                 if (!isr_data->isr)
2989                         continue;
2990
2991                 if (isr_data->mask & irqstatus)
2992                         isr_data->isr(isr_data->arg, irqstatus);
2993         }
2994 }
2995 #endif
2996
2997 static void _omap_dispc_initialize_irq(void)
2998 {
2999         unsigned long flags;
3000
3001         spin_lock_irqsave(&dispc.irq_lock, flags);
3002
3003         memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3004
3005         dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
3006
3007         /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3008          * so clear it */
3009         dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3010
3011         _omap_dispc_set_irqs();
3012
3013         spin_unlock_irqrestore(&dispc.irq_lock, flags);
3014 }
3015
3016 void dispc_enable_sidle(void)
3017 {
3018         REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3);  /* SIDLEMODE: smart idle */
3019 }
3020
3021 void dispc_disable_sidle(void)
3022 {
3023         REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3);  /* SIDLEMODE: no idle */
3024 }
3025
3026 static void _omap_dispc_initial_config(void)
3027 {
3028         u32 l;
3029
3030         l = dispc_read_reg(DISPC_SYSCONFIG);
3031         l = FLD_MOD(l, 2, 13, 12);      /* MIDLEMODE: smart standby */
3032         l = FLD_MOD(l, 2, 4, 3);        /* SIDLEMODE: smart idle */
3033         l = FLD_MOD(l, 1, 2, 2);        /* ENWAKEUP */
3034         l = FLD_MOD(l, 1, 0, 0);        /* AUTOIDLE */
3035         dispc_write_reg(DISPC_SYSCONFIG, l);
3036
3037         /* FUNCGATED */
3038         REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
3039
3040         /* L3 firewall setting: enable access to OCM RAM */
3041         /* XXX this should be somewhere in plat-omap */
3042         if (cpu_is_omap24xx())
3043                 __raw_writel(0x402000b0, OMAP2_L3_IO_ADDRESS(0x680050a0));
3044
3045         _dispc_setup_color_conv_coef();
3046
3047         dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3048
3049         dispc_read_plane_fifo_sizes();
3050 }
3051
3052 int dispc_init(void)
3053 {
3054         u32 rev;
3055
3056         spin_lock_init(&dispc.irq_lock);
3057
3058 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3059         spin_lock_init(&dispc.irq_stats_lock);
3060         dispc.irq_stats.last_reset = jiffies;
3061 #endif
3062
3063         INIT_WORK(&dispc.error_work, dispc_error_worker);
3064
3065         dispc.base = ioremap(DISPC_BASE, DISPC_SZ_REGS);
3066         if (!dispc.base) {
3067                 DSSERR("can't ioremap DISPC\n");
3068                 return -ENOMEM;
3069         }
3070
3071         enable_clocks(1);
3072
3073         _omap_dispc_initial_config();
3074
3075         _omap_dispc_initialize_irq();
3076
3077         dispc_save_context();
3078
3079         rev = dispc_read_reg(DISPC_REVISION);
3080         printk(KERN_INFO "OMAP DISPC rev %d.%d\n",
3081                FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3082
3083         enable_clocks(0);
3084
3085         return 0;
3086 }
3087
3088 void dispc_exit(void)
3089 {
3090         iounmap(dispc.base);
3091 }
3092
3093 int dispc_enable_plane(enum omap_plane plane, bool enable)
3094 {
3095         DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
3096
3097         enable_clocks(1);
3098         _dispc_enable_plane(plane, enable);
3099         enable_clocks(0);
3100
3101         return 0;
3102 }
3103
3104 int dispc_setup_plane(enum omap_plane plane,
3105                        u32 paddr, u16 screen_width,
3106                        u16 pos_x, u16 pos_y,
3107                        u16 width, u16 height,
3108                        u16 out_width, u16 out_height,
3109                        enum omap_color_mode color_mode,
3110                        bool ilace,
3111                        enum omap_dss_rotation_type rotation_type,
3112                        u8 rotation, bool mirror, u8 global_alpha,
3113                        u8 pre_mult_alpha)
3114 {
3115         int r = 0;
3116
3117         DSSDBG("dispc_setup_plane %d, pa %x, sw %d, %d,%d, %dx%d -> "
3118                "%dx%d, ilace %d, cmode %x, rot %d, mir %d\n",
3119                plane, paddr, screen_width, pos_x, pos_y,
3120                width, height,
3121                out_width, out_height,
3122                ilace, color_mode,
3123                rotation, mirror);
3124
3125         enable_clocks(1);
3126
3127         r = _dispc_setup_plane(plane,
3128                            paddr, screen_width,
3129                            pos_x, pos_y,
3130                            width, height,
3131                            out_width, out_height,
3132                            color_mode, ilace,
3133                            rotation_type,
3134                            rotation, mirror,
3135                            global_alpha,
3136                            pre_mult_alpha);
3137
3138         enable_clocks(0);
3139
3140         return r;
3141 }