2 * linux/drivers/video/omap2/dss/dispc.c
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * Some code and ideas taken from drivers/video/omap/ driver
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
23 #define DSS_SUBSYS_NAME "DISPC"
25 #include <linux/kernel.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/vmalloc.h>
28 #include <linux/clk.h>
30 #include <linux/jiffies.h>
31 #include <linux/seq_file.h>
32 #include <linux/delay.h>
33 #include <linux/workqueue.h>
34 #include <linux/hardirq.h>
36 #include <plat/sram.h>
37 #include <plat/clock.h>
39 #include <plat/display.h>
44 #define DISPC_BASE 0x48050400
46 #define DISPC_SZ_REGS SZ_1K
48 struct dispc_reg { u16 idx; };
50 #define DISPC_REG(idx) ((const struct dispc_reg) { idx })
53 #define DISPC_REVISION DISPC_REG(0x0000)
54 #define DISPC_SYSCONFIG DISPC_REG(0x0010)
55 #define DISPC_SYSSTATUS DISPC_REG(0x0014)
56 #define DISPC_IRQSTATUS DISPC_REG(0x0018)
57 #define DISPC_IRQENABLE DISPC_REG(0x001C)
58 #define DISPC_CONTROL DISPC_REG(0x0040)
59 #define DISPC_CONFIG DISPC_REG(0x0044)
60 #define DISPC_CAPABLE DISPC_REG(0x0048)
61 #define DISPC_DEFAULT_COLOR0 DISPC_REG(0x004C)
62 #define DISPC_DEFAULT_COLOR1 DISPC_REG(0x0050)
63 #define DISPC_TRANS_COLOR0 DISPC_REG(0x0054)
64 #define DISPC_TRANS_COLOR1 DISPC_REG(0x0058)
65 #define DISPC_LINE_STATUS DISPC_REG(0x005C)
66 #define DISPC_LINE_NUMBER DISPC_REG(0x0060)
67 #define DISPC_TIMING_H DISPC_REG(0x0064)
68 #define DISPC_TIMING_V DISPC_REG(0x0068)
69 #define DISPC_POL_FREQ DISPC_REG(0x006C)
70 #define DISPC_DIVISOR DISPC_REG(0x0070)
71 #define DISPC_GLOBAL_ALPHA DISPC_REG(0x0074)
72 #define DISPC_SIZE_DIG DISPC_REG(0x0078)
73 #define DISPC_SIZE_LCD DISPC_REG(0x007C)
76 #define DISPC_GFX_BA0 DISPC_REG(0x0080)
77 #define DISPC_GFX_BA1 DISPC_REG(0x0084)
78 #define DISPC_GFX_POSITION DISPC_REG(0x0088)
79 #define DISPC_GFX_SIZE DISPC_REG(0x008C)
80 #define DISPC_GFX_ATTRIBUTES DISPC_REG(0x00A0)
81 #define DISPC_GFX_FIFO_THRESHOLD DISPC_REG(0x00A4)
82 #define DISPC_GFX_FIFO_SIZE_STATUS DISPC_REG(0x00A8)
83 #define DISPC_GFX_ROW_INC DISPC_REG(0x00AC)
84 #define DISPC_GFX_PIXEL_INC DISPC_REG(0x00B0)
85 #define DISPC_GFX_WINDOW_SKIP DISPC_REG(0x00B4)
86 #define DISPC_GFX_TABLE_BA DISPC_REG(0x00B8)
88 #define DISPC_DATA_CYCLE1 DISPC_REG(0x01D4)
89 #define DISPC_DATA_CYCLE2 DISPC_REG(0x01D8)
90 #define DISPC_DATA_CYCLE3 DISPC_REG(0x01DC)
92 #define DISPC_CPR_COEF_R DISPC_REG(0x0220)
93 #define DISPC_CPR_COEF_G DISPC_REG(0x0224)
94 #define DISPC_CPR_COEF_B DISPC_REG(0x0228)
96 #define DISPC_GFX_PRELOAD DISPC_REG(0x022C)
98 /* DISPC Video plane, n = 0 for VID1 and n = 1 for VID2 */
99 #define DISPC_VID_REG(n, idx) DISPC_REG(0x00BC + (n)*0x90 + idx)
101 #define DISPC_VID_BA0(n) DISPC_VID_REG(n, 0x0000)
102 #define DISPC_VID_BA1(n) DISPC_VID_REG(n, 0x0004)
103 #define DISPC_VID_POSITION(n) DISPC_VID_REG(n, 0x0008)
104 #define DISPC_VID_SIZE(n) DISPC_VID_REG(n, 0x000C)
105 #define DISPC_VID_ATTRIBUTES(n) DISPC_VID_REG(n, 0x0010)
106 #define DISPC_VID_FIFO_THRESHOLD(n) DISPC_VID_REG(n, 0x0014)
107 #define DISPC_VID_FIFO_SIZE_STATUS(n) DISPC_VID_REG(n, 0x0018)
108 #define DISPC_VID_ROW_INC(n) DISPC_VID_REG(n, 0x001C)
109 #define DISPC_VID_PIXEL_INC(n) DISPC_VID_REG(n, 0x0020)
110 #define DISPC_VID_FIR(n) DISPC_VID_REG(n, 0x0024)
111 #define DISPC_VID_PICTURE_SIZE(n) DISPC_VID_REG(n, 0x0028)
112 #define DISPC_VID_ACCU0(n) DISPC_VID_REG(n, 0x002C)
113 #define DISPC_VID_ACCU1(n) DISPC_VID_REG(n, 0x0030)
115 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
116 #define DISPC_VID_FIR_COEF_H(n, i) DISPC_REG(0x00F0 + (n)*0x90 + (i)*0x8)
117 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
118 #define DISPC_VID_FIR_COEF_HV(n, i) DISPC_REG(0x00F4 + (n)*0x90 + (i)*0x8)
119 /* coef index i = {0, 1, 2, 3, 4} */
120 #define DISPC_VID_CONV_COEF(n, i) DISPC_REG(0x0130 + (n)*0x90 + (i)*0x4)
121 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
122 #define DISPC_VID_FIR_COEF_V(n, i) DISPC_REG(0x01E0 + (n)*0x20 + (i)*0x4)
124 #define DISPC_VID_PRELOAD(n) DISPC_REG(0x230 + (n)*0x04)
127 #define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
128 DISPC_IRQ_OCP_ERR | \
129 DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
130 DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
131 DISPC_IRQ_SYNC_LOST | \
132 DISPC_IRQ_SYNC_LOST_DIGIT)
134 #define DISPC_MAX_NR_ISRS 8
136 struct omap_dispc_isr_data {
137 omap_dispc_isr_t isr;
142 #define REG_GET(idx, start, end) \
143 FLD_GET(dispc_read_reg(idx), start, end)
145 #define REG_FLD_MOD(idx, val, start, end) \
146 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
148 static const struct dispc_reg dispc_reg_att[] = { DISPC_GFX_ATTRIBUTES,
149 DISPC_VID_ATTRIBUTES(0),
150 DISPC_VID_ATTRIBUTES(1) };
152 struct dispc_irq_stats {
153 unsigned long last_reset;
165 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
167 struct work_struct error_work;
169 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
171 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
172 spinlock_t irq_stats_lock;
173 struct dispc_irq_stats irq_stats;
177 static void _omap_dispc_set_irqs(void);
179 static inline void dispc_write_reg(const struct dispc_reg idx, u32 val)
181 __raw_writel(val, dispc.base + idx.idx);
184 static inline u32 dispc_read_reg(const struct dispc_reg idx)
186 return __raw_readl(dispc.base + idx.idx);
190 dispc.ctx[(DISPC_##reg).idx / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
192 dispc_write_reg(DISPC_##reg, dispc.ctx[(DISPC_##reg).idx / sizeof(u32)])
194 void dispc_save_context(void)
196 if (cpu_is_omap24xx())
221 SR(GFX_FIFO_THRESHOLD);
242 SR(VID_ATTRIBUTES(0));
243 SR(VID_FIFO_THRESHOLD(0));
245 SR(VID_PIXEL_INC(0));
247 SR(VID_PICTURE_SIZE(0));
251 SR(VID_FIR_COEF_H(0, 0));
252 SR(VID_FIR_COEF_H(0, 1));
253 SR(VID_FIR_COEF_H(0, 2));
254 SR(VID_FIR_COEF_H(0, 3));
255 SR(VID_FIR_COEF_H(0, 4));
256 SR(VID_FIR_COEF_H(0, 5));
257 SR(VID_FIR_COEF_H(0, 6));
258 SR(VID_FIR_COEF_H(0, 7));
260 SR(VID_FIR_COEF_HV(0, 0));
261 SR(VID_FIR_COEF_HV(0, 1));
262 SR(VID_FIR_COEF_HV(0, 2));
263 SR(VID_FIR_COEF_HV(0, 3));
264 SR(VID_FIR_COEF_HV(0, 4));
265 SR(VID_FIR_COEF_HV(0, 5));
266 SR(VID_FIR_COEF_HV(0, 6));
267 SR(VID_FIR_COEF_HV(0, 7));
269 SR(VID_CONV_COEF(0, 0));
270 SR(VID_CONV_COEF(0, 1));
271 SR(VID_CONV_COEF(0, 2));
272 SR(VID_CONV_COEF(0, 3));
273 SR(VID_CONV_COEF(0, 4));
275 SR(VID_FIR_COEF_V(0, 0));
276 SR(VID_FIR_COEF_V(0, 1));
277 SR(VID_FIR_COEF_V(0, 2));
278 SR(VID_FIR_COEF_V(0, 3));
279 SR(VID_FIR_COEF_V(0, 4));
280 SR(VID_FIR_COEF_V(0, 5));
281 SR(VID_FIR_COEF_V(0, 6));
282 SR(VID_FIR_COEF_V(0, 7));
291 SR(VID_ATTRIBUTES(1));
292 SR(VID_FIFO_THRESHOLD(1));
294 SR(VID_PIXEL_INC(1));
296 SR(VID_PICTURE_SIZE(1));
300 SR(VID_FIR_COEF_H(1, 0));
301 SR(VID_FIR_COEF_H(1, 1));
302 SR(VID_FIR_COEF_H(1, 2));
303 SR(VID_FIR_COEF_H(1, 3));
304 SR(VID_FIR_COEF_H(1, 4));
305 SR(VID_FIR_COEF_H(1, 5));
306 SR(VID_FIR_COEF_H(1, 6));
307 SR(VID_FIR_COEF_H(1, 7));
309 SR(VID_FIR_COEF_HV(1, 0));
310 SR(VID_FIR_COEF_HV(1, 1));
311 SR(VID_FIR_COEF_HV(1, 2));
312 SR(VID_FIR_COEF_HV(1, 3));
313 SR(VID_FIR_COEF_HV(1, 4));
314 SR(VID_FIR_COEF_HV(1, 5));
315 SR(VID_FIR_COEF_HV(1, 6));
316 SR(VID_FIR_COEF_HV(1, 7));
318 SR(VID_CONV_COEF(1, 0));
319 SR(VID_CONV_COEF(1, 1));
320 SR(VID_CONV_COEF(1, 2));
321 SR(VID_CONV_COEF(1, 3));
322 SR(VID_CONV_COEF(1, 4));
324 SR(VID_FIR_COEF_V(1, 0));
325 SR(VID_FIR_COEF_V(1, 1));
326 SR(VID_FIR_COEF_V(1, 2));
327 SR(VID_FIR_COEF_V(1, 3));
328 SR(VID_FIR_COEF_V(1, 4));
329 SR(VID_FIR_COEF_V(1, 5));
330 SR(VID_FIR_COEF_V(1, 6));
331 SR(VID_FIR_COEF_V(1, 7));
336 void dispc_restore_context(void)
360 RR(GFX_FIFO_THRESHOLD);
381 RR(VID_ATTRIBUTES(0));
382 RR(VID_FIFO_THRESHOLD(0));
384 RR(VID_PIXEL_INC(0));
386 RR(VID_PICTURE_SIZE(0));
390 RR(VID_FIR_COEF_H(0, 0));
391 RR(VID_FIR_COEF_H(0, 1));
392 RR(VID_FIR_COEF_H(0, 2));
393 RR(VID_FIR_COEF_H(0, 3));
394 RR(VID_FIR_COEF_H(0, 4));
395 RR(VID_FIR_COEF_H(0, 5));
396 RR(VID_FIR_COEF_H(0, 6));
397 RR(VID_FIR_COEF_H(0, 7));
399 RR(VID_FIR_COEF_HV(0, 0));
400 RR(VID_FIR_COEF_HV(0, 1));
401 RR(VID_FIR_COEF_HV(0, 2));
402 RR(VID_FIR_COEF_HV(0, 3));
403 RR(VID_FIR_COEF_HV(0, 4));
404 RR(VID_FIR_COEF_HV(0, 5));
405 RR(VID_FIR_COEF_HV(0, 6));
406 RR(VID_FIR_COEF_HV(0, 7));
408 RR(VID_CONV_COEF(0, 0));
409 RR(VID_CONV_COEF(0, 1));
410 RR(VID_CONV_COEF(0, 2));
411 RR(VID_CONV_COEF(0, 3));
412 RR(VID_CONV_COEF(0, 4));
414 RR(VID_FIR_COEF_V(0, 0));
415 RR(VID_FIR_COEF_V(0, 1));
416 RR(VID_FIR_COEF_V(0, 2));
417 RR(VID_FIR_COEF_V(0, 3));
418 RR(VID_FIR_COEF_V(0, 4));
419 RR(VID_FIR_COEF_V(0, 5));
420 RR(VID_FIR_COEF_V(0, 6));
421 RR(VID_FIR_COEF_V(0, 7));
430 RR(VID_ATTRIBUTES(1));
431 RR(VID_FIFO_THRESHOLD(1));
433 RR(VID_PIXEL_INC(1));
435 RR(VID_PICTURE_SIZE(1));
439 RR(VID_FIR_COEF_H(1, 0));
440 RR(VID_FIR_COEF_H(1, 1));
441 RR(VID_FIR_COEF_H(1, 2));
442 RR(VID_FIR_COEF_H(1, 3));
443 RR(VID_FIR_COEF_H(1, 4));
444 RR(VID_FIR_COEF_H(1, 5));
445 RR(VID_FIR_COEF_H(1, 6));
446 RR(VID_FIR_COEF_H(1, 7));
448 RR(VID_FIR_COEF_HV(1, 0));
449 RR(VID_FIR_COEF_HV(1, 1));
450 RR(VID_FIR_COEF_HV(1, 2));
451 RR(VID_FIR_COEF_HV(1, 3));
452 RR(VID_FIR_COEF_HV(1, 4));
453 RR(VID_FIR_COEF_HV(1, 5));
454 RR(VID_FIR_COEF_HV(1, 6));
455 RR(VID_FIR_COEF_HV(1, 7));
457 RR(VID_CONV_COEF(1, 0));
458 RR(VID_CONV_COEF(1, 1));
459 RR(VID_CONV_COEF(1, 2));
460 RR(VID_CONV_COEF(1, 3));
461 RR(VID_CONV_COEF(1, 4));
463 RR(VID_FIR_COEF_V(1, 0));
464 RR(VID_FIR_COEF_V(1, 1));
465 RR(VID_FIR_COEF_V(1, 2));
466 RR(VID_FIR_COEF_V(1, 3));
467 RR(VID_FIR_COEF_V(1, 4));
468 RR(VID_FIR_COEF_V(1, 5));
469 RR(VID_FIR_COEF_V(1, 6));
470 RR(VID_FIR_COEF_V(1, 7));
474 /* enable last, because LCD & DIGIT enable are here */
477 /* clear spurious SYNC_LOST_DIGIT interrupts */
478 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
481 * enable last so IRQs won't trigger before
482 * the context is fully restored
490 static inline void enable_clocks(bool enable)
493 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
495 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
498 bool dispc_go_busy(enum omap_channel channel)
502 if (channel == OMAP_DSS_CHANNEL_LCD)
505 bit = 6; /* GODIGIT */
507 return REG_GET(DISPC_CONTROL, bit, bit) == 1;
510 void dispc_go(enum omap_channel channel)
516 if (channel == OMAP_DSS_CHANNEL_LCD)
517 bit = 0; /* LCDENABLE */
519 bit = 1; /* DIGITALENABLE */
521 /* if the channel is not enabled, we don't need GO */
522 if (REG_GET(DISPC_CONTROL, bit, bit) == 0)
525 if (channel == OMAP_DSS_CHANNEL_LCD)
528 bit = 6; /* GODIGIT */
530 if (REG_GET(DISPC_CONTROL, bit, bit) == 1) {
531 DSSERR("GO bit not down for channel %d\n", channel);
535 DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" : "DIGIT");
537 REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
542 static void _dispc_write_firh_reg(enum omap_plane plane, int reg, u32 value)
544 BUG_ON(plane == OMAP_DSS_GFX);
546 dispc_write_reg(DISPC_VID_FIR_COEF_H(plane-1, reg), value);
549 static void _dispc_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
551 BUG_ON(plane == OMAP_DSS_GFX);
553 dispc_write_reg(DISPC_VID_FIR_COEF_HV(plane-1, reg), value);
556 static void _dispc_write_firv_reg(enum omap_plane plane, int reg, u32 value)
558 BUG_ON(plane == OMAP_DSS_GFX);
560 dispc_write_reg(DISPC_VID_FIR_COEF_V(plane-1, reg), value);
563 static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup,
564 int vscaleup, int five_taps)
566 /* Coefficients for horizontal up-sampling */
567 static const u32 coef_hup[8] = {
578 /* Coefficients for horizontal down-sampling */
579 static const u32 coef_hdown[8] = {
590 /* Coefficients for horizontal and vertical up-sampling */
591 static const u32 coef_hvup[2][8] = {
614 /* Coefficients for horizontal and vertical down-sampling */
615 static const u32 coef_hvdown[2][8] = {
638 /* Coefficients for vertical up-sampling */
639 static const u32 coef_vup[8] = {
651 /* Coefficients for vertical down-sampling */
652 static const u32 coef_vdown[8] = {
665 const u32 *hv_coef_mod;
675 hv_coef = coef_hvup[five_taps];
681 hv_coef_mod = coef_hvdown[five_taps];
683 hv_coef = coef_hvdown[five_taps];
687 hv_coef_mod = coef_hvup[five_taps];
692 for (i = 0; i < 8; i++) {
701 hv |= (hv_coef_mod[i] & 0xff);
704 _dispc_write_firh_reg(plane, i, h);
705 _dispc_write_firhv_reg(plane, i, hv);
711 for (i = 0; i < 8; i++) {
714 _dispc_write_firv_reg(plane, i, v);
718 static void _dispc_setup_color_conv_coef(void)
720 const struct color_conv_coef {
721 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
724 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
727 const struct color_conv_coef *ct;
729 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
733 dispc_write_reg(DISPC_VID_CONV_COEF(0, 0), CVAL(ct->rcr, ct->ry));
734 dispc_write_reg(DISPC_VID_CONV_COEF(0, 1), CVAL(ct->gy, ct->rcb));
735 dispc_write_reg(DISPC_VID_CONV_COEF(0, 2), CVAL(ct->gcb, ct->gcr));
736 dispc_write_reg(DISPC_VID_CONV_COEF(0, 3), CVAL(ct->bcr, ct->by));
737 dispc_write_reg(DISPC_VID_CONV_COEF(0, 4), CVAL(0, ct->bcb));
739 dispc_write_reg(DISPC_VID_CONV_COEF(1, 0), CVAL(ct->rcr, ct->ry));
740 dispc_write_reg(DISPC_VID_CONV_COEF(1, 1), CVAL(ct->gy, ct->rcb));
741 dispc_write_reg(DISPC_VID_CONV_COEF(1, 2), CVAL(ct->gcb, ct->gcr));
742 dispc_write_reg(DISPC_VID_CONV_COEF(1, 3), CVAL(ct->bcr, ct->by));
743 dispc_write_reg(DISPC_VID_CONV_COEF(1, 4), CVAL(0, ct->bcb));
747 REG_FLD_MOD(DISPC_VID_ATTRIBUTES(0), ct->full_range, 11, 11);
748 REG_FLD_MOD(DISPC_VID_ATTRIBUTES(1), ct->full_range, 11, 11);
752 static void _dispc_set_plane_ba0(enum omap_plane plane, u32 paddr)
754 const struct dispc_reg ba0_reg[] = { DISPC_GFX_BA0,
758 dispc_write_reg(ba0_reg[plane], paddr);
761 static void _dispc_set_plane_ba1(enum omap_plane plane, u32 paddr)
763 const struct dispc_reg ba1_reg[] = { DISPC_GFX_BA1,
767 dispc_write_reg(ba1_reg[plane], paddr);
770 static void _dispc_set_plane_pos(enum omap_plane plane, int x, int y)
772 const struct dispc_reg pos_reg[] = { DISPC_GFX_POSITION,
773 DISPC_VID_POSITION(0),
774 DISPC_VID_POSITION(1) };
776 u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
777 dispc_write_reg(pos_reg[plane], val);
780 static void _dispc_set_pic_size(enum omap_plane plane, int width, int height)
782 const struct dispc_reg siz_reg[] = { DISPC_GFX_SIZE,
783 DISPC_VID_PICTURE_SIZE(0),
784 DISPC_VID_PICTURE_SIZE(1) };
785 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
786 dispc_write_reg(siz_reg[plane], val);
789 static void _dispc_set_vid_size(enum omap_plane plane, int width, int height)
792 const struct dispc_reg vsi_reg[] = { DISPC_VID_SIZE(0),
795 BUG_ON(plane == OMAP_DSS_GFX);
797 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
798 dispc_write_reg(vsi_reg[plane-1], val);
801 static void _dispc_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
804 BUG_ON(plane == OMAP_DSS_VIDEO1);
806 if (cpu_is_omap24xx())
809 if (plane == OMAP_DSS_GFX)
810 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 7, 0);
811 else if (plane == OMAP_DSS_VIDEO2)
812 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, 23, 16);
815 static void _dispc_set_pix_inc(enum omap_plane plane, s32 inc)
817 const struct dispc_reg ri_reg[] = { DISPC_GFX_PIXEL_INC,
818 DISPC_VID_PIXEL_INC(0),
819 DISPC_VID_PIXEL_INC(1) };
821 dispc_write_reg(ri_reg[plane], inc);
824 static void _dispc_set_row_inc(enum omap_plane plane, s32 inc)
826 const struct dispc_reg ri_reg[] = { DISPC_GFX_ROW_INC,
827 DISPC_VID_ROW_INC(0),
828 DISPC_VID_ROW_INC(1) };
830 dispc_write_reg(ri_reg[plane], inc);
833 static void _dispc_set_color_mode(enum omap_plane plane,
834 enum omap_color_mode color_mode)
838 switch (color_mode) {
839 case OMAP_DSS_COLOR_CLUT1:
841 case OMAP_DSS_COLOR_CLUT2:
843 case OMAP_DSS_COLOR_CLUT4:
845 case OMAP_DSS_COLOR_CLUT8:
847 case OMAP_DSS_COLOR_RGB12U:
849 case OMAP_DSS_COLOR_ARGB16:
851 case OMAP_DSS_COLOR_RGB16:
853 case OMAP_DSS_COLOR_RGB24U:
855 case OMAP_DSS_COLOR_RGB24P:
857 case OMAP_DSS_COLOR_YUV2:
859 case OMAP_DSS_COLOR_UYVY:
861 case OMAP_DSS_COLOR_ARGB32:
863 case OMAP_DSS_COLOR_RGBA32:
865 case OMAP_DSS_COLOR_RGBX32:
871 REG_FLD_MOD(dispc_reg_att[plane], m, 4, 1);
874 static void _dispc_set_channel_out(enum omap_plane plane,
875 enum omap_channel channel)
884 case OMAP_DSS_VIDEO1:
885 case OMAP_DSS_VIDEO2:
893 val = dispc_read_reg(dispc_reg_att[plane]);
894 val = FLD_MOD(val, channel, shift, shift);
895 dispc_write_reg(dispc_reg_att[plane], val);
898 void dispc_set_burst_size(enum omap_plane plane,
899 enum omap_burst_size burst_size)
910 case OMAP_DSS_VIDEO1:
911 case OMAP_DSS_VIDEO2:
919 val = dispc_read_reg(dispc_reg_att[plane]);
920 val = FLD_MOD(val, burst_size, shift+1, shift);
921 dispc_write_reg(dispc_reg_att[plane], val);
926 static void _dispc_set_vid_color_conv(enum omap_plane plane, bool enable)
930 BUG_ON(plane == OMAP_DSS_GFX);
932 val = dispc_read_reg(dispc_reg_att[plane]);
933 val = FLD_MOD(val, enable, 9, 9);
934 dispc_write_reg(dispc_reg_att[plane], val);
937 void dispc_enable_replication(enum omap_plane plane, bool enable)
941 if (plane == OMAP_DSS_GFX)
947 REG_FLD_MOD(dispc_reg_att[plane], enable, bit, bit);
951 void dispc_set_lcd_size(u16 width, u16 height)
954 BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
955 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
957 dispc_write_reg(DISPC_SIZE_LCD, val);
961 void dispc_set_digit_size(u16 width, u16 height)
964 BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
965 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
967 dispc_write_reg(DISPC_SIZE_DIG, val);
971 static void dispc_read_plane_fifo_sizes(void)
973 const struct dispc_reg fsz_reg[] = { DISPC_GFX_FIFO_SIZE_STATUS,
974 DISPC_VID_FIFO_SIZE_STATUS(0),
975 DISPC_VID_FIFO_SIZE_STATUS(1) };
981 for (plane = 0; plane < ARRAY_SIZE(dispc.fifo_size); ++plane) {
982 if (cpu_is_omap24xx())
983 size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 8, 0);
984 else if (cpu_is_omap34xx())
985 size = FLD_GET(dispc_read_reg(fsz_reg[plane]), 10, 0);
989 dispc.fifo_size[plane] = size;
995 u32 dispc_get_plane_fifo_size(enum omap_plane plane)
997 return dispc.fifo_size[plane];
1000 void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high)
1002 const struct dispc_reg ftrs_reg[] = { DISPC_GFX_FIFO_THRESHOLD,
1003 DISPC_VID_FIFO_THRESHOLD(0),
1004 DISPC_VID_FIFO_THRESHOLD(1) };
1007 DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n",
1009 REG_GET(ftrs_reg[plane], 11, 0),
1010 REG_GET(ftrs_reg[plane], 27, 16),
1013 if (cpu_is_omap24xx())
1014 dispc_write_reg(ftrs_reg[plane],
1015 FLD_VAL(high, 24, 16) | FLD_VAL(low, 8, 0));
1017 dispc_write_reg(ftrs_reg[plane],
1018 FLD_VAL(high, 27, 16) | FLD_VAL(low, 11, 0));
1023 void dispc_enable_fifomerge(bool enable)
1027 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1028 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1033 static void _dispc_set_fir(enum omap_plane plane, int hinc, int vinc)
1036 const struct dispc_reg fir_reg[] = { DISPC_VID_FIR(0),
1039 BUG_ON(plane == OMAP_DSS_GFX);
1041 if (cpu_is_omap24xx())
1042 val = FLD_VAL(vinc, 27, 16) | FLD_VAL(hinc, 11, 0);
1044 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1045 dispc_write_reg(fir_reg[plane-1], val);
1048 static void _dispc_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1051 const struct dispc_reg ac0_reg[] = { DISPC_VID_ACCU0(0),
1052 DISPC_VID_ACCU0(1) };
1054 BUG_ON(plane == OMAP_DSS_GFX);
1056 val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0);
1057 dispc_write_reg(ac0_reg[plane-1], val);
1060 static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1063 const struct dispc_reg ac1_reg[] = { DISPC_VID_ACCU1(0),
1064 DISPC_VID_ACCU1(1) };
1066 BUG_ON(plane == OMAP_DSS_GFX);
1068 val = FLD_VAL(vaccu, 25, 16) | FLD_VAL(haccu, 9, 0);
1069 dispc_write_reg(ac1_reg[plane-1], val);
1073 static void _dispc_set_scaling(enum omap_plane plane,
1074 u16 orig_width, u16 orig_height,
1075 u16 out_width, u16 out_height,
1076 bool ilace, bool five_taps,
1081 int hscaleup, vscaleup;
1086 BUG_ON(plane == OMAP_DSS_GFX);
1088 hscaleup = orig_width <= out_width;
1089 vscaleup = orig_height <= out_height;
1091 _dispc_set_scale_coef(plane, hscaleup, vscaleup, five_taps);
1093 if (!orig_width || orig_width == out_width)
1096 fir_hinc = 1024 * orig_width / out_width;
1098 if (!orig_height || orig_height == out_height)
1101 fir_vinc = 1024 * orig_height / out_height;
1103 _dispc_set_fir(plane, fir_hinc, fir_vinc);
1105 l = dispc_read_reg(dispc_reg_att[plane]);
1106 l &= ~((0x0f << 5) | (0x3 << 21));
1108 l |= fir_hinc ? (1 << 5) : 0;
1109 l |= fir_vinc ? (1 << 6) : 0;
1111 l |= hscaleup ? 0 : (1 << 7);
1112 l |= vscaleup ? 0 : (1 << 8);
1114 l |= five_taps ? (1 << 21) : 0;
1115 l |= five_taps ? (1 << 22) : 0;
1117 dispc_write_reg(dispc_reg_att[plane], l);
1120 * field 0 = even field = bottom field
1121 * field 1 = odd field = top field
1123 if (ilace && !fieldmode) {
1125 accu0 = (fir_vinc / 2) & 0x3ff;
1126 if (accu0 >= 1024/2) {
1132 _dispc_set_vid_accu0(plane, 0, accu0);
1133 _dispc_set_vid_accu1(plane, 0, accu1);
1136 static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1137 bool mirroring, enum omap_color_mode color_mode)
1139 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1140 color_mode == OMAP_DSS_COLOR_UYVY) {
1145 case OMAP_DSS_ROT_0:
1148 case OMAP_DSS_ROT_90:
1151 case OMAP_DSS_ROT_180:
1154 case OMAP_DSS_ROT_270:
1160 case OMAP_DSS_ROT_0:
1163 case OMAP_DSS_ROT_90:
1166 case OMAP_DSS_ROT_180:
1169 case OMAP_DSS_ROT_270:
1175 REG_FLD_MOD(dispc_reg_att[plane], vidrot, 13, 12);
1177 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
1178 REG_FLD_MOD(dispc_reg_att[plane], 0x1, 18, 18);
1180 REG_FLD_MOD(dispc_reg_att[plane], 0x0, 18, 18);
1182 REG_FLD_MOD(dispc_reg_att[plane], 0, 13, 12);
1183 REG_FLD_MOD(dispc_reg_att[plane], 0, 18, 18);
1187 static int color_mode_to_bpp(enum omap_color_mode color_mode)
1189 switch (color_mode) {
1190 case OMAP_DSS_COLOR_CLUT1:
1192 case OMAP_DSS_COLOR_CLUT2:
1194 case OMAP_DSS_COLOR_CLUT4:
1196 case OMAP_DSS_COLOR_CLUT8:
1198 case OMAP_DSS_COLOR_RGB12U:
1199 case OMAP_DSS_COLOR_RGB16:
1200 case OMAP_DSS_COLOR_ARGB16:
1201 case OMAP_DSS_COLOR_YUV2:
1202 case OMAP_DSS_COLOR_UYVY:
1204 case OMAP_DSS_COLOR_RGB24P:
1206 case OMAP_DSS_COLOR_RGB24U:
1207 case OMAP_DSS_COLOR_ARGB32:
1208 case OMAP_DSS_COLOR_RGBA32:
1209 case OMAP_DSS_COLOR_RGBX32:
1216 static s32 pixinc(int pixels, u8 ps)
1220 else if (pixels > 1)
1221 return 1 + (pixels - 1) * ps;
1222 else if (pixels < 0)
1223 return 1 - (-pixels + 1) * ps;
1228 static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1230 u16 width, u16 height,
1231 enum omap_color_mode color_mode, bool fieldmode,
1232 unsigned int field_offset,
1233 unsigned *offset0, unsigned *offset1,
1234 s32 *row_inc, s32 *pix_inc)
1238 /* FIXME CLUT formats */
1239 switch (color_mode) {
1240 case OMAP_DSS_COLOR_CLUT1:
1241 case OMAP_DSS_COLOR_CLUT2:
1242 case OMAP_DSS_COLOR_CLUT4:
1243 case OMAP_DSS_COLOR_CLUT8:
1246 case OMAP_DSS_COLOR_YUV2:
1247 case OMAP_DSS_COLOR_UYVY:
1251 ps = color_mode_to_bpp(color_mode) / 8;
1255 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1259 * field 0 = even field = bottom field
1260 * field 1 = odd field = top field
1262 switch (rotation + mirror * 4) {
1263 case OMAP_DSS_ROT_0:
1264 case OMAP_DSS_ROT_180:
1266 * If the pixel format is YUV or UYVY divide the width
1267 * of the image by 2 for 0 and 180 degree rotation.
1269 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1270 color_mode == OMAP_DSS_COLOR_UYVY)
1272 case OMAP_DSS_ROT_90:
1273 case OMAP_DSS_ROT_270:
1276 *offset0 = field_offset * screen_width * ps;
1280 *row_inc = pixinc(1 + (screen_width - width) +
1281 (fieldmode ? screen_width : 0),
1283 *pix_inc = pixinc(1, ps);
1286 case OMAP_DSS_ROT_0 + 4:
1287 case OMAP_DSS_ROT_180 + 4:
1288 /* If the pixel format is YUV or UYVY divide the width
1289 * of the image by 2 for 0 degree and 180 degree
1291 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1292 color_mode == OMAP_DSS_COLOR_UYVY)
1294 case OMAP_DSS_ROT_90 + 4:
1295 case OMAP_DSS_ROT_270 + 4:
1298 *offset0 = field_offset * screen_width * ps;
1301 *row_inc = pixinc(1 - (screen_width + width) -
1302 (fieldmode ? screen_width : 0),
1304 *pix_inc = pixinc(1, ps);
1312 static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1314 u16 width, u16 height,
1315 enum omap_color_mode color_mode, bool fieldmode,
1316 unsigned int field_offset,
1317 unsigned *offset0, unsigned *offset1,
1318 s32 *row_inc, s32 *pix_inc)
1323 /* FIXME CLUT formats */
1324 switch (color_mode) {
1325 case OMAP_DSS_COLOR_CLUT1:
1326 case OMAP_DSS_COLOR_CLUT2:
1327 case OMAP_DSS_COLOR_CLUT4:
1328 case OMAP_DSS_COLOR_CLUT8:
1332 ps = color_mode_to_bpp(color_mode) / 8;
1336 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1339 /* width & height are overlay sizes, convert to fb sizes */
1341 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1350 * field 0 = even field = bottom field
1351 * field 1 = odd field = top field
1353 switch (rotation + mirror * 4) {
1354 case OMAP_DSS_ROT_0:
1357 *offset0 = *offset1 + field_offset * screen_width * ps;
1359 *offset0 = *offset1;
1360 *row_inc = pixinc(1 + (screen_width - fbw) +
1361 (fieldmode ? screen_width : 0),
1363 *pix_inc = pixinc(1, ps);
1365 case OMAP_DSS_ROT_90:
1366 *offset1 = screen_width * (fbh - 1) * ps;
1368 *offset0 = *offset1 + field_offset * ps;
1370 *offset0 = *offset1;
1371 *row_inc = pixinc(screen_width * (fbh - 1) + 1 +
1372 (fieldmode ? 1 : 0), ps);
1373 *pix_inc = pixinc(-screen_width, ps);
1375 case OMAP_DSS_ROT_180:
1376 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1378 *offset0 = *offset1 - field_offset * screen_width * ps;
1380 *offset0 = *offset1;
1381 *row_inc = pixinc(-1 -
1382 (screen_width - fbw) -
1383 (fieldmode ? screen_width : 0),
1385 *pix_inc = pixinc(-1, ps);
1387 case OMAP_DSS_ROT_270:
1388 *offset1 = (fbw - 1) * ps;
1390 *offset0 = *offset1 - field_offset * ps;
1392 *offset0 = *offset1;
1393 *row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
1394 (fieldmode ? 1 : 0), ps);
1395 *pix_inc = pixinc(screen_width, ps);
1399 case OMAP_DSS_ROT_0 + 4:
1400 *offset1 = (fbw - 1) * ps;
1402 *offset0 = *offset1 + field_offset * screen_width * ps;
1404 *offset0 = *offset1;
1405 *row_inc = pixinc(screen_width * 2 - 1 +
1406 (fieldmode ? screen_width : 0),
1408 *pix_inc = pixinc(-1, ps);
1411 case OMAP_DSS_ROT_90 + 4:
1414 *offset0 = *offset1 + field_offset * ps;
1416 *offset0 = *offset1;
1417 *row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
1418 (fieldmode ? 1 : 0),
1420 *pix_inc = pixinc(screen_width, ps);
1423 case OMAP_DSS_ROT_180 + 4:
1424 *offset1 = screen_width * (fbh - 1) * ps;
1426 *offset0 = *offset1 - field_offset * screen_width * ps;
1428 *offset0 = *offset1;
1429 *row_inc = pixinc(1 - screen_width * 2 -
1430 (fieldmode ? screen_width : 0),
1432 *pix_inc = pixinc(1, ps);
1435 case OMAP_DSS_ROT_270 + 4:
1436 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1438 *offset0 = *offset1 - field_offset * ps;
1440 *offset0 = *offset1;
1441 *row_inc = pixinc(screen_width * (fbh - 1) - 1 -
1442 (fieldmode ? 1 : 0),
1444 *pix_inc = pixinc(-screen_width, ps);
1452 static unsigned long calc_fclk_five_taps(u16 width, u16 height,
1453 u16 out_width, u16 out_height, enum omap_color_mode color_mode)
1456 /* FIXME venc pclk? */
1457 u64 tmp, pclk = dispc_pclk_rate();
1459 if (height > out_height) {
1460 /* FIXME get real display PPL */
1461 unsigned int ppl = 800;
1463 tmp = pclk * height * out_width;
1464 do_div(tmp, 2 * out_height * ppl);
1467 if (height > 2 * out_height) {
1468 if (ppl == out_width)
1471 tmp = pclk * (height - 2 * out_height) * out_width;
1472 do_div(tmp, 2 * out_height * (ppl - out_width));
1473 fclk = max(fclk, (u32) tmp);
1477 if (width > out_width) {
1479 do_div(tmp, out_width);
1480 fclk = max(fclk, (u32) tmp);
1482 if (color_mode == OMAP_DSS_COLOR_RGB24U)
1489 static unsigned long calc_fclk(u16 width, u16 height,
1490 u16 out_width, u16 out_height)
1492 unsigned int hf, vf;
1495 * FIXME how to determine the 'A' factor
1496 * for the no downscaling case ?
1499 if (width > 3 * out_width)
1501 else if (width > 2 * out_width)
1503 else if (width > out_width)
1508 if (height > out_height)
1513 /* FIXME venc pclk? */
1514 return dispc_pclk_rate() * vf * hf;
1517 void dispc_set_channel_out(enum omap_plane plane, enum omap_channel channel_out)
1520 _dispc_set_channel_out(plane, channel_out);
1524 static int _dispc_setup_plane(enum omap_plane plane,
1525 u32 paddr, u16 screen_width,
1526 u16 pos_x, u16 pos_y,
1527 u16 width, u16 height,
1528 u16 out_width, u16 out_height,
1529 enum omap_color_mode color_mode,
1531 enum omap_dss_rotation_type rotation_type,
1532 u8 rotation, int mirror,
1535 const int maxdownscale = cpu_is_omap34xx() ? 4 : 2;
1539 unsigned offset0, offset1;
1542 u16 frame_height = height;
1543 unsigned int field_offset = 0;
1548 if (ilace && height == out_height)
1557 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
1559 height, pos_y, out_height);
1562 if (plane == OMAP_DSS_GFX) {
1563 if (width != out_width || height != out_height)
1566 switch (color_mode) {
1567 case OMAP_DSS_COLOR_ARGB16:
1568 case OMAP_DSS_COLOR_ARGB32:
1569 case OMAP_DSS_COLOR_RGBA32:
1570 case OMAP_DSS_COLOR_RGBX32:
1571 if (cpu_is_omap24xx())
1574 case OMAP_DSS_COLOR_RGB12U:
1575 case OMAP_DSS_COLOR_RGB16:
1576 case OMAP_DSS_COLOR_RGB24P:
1577 case OMAP_DSS_COLOR_RGB24U:
1586 unsigned long fclk = 0;
1588 if (out_width < width / maxdownscale ||
1589 out_width > width * 8)
1592 if (out_height < height / maxdownscale ||
1593 out_height > height * 8)
1596 switch (color_mode) {
1597 case OMAP_DSS_COLOR_RGBX32:
1598 case OMAP_DSS_COLOR_RGB12U:
1599 if (cpu_is_omap24xx())
1602 case OMAP_DSS_COLOR_RGB16:
1603 case OMAP_DSS_COLOR_RGB24P:
1604 case OMAP_DSS_COLOR_RGB24U:
1607 case OMAP_DSS_COLOR_ARGB16:
1608 case OMAP_DSS_COLOR_ARGB32:
1609 case OMAP_DSS_COLOR_RGBA32:
1610 if (cpu_is_omap24xx())
1612 if (plane == OMAP_DSS_VIDEO1)
1616 case OMAP_DSS_COLOR_YUV2:
1617 case OMAP_DSS_COLOR_UYVY:
1625 /* Must use 5-tap filter? */
1626 five_taps = height > out_height * 2;
1629 fclk = calc_fclk(width, height,
1630 out_width, out_height);
1632 /* Try 5-tap filter if 3-tap fclk is too high */
1633 if (cpu_is_omap34xx() && height > out_height &&
1634 fclk > dispc_fclk_rate())
1638 if (width > (2048 >> five_taps)) {
1639 DSSERR("failed to set up scaling, fclk too low\n");
1644 fclk = calc_fclk_five_taps(width, height,
1645 out_width, out_height, color_mode);
1647 DSSDBG("required fclk rate = %lu Hz\n", fclk);
1648 DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
1650 if (!fclk || fclk > dispc_fclk_rate()) {
1651 DSSERR("failed to set up scaling, "
1652 "required fclk rate = %lu Hz, "
1653 "current fclk rate = %lu Hz\n",
1654 fclk, dispc_fclk_rate());
1659 if (ilace && !fieldmode) {
1661 * when downscaling the bottom field may have to start several
1662 * source lines below the top field. Unfortunately ACCUI
1663 * registers will only hold the fractional part of the offset
1664 * so the integer part must be added to the base address of the
1667 if (!height || height == out_height)
1670 field_offset = height / out_height / 2;
1673 /* Fields are independent but interleaved in memory. */
1677 if (rotation_type == OMAP_DSS_ROT_DMA)
1678 calc_dma_rotation_offset(rotation, mirror,
1679 screen_width, width, frame_height, color_mode,
1680 fieldmode, field_offset,
1681 &offset0, &offset1, &row_inc, &pix_inc);
1683 calc_vrfb_rotation_offset(rotation, mirror,
1684 screen_width, width, frame_height, color_mode,
1685 fieldmode, field_offset,
1686 &offset0, &offset1, &row_inc, &pix_inc);
1688 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
1689 offset0, offset1, row_inc, pix_inc);
1691 _dispc_set_color_mode(plane, color_mode);
1693 _dispc_set_plane_ba0(plane, paddr + offset0);
1694 _dispc_set_plane_ba1(plane, paddr + offset1);
1696 _dispc_set_row_inc(plane, row_inc);
1697 _dispc_set_pix_inc(plane, pix_inc);
1699 DSSDBG("%d,%d %dx%d -> %dx%d\n", pos_x, pos_y, width, height,
1700 out_width, out_height);
1702 _dispc_set_plane_pos(plane, pos_x, pos_y);
1704 _dispc_set_pic_size(plane, width, height);
1706 if (plane != OMAP_DSS_GFX) {
1707 _dispc_set_scaling(plane, width, height,
1708 out_width, out_height,
1709 ilace, five_taps, fieldmode);
1710 _dispc_set_vid_size(plane, out_width, out_height);
1711 _dispc_set_vid_color_conv(plane, cconv);
1714 _dispc_set_rotation_attrs(plane, rotation, mirror, color_mode);
1716 if (plane != OMAP_DSS_VIDEO1)
1717 _dispc_setup_global_alpha(plane, global_alpha);
1722 static void _dispc_enable_plane(enum omap_plane plane, bool enable)
1724 REG_FLD_MOD(dispc_reg_att[plane], enable ? 1 : 0, 0, 0);
1727 static void dispc_disable_isr(void *data, u32 mask)
1729 struct completion *compl = data;
1733 static void _enable_lcd_out(bool enable)
1735 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
1738 static void dispc_enable_lcd_out(bool enable)
1740 struct completion frame_done_completion;
1746 /* When we disable LCD output, we need to wait until frame is done.
1747 * Otherwise the DSS is still working, and turning off the clocks
1748 * prevents DSS from going to OFF mode */
1749 is_on = REG_GET(DISPC_CONTROL, 0, 0);
1751 if (!enable && is_on) {
1752 init_completion(&frame_done_completion);
1754 r = omap_dispc_register_isr(dispc_disable_isr,
1755 &frame_done_completion,
1756 DISPC_IRQ_FRAMEDONE);
1759 DSSERR("failed to register FRAMEDONE isr\n");
1762 _enable_lcd_out(enable);
1764 if (!enable && is_on) {
1765 if (!wait_for_completion_timeout(&frame_done_completion,
1766 msecs_to_jiffies(100)))
1767 DSSERR("timeout waiting for FRAME DONE\n");
1769 r = omap_dispc_unregister_isr(dispc_disable_isr,
1770 &frame_done_completion,
1771 DISPC_IRQ_FRAMEDONE);
1774 DSSERR("failed to unregister FRAMEDONE isr\n");
1780 static void _enable_digit_out(bool enable)
1782 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
1785 static void dispc_enable_digit_out(bool enable)
1787 struct completion frame_done_completion;
1792 if (REG_GET(DISPC_CONTROL, 1, 1) == enable) {
1798 unsigned long flags;
1799 /* When we enable digit output, we'll get an extra digit
1800 * sync lost interrupt, that we need to ignore */
1801 spin_lock_irqsave(&dispc.irq_lock, flags);
1802 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
1803 _omap_dispc_set_irqs();
1804 spin_unlock_irqrestore(&dispc.irq_lock, flags);
1807 /* When we disable digit output, we need to wait until fields are done.
1808 * Otherwise the DSS is still working, and turning off the clocks
1809 * prevents DSS from going to OFF mode. And when enabling, we need to
1810 * wait for the extra sync losts */
1811 init_completion(&frame_done_completion);
1813 r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
1814 DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1816 DSSERR("failed to register EVSYNC isr\n");
1818 _enable_digit_out(enable);
1820 /* XXX I understand from TRM that we should only wait for the
1821 * current field to complete. But it seems we have to wait
1822 * for both fields */
1823 if (!wait_for_completion_timeout(&frame_done_completion,
1824 msecs_to_jiffies(100)))
1825 DSSERR("timeout waiting for EVSYNC\n");
1827 if (!wait_for_completion_timeout(&frame_done_completion,
1828 msecs_to_jiffies(100)))
1829 DSSERR("timeout waiting for EVSYNC\n");
1831 r = omap_dispc_unregister_isr(dispc_disable_isr,
1832 &frame_done_completion,
1833 DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD);
1835 DSSERR("failed to unregister EVSYNC isr\n");
1838 unsigned long flags;
1839 spin_lock_irqsave(&dispc.irq_lock, flags);
1840 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
1841 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
1842 _omap_dispc_set_irqs();
1843 spin_unlock_irqrestore(&dispc.irq_lock, flags);
1849 bool dispc_is_channel_enabled(enum omap_channel channel)
1851 if (channel == OMAP_DSS_CHANNEL_LCD)
1852 return !!REG_GET(DISPC_CONTROL, 0, 0);
1853 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
1854 return !!REG_GET(DISPC_CONTROL, 1, 1);
1859 void dispc_enable_channel(enum omap_channel channel, bool enable)
1861 if (channel == OMAP_DSS_CHANNEL_LCD)
1862 dispc_enable_lcd_out(enable);
1863 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
1864 dispc_enable_digit_out(enable);
1869 void dispc_lcd_enable_signal_polarity(bool act_high)
1872 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
1876 void dispc_lcd_enable_signal(bool enable)
1879 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
1883 void dispc_pck_free_enable(bool enable)
1886 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
1890 void dispc_enable_fifohandcheck(bool enable)
1893 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
1898 void dispc_set_lcd_display_type(enum omap_lcd_display_type type)
1903 case OMAP_DSS_LCD_DISPLAY_STN:
1907 case OMAP_DSS_LCD_DISPLAY_TFT:
1917 REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
1921 void dispc_set_loadmode(enum omap_dss_load_mode mode)
1924 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
1929 void dispc_set_default_color(enum omap_channel channel, u32 color)
1931 const struct dispc_reg def_reg[] = { DISPC_DEFAULT_COLOR0,
1932 DISPC_DEFAULT_COLOR1 };
1935 dispc_write_reg(def_reg[channel], color);
1939 u32 dispc_get_default_color(enum omap_channel channel)
1941 const struct dispc_reg def_reg[] = { DISPC_DEFAULT_COLOR0,
1942 DISPC_DEFAULT_COLOR1 };
1945 BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT &&
1946 channel != OMAP_DSS_CHANNEL_LCD);
1949 l = dispc_read_reg(def_reg[channel]);
1955 void dispc_set_trans_key(enum omap_channel ch,
1956 enum omap_dss_trans_key_type type,
1959 const struct dispc_reg tr_reg[] = {
1960 DISPC_TRANS_COLOR0, DISPC_TRANS_COLOR1 };
1963 if (ch == OMAP_DSS_CHANNEL_LCD)
1964 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
1965 else /* OMAP_DSS_CHANNEL_DIGIT */
1966 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
1968 dispc_write_reg(tr_reg[ch], trans_key);
1972 void dispc_get_trans_key(enum omap_channel ch,
1973 enum omap_dss_trans_key_type *type,
1976 const struct dispc_reg tr_reg[] = {
1977 DISPC_TRANS_COLOR0, DISPC_TRANS_COLOR1 };
1981 if (ch == OMAP_DSS_CHANNEL_LCD)
1982 *type = REG_GET(DISPC_CONFIG, 11, 11);
1983 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
1984 *type = REG_GET(DISPC_CONFIG, 13, 13);
1990 *trans_key = dispc_read_reg(tr_reg[ch]);
1994 void dispc_enable_trans_key(enum omap_channel ch, bool enable)
1997 if (ch == OMAP_DSS_CHANNEL_LCD)
1998 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
1999 else /* OMAP_DSS_CHANNEL_DIGIT */
2000 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
2003 void dispc_enable_alpha_blending(enum omap_channel ch, bool enable)
2005 if (cpu_is_omap24xx())
2009 if (ch == OMAP_DSS_CHANNEL_LCD)
2010 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2011 else /* OMAP_DSS_CHANNEL_DIGIT */
2012 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2015 bool dispc_alpha_blending_enabled(enum omap_channel ch)
2019 if (cpu_is_omap24xx())
2023 if (ch == OMAP_DSS_CHANNEL_LCD)
2024 enabled = REG_GET(DISPC_CONFIG, 18, 18);
2025 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2026 enabled = REG_GET(DISPC_CONFIG, 18, 18);
2036 bool dispc_trans_key_enabled(enum omap_channel ch)
2041 if (ch == OMAP_DSS_CHANNEL_LCD)
2042 enabled = REG_GET(DISPC_CONFIG, 10, 10);
2043 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2044 enabled = REG_GET(DISPC_CONFIG, 12, 12);
2053 void dispc_set_tft_data_lines(u8 data_lines)
2057 switch (data_lines) {
2076 REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
2080 void dispc_set_parallel_interface_mode(enum omap_parallel_interface_mode mode)
2088 case OMAP_DSS_PARALLELMODE_BYPASS:
2093 case OMAP_DSS_PARALLELMODE_RFBI:
2098 case OMAP_DSS_PARALLELMODE_DSI:
2110 l = dispc_read_reg(DISPC_CONTROL);
2112 l = FLD_MOD(l, stallmode, 11, 11);
2113 l = FLD_MOD(l, gpout0, 15, 15);
2114 l = FLD_MOD(l, gpout1, 16, 16);
2116 dispc_write_reg(DISPC_CONTROL, l);
2121 static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2122 int vsw, int vfp, int vbp)
2124 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2125 if (hsw < 1 || hsw > 64 ||
2126 hfp < 1 || hfp > 256 ||
2127 hbp < 1 || hbp > 256 ||
2128 vsw < 1 || vsw > 64 ||
2129 vfp < 0 || vfp > 255 ||
2130 vbp < 0 || vbp > 255)
2133 if (hsw < 1 || hsw > 256 ||
2134 hfp < 1 || hfp > 4096 ||
2135 hbp < 1 || hbp > 4096 ||
2136 vsw < 1 || vsw > 256 ||
2137 vfp < 0 || vfp > 4095 ||
2138 vbp < 0 || vbp > 4095)
2145 bool dispc_lcd_timings_ok(struct omap_video_timings *timings)
2147 return _dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2148 timings->hbp, timings->vsw,
2149 timings->vfp, timings->vbp);
2152 static void _dispc_set_lcd_timings(int hsw, int hfp, int hbp,
2153 int vsw, int vfp, int vbp)
2155 u32 timing_h, timing_v;
2157 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2158 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
2159 FLD_VAL(hbp-1, 27, 20);
2161 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
2162 FLD_VAL(vbp, 27, 20);
2164 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
2165 FLD_VAL(hbp-1, 31, 20);
2167 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
2168 FLD_VAL(vbp, 31, 20);
2172 dispc_write_reg(DISPC_TIMING_H, timing_h);
2173 dispc_write_reg(DISPC_TIMING_V, timing_v);
2177 /* change name to mode? */
2178 void dispc_set_lcd_timings(struct omap_video_timings *timings)
2180 unsigned xtot, ytot;
2181 unsigned long ht, vt;
2183 if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2184 timings->hbp, timings->vsw,
2185 timings->vfp, timings->vbp))
2188 _dispc_set_lcd_timings(timings->hsw, timings->hfp, timings->hbp,
2189 timings->vsw, timings->vfp, timings->vbp);
2191 dispc_set_lcd_size(timings->x_res, timings->y_res);
2193 xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
2194 ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
2196 ht = (timings->pixel_clock * 1000) / xtot;
2197 vt = (timings->pixel_clock * 1000) / xtot / ytot;
2199 DSSDBG("xres %u yres %u\n", timings->x_res, timings->y_res);
2200 DSSDBG("pck %u\n", timings->pixel_clock);
2201 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2202 timings->hsw, timings->hfp, timings->hbp,
2203 timings->vsw, timings->vfp, timings->vbp);
2205 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2208 static void dispc_set_lcd_divisor(u16 lck_div, u16 pck_div)
2210 BUG_ON(lck_div < 1);
2211 BUG_ON(pck_div < 2);
2214 dispc_write_reg(DISPC_DIVISOR,
2215 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
2219 static void dispc_get_lcd_divisor(int *lck_div, int *pck_div)
2222 l = dispc_read_reg(DISPC_DIVISOR);
2223 *lck_div = FLD_GET(l, 23, 16);
2224 *pck_div = FLD_GET(l, 7, 0);
2227 unsigned long dispc_fclk_rate(void)
2229 unsigned long r = 0;
2231 if (dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK)
2232 r = dss_clk_get_rate(DSS_CLK_FCK1);
2234 #ifdef CONFIG_OMAP2_DSS_DSI
2235 r = dsi_get_dsi1_pll_rate();
2242 unsigned long dispc_lclk_rate(void)
2248 l = dispc_read_reg(DISPC_DIVISOR);
2250 lcd = FLD_GET(l, 23, 16);
2252 r = dispc_fclk_rate();
2257 unsigned long dispc_pclk_rate(void)
2263 l = dispc_read_reg(DISPC_DIVISOR);
2265 lcd = FLD_GET(l, 23, 16);
2266 pcd = FLD_GET(l, 7, 0);
2268 r = dispc_fclk_rate();
2270 return r / lcd / pcd;
2273 void dispc_dump_clocks(struct seq_file *s)
2279 dispc_get_lcd_divisor(&lcd, &pcd);
2281 seq_printf(s, "- DISPC -\n");
2283 seq_printf(s, "dispc fclk source = %s\n",
2284 dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ?
2285 "dss1_alwon_fclk" : "dsi1_pll_fclk");
2287 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2288 seq_printf(s, "lck\t\t%-16lulck div\t%u\n", dispc_lclk_rate(), lcd);
2289 seq_printf(s, "pck\t\t%-16lupck div\t%u\n", dispc_pclk_rate(), pcd);
2294 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2295 void dispc_dump_irqs(struct seq_file *s)
2297 unsigned long flags;
2298 struct dispc_irq_stats stats;
2300 spin_lock_irqsave(&dispc.irq_stats_lock, flags);
2302 stats = dispc.irq_stats;
2303 memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
2304 dispc.irq_stats.last_reset = jiffies;
2306 spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
2308 seq_printf(s, "period %u ms\n",
2309 jiffies_to_msecs(jiffies - stats.last_reset));
2311 seq_printf(s, "irqs %d\n", stats.irq_count);
2313 seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
2319 PIS(ACBIAS_COUNT_STAT);
2321 PIS(GFX_FIFO_UNDERFLOW);
2323 PIS(PAL_GAMMA_MASK);
2325 PIS(VID1_FIFO_UNDERFLOW);
2327 PIS(VID2_FIFO_UNDERFLOW);
2330 PIS(SYNC_LOST_DIGIT);
2336 void dispc_dump_regs(struct seq_file *s)
2338 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dispc_read_reg(r))
2340 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK1);
2342 DUMPREG(DISPC_REVISION);
2343 DUMPREG(DISPC_SYSCONFIG);
2344 DUMPREG(DISPC_SYSSTATUS);
2345 DUMPREG(DISPC_IRQSTATUS);
2346 DUMPREG(DISPC_IRQENABLE);
2347 DUMPREG(DISPC_CONTROL);
2348 DUMPREG(DISPC_CONFIG);
2349 DUMPREG(DISPC_CAPABLE);
2350 DUMPREG(DISPC_DEFAULT_COLOR0);
2351 DUMPREG(DISPC_DEFAULT_COLOR1);
2352 DUMPREG(DISPC_TRANS_COLOR0);
2353 DUMPREG(DISPC_TRANS_COLOR1);
2354 DUMPREG(DISPC_LINE_STATUS);
2355 DUMPREG(DISPC_LINE_NUMBER);
2356 DUMPREG(DISPC_TIMING_H);
2357 DUMPREG(DISPC_TIMING_V);
2358 DUMPREG(DISPC_POL_FREQ);
2359 DUMPREG(DISPC_DIVISOR);
2360 DUMPREG(DISPC_GLOBAL_ALPHA);
2361 DUMPREG(DISPC_SIZE_DIG);
2362 DUMPREG(DISPC_SIZE_LCD);
2364 DUMPREG(DISPC_GFX_BA0);
2365 DUMPREG(DISPC_GFX_BA1);
2366 DUMPREG(DISPC_GFX_POSITION);
2367 DUMPREG(DISPC_GFX_SIZE);
2368 DUMPREG(DISPC_GFX_ATTRIBUTES);
2369 DUMPREG(DISPC_GFX_FIFO_THRESHOLD);
2370 DUMPREG(DISPC_GFX_FIFO_SIZE_STATUS);
2371 DUMPREG(DISPC_GFX_ROW_INC);
2372 DUMPREG(DISPC_GFX_PIXEL_INC);
2373 DUMPREG(DISPC_GFX_WINDOW_SKIP);
2374 DUMPREG(DISPC_GFX_TABLE_BA);
2376 DUMPREG(DISPC_DATA_CYCLE1);
2377 DUMPREG(DISPC_DATA_CYCLE2);
2378 DUMPREG(DISPC_DATA_CYCLE3);
2380 DUMPREG(DISPC_CPR_COEF_R);
2381 DUMPREG(DISPC_CPR_COEF_G);
2382 DUMPREG(DISPC_CPR_COEF_B);
2384 DUMPREG(DISPC_GFX_PRELOAD);
2386 DUMPREG(DISPC_VID_BA0(0));
2387 DUMPREG(DISPC_VID_BA1(0));
2388 DUMPREG(DISPC_VID_POSITION(0));
2389 DUMPREG(DISPC_VID_SIZE(0));
2390 DUMPREG(DISPC_VID_ATTRIBUTES(0));
2391 DUMPREG(DISPC_VID_FIFO_THRESHOLD(0));
2392 DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(0));
2393 DUMPREG(DISPC_VID_ROW_INC(0));
2394 DUMPREG(DISPC_VID_PIXEL_INC(0));
2395 DUMPREG(DISPC_VID_FIR(0));
2396 DUMPREG(DISPC_VID_PICTURE_SIZE(0));
2397 DUMPREG(DISPC_VID_ACCU0(0));
2398 DUMPREG(DISPC_VID_ACCU1(0));
2400 DUMPREG(DISPC_VID_BA0(1));
2401 DUMPREG(DISPC_VID_BA1(1));
2402 DUMPREG(DISPC_VID_POSITION(1));
2403 DUMPREG(DISPC_VID_SIZE(1));
2404 DUMPREG(DISPC_VID_ATTRIBUTES(1));
2405 DUMPREG(DISPC_VID_FIFO_THRESHOLD(1));
2406 DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(1));
2407 DUMPREG(DISPC_VID_ROW_INC(1));
2408 DUMPREG(DISPC_VID_PIXEL_INC(1));
2409 DUMPREG(DISPC_VID_FIR(1));
2410 DUMPREG(DISPC_VID_PICTURE_SIZE(1));
2411 DUMPREG(DISPC_VID_ACCU0(1));
2412 DUMPREG(DISPC_VID_ACCU1(1));
2414 DUMPREG(DISPC_VID_FIR_COEF_H(0, 0));
2415 DUMPREG(DISPC_VID_FIR_COEF_H(0, 1));
2416 DUMPREG(DISPC_VID_FIR_COEF_H(0, 2));
2417 DUMPREG(DISPC_VID_FIR_COEF_H(0, 3));
2418 DUMPREG(DISPC_VID_FIR_COEF_H(0, 4));
2419 DUMPREG(DISPC_VID_FIR_COEF_H(0, 5));
2420 DUMPREG(DISPC_VID_FIR_COEF_H(0, 6));
2421 DUMPREG(DISPC_VID_FIR_COEF_H(0, 7));
2422 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 0));
2423 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 1));
2424 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 2));
2425 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 3));
2426 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 4));
2427 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 5));
2428 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 6));
2429 DUMPREG(DISPC_VID_FIR_COEF_HV(0, 7));
2430 DUMPREG(DISPC_VID_CONV_COEF(0, 0));
2431 DUMPREG(DISPC_VID_CONV_COEF(0, 1));
2432 DUMPREG(DISPC_VID_CONV_COEF(0, 2));
2433 DUMPREG(DISPC_VID_CONV_COEF(0, 3));
2434 DUMPREG(DISPC_VID_CONV_COEF(0, 4));
2435 DUMPREG(DISPC_VID_FIR_COEF_V(0, 0));
2436 DUMPREG(DISPC_VID_FIR_COEF_V(0, 1));
2437 DUMPREG(DISPC_VID_FIR_COEF_V(0, 2));
2438 DUMPREG(DISPC_VID_FIR_COEF_V(0, 3));
2439 DUMPREG(DISPC_VID_FIR_COEF_V(0, 4));
2440 DUMPREG(DISPC_VID_FIR_COEF_V(0, 5));
2441 DUMPREG(DISPC_VID_FIR_COEF_V(0, 6));
2442 DUMPREG(DISPC_VID_FIR_COEF_V(0, 7));
2444 DUMPREG(DISPC_VID_FIR_COEF_H(1, 0));
2445 DUMPREG(DISPC_VID_FIR_COEF_H(1, 1));
2446 DUMPREG(DISPC_VID_FIR_COEF_H(1, 2));
2447 DUMPREG(DISPC_VID_FIR_COEF_H(1, 3));
2448 DUMPREG(DISPC_VID_FIR_COEF_H(1, 4));
2449 DUMPREG(DISPC_VID_FIR_COEF_H(1, 5));
2450 DUMPREG(DISPC_VID_FIR_COEF_H(1, 6));
2451 DUMPREG(DISPC_VID_FIR_COEF_H(1, 7));
2452 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 0));
2453 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 1));
2454 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 2));
2455 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 3));
2456 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 4));
2457 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 5));
2458 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 6));
2459 DUMPREG(DISPC_VID_FIR_COEF_HV(1, 7));
2460 DUMPREG(DISPC_VID_CONV_COEF(1, 0));
2461 DUMPREG(DISPC_VID_CONV_COEF(1, 1));
2462 DUMPREG(DISPC_VID_CONV_COEF(1, 2));
2463 DUMPREG(DISPC_VID_CONV_COEF(1, 3));
2464 DUMPREG(DISPC_VID_CONV_COEF(1, 4));
2465 DUMPREG(DISPC_VID_FIR_COEF_V(1, 0));
2466 DUMPREG(DISPC_VID_FIR_COEF_V(1, 1));
2467 DUMPREG(DISPC_VID_FIR_COEF_V(1, 2));
2468 DUMPREG(DISPC_VID_FIR_COEF_V(1, 3));
2469 DUMPREG(DISPC_VID_FIR_COEF_V(1, 4));
2470 DUMPREG(DISPC_VID_FIR_COEF_V(1, 5));
2471 DUMPREG(DISPC_VID_FIR_COEF_V(1, 6));
2472 DUMPREG(DISPC_VID_FIR_COEF_V(1, 7));
2474 DUMPREG(DISPC_VID_PRELOAD(0));
2475 DUMPREG(DISPC_VID_PRELOAD(1));
2477 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK1);
2481 static void _dispc_set_pol_freq(bool onoff, bool rf, bool ieo, bool ipc,
2482 bool ihs, bool ivs, u8 acbi, u8 acb)
2486 DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
2487 onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
2489 l |= FLD_VAL(onoff, 17, 17);
2490 l |= FLD_VAL(rf, 16, 16);
2491 l |= FLD_VAL(ieo, 15, 15);
2492 l |= FLD_VAL(ipc, 14, 14);
2493 l |= FLD_VAL(ihs, 13, 13);
2494 l |= FLD_VAL(ivs, 12, 12);
2495 l |= FLD_VAL(acbi, 11, 8);
2496 l |= FLD_VAL(acb, 7, 0);
2499 dispc_write_reg(DISPC_POL_FREQ, l);
2503 void dispc_set_pol_freq(enum omap_panel_config config, u8 acbi, u8 acb)
2505 _dispc_set_pol_freq((config & OMAP_DSS_LCD_ONOFF) != 0,
2506 (config & OMAP_DSS_LCD_RF) != 0,
2507 (config & OMAP_DSS_LCD_IEO) != 0,
2508 (config & OMAP_DSS_LCD_IPC) != 0,
2509 (config & OMAP_DSS_LCD_IHS) != 0,
2510 (config & OMAP_DSS_LCD_IVS) != 0,
2514 /* with fck as input clock rate, find dispc dividers that produce req_pck */
2515 void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
2516 struct dispc_clock_info *cinfo)
2518 u16 pcd_min = is_tft ? 2 : 3;
2519 unsigned long best_pck;
2520 u16 best_ld, cur_ld;
2521 u16 best_pd, cur_pd;
2527 for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
2528 unsigned long lck = fck / cur_ld;
2530 for (cur_pd = pcd_min; cur_pd <= 255; ++cur_pd) {
2531 unsigned long pck = lck / cur_pd;
2532 long old_delta = abs(best_pck - req_pck);
2533 long new_delta = abs(pck - req_pck);
2535 if (best_pck == 0 || new_delta < old_delta) {
2548 if (lck / pcd_min < req_pck)
2553 cinfo->lck_div = best_ld;
2554 cinfo->pck_div = best_pd;
2555 cinfo->lck = fck / cinfo->lck_div;
2556 cinfo->pck = cinfo->lck / cinfo->pck_div;
2559 /* calculate clock rates using dividers in cinfo */
2560 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
2561 struct dispc_clock_info *cinfo)
2563 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
2565 if (cinfo->pck_div < 2 || cinfo->pck_div > 255)
2568 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
2569 cinfo->pck = cinfo->lck / cinfo->pck_div;
2574 int dispc_set_clock_div(struct dispc_clock_info *cinfo)
2576 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
2577 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
2579 dispc_set_lcd_divisor(cinfo->lck_div, cinfo->pck_div);
2584 int dispc_get_clock_div(struct dispc_clock_info *cinfo)
2588 fck = dispc_fclk_rate();
2590 cinfo->lck_div = REG_GET(DISPC_DIVISOR, 23, 16);
2591 cinfo->pck_div = REG_GET(DISPC_DIVISOR, 7, 0);
2593 cinfo->lck = fck / cinfo->lck_div;
2594 cinfo->pck = cinfo->lck / cinfo->pck_div;
2599 /* dispc.irq_lock has to be locked by the caller */
2600 static void _omap_dispc_set_irqs(void)
2605 struct omap_dispc_isr_data *isr_data;
2607 mask = dispc.irq_error_mask;
2609 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2610 isr_data = &dispc.registered_isr[i];
2612 if (isr_data->isr == NULL)
2615 mask |= isr_data->mask;
2620 old_mask = dispc_read_reg(DISPC_IRQENABLE);
2621 /* clear the irqstatus for newly enabled irqs */
2622 dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
2624 dispc_write_reg(DISPC_IRQENABLE, mask);
2629 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2633 unsigned long flags;
2634 struct omap_dispc_isr_data *isr_data;
2639 spin_lock_irqsave(&dispc.irq_lock, flags);
2641 /* check for duplicate entry */
2642 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2643 isr_data = &dispc.registered_isr[i];
2644 if (isr_data->isr == isr && isr_data->arg == arg &&
2645 isr_data->mask == mask) {
2654 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2655 isr_data = &dispc.registered_isr[i];
2657 if (isr_data->isr != NULL)
2660 isr_data->isr = isr;
2661 isr_data->arg = arg;
2662 isr_data->mask = mask;
2668 _omap_dispc_set_irqs();
2670 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2674 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2678 EXPORT_SYMBOL(omap_dispc_register_isr);
2680 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2683 unsigned long flags;
2685 struct omap_dispc_isr_data *isr_data;
2687 spin_lock_irqsave(&dispc.irq_lock, flags);
2689 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2690 isr_data = &dispc.registered_isr[i];
2691 if (isr_data->isr != isr || isr_data->arg != arg ||
2692 isr_data->mask != mask)
2695 /* found the correct isr */
2697 isr_data->isr = NULL;
2698 isr_data->arg = NULL;
2706 _omap_dispc_set_irqs();
2708 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2712 EXPORT_SYMBOL(omap_dispc_unregister_isr);
2715 static void print_irq_status(u32 status)
2717 if ((status & dispc.irq_error_mask) == 0)
2720 printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
2723 if (status & DISPC_IRQ_##x) \
2725 PIS(GFX_FIFO_UNDERFLOW);
2727 PIS(VID1_FIFO_UNDERFLOW);
2728 PIS(VID2_FIFO_UNDERFLOW);
2730 PIS(SYNC_LOST_DIGIT);
2737 /* Called from dss.c. Note that we don't touch clocks here,
2738 * but we presume they are on because we got an IRQ. However,
2739 * an irq handler may turn the clocks off, so we may not have
2740 * clock later in the function. */
2741 void dispc_irq_handler(void)
2745 u32 handledirqs = 0;
2746 u32 unhandled_errors;
2747 struct omap_dispc_isr_data *isr_data;
2748 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
2750 spin_lock(&dispc.irq_lock);
2752 irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
2754 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2755 spin_lock(&dispc.irq_stats_lock);
2756 dispc.irq_stats.irq_count++;
2757 dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
2758 spin_unlock(&dispc.irq_stats_lock);
2763 print_irq_status(irqstatus);
2765 /* Ack the interrupt. Do it here before clocks are possibly turned
2767 dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
2768 /* flush posted write */
2769 dispc_read_reg(DISPC_IRQSTATUS);
2771 /* make a copy and unlock, so that isrs can unregister
2773 memcpy(registered_isr, dispc.registered_isr,
2774 sizeof(registered_isr));
2776 spin_unlock(&dispc.irq_lock);
2778 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2779 isr_data = ®istered_isr[i];
2784 if (isr_data->mask & irqstatus) {
2785 isr_data->isr(isr_data->arg, irqstatus);
2786 handledirqs |= isr_data->mask;
2790 spin_lock(&dispc.irq_lock);
2792 unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
2794 if (unhandled_errors) {
2795 dispc.error_irqs |= unhandled_errors;
2797 dispc.irq_error_mask &= ~unhandled_errors;
2798 _omap_dispc_set_irqs();
2800 schedule_work(&dispc.error_work);
2803 spin_unlock(&dispc.irq_lock);
2806 static void dispc_error_worker(struct work_struct *work)
2810 unsigned long flags;
2812 spin_lock_irqsave(&dispc.irq_lock, flags);
2813 errors = dispc.error_irqs;
2814 dispc.error_irqs = 0;
2815 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2817 if (errors & DISPC_IRQ_GFX_FIFO_UNDERFLOW) {
2818 DSSERR("GFX_FIFO_UNDERFLOW, disabling GFX\n");
2819 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2820 struct omap_overlay *ovl;
2821 ovl = omap_dss_get_overlay(i);
2823 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2827 dispc_enable_plane(ovl->id, 0);
2828 dispc_go(ovl->manager->id);
2835 if (errors & DISPC_IRQ_VID1_FIFO_UNDERFLOW) {
2836 DSSERR("VID1_FIFO_UNDERFLOW, disabling VID1\n");
2837 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2838 struct omap_overlay *ovl;
2839 ovl = omap_dss_get_overlay(i);
2841 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2845 dispc_enable_plane(ovl->id, 0);
2846 dispc_go(ovl->manager->id);
2853 if (errors & DISPC_IRQ_VID2_FIFO_UNDERFLOW) {
2854 DSSERR("VID2_FIFO_UNDERFLOW, disabling VID2\n");
2855 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2856 struct omap_overlay *ovl;
2857 ovl = omap_dss_get_overlay(i);
2859 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2863 dispc_enable_plane(ovl->id, 0);
2864 dispc_go(ovl->manager->id);
2871 if (errors & DISPC_IRQ_SYNC_LOST) {
2872 struct omap_overlay_manager *manager = NULL;
2873 bool enable = false;
2875 DSSERR("SYNC_LOST, disabling LCD\n");
2877 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
2878 struct omap_overlay_manager *mgr;
2879 mgr = omap_dss_get_overlay_manager(i);
2881 if (mgr->id == OMAP_DSS_CHANNEL_LCD) {
2883 enable = mgr->device->state ==
2884 OMAP_DSS_DISPLAY_ACTIVE;
2885 mgr->device->driver->disable(mgr->device);
2891 struct omap_dss_device *dssdev = manager->device;
2892 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2893 struct omap_overlay *ovl;
2894 ovl = omap_dss_get_overlay(i);
2896 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2899 if (ovl->id != 0 && ovl->manager == manager)
2900 dispc_enable_plane(ovl->id, 0);
2903 dispc_go(manager->id);
2906 dssdev->driver->enable(dssdev);
2910 if (errors & DISPC_IRQ_SYNC_LOST_DIGIT) {
2911 struct omap_overlay_manager *manager = NULL;
2912 bool enable = false;
2914 DSSERR("SYNC_LOST_DIGIT, disabling TV\n");
2916 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
2917 struct omap_overlay_manager *mgr;
2918 mgr = omap_dss_get_overlay_manager(i);
2920 if (mgr->id == OMAP_DSS_CHANNEL_DIGIT) {
2922 enable = mgr->device->state ==
2923 OMAP_DSS_DISPLAY_ACTIVE;
2924 mgr->device->driver->disable(mgr->device);
2930 struct omap_dss_device *dssdev = manager->device;
2931 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
2932 struct omap_overlay *ovl;
2933 ovl = omap_dss_get_overlay(i);
2935 if (!(ovl->caps & OMAP_DSS_OVL_CAP_DISPC))
2938 if (ovl->id != 0 && ovl->manager == manager)
2939 dispc_enable_plane(ovl->id, 0);
2942 dispc_go(manager->id);
2945 dssdev->driver->enable(dssdev);
2949 if (errors & DISPC_IRQ_OCP_ERR) {
2950 DSSERR("OCP_ERR\n");
2951 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
2952 struct omap_overlay_manager *mgr;
2953 mgr = omap_dss_get_overlay_manager(i);
2955 if (mgr->caps & OMAP_DSS_OVL_CAP_DISPC)
2956 mgr->device->driver->disable(mgr->device);
2960 spin_lock_irqsave(&dispc.irq_lock, flags);
2961 dispc.irq_error_mask |= errors;
2962 _omap_dispc_set_irqs();
2963 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2966 int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
2968 void dispc_irq_wait_handler(void *data, u32 mask)
2970 complete((struct completion *)data);
2974 DECLARE_COMPLETION_ONSTACK(completion);
2976 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
2982 timeout = wait_for_completion_timeout(&completion, timeout);
2984 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
2989 if (timeout == -ERESTARTSYS)
2990 return -ERESTARTSYS;
2995 int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
2996 unsigned long timeout)
2998 void dispc_irq_wait_handler(void *data, u32 mask)
3000 complete((struct completion *)data);
3004 DECLARE_COMPLETION_ONSTACK(completion);
3006 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3012 timeout = wait_for_completion_interruptible_timeout(&completion,
3015 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3020 if (timeout == -ERESTARTSYS)
3021 return -ERESTARTSYS;
3026 #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
3027 void dispc_fake_vsync_irq(void)
3029 u32 irqstatus = DISPC_IRQ_VSYNC;
3032 WARN_ON(!in_interrupt());
3034 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3035 struct omap_dispc_isr_data *isr_data;
3036 isr_data = &dispc.registered_isr[i];
3041 if (isr_data->mask & irqstatus)
3042 isr_data->isr(isr_data->arg, irqstatus);
3047 static void _omap_dispc_initialize_irq(void)
3049 unsigned long flags;
3051 spin_lock_irqsave(&dispc.irq_lock, flags);
3053 memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3055 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
3057 /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3059 dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3061 _omap_dispc_set_irqs();
3063 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3066 void dispc_enable_sidle(void)
3068 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3071 void dispc_disable_sidle(void)
3073 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3076 static void _omap_dispc_initial_config(void)
3080 l = dispc_read_reg(DISPC_SYSCONFIG);
3081 l = FLD_MOD(l, 2, 13, 12); /* MIDLEMODE: smart standby */
3082 l = FLD_MOD(l, 2, 4, 3); /* SIDLEMODE: smart idle */
3083 l = FLD_MOD(l, 1, 2, 2); /* ENWAKEUP */
3084 l = FLD_MOD(l, 1, 0, 0); /* AUTOIDLE */
3085 dispc_write_reg(DISPC_SYSCONFIG, l);
3088 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
3090 /* L3 firewall setting: enable access to OCM RAM */
3091 /* XXX this should be somewhere in plat-omap */
3092 if (cpu_is_omap24xx())
3093 __raw_writel(0x402000b0, OMAP2_L3_IO_ADDRESS(0x680050a0));
3095 _dispc_setup_color_conv_coef();
3097 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3099 dispc_read_plane_fifo_sizes();
3102 int dispc_init(void)
3106 spin_lock_init(&dispc.irq_lock);
3108 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3109 spin_lock_init(&dispc.irq_stats_lock);
3110 dispc.irq_stats.last_reset = jiffies;
3113 INIT_WORK(&dispc.error_work, dispc_error_worker);
3115 dispc.base = ioremap(DISPC_BASE, DISPC_SZ_REGS);
3117 DSSERR("can't ioremap DISPC\n");
3123 _omap_dispc_initial_config();
3125 _omap_dispc_initialize_irq();
3127 dispc_save_context();
3129 rev = dispc_read_reg(DISPC_REVISION);
3130 printk(KERN_INFO "OMAP DISPC rev %d.%d\n",
3131 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3138 void dispc_exit(void)
3140 iounmap(dispc.base);
3143 int dispc_enable_plane(enum omap_plane plane, bool enable)
3145 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
3148 _dispc_enable_plane(plane, enable);
3154 int dispc_setup_plane(enum omap_plane plane,
3155 u32 paddr, u16 screen_width,
3156 u16 pos_x, u16 pos_y,
3157 u16 width, u16 height,
3158 u16 out_width, u16 out_height,
3159 enum omap_color_mode color_mode,
3161 enum omap_dss_rotation_type rotation_type,
3162 u8 rotation, bool mirror, u8 global_alpha)
3166 DSSDBG("dispc_setup_plane %d, pa %x, sw %d, %d,%d, %dx%d -> "
3167 "%dx%d, ilace %d, cmode %x, rot %d, mir %d\n",
3168 plane, paddr, screen_width, pos_x, pos_y,
3170 out_width, out_height,
3176 r = _dispc_setup_plane(plane,
3177 paddr, screen_width,
3180 out_width, out_height,