2 * linux/drivers/video/omap2/dss/dispc.c
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * Some code and ideas taken from drivers/video/omap/ driver
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
23 #define DSS_SUBSYS_NAME "DISPC"
25 #include <linux/kernel.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/vmalloc.h>
28 #include <linux/clk.h>
30 #include <linux/jiffies.h>
31 #include <linux/seq_file.h>
32 #include <linux/delay.h>
33 #include <linux/workqueue.h>
34 #include <linux/hardirq.h>
35 #include <linux/interrupt.h>
36 #include <linux/platform_device.h>
37 #include <linux/pm_runtime.h>
39 #include <plat/sram.h>
40 #include <plat/clock.h>
42 #include <video/omapdss.h>
45 #include "dss_features.h"
49 #define DISPC_SZ_REGS SZ_4K
51 #define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
53 DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
54 DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
55 DISPC_IRQ_SYNC_LOST | \
56 DISPC_IRQ_SYNC_LOST_DIGIT)
58 #define DISPC_MAX_NR_ISRS 8
60 struct omap_dispc_isr_data {
82 enum omap_burst_size {
88 #define REG_GET(idx, start, end) \
89 FLD_GET(dispc_read_reg(idx), start, end)
91 #define REG_FLD_MOD(idx, val, start, end) \
92 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
94 struct dispc_irq_stats {
95 unsigned long last_reset;
101 struct platform_device *pdev;
109 u32 fifo_size[MAX_DSS_OVERLAYS];
113 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
115 struct work_struct error_work;
118 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
120 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
121 spinlock_t irq_stats_lock;
122 struct dispc_irq_stats irq_stats;
126 enum omap_color_component {
127 /* used for all color formats for OMAP3 and earlier
128 * and for RGB and Y color component on OMAP4
130 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
131 /* used for UV component for
132 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
133 * color formats on OMAP4
135 DISPC_COLOR_COMPONENT_UV = 1 << 1,
138 static void _omap_dispc_set_irqs(void);
140 static inline void dispc_write_reg(const u16 idx, u32 val)
142 __raw_writel(val, dispc.base + idx);
145 static inline u32 dispc_read_reg(const u16 idx)
147 return __raw_readl(dispc.base + idx);
150 static int dispc_get_ctx_loss_count(void)
152 struct device *dev = &dispc.pdev->dev;
153 struct omap_display_platform_data *pdata = dev->platform_data;
154 struct omap_dss_board_info *board_data = pdata->board_data;
157 if (!board_data->get_context_loss_count)
160 cnt = board_data->get_context_loss_count(dev);
162 WARN_ONCE(cnt < 0, "get_context_loss_count failed: %d\n", cnt);
168 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
170 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
172 static void dispc_save_context(void)
176 DSSDBG("dispc_save_context\n");
182 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
183 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
185 if (dss_has_feature(FEAT_MGR_LCD2)) {
190 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
191 SR(DEFAULT_COLOR(i));
194 if (i == OMAP_DSS_CHANNEL_DIGIT)
205 if (dss_has_feature(FEAT_CPR)) {
212 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
217 SR(OVL_ATTRIBUTES(i));
218 SR(OVL_FIFO_THRESHOLD(i));
220 SR(OVL_PIXEL_INC(i));
221 if (dss_has_feature(FEAT_PRELOAD))
223 if (i == OMAP_DSS_GFX) {
224 SR(OVL_WINDOW_SKIP(i));
229 SR(OVL_PICTURE_SIZE(i));
233 for (j = 0; j < 8; j++)
234 SR(OVL_FIR_COEF_H(i, j));
236 for (j = 0; j < 8; j++)
237 SR(OVL_FIR_COEF_HV(i, j));
239 for (j = 0; j < 5; j++)
240 SR(OVL_CONV_COEF(i, j));
242 if (dss_has_feature(FEAT_FIR_COEF_V)) {
243 for (j = 0; j < 8; j++)
244 SR(OVL_FIR_COEF_V(i, j));
247 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
254 for (j = 0; j < 8; j++)
255 SR(OVL_FIR_COEF_H2(i, j));
257 for (j = 0; j < 8; j++)
258 SR(OVL_FIR_COEF_HV2(i, j));
260 for (j = 0; j < 8; j++)
261 SR(OVL_FIR_COEF_V2(i, j));
263 if (dss_has_feature(FEAT_ATTR2))
264 SR(OVL_ATTRIBUTES2(i));
267 if (dss_has_feature(FEAT_CORE_CLK_DIV))
270 dispc.ctx_loss_cnt = dispc_get_ctx_loss_count();
271 dispc.ctx_valid = true;
273 DSSDBG("context saved, ctx_loss_count %d\n", dispc.ctx_loss_cnt);
276 static void dispc_restore_context(void)
280 DSSDBG("dispc_restore_context\n");
282 if (!dispc.ctx_valid)
285 ctx = dispc_get_ctx_loss_count();
287 if (ctx >= 0 && ctx == dispc.ctx_loss_cnt)
290 DSSDBG("ctx_loss_count: saved %d, current %d\n",
291 dispc.ctx_loss_cnt, ctx);
297 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
298 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
300 if (dss_has_feature(FEAT_MGR_LCD2))
303 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
304 RR(DEFAULT_COLOR(i));
307 if (i == OMAP_DSS_CHANNEL_DIGIT)
318 if (dss_has_feature(FEAT_CPR)) {
325 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
330 RR(OVL_ATTRIBUTES(i));
331 RR(OVL_FIFO_THRESHOLD(i));
333 RR(OVL_PIXEL_INC(i));
334 if (dss_has_feature(FEAT_PRELOAD))
336 if (i == OMAP_DSS_GFX) {
337 RR(OVL_WINDOW_SKIP(i));
342 RR(OVL_PICTURE_SIZE(i));
346 for (j = 0; j < 8; j++)
347 RR(OVL_FIR_COEF_H(i, j));
349 for (j = 0; j < 8; j++)
350 RR(OVL_FIR_COEF_HV(i, j));
352 for (j = 0; j < 5; j++)
353 RR(OVL_CONV_COEF(i, j));
355 if (dss_has_feature(FEAT_FIR_COEF_V)) {
356 for (j = 0; j < 8; j++)
357 RR(OVL_FIR_COEF_V(i, j));
360 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
367 for (j = 0; j < 8; j++)
368 RR(OVL_FIR_COEF_H2(i, j));
370 for (j = 0; j < 8; j++)
371 RR(OVL_FIR_COEF_HV2(i, j));
373 for (j = 0; j < 8; j++)
374 RR(OVL_FIR_COEF_V2(i, j));
376 if (dss_has_feature(FEAT_ATTR2))
377 RR(OVL_ATTRIBUTES2(i));
380 if (dss_has_feature(FEAT_CORE_CLK_DIV))
383 /* enable last, because LCD & DIGIT enable are here */
385 if (dss_has_feature(FEAT_MGR_LCD2))
387 /* clear spurious SYNC_LOST_DIGIT interrupts */
388 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
391 * enable last so IRQs won't trigger before
392 * the context is fully restored
396 DSSDBG("context restored\n");
402 int dispc_runtime_get(void)
406 DSSDBG("dispc_runtime_get\n");
408 r = pm_runtime_get_sync(&dispc.pdev->dev);
410 return r < 0 ? r : 0;
413 void dispc_runtime_put(void)
417 DSSDBG("dispc_runtime_put\n");
419 r = pm_runtime_put(&dispc.pdev->dev);
423 static inline bool dispc_mgr_is_lcd(enum omap_channel channel)
425 if (channel == OMAP_DSS_CHANNEL_LCD ||
426 channel == OMAP_DSS_CHANNEL_LCD2)
432 static struct omap_dss_device *dispc_mgr_get_device(enum omap_channel channel)
434 struct omap_overlay_manager *mgr =
435 omap_dss_get_overlay_manager(channel);
437 return mgr ? mgr->device : NULL;
440 bool dispc_mgr_go_busy(enum omap_channel channel)
444 if (dispc_mgr_is_lcd(channel))
447 bit = 6; /* GODIGIT */
449 if (channel == OMAP_DSS_CHANNEL_LCD2)
450 return REG_GET(DISPC_CONTROL2, bit, bit) == 1;
452 return REG_GET(DISPC_CONTROL, bit, bit) == 1;
455 void dispc_mgr_go(enum omap_channel channel)
458 bool enable_bit, go_bit;
460 if (dispc_mgr_is_lcd(channel))
461 bit = 0; /* LCDENABLE */
463 bit = 1; /* DIGITALENABLE */
465 /* if the channel is not enabled, we don't need GO */
466 if (channel == OMAP_DSS_CHANNEL_LCD2)
467 enable_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
469 enable_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
474 if (dispc_mgr_is_lcd(channel))
477 bit = 6; /* GODIGIT */
479 if (channel == OMAP_DSS_CHANNEL_LCD2)
480 go_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
482 go_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
485 DSSERR("GO bit not down for channel %d\n", channel);
489 DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" :
490 (channel == OMAP_DSS_CHANNEL_LCD2 ? "LCD2" : "DIGIT"));
492 if (channel == OMAP_DSS_CHANNEL_LCD2)
493 REG_FLD_MOD(DISPC_CONTROL2, 1, bit, bit);
495 REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
498 static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
500 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
503 static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
505 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
508 static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
510 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
513 static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
515 BUG_ON(plane == OMAP_DSS_GFX);
517 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
520 static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
523 BUG_ON(plane == OMAP_DSS_GFX);
525 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
528 static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
530 BUG_ON(plane == OMAP_DSS_GFX);
532 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
535 static void dispc_ovl_set_scale_coef(enum omap_plane plane, int hscaleup,
536 int vscaleup, int five_taps,
537 enum omap_color_component color_comp)
539 /* Coefficients for horizontal up-sampling */
540 static const struct dispc_h_coef coef_hup[8] = {
542 { -1, 13, 124, -8, 0 },
543 { -2, 30, 112, -11, -1 },
544 { -5, 51, 95, -11, -2 },
545 { 0, -9, 73, 73, -9 },
546 { -2, -11, 95, 51, -5 },
547 { -1, -11, 112, 30, -2 },
548 { 0, -8, 124, 13, -1 },
551 /* Coefficients for vertical up-sampling */
552 static const struct dispc_v_coef coef_vup_3tap[8] = {
555 { 0, 12, 111, 5, 0 },
559 { 0, 5, 111, 12, 0 },
563 static const struct dispc_v_coef coef_vup_5tap[8] = {
565 { -1, 13, 124, -8, 0 },
566 { -2, 30, 112, -11, -1 },
567 { -5, 51, 95, -11, -2 },
568 { 0, -9, 73, 73, -9 },
569 { -2, -11, 95, 51, -5 },
570 { -1, -11, 112, 30, -2 },
571 { 0, -8, 124, 13, -1 },
574 /* Coefficients for horizontal down-sampling */
575 static const struct dispc_h_coef coef_hdown[8] = {
576 { 0, 36, 56, 36, 0 },
577 { 4, 40, 55, 31, -2 },
578 { 8, 44, 54, 27, -5 },
579 { 12, 48, 53, 22, -7 },
580 { -9, 17, 52, 51, 17 },
581 { -7, 22, 53, 48, 12 },
582 { -5, 27, 54, 44, 8 },
583 { -2, 31, 55, 40, 4 },
586 /* Coefficients for vertical down-sampling */
587 static const struct dispc_v_coef coef_vdown_3tap[8] = {
588 { 0, 36, 56, 36, 0 },
589 { 0, 40, 57, 31, 0 },
590 { 0, 45, 56, 27, 0 },
591 { 0, 50, 55, 23, 0 },
592 { 0, 18, 55, 55, 0 },
593 { 0, 23, 55, 50, 0 },
594 { 0, 27, 56, 45, 0 },
595 { 0, 31, 57, 40, 0 },
598 static const struct dispc_v_coef coef_vdown_5tap[8] = {
599 { 0, 36, 56, 36, 0 },
600 { 4, 40, 55, 31, -2 },
601 { 8, 44, 54, 27, -5 },
602 { 12, 48, 53, 22, -7 },
603 { -9, 17, 52, 51, 17 },
604 { -7, 22, 53, 48, 12 },
605 { -5, 27, 54, 44, 8 },
606 { -2, 31, 55, 40, 4 },
609 const struct dispc_h_coef *h_coef;
610 const struct dispc_v_coef *v_coef;
619 v_coef = five_taps ? coef_vup_5tap : coef_vup_3tap;
621 v_coef = five_taps ? coef_vdown_5tap : coef_vdown_3tap;
623 for (i = 0; i < 8; i++) {
626 h = FLD_VAL(h_coef[i].hc0, 7, 0)
627 | FLD_VAL(h_coef[i].hc1, 15, 8)
628 | FLD_VAL(h_coef[i].hc2, 23, 16)
629 | FLD_VAL(h_coef[i].hc3, 31, 24);
630 hv = FLD_VAL(h_coef[i].hc4, 7, 0)
631 | FLD_VAL(v_coef[i].vc0, 15, 8)
632 | FLD_VAL(v_coef[i].vc1, 23, 16)
633 | FLD_VAL(v_coef[i].vc2, 31, 24);
635 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
636 dispc_ovl_write_firh_reg(plane, i, h);
637 dispc_ovl_write_firhv_reg(plane, i, hv);
639 dispc_ovl_write_firh2_reg(plane, i, h);
640 dispc_ovl_write_firhv2_reg(plane, i, hv);
646 for (i = 0; i < 8; i++) {
648 v = FLD_VAL(v_coef[i].vc00, 7, 0)
649 | FLD_VAL(v_coef[i].vc22, 15, 8);
650 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
651 dispc_ovl_write_firv_reg(plane, i, v);
653 dispc_ovl_write_firv2_reg(plane, i, v);
658 static void _dispc_setup_color_conv_coef(void)
661 const struct color_conv_coef {
662 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
665 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
668 const struct color_conv_coef *ct;
670 #define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
674 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
675 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 0),
676 CVAL(ct->rcr, ct->ry));
677 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 1),
678 CVAL(ct->gy, ct->rcb));
679 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 2),
680 CVAL(ct->gcb, ct->gcr));
681 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 3),
682 CVAL(ct->bcr, ct->by));
683 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 4),
686 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), ct->full_range,
694 static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
696 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
699 static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
701 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
704 static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
706 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
709 static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
711 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
714 static void dispc_ovl_set_pos(enum omap_plane plane, int x, int y)
716 u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
718 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
721 static void dispc_ovl_set_pic_size(enum omap_plane plane, int width, int height)
723 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
725 if (plane == OMAP_DSS_GFX)
726 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
728 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
731 static void dispc_ovl_set_vid_size(enum omap_plane plane, int width, int height)
735 BUG_ON(plane == OMAP_DSS_GFX);
737 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
739 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
742 static void dispc_ovl_set_zorder(enum omap_plane plane, u8 zorder)
744 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
746 if ((ovl->caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
749 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
752 static void dispc_ovl_enable_zorder_planes(void)
756 if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
759 for (i = 0; i < dss_feat_get_num_ovls(); i++)
760 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
763 static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane, bool enable)
765 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
767 if ((ovl->caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
770 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
773 static void dispc_ovl_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
775 static const unsigned shifts[] = { 0, 8, 16, 24, };
777 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
779 if ((ovl->caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
782 shift = shifts[plane];
783 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
786 static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
788 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
791 static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
793 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
796 static void dispc_ovl_set_color_mode(enum omap_plane plane,
797 enum omap_color_mode color_mode)
800 if (plane != OMAP_DSS_GFX) {
801 switch (color_mode) {
802 case OMAP_DSS_COLOR_NV12:
804 case OMAP_DSS_COLOR_RGB12U:
806 case OMAP_DSS_COLOR_RGBA16:
808 case OMAP_DSS_COLOR_RGBX16:
810 case OMAP_DSS_COLOR_ARGB16:
812 case OMAP_DSS_COLOR_RGB16:
814 case OMAP_DSS_COLOR_ARGB16_1555:
816 case OMAP_DSS_COLOR_RGB24U:
818 case OMAP_DSS_COLOR_RGB24P:
820 case OMAP_DSS_COLOR_YUV2:
822 case OMAP_DSS_COLOR_UYVY:
824 case OMAP_DSS_COLOR_ARGB32:
826 case OMAP_DSS_COLOR_RGBA32:
828 case OMAP_DSS_COLOR_RGBX32:
830 case OMAP_DSS_COLOR_XRGB16_1555:
836 switch (color_mode) {
837 case OMAP_DSS_COLOR_CLUT1:
839 case OMAP_DSS_COLOR_CLUT2:
841 case OMAP_DSS_COLOR_CLUT4:
843 case OMAP_DSS_COLOR_CLUT8:
845 case OMAP_DSS_COLOR_RGB12U:
847 case OMAP_DSS_COLOR_ARGB16:
849 case OMAP_DSS_COLOR_RGB16:
851 case OMAP_DSS_COLOR_ARGB16_1555:
853 case OMAP_DSS_COLOR_RGB24U:
855 case OMAP_DSS_COLOR_RGB24P:
857 case OMAP_DSS_COLOR_YUV2:
859 case OMAP_DSS_COLOR_UYVY:
861 case OMAP_DSS_COLOR_ARGB32:
863 case OMAP_DSS_COLOR_RGBA32:
865 case OMAP_DSS_COLOR_RGBX32:
867 case OMAP_DSS_COLOR_XRGB16_1555:
874 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
877 static void dispc_ovl_set_channel_out(enum omap_plane plane,
878 enum omap_channel channel)
882 int chan = 0, chan2 = 0;
888 case OMAP_DSS_VIDEO1:
889 case OMAP_DSS_VIDEO2:
890 case OMAP_DSS_VIDEO3:
898 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
899 if (dss_has_feature(FEAT_MGR_LCD2)) {
901 case OMAP_DSS_CHANNEL_LCD:
905 case OMAP_DSS_CHANNEL_DIGIT:
909 case OMAP_DSS_CHANNEL_LCD2:
917 val = FLD_MOD(val, chan, shift, shift);
918 val = FLD_MOD(val, chan2, 31, 30);
920 val = FLD_MOD(val, channel, shift, shift);
922 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
925 static void dispc_ovl_set_burst_size(enum omap_plane plane,
926 enum omap_burst_size burst_size)
928 static const unsigned shifts[] = { 6, 14, 14, 14, };
931 shift = shifts[plane];
932 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
935 static void dispc_configure_burst_sizes(void)
938 const int burst_size = BURST_SIZE_X8;
940 /* Configure burst size always to maximum size */
941 for (i = 0; i < omap_dss_get_num_overlays(); ++i)
942 dispc_ovl_set_burst_size(i, burst_size);
945 u32 dispc_ovl_get_burst_size(enum omap_plane plane)
947 unsigned unit = dss_feat_get_burst_size_unit();
948 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
952 void dispc_enable_gamma_table(bool enable)
955 * This is partially implemented to support only disabling of
959 DSSWARN("Gamma table enabling for TV not yet supported");
963 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
966 void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
970 if (channel == OMAP_DSS_CHANNEL_LCD)
972 else if (channel == OMAP_DSS_CHANNEL_LCD2)
977 REG_FLD_MOD(reg, enable, 15, 15);
980 void dispc_mgr_set_cpr_coef(enum omap_channel channel,
981 struct omap_dss_cpr_coefs *coefs)
983 u32 coef_r, coef_g, coef_b;
985 if (!dispc_mgr_is_lcd(channel))
988 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
989 FLD_VAL(coefs->rb, 9, 0);
990 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
991 FLD_VAL(coefs->gb, 9, 0);
992 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
993 FLD_VAL(coefs->bb, 9, 0);
995 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
996 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
997 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
1000 static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
1004 BUG_ON(plane == OMAP_DSS_GFX);
1006 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1007 val = FLD_MOD(val, enable, 9, 9);
1008 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
1011 static void dispc_ovl_enable_replication(enum omap_plane plane, bool enable)
1013 static const unsigned shifts[] = { 5, 10, 10, 10 };
1016 shift = shifts[plane];
1017 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
1020 void dispc_mgr_set_lcd_size(enum omap_channel channel, u16 width, u16 height)
1023 BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
1024 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
1025 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
1028 void dispc_set_digit_size(u16 width, u16 height)
1031 BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
1032 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
1033 dispc_write_reg(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT), val);
1036 static void dispc_read_plane_fifo_sizes(void)
1043 unit = dss_feat_get_buffer_size_unit();
1045 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
1047 for (plane = 0; plane < dss_feat_get_num_ovls(); ++plane) {
1048 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(plane), start, end);
1050 dispc.fifo_size[plane] = size;
1054 u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
1056 return dispc.fifo_size[plane];
1059 static void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low,
1062 u8 hi_start, hi_end, lo_start, lo_end;
1065 unit = dss_feat_get_buffer_size_unit();
1067 WARN_ON(low % unit != 0);
1068 WARN_ON(high % unit != 0);
1073 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1074 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1076 DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n",
1078 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1080 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
1084 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
1085 FLD_VAL(high, hi_start, hi_end) |
1086 FLD_VAL(low, lo_start, lo_end));
1089 void dispc_enable_fifomerge(bool enable)
1091 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1092 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
1095 static void dispc_ovl_set_fir(enum omap_plane plane,
1097 enum omap_color_component color_comp)
1101 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1102 u8 hinc_start, hinc_end, vinc_start, vinc_end;
1104 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1105 &hinc_start, &hinc_end);
1106 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1107 &vinc_start, &vinc_end);
1108 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1109 FLD_VAL(hinc, hinc_start, hinc_end);
1111 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1113 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1114 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1118 static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
1121 u8 hor_start, hor_end, vert_start, vert_end;
1123 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1124 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1126 val = FLD_VAL(vaccu, vert_start, vert_end) |
1127 FLD_VAL(haccu, hor_start, hor_end);
1129 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
1132 static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
1135 u8 hor_start, hor_end, vert_start, vert_end;
1137 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1138 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1140 val = FLD_VAL(vaccu, vert_start, vert_end) |
1141 FLD_VAL(haccu, hor_start, hor_end);
1143 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
1146 static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1151 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1152 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1155 static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1160 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1161 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1164 static void dispc_ovl_set_scale_param(enum omap_plane plane,
1165 u16 orig_width, u16 orig_height,
1166 u16 out_width, u16 out_height,
1167 bool five_taps, u8 rotation,
1168 enum omap_color_component color_comp)
1170 int fir_hinc, fir_vinc;
1171 int hscaleup, vscaleup;
1173 hscaleup = orig_width <= out_width;
1174 vscaleup = orig_height <= out_height;
1176 dispc_ovl_set_scale_coef(plane, hscaleup, vscaleup, five_taps,
1179 fir_hinc = 1024 * orig_width / out_width;
1180 fir_vinc = 1024 * orig_height / out_height;
1182 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
1185 static void dispc_ovl_set_scaling_common(enum omap_plane plane,
1186 u16 orig_width, u16 orig_height,
1187 u16 out_width, u16 out_height,
1188 bool ilace, bool five_taps,
1189 bool fieldmode, enum omap_color_mode color_mode,
1196 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1197 out_width, out_height, five_taps,
1198 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
1199 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
1201 /* RESIZEENABLE and VERTICALTAPS */
1202 l &= ~((0x3 << 5) | (0x1 << 21));
1203 l |= (orig_width != out_width) ? (1 << 5) : 0;
1204 l |= (orig_height != out_height) ? (1 << 6) : 0;
1205 l |= five_taps ? (1 << 21) : 0;
1207 /* VRESIZECONF and HRESIZECONF */
1208 if (dss_has_feature(FEAT_RESIZECONF)) {
1210 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1211 l |= (orig_height <= out_height) ? 0 : (1 << 8);
1214 /* LINEBUFFERSPLIT */
1215 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1217 l |= five_taps ? (1 << 22) : 0;
1220 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
1223 * field 0 = even field = bottom field
1224 * field 1 = odd field = top field
1226 if (ilace && !fieldmode) {
1228 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
1229 if (accu0 >= 1024/2) {
1235 dispc_ovl_set_vid_accu0(plane, 0, accu0);
1236 dispc_ovl_set_vid_accu1(plane, 0, accu1);
1239 static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
1240 u16 orig_width, u16 orig_height,
1241 u16 out_width, u16 out_height,
1242 bool ilace, bool five_taps,
1243 bool fieldmode, enum omap_color_mode color_mode,
1246 int scale_x = out_width != orig_width;
1247 int scale_y = out_height != orig_height;
1249 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1251 if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1252 color_mode != OMAP_DSS_COLOR_UYVY &&
1253 color_mode != OMAP_DSS_COLOR_NV12)) {
1254 /* reset chroma resampling for RGB formats */
1255 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1258 switch (color_mode) {
1259 case OMAP_DSS_COLOR_NV12:
1260 /* UV is subsampled by 2 vertically*/
1262 /* UV is subsampled by 2 horz.*/
1265 case OMAP_DSS_COLOR_YUV2:
1266 case OMAP_DSS_COLOR_UYVY:
1267 /*For YUV422 with 90/270 rotation,
1268 *we don't upsample chroma
1270 if (rotation == OMAP_DSS_ROT_0 ||
1271 rotation == OMAP_DSS_ROT_180)
1272 /* UV is subsampled by 2 hrz*/
1274 /* must use FIR for YUV422 if rotated */
1275 if (rotation != OMAP_DSS_ROT_0)
1276 scale_x = scale_y = true;
1282 if (out_width != orig_width)
1284 if (out_height != orig_height)
1287 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
1288 out_width, out_height, five_taps,
1289 rotation, DISPC_COLOR_COMPONENT_UV);
1291 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1292 (scale_x || scale_y) ? 1 : 0, 8, 8);
1294 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1296 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
1298 dispc_ovl_set_vid_accu2_0(plane, 0x80, 0);
1299 dispc_ovl_set_vid_accu2_1(plane, 0x80, 0);
1302 static void dispc_ovl_set_scaling(enum omap_plane plane,
1303 u16 orig_width, u16 orig_height,
1304 u16 out_width, u16 out_height,
1305 bool ilace, bool five_taps,
1306 bool fieldmode, enum omap_color_mode color_mode,
1309 BUG_ON(plane == OMAP_DSS_GFX);
1311 dispc_ovl_set_scaling_common(plane,
1312 orig_width, orig_height,
1313 out_width, out_height,
1315 fieldmode, color_mode,
1318 dispc_ovl_set_scaling_uv(plane,
1319 orig_width, orig_height,
1320 out_width, out_height,
1322 fieldmode, color_mode,
1326 static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
1327 bool mirroring, enum omap_color_mode color_mode)
1329 bool row_repeat = false;
1332 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1333 color_mode == OMAP_DSS_COLOR_UYVY) {
1337 case OMAP_DSS_ROT_0:
1340 case OMAP_DSS_ROT_90:
1343 case OMAP_DSS_ROT_180:
1346 case OMAP_DSS_ROT_270:
1352 case OMAP_DSS_ROT_0:
1355 case OMAP_DSS_ROT_90:
1358 case OMAP_DSS_ROT_180:
1361 case OMAP_DSS_ROT_270:
1367 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
1373 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
1374 if (dss_has_feature(FEAT_ROWREPEATENABLE))
1375 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1376 row_repeat ? 1 : 0, 18, 18);
1379 static int color_mode_to_bpp(enum omap_color_mode color_mode)
1381 switch (color_mode) {
1382 case OMAP_DSS_COLOR_CLUT1:
1384 case OMAP_DSS_COLOR_CLUT2:
1386 case OMAP_DSS_COLOR_CLUT4:
1388 case OMAP_DSS_COLOR_CLUT8:
1389 case OMAP_DSS_COLOR_NV12:
1391 case OMAP_DSS_COLOR_RGB12U:
1392 case OMAP_DSS_COLOR_RGB16:
1393 case OMAP_DSS_COLOR_ARGB16:
1394 case OMAP_DSS_COLOR_YUV2:
1395 case OMAP_DSS_COLOR_UYVY:
1396 case OMAP_DSS_COLOR_RGBA16:
1397 case OMAP_DSS_COLOR_RGBX16:
1398 case OMAP_DSS_COLOR_ARGB16_1555:
1399 case OMAP_DSS_COLOR_XRGB16_1555:
1401 case OMAP_DSS_COLOR_RGB24P:
1403 case OMAP_DSS_COLOR_RGB24U:
1404 case OMAP_DSS_COLOR_ARGB32:
1405 case OMAP_DSS_COLOR_RGBA32:
1406 case OMAP_DSS_COLOR_RGBX32:
1413 static s32 pixinc(int pixels, u8 ps)
1417 else if (pixels > 1)
1418 return 1 + (pixels - 1) * ps;
1419 else if (pixels < 0)
1420 return 1 - (-pixels + 1) * ps;
1425 static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1427 u16 width, u16 height,
1428 enum omap_color_mode color_mode, bool fieldmode,
1429 unsigned int field_offset,
1430 unsigned *offset0, unsigned *offset1,
1431 s32 *row_inc, s32 *pix_inc)
1435 /* FIXME CLUT formats */
1436 switch (color_mode) {
1437 case OMAP_DSS_COLOR_CLUT1:
1438 case OMAP_DSS_COLOR_CLUT2:
1439 case OMAP_DSS_COLOR_CLUT4:
1440 case OMAP_DSS_COLOR_CLUT8:
1443 case OMAP_DSS_COLOR_YUV2:
1444 case OMAP_DSS_COLOR_UYVY:
1448 ps = color_mode_to_bpp(color_mode) / 8;
1452 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1456 * field 0 = even field = bottom field
1457 * field 1 = odd field = top field
1459 switch (rotation + mirror * 4) {
1460 case OMAP_DSS_ROT_0:
1461 case OMAP_DSS_ROT_180:
1463 * If the pixel format is YUV or UYVY divide the width
1464 * of the image by 2 for 0 and 180 degree rotation.
1466 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1467 color_mode == OMAP_DSS_COLOR_UYVY)
1469 case OMAP_DSS_ROT_90:
1470 case OMAP_DSS_ROT_270:
1473 *offset0 = field_offset * screen_width * ps;
1477 *row_inc = pixinc(1 + (screen_width - width) +
1478 (fieldmode ? screen_width : 0),
1480 *pix_inc = pixinc(1, ps);
1483 case OMAP_DSS_ROT_0 + 4:
1484 case OMAP_DSS_ROT_180 + 4:
1485 /* If the pixel format is YUV or UYVY divide the width
1486 * of the image by 2 for 0 degree and 180 degree
1488 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1489 color_mode == OMAP_DSS_COLOR_UYVY)
1491 case OMAP_DSS_ROT_90 + 4:
1492 case OMAP_DSS_ROT_270 + 4:
1495 *offset0 = field_offset * screen_width * ps;
1498 *row_inc = pixinc(1 - (screen_width + width) -
1499 (fieldmode ? screen_width : 0),
1501 *pix_inc = pixinc(1, ps);
1509 static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1511 u16 width, u16 height,
1512 enum omap_color_mode color_mode, bool fieldmode,
1513 unsigned int field_offset,
1514 unsigned *offset0, unsigned *offset1,
1515 s32 *row_inc, s32 *pix_inc)
1520 /* FIXME CLUT formats */
1521 switch (color_mode) {
1522 case OMAP_DSS_COLOR_CLUT1:
1523 case OMAP_DSS_COLOR_CLUT2:
1524 case OMAP_DSS_COLOR_CLUT4:
1525 case OMAP_DSS_COLOR_CLUT8:
1529 ps = color_mode_to_bpp(color_mode) / 8;
1533 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1536 /* width & height are overlay sizes, convert to fb sizes */
1538 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1547 * field 0 = even field = bottom field
1548 * field 1 = odd field = top field
1550 switch (rotation + mirror * 4) {
1551 case OMAP_DSS_ROT_0:
1554 *offset0 = *offset1 + field_offset * screen_width * ps;
1556 *offset0 = *offset1;
1557 *row_inc = pixinc(1 + (screen_width - fbw) +
1558 (fieldmode ? screen_width : 0),
1560 *pix_inc = pixinc(1, ps);
1562 case OMAP_DSS_ROT_90:
1563 *offset1 = screen_width * (fbh - 1) * ps;
1565 *offset0 = *offset1 + field_offset * ps;
1567 *offset0 = *offset1;
1568 *row_inc = pixinc(screen_width * (fbh - 1) + 1 +
1569 (fieldmode ? 1 : 0), ps);
1570 *pix_inc = pixinc(-screen_width, ps);
1572 case OMAP_DSS_ROT_180:
1573 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1575 *offset0 = *offset1 - field_offset * screen_width * ps;
1577 *offset0 = *offset1;
1578 *row_inc = pixinc(-1 -
1579 (screen_width - fbw) -
1580 (fieldmode ? screen_width : 0),
1582 *pix_inc = pixinc(-1, ps);
1584 case OMAP_DSS_ROT_270:
1585 *offset1 = (fbw - 1) * ps;
1587 *offset0 = *offset1 - field_offset * ps;
1589 *offset0 = *offset1;
1590 *row_inc = pixinc(-screen_width * (fbh - 1) - 1 -
1591 (fieldmode ? 1 : 0), ps);
1592 *pix_inc = pixinc(screen_width, ps);
1596 case OMAP_DSS_ROT_0 + 4:
1597 *offset1 = (fbw - 1) * ps;
1599 *offset0 = *offset1 + field_offset * screen_width * ps;
1601 *offset0 = *offset1;
1602 *row_inc = pixinc(screen_width * 2 - 1 +
1603 (fieldmode ? screen_width : 0),
1605 *pix_inc = pixinc(-1, ps);
1608 case OMAP_DSS_ROT_90 + 4:
1611 *offset0 = *offset1 + field_offset * ps;
1613 *offset0 = *offset1;
1614 *row_inc = pixinc(-screen_width * (fbh - 1) + 1 +
1615 (fieldmode ? 1 : 0),
1617 *pix_inc = pixinc(screen_width, ps);
1620 case OMAP_DSS_ROT_180 + 4:
1621 *offset1 = screen_width * (fbh - 1) * ps;
1623 *offset0 = *offset1 - field_offset * screen_width * ps;
1625 *offset0 = *offset1;
1626 *row_inc = pixinc(1 - screen_width * 2 -
1627 (fieldmode ? screen_width : 0),
1629 *pix_inc = pixinc(1, ps);
1632 case OMAP_DSS_ROT_270 + 4:
1633 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1635 *offset0 = *offset1 - field_offset * ps;
1637 *offset0 = *offset1;
1638 *row_inc = pixinc(screen_width * (fbh - 1) - 1 -
1639 (fieldmode ? 1 : 0),
1641 *pix_inc = pixinc(-screen_width, ps);
1649 static unsigned long calc_fclk_five_taps(enum omap_channel channel, u16 width,
1650 u16 height, u16 out_width, u16 out_height,
1651 enum omap_color_mode color_mode)
1654 u64 tmp, pclk = dispc_mgr_pclk_rate(channel);
1656 if (height > out_height) {
1657 struct omap_dss_device *dssdev = dispc_mgr_get_device(channel);
1658 unsigned int ppl = dssdev->panel.timings.x_res;
1660 tmp = pclk * height * out_width;
1661 do_div(tmp, 2 * out_height * ppl);
1664 if (height > 2 * out_height) {
1665 if (ppl == out_width)
1668 tmp = pclk * (height - 2 * out_height) * out_width;
1669 do_div(tmp, 2 * out_height * (ppl - out_width));
1670 fclk = max(fclk, (u32) tmp);
1674 if (width > out_width) {
1676 do_div(tmp, out_width);
1677 fclk = max(fclk, (u32) tmp);
1679 if (color_mode == OMAP_DSS_COLOR_RGB24U)
1686 static unsigned long calc_fclk(enum omap_channel channel, u16 width,
1687 u16 height, u16 out_width, u16 out_height)
1689 unsigned int hf, vf;
1692 * FIXME how to determine the 'A' factor
1693 * for the no downscaling case ?
1696 if (width > 3 * out_width)
1698 else if (width > 2 * out_width)
1700 else if (width > out_width)
1705 if (height > out_height)
1710 return dispc_mgr_pclk_rate(channel) * vf * hf;
1713 static int dispc_ovl_calc_scaling(enum omap_plane plane,
1714 enum omap_channel channel, u16 width, u16 height,
1715 u16 out_width, u16 out_height,
1716 enum omap_color_mode color_mode, bool *five_taps)
1718 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
1719 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
1720 unsigned long fclk = 0;
1722 if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0) {
1723 if (width != out_width || height != out_height)
1729 if (out_width < width / maxdownscale ||
1730 out_width > width * 8)
1733 if (out_height < height / maxdownscale ||
1734 out_height > height * 8)
1737 /* Must use 5-tap filter? */
1738 *five_taps = height > out_height * 2;
1741 fclk = calc_fclk(channel, width, height, out_width,
1744 /* Try 5-tap filter if 3-tap fclk is too high */
1745 if (cpu_is_omap34xx() && height > out_height &&
1746 fclk > dispc_fclk_rate())
1750 if (width > (2048 >> *five_taps)) {
1751 DSSERR("failed to set up scaling, fclk too low\n");
1756 fclk = calc_fclk_five_taps(channel, width, height,
1757 out_width, out_height, color_mode);
1759 DSSDBG("required fclk rate = %lu Hz\n", fclk);
1760 DSSDBG("current fclk rate = %lu Hz\n", dispc_fclk_rate());
1762 if (!fclk || fclk > dispc_fclk_rate()) {
1763 DSSERR("failed to set up scaling, "
1764 "required fclk rate = %lu Hz, "
1765 "current fclk rate = %lu Hz\n",
1766 fclk, dispc_fclk_rate());
1773 int dispc_ovl_setup(enum omap_plane plane, struct omap_overlay_info *oi,
1774 bool ilace, enum omap_channel channel, bool replication,
1775 u32 fifo_low, u32 fifo_high)
1777 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
1778 bool five_taps = false;
1781 unsigned offset0, offset1;
1784 u16 frame_height = oi->height;
1785 unsigned int field_offset = 0;
1787 DSSDBG("dispc_ovl_setup %d, pa %x, pa_uv %x, sw %d, %d,%d, %dx%d -> "
1788 "%dx%d, cmode %x, rot %d, mir %d, ilace %d chan %d repl %d "
1789 "fifo_low %d fifo high %d\n", plane, oi->paddr, oi->p_uv_addr,
1790 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
1791 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
1792 oi->mirror, ilace, channel, replication, fifo_low, fifo_high);
1797 if (ilace && oi->height == oi->out_height)
1804 oi->out_height /= 2;
1806 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
1808 oi->height, oi->pos_y, oi->out_height);
1811 if (!dss_feat_color_mode_supported(plane, oi->color_mode))
1814 r = dispc_ovl_calc_scaling(plane, channel, oi->width, oi->height,
1815 oi->out_width, oi->out_height, oi->color_mode,
1820 if (oi->color_mode == OMAP_DSS_COLOR_YUV2 ||
1821 oi->color_mode == OMAP_DSS_COLOR_UYVY ||
1822 oi->color_mode == OMAP_DSS_COLOR_NV12)
1825 if (ilace && !fieldmode) {
1827 * when downscaling the bottom field may have to start several
1828 * source lines below the top field. Unfortunately ACCUI
1829 * registers will only hold the fractional part of the offset
1830 * so the integer part must be added to the base address of the
1833 if (!oi->height || oi->height == oi->out_height)
1836 field_offset = oi->height / oi->out_height / 2;
1839 /* Fields are independent but interleaved in memory. */
1843 if (oi->rotation_type == OMAP_DSS_ROT_DMA)
1844 calc_dma_rotation_offset(oi->rotation, oi->mirror,
1845 oi->screen_width, oi->width, frame_height,
1846 oi->color_mode, fieldmode, field_offset,
1847 &offset0, &offset1, &row_inc, &pix_inc);
1849 calc_vrfb_rotation_offset(oi->rotation, oi->mirror,
1850 oi->screen_width, oi->width, frame_height,
1851 oi->color_mode, fieldmode, field_offset,
1852 &offset0, &offset1, &row_inc, &pix_inc);
1854 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
1855 offset0, offset1, row_inc, pix_inc);
1857 dispc_ovl_set_color_mode(plane, oi->color_mode);
1859 dispc_ovl_set_ba0(plane, oi->paddr + offset0);
1860 dispc_ovl_set_ba1(plane, oi->paddr + offset1);
1862 if (OMAP_DSS_COLOR_NV12 == oi->color_mode) {
1863 dispc_ovl_set_ba0_uv(plane, oi->p_uv_addr + offset0);
1864 dispc_ovl_set_ba1_uv(plane, oi->p_uv_addr + offset1);
1868 dispc_ovl_set_row_inc(plane, row_inc);
1869 dispc_ovl_set_pix_inc(plane, pix_inc);
1871 DSSDBG("%d,%d %dx%d -> %dx%d\n", oi->pos_x, oi->pos_y, oi->width,
1872 oi->height, oi->out_width, oi->out_height);
1874 dispc_ovl_set_pos(plane, oi->pos_x, oi->pos_y);
1876 dispc_ovl_set_pic_size(plane, oi->width, oi->height);
1878 if (ovl->caps & OMAP_DSS_OVL_CAP_SCALE) {
1879 dispc_ovl_set_scaling(plane, oi->width, oi->height,
1880 oi->out_width, oi->out_height,
1881 ilace, five_taps, fieldmode,
1882 oi->color_mode, oi->rotation);
1883 dispc_ovl_set_vid_size(plane, oi->out_width, oi->out_height);
1884 dispc_ovl_set_vid_color_conv(plane, cconv);
1887 dispc_ovl_set_rotation_attrs(plane, oi->rotation, oi->mirror,
1890 dispc_ovl_set_zorder(plane, oi->zorder);
1891 dispc_ovl_set_pre_mult_alpha(plane, oi->pre_mult_alpha);
1892 dispc_ovl_setup_global_alpha(plane, oi->global_alpha);
1894 dispc_ovl_set_channel_out(plane, channel);
1896 dispc_ovl_enable_replication(plane, replication);
1897 dispc_ovl_set_fifo_threshold(plane, fifo_low, fifo_high);
1902 int dispc_ovl_enable(enum omap_plane plane, bool enable)
1904 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
1906 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
1911 static void dispc_disable_isr(void *data, u32 mask)
1913 struct completion *compl = data;
1917 static void _enable_lcd_out(enum omap_channel channel, bool enable)
1919 if (channel == OMAP_DSS_CHANNEL_LCD2)
1920 REG_FLD_MOD(DISPC_CONTROL2, enable ? 1 : 0, 0, 0);
1922 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
1925 static void dispc_mgr_enable_lcd_out(enum omap_channel channel, bool enable)
1927 struct completion frame_done_completion;
1932 /* When we disable LCD output, we need to wait until frame is done.
1933 * Otherwise the DSS is still working, and turning off the clocks
1934 * prevents DSS from going to OFF mode */
1935 is_on = channel == OMAP_DSS_CHANNEL_LCD2 ?
1936 REG_GET(DISPC_CONTROL2, 0, 0) :
1937 REG_GET(DISPC_CONTROL, 0, 0);
1939 irq = channel == OMAP_DSS_CHANNEL_LCD2 ? DISPC_IRQ_FRAMEDONE2 :
1940 DISPC_IRQ_FRAMEDONE;
1942 if (!enable && is_on) {
1943 init_completion(&frame_done_completion);
1945 r = omap_dispc_register_isr(dispc_disable_isr,
1946 &frame_done_completion, irq);
1949 DSSERR("failed to register FRAMEDONE isr\n");
1952 _enable_lcd_out(channel, enable);
1954 if (!enable && is_on) {
1955 if (!wait_for_completion_timeout(&frame_done_completion,
1956 msecs_to_jiffies(100)))
1957 DSSERR("timeout waiting for FRAME DONE\n");
1959 r = omap_dispc_unregister_isr(dispc_disable_isr,
1960 &frame_done_completion, irq);
1963 DSSERR("failed to unregister FRAMEDONE isr\n");
1967 static void _enable_digit_out(bool enable)
1969 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
1972 static void dispc_mgr_enable_digit_out(bool enable)
1974 struct completion frame_done_completion;
1975 enum dss_hdmi_venc_clk_source_select src;
1980 if (REG_GET(DISPC_CONTROL, 1, 1) == enable)
1983 src = dss_get_hdmi_venc_clk_source();
1986 unsigned long flags;
1987 /* When we enable digit output, we'll get an extra digit
1988 * sync lost interrupt, that we need to ignore */
1989 spin_lock_irqsave(&dispc.irq_lock, flags);
1990 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
1991 _omap_dispc_set_irqs();
1992 spin_unlock_irqrestore(&dispc.irq_lock, flags);
1995 /* When we disable digit output, we need to wait until fields are done.
1996 * Otherwise the DSS is still working, and turning off the clocks
1997 * prevents DSS from going to OFF mode. And when enabling, we need to
1998 * wait for the extra sync losts */
1999 init_completion(&frame_done_completion);
2001 if (src == DSS_HDMI_M_PCLK && enable == false) {
2002 irq_mask = DISPC_IRQ_FRAMEDONETV;
2005 irq_mask = DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD;
2006 /* XXX I understand from TRM that we should only wait for the
2007 * current field to complete. But it seems we have to wait for
2012 r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
2015 DSSERR("failed to register %x isr\n", irq_mask);
2017 _enable_digit_out(enable);
2019 for (i = 0; i < num_irqs; ++i) {
2020 if (!wait_for_completion_timeout(&frame_done_completion,
2021 msecs_to_jiffies(100)))
2022 DSSERR("timeout waiting for digit out to %s\n",
2023 enable ? "start" : "stop");
2026 r = omap_dispc_unregister_isr(dispc_disable_isr, &frame_done_completion,
2029 DSSERR("failed to unregister %x isr\n", irq_mask);
2032 unsigned long flags;
2033 spin_lock_irqsave(&dispc.irq_lock, flags);
2034 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST_DIGIT;
2035 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
2036 _omap_dispc_set_irqs();
2037 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2041 bool dispc_mgr_is_enabled(enum omap_channel channel)
2043 if (channel == OMAP_DSS_CHANNEL_LCD)
2044 return !!REG_GET(DISPC_CONTROL, 0, 0);
2045 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
2046 return !!REG_GET(DISPC_CONTROL, 1, 1);
2047 else if (channel == OMAP_DSS_CHANNEL_LCD2)
2048 return !!REG_GET(DISPC_CONTROL2, 0, 0);
2053 void dispc_mgr_enable(enum omap_channel channel, bool enable)
2055 if (dispc_mgr_is_lcd(channel))
2056 dispc_mgr_enable_lcd_out(channel, enable);
2057 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
2058 dispc_mgr_enable_digit_out(enable);
2063 void dispc_lcd_enable_signal_polarity(bool act_high)
2065 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2068 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
2071 void dispc_lcd_enable_signal(bool enable)
2073 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2076 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
2079 void dispc_pck_free_enable(bool enable)
2081 if (!dss_has_feature(FEAT_PCKFREEENABLE))
2084 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
2087 void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
2089 if (channel == OMAP_DSS_CHANNEL_LCD2)
2090 REG_FLD_MOD(DISPC_CONFIG2, enable ? 1 : 0, 16, 16);
2092 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
2096 void dispc_mgr_set_lcd_display_type(enum omap_channel channel,
2097 enum omap_lcd_display_type type)
2102 case OMAP_DSS_LCD_DISPLAY_STN:
2106 case OMAP_DSS_LCD_DISPLAY_TFT:
2115 if (channel == OMAP_DSS_CHANNEL_LCD2)
2116 REG_FLD_MOD(DISPC_CONTROL2, mode, 3, 3);
2118 REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
2121 void dispc_set_loadmode(enum omap_dss_load_mode mode)
2123 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
2127 void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
2129 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
2132 u32 dispc_mgr_get_default_color(enum omap_channel channel)
2136 BUG_ON(channel != OMAP_DSS_CHANNEL_DIGIT &&
2137 channel != OMAP_DSS_CHANNEL_LCD &&
2138 channel != OMAP_DSS_CHANNEL_LCD2);
2140 l = dispc_read_reg(DISPC_DEFAULT_COLOR(channel));
2145 void dispc_mgr_set_trans_key(enum omap_channel ch,
2146 enum omap_dss_trans_key_type type,
2149 if (ch == OMAP_DSS_CHANNEL_LCD)
2150 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
2151 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2152 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
2153 else /* OMAP_DSS_CHANNEL_LCD2 */
2154 REG_FLD_MOD(DISPC_CONFIG2, type, 11, 11);
2156 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
2159 void dispc_mgr_get_trans_key(enum omap_channel ch,
2160 enum omap_dss_trans_key_type *type,
2164 if (ch == OMAP_DSS_CHANNEL_LCD)
2165 *type = REG_GET(DISPC_CONFIG, 11, 11);
2166 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2167 *type = REG_GET(DISPC_CONFIG, 13, 13);
2168 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2169 *type = REG_GET(DISPC_CONFIG2, 11, 11);
2175 *trans_key = dispc_read_reg(DISPC_TRANS_COLOR(ch));
2178 void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
2180 if (ch == OMAP_DSS_CHANNEL_LCD)
2181 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
2182 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2183 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
2184 else /* OMAP_DSS_CHANNEL_LCD2 */
2185 REG_FLD_MOD(DISPC_CONFIG2, enable, 10, 10);
2188 void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch, bool enable)
2190 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
2193 if (ch == OMAP_DSS_CHANNEL_LCD)
2194 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
2195 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2196 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
2199 bool dispc_mgr_alpha_fixed_zorder_enabled(enum omap_channel ch)
2203 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
2206 if (ch == OMAP_DSS_CHANNEL_LCD)
2207 enabled = REG_GET(DISPC_CONFIG, 18, 18);
2208 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2209 enabled = REG_GET(DISPC_CONFIG, 19, 19);
2216 bool dispc_mgr_trans_key_enabled(enum omap_channel ch)
2220 if (ch == OMAP_DSS_CHANNEL_LCD)
2221 enabled = REG_GET(DISPC_CONFIG, 10, 10);
2222 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
2223 enabled = REG_GET(DISPC_CONFIG, 12, 12);
2224 else if (ch == OMAP_DSS_CHANNEL_LCD2)
2225 enabled = REG_GET(DISPC_CONFIG2, 10, 10);
2233 void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
2237 switch (data_lines) {
2255 if (channel == OMAP_DSS_CHANNEL_LCD2)
2256 REG_FLD_MOD(DISPC_CONTROL2, code, 9, 8);
2258 REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
2261 void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
2267 case DSS_IO_PAD_MODE_RESET:
2271 case DSS_IO_PAD_MODE_RFBI:
2275 case DSS_IO_PAD_MODE_BYPASS:
2284 l = dispc_read_reg(DISPC_CONTROL);
2285 l = FLD_MOD(l, gpout0, 15, 15);
2286 l = FLD_MOD(l, gpout1, 16, 16);
2287 dispc_write_reg(DISPC_CONTROL, l);
2290 void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
2292 if (channel == OMAP_DSS_CHANNEL_LCD2)
2293 REG_FLD_MOD(DISPC_CONTROL2, enable, 11, 11);
2295 REG_FLD_MOD(DISPC_CONTROL, enable, 11, 11);
2298 static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2299 int vsw, int vfp, int vbp)
2301 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2302 if (hsw < 1 || hsw > 64 ||
2303 hfp < 1 || hfp > 256 ||
2304 hbp < 1 || hbp > 256 ||
2305 vsw < 1 || vsw > 64 ||
2306 vfp < 0 || vfp > 255 ||
2307 vbp < 0 || vbp > 255)
2310 if (hsw < 1 || hsw > 256 ||
2311 hfp < 1 || hfp > 4096 ||
2312 hbp < 1 || hbp > 4096 ||
2313 vsw < 1 || vsw > 256 ||
2314 vfp < 0 || vfp > 4095 ||
2315 vbp < 0 || vbp > 4095)
2322 bool dispc_lcd_timings_ok(struct omap_video_timings *timings)
2324 return _dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2325 timings->hbp, timings->vsw,
2326 timings->vfp, timings->vbp);
2329 static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
2330 int hfp, int hbp, int vsw, int vfp, int vbp)
2332 u32 timing_h, timing_v;
2334 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2335 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
2336 FLD_VAL(hbp-1, 27, 20);
2338 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
2339 FLD_VAL(vbp, 27, 20);
2341 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
2342 FLD_VAL(hbp-1, 31, 20);
2344 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
2345 FLD_VAL(vbp, 31, 20);
2348 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2349 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
2352 /* change name to mode? */
2353 void dispc_mgr_set_lcd_timings(enum omap_channel channel,
2354 struct omap_video_timings *timings)
2356 unsigned xtot, ytot;
2357 unsigned long ht, vt;
2359 if (!_dispc_lcd_timings_ok(timings->hsw, timings->hfp,
2360 timings->hbp, timings->vsw,
2361 timings->vfp, timings->vbp))
2364 _dispc_mgr_set_lcd_timings(channel, timings->hsw, timings->hfp,
2365 timings->hbp, timings->vsw, timings->vfp,
2368 dispc_mgr_set_lcd_size(channel, timings->x_res, timings->y_res);
2370 xtot = timings->x_res + timings->hfp + timings->hsw + timings->hbp;
2371 ytot = timings->y_res + timings->vfp + timings->vsw + timings->vbp;
2373 ht = (timings->pixel_clock * 1000) / xtot;
2374 vt = (timings->pixel_clock * 1000) / xtot / ytot;
2376 DSSDBG("channel %d xres %u yres %u\n", channel, timings->x_res,
2378 DSSDBG("pck %u\n", timings->pixel_clock);
2379 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
2380 timings->hsw, timings->hfp, timings->hbp,
2381 timings->vsw, timings->vfp, timings->vbp);
2383 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
2386 static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
2389 BUG_ON(lck_div < 1);
2390 BUG_ON(pck_div < 1);
2392 dispc_write_reg(DISPC_DIVISORo(channel),
2393 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
2396 static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
2400 l = dispc_read_reg(DISPC_DIVISORo(channel));
2401 *lck_div = FLD_GET(l, 23, 16);
2402 *pck_div = FLD_GET(l, 7, 0);
2405 unsigned long dispc_fclk_rate(void)
2407 struct platform_device *dsidev;
2408 unsigned long r = 0;
2410 switch (dss_get_dispc_clk_source()) {
2411 case OMAP_DSS_CLK_SRC_FCK:
2412 r = clk_get_rate(dispc.dss_clk);
2414 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
2415 dsidev = dsi_get_dsidev_from_id(0);
2416 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2418 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2419 dsidev = dsi_get_dsidev_from_id(1);
2420 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2429 unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
2431 struct platform_device *dsidev;
2436 l = dispc_read_reg(DISPC_DIVISORo(channel));
2438 lcd = FLD_GET(l, 23, 16);
2440 switch (dss_get_lcd_clk_source(channel)) {
2441 case OMAP_DSS_CLK_SRC_FCK:
2442 r = clk_get_rate(dispc.dss_clk);
2444 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
2445 dsidev = dsi_get_dsidev_from_id(0);
2446 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2448 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2449 dsidev = dsi_get_dsidev_from_id(1);
2450 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2459 unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
2463 if (dispc_mgr_is_lcd(channel)) {
2467 l = dispc_read_reg(DISPC_DIVISORo(channel));
2469 pcd = FLD_GET(l, 7, 0);
2471 r = dispc_mgr_lclk_rate(channel);
2475 struct omap_dss_device *dssdev =
2476 dispc_mgr_get_device(channel);
2478 switch (dssdev->type) {
2479 case OMAP_DISPLAY_TYPE_VENC:
2480 return venc_get_pixel_clock();
2481 case OMAP_DISPLAY_TYPE_HDMI:
2482 return hdmi_get_pixel_clock();
2489 void dispc_dump_clocks(struct seq_file *s)
2493 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
2494 enum omap_dss_clk_source lcd_clk_src;
2496 if (dispc_runtime_get())
2499 seq_printf(s, "- DISPC -\n");
2501 seq_printf(s, "dispc fclk source = %s (%s)\n",
2502 dss_get_generic_clk_source_name(dispc_clk_src),
2503 dss_feat_get_clk_source_name(dispc_clk_src));
2505 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
2507 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
2508 seq_printf(s, "- DISPC-CORE-CLK -\n");
2509 l = dispc_read_reg(DISPC_DIVISOR);
2510 lcd = FLD_GET(l, 23, 16);
2512 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2513 (dispc_fclk_rate()/lcd), lcd);
2515 seq_printf(s, "- LCD1 -\n");
2517 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD);
2519 seq_printf(s, "lcd1_clk source = %s (%s)\n",
2520 dss_get_generic_clk_source_name(lcd_clk_src),
2521 dss_feat_get_clk_source_name(lcd_clk_src));
2523 dispc_mgr_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD, &lcd, &pcd);
2525 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2526 dispc_mgr_lclk_rate(OMAP_DSS_CHANNEL_LCD), lcd);
2527 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2528 dispc_mgr_pclk_rate(OMAP_DSS_CHANNEL_LCD), pcd);
2529 if (dss_has_feature(FEAT_MGR_LCD2)) {
2530 seq_printf(s, "- LCD2 -\n");
2532 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD2);
2534 seq_printf(s, "lcd2_clk source = %s (%s)\n",
2535 dss_get_generic_clk_source_name(lcd_clk_src),
2536 dss_feat_get_clk_source_name(lcd_clk_src));
2538 dispc_mgr_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD2, &lcd, &pcd);
2540 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2541 dispc_mgr_lclk_rate(OMAP_DSS_CHANNEL_LCD2), lcd);
2542 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
2543 dispc_mgr_pclk_rate(OMAP_DSS_CHANNEL_LCD2), pcd);
2546 dispc_runtime_put();
2549 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2550 void dispc_dump_irqs(struct seq_file *s)
2552 unsigned long flags;
2553 struct dispc_irq_stats stats;
2555 spin_lock_irqsave(&dispc.irq_stats_lock, flags);
2557 stats = dispc.irq_stats;
2558 memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
2559 dispc.irq_stats.last_reset = jiffies;
2561 spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
2563 seq_printf(s, "period %u ms\n",
2564 jiffies_to_msecs(jiffies - stats.last_reset));
2566 seq_printf(s, "irqs %d\n", stats.irq_count);
2568 seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
2574 PIS(ACBIAS_COUNT_STAT);
2576 PIS(GFX_FIFO_UNDERFLOW);
2578 PIS(PAL_GAMMA_MASK);
2580 PIS(VID1_FIFO_UNDERFLOW);
2582 PIS(VID2_FIFO_UNDERFLOW);
2584 if (dss_feat_get_num_ovls() > 3) {
2585 PIS(VID3_FIFO_UNDERFLOW);
2589 PIS(SYNC_LOST_DIGIT);
2591 if (dss_has_feature(FEAT_MGR_LCD2)) {
2594 PIS(ACBIAS_COUNT_STAT2);
2601 void dispc_dump_regs(struct seq_file *s)
2604 const char *mgr_names[] = {
2605 [OMAP_DSS_CHANNEL_LCD] = "LCD",
2606 [OMAP_DSS_CHANNEL_DIGIT] = "TV",
2607 [OMAP_DSS_CHANNEL_LCD2] = "LCD2",
2609 const char *ovl_names[] = {
2610 [OMAP_DSS_GFX] = "GFX",
2611 [OMAP_DSS_VIDEO1] = "VID1",
2612 [OMAP_DSS_VIDEO2] = "VID2",
2613 [OMAP_DSS_VIDEO3] = "VID3",
2615 const char **p_names;
2617 #define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
2619 if (dispc_runtime_get())
2622 /* DISPC common registers */
2623 DUMPREG(DISPC_REVISION);
2624 DUMPREG(DISPC_SYSCONFIG);
2625 DUMPREG(DISPC_SYSSTATUS);
2626 DUMPREG(DISPC_IRQSTATUS);
2627 DUMPREG(DISPC_IRQENABLE);
2628 DUMPREG(DISPC_CONTROL);
2629 DUMPREG(DISPC_CONFIG);
2630 DUMPREG(DISPC_CAPABLE);
2631 DUMPREG(DISPC_LINE_STATUS);
2632 DUMPREG(DISPC_LINE_NUMBER);
2633 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
2634 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
2635 DUMPREG(DISPC_GLOBAL_ALPHA);
2636 if (dss_has_feature(FEAT_MGR_LCD2)) {
2637 DUMPREG(DISPC_CONTROL2);
2638 DUMPREG(DISPC_CONFIG2);
2643 #define DISPC_REG(i, name) name(i)
2644 #define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
2645 48 - strlen(#r) - strlen(p_names[i]), " ", \
2646 dispc_read_reg(DISPC_REG(i, r)))
2648 p_names = mgr_names;
2650 /* DISPC channel specific registers */
2651 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
2652 DUMPREG(i, DISPC_DEFAULT_COLOR);
2653 DUMPREG(i, DISPC_TRANS_COLOR);
2654 DUMPREG(i, DISPC_SIZE_MGR);
2656 if (i == OMAP_DSS_CHANNEL_DIGIT)
2659 DUMPREG(i, DISPC_DEFAULT_COLOR);
2660 DUMPREG(i, DISPC_TRANS_COLOR);
2661 DUMPREG(i, DISPC_TIMING_H);
2662 DUMPREG(i, DISPC_TIMING_V);
2663 DUMPREG(i, DISPC_POL_FREQ);
2664 DUMPREG(i, DISPC_DIVISORo);
2665 DUMPREG(i, DISPC_SIZE_MGR);
2667 DUMPREG(i, DISPC_DATA_CYCLE1);
2668 DUMPREG(i, DISPC_DATA_CYCLE2);
2669 DUMPREG(i, DISPC_DATA_CYCLE3);
2671 if (dss_has_feature(FEAT_CPR)) {
2672 DUMPREG(i, DISPC_CPR_COEF_R);
2673 DUMPREG(i, DISPC_CPR_COEF_G);
2674 DUMPREG(i, DISPC_CPR_COEF_B);
2678 p_names = ovl_names;
2680 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
2681 DUMPREG(i, DISPC_OVL_BA0);
2682 DUMPREG(i, DISPC_OVL_BA1);
2683 DUMPREG(i, DISPC_OVL_POSITION);
2684 DUMPREG(i, DISPC_OVL_SIZE);
2685 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
2686 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
2687 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
2688 DUMPREG(i, DISPC_OVL_ROW_INC);
2689 DUMPREG(i, DISPC_OVL_PIXEL_INC);
2690 if (dss_has_feature(FEAT_PRELOAD))
2691 DUMPREG(i, DISPC_OVL_PRELOAD);
2693 if (i == OMAP_DSS_GFX) {
2694 DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
2695 DUMPREG(i, DISPC_OVL_TABLE_BA);
2699 DUMPREG(i, DISPC_OVL_FIR);
2700 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
2701 DUMPREG(i, DISPC_OVL_ACCU0);
2702 DUMPREG(i, DISPC_OVL_ACCU1);
2703 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2704 DUMPREG(i, DISPC_OVL_BA0_UV);
2705 DUMPREG(i, DISPC_OVL_BA1_UV);
2706 DUMPREG(i, DISPC_OVL_FIR2);
2707 DUMPREG(i, DISPC_OVL_ACCU2_0);
2708 DUMPREG(i, DISPC_OVL_ACCU2_1);
2710 if (dss_has_feature(FEAT_ATTR2))
2711 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
2712 if (dss_has_feature(FEAT_PRELOAD))
2713 DUMPREG(i, DISPC_OVL_PRELOAD);
2719 #define DISPC_REG(plane, name, i) name(plane, i)
2720 #define DUMPREG(plane, name, i) \
2721 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
2722 46 - strlen(#name) - strlen(p_names[plane]), " ", \
2723 dispc_read_reg(DISPC_REG(plane, name, i)))
2725 /* Video pipeline coefficient registers */
2727 /* start from OMAP_DSS_VIDEO1 */
2728 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
2729 for (j = 0; j < 8; j++)
2730 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
2732 for (j = 0; j < 8; j++)
2733 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
2735 for (j = 0; j < 5; j++)
2736 DUMPREG(i, DISPC_OVL_CONV_COEF, j);
2738 if (dss_has_feature(FEAT_FIR_COEF_V)) {
2739 for (j = 0; j < 8; j++)
2740 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
2743 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2744 for (j = 0; j < 8; j++)
2745 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
2747 for (j = 0; j < 8; j++)
2748 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
2750 for (j = 0; j < 8; j++)
2751 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
2755 dispc_runtime_put();
2761 static void _dispc_mgr_set_pol_freq(enum omap_channel channel, bool onoff,
2762 bool rf, bool ieo, bool ipc, bool ihs, bool ivs, u8 acbi,
2767 DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
2768 onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
2770 l |= FLD_VAL(onoff, 17, 17);
2771 l |= FLD_VAL(rf, 16, 16);
2772 l |= FLD_VAL(ieo, 15, 15);
2773 l |= FLD_VAL(ipc, 14, 14);
2774 l |= FLD_VAL(ihs, 13, 13);
2775 l |= FLD_VAL(ivs, 12, 12);
2776 l |= FLD_VAL(acbi, 11, 8);
2777 l |= FLD_VAL(acb, 7, 0);
2779 dispc_write_reg(DISPC_POL_FREQ(channel), l);
2782 void dispc_mgr_set_pol_freq(enum omap_channel channel,
2783 enum omap_panel_config config, u8 acbi, u8 acb)
2785 _dispc_mgr_set_pol_freq(channel, (config & OMAP_DSS_LCD_ONOFF) != 0,
2786 (config & OMAP_DSS_LCD_RF) != 0,
2787 (config & OMAP_DSS_LCD_IEO) != 0,
2788 (config & OMAP_DSS_LCD_IPC) != 0,
2789 (config & OMAP_DSS_LCD_IHS) != 0,
2790 (config & OMAP_DSS_LCD_IVS) != 0,
2794 /* with fck as input clock rate, find dispc dividers that produce req_pck */
2795 void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
2796 struct dispc_clock_info *cinfo)
2798 u16 pcd_min, pcd_max;
2799 unsigned long best_pck;
2800 u16 best_ld, cur_ld;
2801 u16 best_pd, cur_pd;
2803 pcd_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
2804 pcd_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
2813 for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
2814 unsigned long lck = fck / cur_ld;
2816 for (cur_pd = pcd_min; cur_pd <= pcd_max; ++cur_pd) {
2817 unsigned long pck = lck / cur_pd;
2818 long old_delta = abs(best_pck - req_pck);
2819 long new_delta = abs(pck - req_pck);
2821 if (best_pck == 0 || new_delta < old_delta) {
2834 if (lck / pcd_min < req_pck)
2839 cinfo->lck_div = best_ld;
2840 cinfo->pck_div = best_pd;
2841 cinfo->lck = fck / cinfo->lck_div;
2842 cinfo->pck = cinfo->lck / cinfo->pck_div;
2845 /* calculate clock rates using dividers in cinfo */
2846 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
2847 struct dispc_clock_info *cinfo)
2849 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
2851 if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
2854 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
2855 cinfo->pck = cinfo->lck / cinfo->pck_div;
2860 int dispc_mgr_set_clock_div(enum omap_channel channel,
2861 struct dispc_clock_info *cinfo)
2863 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
2864 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
2866 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
2871 int dispc_mgr_get_clock_div(enum omap_channel channel,
2872 struct dispc_clock_info *cinfo)
2876 fck = dispc_fclk_rate();
2878 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
2879 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
2881 cinfo->lck = fck / cinfo->lck_div;
2882 cinfo->pck = cinfo->lck / cinfo->pck_div;
2887 /* dispc.irq_lock has to be locked by the caller */
2888 static void _omap_dispc_set_irqs(void)
2893 struct omap_dispc_isr_data *isr_data;
2895 mask = dispc.irq_error_mask;
2897 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2898 isr_data = &dispc.registered_isr[i];
2900 if (isr_data->isr == NULL)
2903 mask |= isr_data->mask;
2906 old_mask = dispc_read_reg(DISPC_IRQENABLE);
2907 /* clear the irqstatus for newly enabled irqs */
2908 dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
2910 dispc_write_reg(DISPC_IRQENABLE, mask);
2913 int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2917 unsigned long flags;
2918 struct omap_dispc_isr_data *isr_data;
2923 spin_lock_irqsave(&dispc.irq_lock, flags);
2925 /* check for duplicate entry */
2926 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2927 isr_data = &dispc.registered_isr[i];
2928 if (isr_data->isr == isr && isr_data->arg == arg &&
2929 isr_data->mask == mask) {
2938 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2939 isr_data = &dispc.registered_isr[i];
2941 if (isr_data->isr != NULL)
2944 isr_data->isr = isr;
2945 isr_data->arg = arg;
2946 isr_data->mask = mask;
2955 _omap_dispc_set_irqs();
2957 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2961 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2965 EXPORT_SYMBOL(omap_dispc_register_isr);
2967 int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
2970 unsigned long flags;
2972 struct omap_dispc_isr_data *isr_data;
2974 spin_lock_irqsave(&dispc.irq_lock, flags);
2976 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
2977 isr_data = &dispc.registered_isr[i];
2978 if (isr_data->isr != isr || isr_data->arg != arg ||
2979 isr_data->mask != mask)
2982 /* found the correct isr */
2984 isr_data->isr = NULL;
2985 isr_data->arg = NULL;
2993 _omap_dispc_set_irqs();
2995 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2999 EXPORT_SYMBOL(omap_dispc_unregister_isr);
3002 static void print_irq_status(u32 status)
3004 if ((status & dispc.irq_error_mask) == 0)
3007 printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
3010 if (status & DISPC_IRQ_##x) \
3012 PIS(GFX_FIFO_UNDERFLOW);
3014 PIS(VID1_FIFO_UNDERFLOW);
3015 PIS(VID2_FIFO_UNDERFLOW);
3016 if (dss_feat_get_num_ovls() > 3)
3017 PIS(VID3_FIFO_UNDERFLOW);
3019 PIS(SYNC_LOST_DIGIT);
3020 if (dss_has_feature(FEAT_MGR_LCD2))
3028 /* Called from dss.c. Note that we don't touch clocks here,
3029 * but we presume they are on because we got an IRQ. However,
3030 * an irq handler may turn the clocks off, so we may not have
3031 * clock later in the function. */
3032 static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
3035 u32 irqstatus, irqenable;
3036 u32 handledirqs = 0;
3037 u32 unhandled_errors;
3038 struct omap_dispc_isr_data *isr_data;
3039 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
3041 spin_lock(&dispc.irq_lock);
3043 irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
3044 irqenable = dispc_read_reg(DISPC_IRQENABLE);
3046 /* IRQ is not for us */
3047 if (!(irqstatus & irqenable)) {
3048 spin_unlock(&dispc.irq_lock);
3052 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3053 spin_lock(&dispc.irq_stats_lock);
3054 dispc.irq_stats.irq_count++;
3055 dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
3056 spin_unlock(&dispc.irq_stats_lock);
3061 print_irq_status(irqstatus);
3063 /* Ack the interrupt. Do it here before clocks are possibly turned
3065 dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
3066 /* flush posted write */
3067 dispc_read_reg(DISPC_IRQSTATUS);
3069 /* make a copy and unlock, so that isrs can unregister
3071 memcpy(registered_isr, dispc.registered_isr,
3072 sizeof(registered_isr));
3074 spin_unlock(&dispc.irq_lock);
3076 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3077 isr_data = ®istered_isr[i];
3082 if (isr_data->mask & irqstatus) {
3083 isr_data->isr(isr_data->arg, irqstatus);
3084 handledirqs |= isr_data->mask;
3088 spin_lock(&dispc.irq_lock);
3090 unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
3092 if (unhandled_errors) {
3093 dispc.error_irqs |= unhandled_errors;
3095 dispc.irq_error_mask &= ~unhandled_errors;
3096 _omap_dispc_set_irqs();
3098 schedule_work(&dispc.error_work);
3101 spin_unlock(&dispc.irq_lock);
3106 static void dispc_error_worker(struct work_struct *work)
3110 unsigned long flags;
3111 static const unsigned fifo_underflow_bits[] = {
3112 DISPC_IRQ_GFX_FIFO_UNDERFLOW,
3113 DISPC_IRQ_VID1_FIFO_UNDERFLOW,
3114 DISPC_IRQ_VID2_FIFO_UNDERFLOW,
3115 DISPC_IRQ_VID3_FIFO_UNDERFLOW,
3118 static const unsigned sync_lost_bits[] = {
3119 DISPC_IRQ_SYNC_LOST,
3120 DISPC_IRQ_SYNC_LOST_DIGIT,
3121 DISPC_IRQ_SYNC_LOST2,
3124 spin_lock_irqsave(&dispc.irq_lock, flags);
3125 errors = dispc.error_irqs;
3126 dispc.error_irqs = 0;
3127 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3129 dispc_runtime_get();
3131 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3132 struct omap_overlay *ovl;
3135 ovl = omap_dss_get_overlay(i);
3136 bit = fifo_underflow_bits[i];
3139 DSSERR("FIFO UNDERFLOW on %s, disabling the overlay\n",
3141 dispc_ovl_enable(ovl->id, false);
3142 dispc_mgr_go(ovl->manager->id);
3147 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3148 struct omap_overlay_manager *mgr;
3151 mgr = omap_dss_get_overlay_manager(i);
3152 bit = sync_lost_bits[i];
3155 struct omap_dss_device *dssdev = mgr->device;
3158 DSSERR("SYNC_LOST on channel %s, restarting the output "
3159 "with video overlays disabled\n",
3162 enable = dssdev->state == OMAP_DSS_DISPLAY_ACTIVE;
3163 dssdev->driver->disable(dssdev);
3165 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3166 struct omap_overlay *ovl;
3167 ovl = omap_dss_get_overlay(i);
3169 if (ovl->id != OMAP_DSS_GFX &&
3170 ovl->manager == mgr)
3171 dispc_ovl_enable(ovl->id, false);
3174 dispc_mgr_go(mgr->id);
3178 dssdev->driver->enable(dssdev);
3182 if (errors & DISPC_IRQ_OCP_ERR) {
3183 DSSERR("OCP_ERR\n");
3184 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3185 struct omap_overlay_manager *mgr;
3186 mgr = omap_dss_get_overlay_manager(i);
3187 mgr->device->driver->disable(mgr->device);
3191 spin_lock_irqsave(&dispc.irq_lock, flags);
3192 dispc.irq_error_mask |= errors;
3193 _omap_dispc_set_irqs();
3194 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3196 dispc_runtime_put();
3199 int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
3201 void dispc_irq_wait_handler(void *data, u32 mask)
3203 complete((struct completion *)data);
3207 DECLARE_COMPLETION_ONSTACK(completion);
3209 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3215 timeout = wait_for_completion_timeout(&completion, timeout);
3217 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3222 if (timeout == -ERESTARTSYS)
3223 return -ERESTARTSYS;
3228 int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
3229 unsigned long timeout)
3231 void dispc_irq_wait_handler(void *data, u32 mask)
3233 complete((struct completion *)data);
3237 DECLARE_COMPLETION_ONSTACK(completion);
3239 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3245 timeout = wait_for_completion_interruptible_timeout(&completion,
3248 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3253 if (timeout == -ERESTARTSYS)
3254 return -ERESTARTSYS;
3259 #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
3260 void dispc_fake_vsync_irq(void)
3262 u32 irqstatus = DISPC_IRQ_VSYNC;
3265 WARN_ON(!in_interrupt());
3267 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3268 struct omap_dispc_isr_data *isr_data;
3269 isr_data = &dispc.registered_isr[i];
3274 if (isr_data->mask & irqstatus)
3275 isr_data->isr(isr_data->arg, irqstatus);
3280 static void _omap_dispc_initialize_irq(void)
3282 unsigned long flags;
3284 spin_lock_irqsave(&dispc.irq_lock, flags);
3286 memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3288 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
3289 if (dss_has_feature(FEAT_MGR_LCD2))
3290 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
3291 if (dss_feat_get_num_ovls() > 3)
3292 dispc.irq_error_mask |= DISPC_IRQ_VID3_FIFO_UNDERFLOW;
3294 /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3296 dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3298 _omap_dispc_set_irqs();
3300 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3303 void dispc_enable_sidle(void)
3305 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3308 void dispc_disable_sidle(void)
3310 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3313 static void _omap_dispc_initial_config(void)
3317 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3318 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3319 l = dispc_read_reg(DISPC_DIVISOR);
3320 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3321 l = FLD_MOD(l, 1, 0, 0);
3322 l = FLD_MOD(l, 1, 23, 16);
3323 dispc_write_reg(DISPC_DIVISOR, l);
3327 if (dss_has_feature(FEAT_FUNCGATED))
3328 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
3330 /* L3 firewall setting: enable access to OCM RAM */
3331 /* XXX this should be somewhere in plat-omap */
3332 if (cpu_is_omap24xx())
3333 __raw_writel(0x402000b0, OMAP2_L3_IO_ADDRESS(0x680050a0));
3335 _dispc_setup_color_conv_coef();
3337 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3339 dispc_read_plane_fifo_sizes();
3341 dispc_configure_burst_sizes();
3343 dispc_ovl_enable_zorder_planes();
3346 /* DISPC HW IP initialisation */
3347 static int omap_dispchw_probe(struct platform_device *pdev)
3351 struct resource *dispc_mem;
3356 clk = clk_get(&pdev->dev, "fck");
3358 DSSERR("can't get fck\n");
3363 dispc.dss_clk = clk;
3365 spin_lock_init(&dispc.irq_lock);
3367 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3368 spin_lock_init(&dispc.irq_stats_lock);
3369 dispc.irq_stats.last_reset = jiffies;
3372 INIT_WORK(&dispc.error_work, dispc_error_worker);
3374 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3376 DSSERR("can't get IORESOURCE_MEM DISPC\n");
3380 dispc.base = ioremap(dispc_mem->start, resource_size(dispc_mem));
3382 DSSERR("can't ioremap DISPC\n");
3386 dispc.irq = platform_get_irq(dispc.pdev, 0);
3387 if (dispc.irq < 0) {
3388 DSSERR("platform_get_irq failed\n");
3393 r = request_irq(dispc.irq, omap_dispc_irq_handler, IRQF_SHARED,
3394 "OMAP DISPC", dispc.pdev);
3396 DSSERR("request_irq failed\n");
3400 pm_runtime_enable(&pdev->dev);
3402 r = dispc_runtime_get();
3404 goto err_runtime_get;
3406 _omap_dispc_initial_config();
3408 _omap_dispc_initialize_irq();
3410 rev = dispc_read_reg(DISPC_REVISION);
3411 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
3412 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3414 dispc_runtime_put();
3419 pm_runtime_disable(&pdev->dev);
3420 free_irq(dispc.irq, dispc.pdev);
3422 iounmap(dispc.base);
3424 clk_put(dispc.dss_clk);
3429 static int omap_dispchw_remove(struct platform_device *pdev)
3431 pm_runtime_disable(&pdev->dev);
3433 clk_put(dispc.dss_clk);
3435 free_irq(dispc.irq, dispc.pdev);
3436 iounmap(dispc.base);
3440 static int dispc_runtime_suspend(struct device *dev)
3442 dispc_save_context();
3448 static int dispc_runtime_resume(struct device *dev)
3452 r = dss_runtime_get();
3456 dispc_restore_context();
3461 static const struct dev_pm_ops dispc_pm_ops = {
3462 .runtime_suspend = dispc_runtime_suspend,
3463 .runtime_resume = dispc_runtime_resume,
3466 static struct platform_driver omap_dispchw_driver = {
3467 .probe = omap_dispchw_probe,
3468 .remove = omap_dispchw_remove,
3470 .name = "omapdss_dispc",
3471 .owner = THIS_MODULE,
3472 .pm = &dispc_pm_ops,
3476 int dispc_init_platform_driver(void)
3478 return platform_driver_register(&omap_dispchw_driver);
3481 void dispc_uninit_platform_driver(void)
3483 return platform_driver_unregister(&omap_dispchw_driver);