2 * linux/drivers/video/omap2/dss/dispc.h
4 * Copyright (C) 2011 Texas Instruments
5 * Author: Archit Taneja <archit@ti.com>
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License version 2 as published by
10 * the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * You should have received a copy of the GNU General Public License along with
18 * this program. If not, see <http://www.gnu.org/licenses/>.
21 #ifndef __OMAP2_DISPC_REG_H
22 #define __OMAP2_DISPC_REG_H
24 /* DISPC common registers */
25 #define DISPC_REVISION 0x0000
26 #define DISPC_SYSCONFIG 0x0010
27 #define DISPC_SYSSTATUS 0x0014
28 #define DISPC_IRQSTATUS 0x0018
29 #define DISPC_IRQENABLE 0x001C
30 #define DISPC_CONTROL 0x0040
31 #define DISPC_CONFIG 0x0044
32 #define DISPC_CAPABLE 0x0048
33 #define DISPC_LINE_STATUS 0x005C
34 #define DISPC_LINE_NUMBER 0x0060
35 #define DISPC_GLOBAL_ALPHA 0x0074
36 #define DISPC_CONTROL2 0x0238
37 #define DISPC_CONFIG2 0x0620
38 #define DISPC_DIVISOR 0x0804
39 #define DISPC_GLOBAL_BUFFER 0x0800
40 #define DISPC_CONTROL3 0x0848
41 #define DISPC_CONFIG3 0x084C
42 #define DISPC_MSTANDBY_CTRL 0x0858
43 #define DISPC_GLOBAL_MFLAG_ATTRIBUTE 0x085C
45 /* DISPC overlay registers */
46 #define DISPC_OVL_BA0(n) (DISPC_OVL_BASE(n) + \
48 #define DISPC_OVL_BA1(n) (DISPC_OVL_BASE(n) + \
50 #define DISPC_OVL_BA0_UV(n) (DISPC_OVL_BASE(n) + \
51 DISPC_BA0_UV_OFFSET(n))
52 #define DISPC_OVL_BA1_UV(n) (DISPC_OVL_BASE(n) + \
53 DISPC_BA1_UV_OFFSET(n))
54 #define DISPC_OVL_POSITION(n) (DISPC_OVL_BASE(n) + \
56 #define DISPC_OVL_SIZE(n) (DISPC_OVL_BASE(n) + \
58 #define DISPC_OVL_ATTRIBUTES(n) (DISPC_OVL_BASE(n) + \
60 #define DISPC_OVL_ATTRIBUTES2(n) (DISPC_OVL_BASE(n) + \
61 DISPC_ATTR2_OFFSET(n))
62 #define DISPC_OVL_FIFO_THRESHOLD(n) (DISPC_OVL_BASE(n) + \
63 DISPC_FIFO_THRESH_OFFSET(n))
64 #define DISPC_OVL_FIFO_SIZE_STATUS(n) (DISPC_OVL_BASE(n) + \
65 DISPC_FIFO_SIZE_STATUS_OFFSET(n))
66 #define DISPC_OVL_ROW_INC(n) (DISPC_OVL_BASE(n) + \
67 DISPC_ROW_INC_OFFSET(n))
68 #define DISPC_OVL_PIXEL_INC(n) (DISPC_OVL_BASE(n) + \
69 DISPC_PIX_INC_OFFSET(n))
70 #define DISPC_OVL_WINDOW_SKIP(n) (DISPC_OVL_BASE(n) + \
71 DISPC_WINDOW_SKIP_OFFSET(n))
72 #define DISPC_OVL_TABLE_BA(n) (DISPC_OVL_BASE(n) + \
73 DISPC_TABLE_BA_OFFSET(n))
74 #define DISPC_OVL_FIR(n) (DISPC_OVL_BASE(n) + \
76 #define DISPC_OVL_FIR2(n) (DISPC_OVL_BASE(n) + \
78 #define DISPC_OVL_PICTURE_SIZE(n) (DISPC_OVL_BASE(n) + \
79 DISPC_PIC_SIZE_OFFSET(n))
80 #define DISPC_OVL_ACCU0(n) (DISPC_OVL_BASE(n) + \
81 DISPC_ACCU0_OFFSET(n))
82 #define DISPC_OVL_ACCU1(n) (DISPC_OVL_BASE(n) + \
83 DISPC_ACCU1_OFFSET(n))
84 #define DISPC_OVL_ACCU2_0(n) (DISPC_OVL_BASE(n) + \
85 DISPC_ACCU2_0_OFFSET(n))
86 #define DISPC_OVL_ACCU2_1(n) (DISPC_OVL_BASE(n) + \
87 DISPC_ACCU2_1_OFFSET(n))
88 #define DISPC_OVL_FIR_COEF_H(n, i) (DISPC_OVL_BASE(n) + \
89 DISPC_FIR_COEF_H_OFFSET(n, i))
90 #define DISPC_OVL_FIR_COEF_HV(n, i) (DISPC_OVL_BASE(n) + \
91 DISPC_FIR_COEF_HV_OFFSET(n, i))
92 #define DISPC_OVL_FIR_COEF_H2(n, i) (DISPC_OVL_BASE(n) + \
93 DISPC_FIR_COEF_H2_OFFSET(n, i))
94 #define DISPC_OVL_FIR_COEF_HV2(n, i) (DISPC_OVL_BASE(n) + \
95 DISPC_FIR_COEF_HV2_OFFSET(n, i))
96 #define DISPC_OVL_CONV_COEF(n, i) (DISPC_OVL_BASE(n) + \
97 DISPC_CONV_COEF_OFFSET(n, i))
98 #define DISPC_OVL_FIR_COEF_V(n, i) (DISPC_OVL_BASE(n) + \
99 DISPC_FIR_COEF_V_OFFSET(n, i))
100 #define DISPC_OVL_FIR_COEF_V2(n, i) (DISPC_OVL_BASE(n) + \
101 DISPC_FIR_COEF_V2_OFFSET(n, i))
102 #define DISPC_OVL_PRELOAD(n) (DISPC_OVL_BASE(n) + \
103 DISPC_PRELOAD_OFFSET(n))
104 #define DISPC_OVL_MFLAG_THRESHOLD(n) (DISPC_OVL_BASE(n) + \
105 DISPC_MFLAG_THRESHOLD_OFFSET(n))
107 /* DISPC up/downsampling FIR filter coefficient structure */
116 const struct dispc_coef *dispc_ovl_get_scale_coef(int inc, int five_taps);
118 /* DISPC manager/channel specific registers */
119 static inline u16 DISPC_DEFAULT_COLOR(enum omap_channel channel)
122 case OMAP_DSS_CHANNEL_LCD:
124 case OMAP_DSS_CHANNEL_DIGIT:
126 case OMAP_DSS_CHANNEL_LCD2:
128 case OMAP_DSS_CHANNEL_LCD3:
136 static inline u16 DISPC_TRANS_COLOR(enum omap_channel channel)
139 case OMAP_DSS_CHANNEL_LCD:
141 case OMAP_DSS_CHANNEL_DIGIT:
143 case OMAP_DSS_CHANNEL_LCD2:
145 case OMAP_DSS_CHANNEL_LCD3:
153 static inline u16 DISPC_TIMING_H(enum omap_channel channel)
156 case OMAP_DSS_CHANNEL_LCD:
158 case OMAP_DSS_CHANNEL_DIGIT:
161 case OMAP_DSS_CHANNEL_LCD2:
163 case OMAP_DSS_CHANNEL_LCD3:
171 static inline u16 DISPC_TIMING_V(enum omap_channel channel)
174 case OMAP_DSS_CHANNEL_LCD:
176 case OMAP_DSS_CHANNEL_DIGIT:
179 case OMAP_DSS_CHANNEL_LCD2:
181 case OMAP_DSS_CHANNEL_LCD3:
189 static inline u16 DISPC_POL_FREQ(enum omap_channel channel)
192 case OMAP_DSS_CHANNEL_LCD:
194 case OMAP_DSS_CHANNEL_DIGIT:
197 case OMAP_DSS_CHANNEL_LCD2:
199 case OMAP_DSS_CHANNEL_LCD3:
207 static inline u16 DISPC_DIVISORo(enum omap_channel channel)
210 case OMAP_DSS_CHANNEL_LCD:
212 case OMAP_DSS_CHANNEL_DIGIT:
215 case OMAP_DSS_CHANNEL_LCD2:
217 case OMAP_DSS_CHANNEL_LCD3:
225 /* Named as DISPC_SIZE_LCD, DISPC_SIZE_DIGIT and DISPC_SIZE_LCD2 in TRM */
226 static inline u16 DISPC_SIZE_MGR(enum omap_channel channel)
229 case OMAP_DSS_CHANNEL_LCD:
231 case OMAP_DSS_CHANNEL_DIGIT:
233 case OMAP_DSS_CHANNEL_LCD2:
235 case OMAP_DSS_CHANNEL_LCD3:
243 static inline u16 DISPC_DATA_CYCLE1(enum omap_channel channel)
246 case OMAP_DSS_CHANNEL_LCD:
248 case OMAP_DSS_CHANNEL_DIGIT:
251 case OMAP_DSS_CHANNEL_LCD2:
253 case OMAP_DSS_CHANNEL_LCD3:
261 static inline u16 DISPC_DATA_CYCLE2(enum omap_channel channel)
264 case OMAP_DSS_CHANNEL_LCD:
266 case OMAP_DSS_CHANNEL_DIGIT:
269 case OMAP_DSS_CHANNEL_LCD2:
271 case OMAP_DSS_CHANNEL_LCD3:
279 static inline u16 DISPC_DATA_CYCLE3(enum omap_channel channel)
282 case OMAP_DSS_CHANNEL_LCD:
284 case OMAP_DSS_CHANNEL_DIGIT:
287 case OMAP_DSS_CHANNEL_LCD2:
289 case OMAP_DSS_CHANNEL_LCD3:
297 static inline u16 DISPC_CPR_COEF_R(enum omap_channel channel)
300 case OMAP_DSS_CHANNEL_LCD:
302 case OMAP_DSS_CHANNEL_DIGIT:
305 case OMAP_DSS_CHANNEL_LCD2:
307 case OMAP_DSS_CHANNEL_LCD3:
315 static inline u16 DISPC_CPR_COEF_G(enum omap_channel channel)
318 case OMAP_DSS_CHANNEL_LCD:
320 case OMAP_DSS_CHANNEL_DIGIT:
323 case OMAP_DSS_CHANNEL_LCD2:
325 case OMAP_DSS_CHANNEL_LCD3:
333 static inline u16 DISPC_CPR_COEF_B(enum omap_channel channel)
336 case OMAP_DSS_CHANNEL_LCD:
338 case OMAP_DSS_CHANNEL_DIGIT:
341 case OMAP_DSS_CHANNEL_LCD2:
343 case OMAP_DSS_CHANNEL_LCD3:
351 /* DISPC overlay register base addresses */
352 static inline u16 DISPC_OVL_BASE(enum omap_plane plane)
357 case OMAP_DSS_VIDEO1:
359 case OMAP_DSS_VIDEO2:
361 case OMAP_DSS_VIDEO3:
371 /* DISPC overlay register offsets */
372 static inline u16 DISPC_BA0_OFFSET(enum omap_plane plane)
376 case OMAP_DSS_VIDEO1:
377 case OMAP_DSS_VIDEO2:
379 case OMAP_DSS_VIDEO3:
388 static inline u16 DISPC_BA1_OFFSET(enum omap_plane plane)
392 case OMAP_DSS_VIDEO1:
393 case OMAP_DSS_VIDEO2:
395 case OMAP_DSS_VIDEO3:
404 static inline u16 DISPC_BA0_UV_OFFSET(enum omap_plane plane)
410 case OMAP_DSS_VIDEO1:
412 case OMAP_DSS_VIDEO2:
414 case OMAP_DSS_VIDEO3:
424 static inline u16 DISPC_BA1_UV_OFFSET(enum omap_plane plane)
430 case OMAP_DSS_VIDEO1:
432 case OMAP_DSS_VIDEO2:
434 case OMAP_DSS_VIDEO3:
444 static inline u16 DISPC_POS_OFFSET(enum omap_plane plane)
448 case OMAP_DSS_VIDEO1:
449 case OMAP_DSS_VIDEO2:
451 case OMAP_DSS_VIDEO3:
459 static inline u16 DISPC_SIZE_OFFSET(enum omap_plane plane)
463 case OMAP_DSS_VIDEO1:
464 case OMAP_DSS_VIDEO2:
466 case OMAP_DSS_VIDEO3:
475 static inline u16 DISPC_ATTR_OFFSET(enum omap_plane plane)
480 case OMAP_DSS_VIDEO1:
481 case OMAP_DSS_VIDEO2:
483 case OMAP_DSS_VIDEO3:
492 static inline u16 DISPC_ATTR2_OFFSET(enum omap_plane plane)
498 case OMAP_DSS_VIDEO1:
500 case OMAP_DSS_VIDEO2:
502 case OMAP_DSS_VIDEO3:
512 static inline u16 DISPC_FIFO_THRESH_OFFSET(enum omap_plane plane)
517 case OMAP_DSS_VIDEO1:
518 case OMAP_DSS_VIDEO2:
520 case OMAP_DSS_VIDEO3:
529 static inline u16 DISPC_FIFO_SIZE_STATUS_OFFSET(enum omap_plane plane)
534 case OMAP_DSS_VIDEO1:
535 case OMAP_DSS_VIDEO2:
537 case OMAP_DSS_VIDEO3:
546 static inline u16 DISPC_ROW_INC_OFFSET(enum omap_plane plane)
551 case OMAP_DSS_VIDEO1:
552 case OMAP_DSS_VIDEO2:
554 case OMAP_DSS_VIDEO3:
563 static inline u16 DISPC_PIX_INC_OFFSET(enum omap_plane plane)
568 case OMAP_DSS_VIDEO1:
569 case OMAP_DSS_VIDEO2:
571 case OMAP_DSS_VIDEO3:
580 static inline u16 DISPC_WINDOW_SKIP_OFFSET(enum omap_plane plane)
585 case OMAP_DSS_VIDEO1:
586 case OMAP_DSS_VIDEO2:
587 case OMAP_DSS_VIDEO3:
596 static inline u16 DISPC_TABLE_BA_OFFSET(enum omap_plane plane)
601 case OMAP_DSS_VIDEO1:
602 case OMAP_DSS_VIDEO2:
603 case OMAP_DSS_VIDEO3:
612 static inline u16 DISPC_FIR_OFFSET(enum omap_plane plane)
618 case OMAP_DSS_VIDEO1:
619 case OMAP_DSS_VIDEO2:
621 case OMAP_DSS_VIDEO3:
630 static inline u16 DISPC_FIR2_OFFSET(enum omap_plane plane)
636 case OMAP_DSS_VIDEO1:
638 case OMAP_DSS_VIDEO2:
640 case OMAP_DSS_VIDEO3:
650 static inline u16 DISPC_PIC_SIZE_OFFSET(enum omap_plane plane)
656 case OMAP_DSS_VIDEO1:
657 case OMAP_DSS_VIDEO2:
659 case OMAP_DSS_VIDEO3:
669 static inline u16 DISPC_ACCU0_OFFSET(enum omap_plane plane)
675 case OMAP_DSS_VIDEO1:
676 case OMAP_DSS_VIDEO2:
678 case OMAP_DSS_VIDEO3:
687 static inline u16 DISPC_ACCU2_0_OFFSET(enum omap_plane plane)
693 case OMAP_DSS_VIDEO1:
695 case OMAP_DSS_VIDEO2:
697 case OMAP_DSS_VIDEO3:
707 static inline u16 DISPC_ACCU1_OFFSET(enum omap_plane plane)
713 case OMAP_DSS_VIDEO1:
714 case OMAP_DSS_VIDEO2:
716 case OMAP_DSS_VIDEO3:
725 static inline u16 DISPC_ACCU2_1_OFFSET(enum omap_plane plane)
731 case OMAP_DSS_VIDEO1:
733 case OMAP_DSS_VIDEO2:
735 case OMAP_DSS_VIDEO3:
745 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
746 static inline u16 DISPC_FIR_COEF_H_OFFSET(enum omap_plane plane, u16 i)
752 case OMAP_DSS_VIDEO1:
753 case OMAP_DSS_VIDEO2:
754 return 0x0034 + i * 0x8;
755 case OMAP_DSS_VIDEO3:
757 return 0x0010 + i * 0x8;
764 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
765 static inline u16 DISPC_FIR_COEF_H2_OFFSET(enum omap_plane plane, u16 i)
771 case OMAP_DSS_VIDEO1:
772 return 0x058C + i * 0x8;
773 case OMAP_DSS_VIDEO2:
774 return 0x0568 + i * 0x8;
775 case OMAP_DSS_VIDEO3:
776 return 0x0430 + i * 0x8;
778 return 0x02A0 + i * 0x8;
785 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
786 static inline u16 DISPC_FIR_COEF_HV_OFFSET(enum omap_plane plane, u16 i)
792 case OMAP_DSS_VIDEO1:
793 case OMAP_DSS_VIDEO2:
794 return 0x0038 + i * 0x8;
795 case OMAP_DSS_VIDEO3:
797 return 0x0014 + i * 0x8;
804 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
805 static inline u16 DISPC_FIR_COEF_HV2_OFFSET(enum omap_plane plane, u16 i)
811 case OMAP_DSS_VIDEO1:
812 return 0x0590 + i * 8;
813 case OMAP_DSS_VIDEO2:
814 return 0x056C + i * 0x8;
815 case OMAP_DSS_VIDEO3:
816 return 0x0434 + i * 0x8;
818 return 0x02A4 + i * 0x8;
825 /* coef index i = {0, 1, 2, 3, 4,} */
826 static inline u16 DISPC_CONV_COEF_OFFSET(enum omap_plane plane, u16 i)
832 case OMAP_DSS_VIDEO1:
833 case OMAP_DSS_VIDEO2:
834 case OMAP_DSS_VIDEO3:
836 return 0x0074 + i * 0x4;
843 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
844 static inline u16 DISPC_FIR_COEF_V_OFFSET(enum omap_plane plane, u16 i)
850 case OMAP_DSS_VIDEO1:
851 return 0x0124 + i * 0x4;
852 case OMAP_DSS_VIDEO2:
853 return 0x00B4 + i * 0x4;
854 case OMAP_DSS_VIDEO3:
856 return 0x0050 + i * 0x4;
863 /* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
864 static inline u16 DISPC_FIR_COEF_V2_OFFSET(enum omap_plane plane, u16 i)
870 case OMAP_DSS_VIDEO1:
871 return 0x05CC + i * 0x4;
872 case OMAP_DSS_VIDEO2:
873 return 0x05A8 + i * 0x4;
874 case OMAP_DSS_VIDEO3:
875 return 0x0470 + i * 0x4;
877 return 0x02E0 + i * 0x4;
884 static inline u16 DISPC_PRELOAD_OFFSET(enum omap_plane plane)
889 case OMAP_DSS_VIDEO1:
891 case OMAP_DSS_VIDEO2:
893 case OMAP_DSS_VIDEO3:
901 static inline u16 DISPC_MFLAG_THRESHOLD_OFFSET(enum omap_plane plane)
906 case OMAP_DSS_VIDEO1:
908 case OMAP_DSS_VIDEO2:
910 case OMAP_DSS_VIDEO3: