2 * linux/drivers/video/omap2/dss/dpi.c
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * Some code and ideas taken from drivers/video/omap/ driver
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
23 #define DSS_SUBSYS_NAME "DPI"
25 #include <linux/kernel.h>
26 #include <linux/delay.h>
27 #include <linux/export.h>
28 #include <linux/err.h>
29 #include <linux/errno.h>
30 #include <linux/platform_device.h>
31 #include <linux/regulator/consumer.h>
33 #include <video/omapdss.h>
39 struct regulator *vdds_dsi_reg;
40 struct platform_device *dsidev;
43 static struct platform_device *dpi_get_dsidev(enum omap_dss_clk_source clk)
47 dsi_module = clk == OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC ? 0 : 1;
49 return dsi_get_dsidev_from_id(dsi_module);
52 static bool dpi_use_dsi_pll(struct omap_dss_device *dssdev)
54 if (dssdev->clocks.dispc.dispc_fclk_src ==
55 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC ||
56 dssdev->clocks.dispc.dispc_fclk_src ==
57 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC ||
58 dssdev->clocks.dispc.channel.lcd_clk_src ==
59 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC ||
60 dssdev->clocks.dispc.channel.lcd_clk_src ==
61 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC)
67 static int dpi_set_dsi_clk(struct omap_dss_device *dssdev,
68 unsigned long pck_req, unsigned long *fck, int *lck_div,
71 struct dsi_clock_info dsi_cinfo;
72 struct dispc_clock_info dispc_cinfo;
75 r = dsi_pll_calc_clock_div_pck(dpi.dsidev, pck_req, &dsi_cinfo,
80 r = dsi_pll_set_clock_div(dpi.dsidev, &dsi_cinfo);
84 dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src);
86 r = dispc_mgr_set_clock_div(dssdev->manager->id, &dispc_cinfo);
88 dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
92 *fck = dsi_cinfo.dsi_pll_hsdiv_dispc_clk;
93 *lck_div = dispc_cinfo.lck_div;
94 *pck_div = dispc_cinfo.pck_div;
99 static int dpi_set_dispc_clk(struct omap_dss_device *dssdev,
100 unsigned long pck_req, unsigned long *fck, int *lck_div,
103 struct dss_clock_info dss_cinfo;
104 struct dispc_clock_info dispc_cinfo;
107 r = dss_calc_clock_div(pck_req, &dss_cinfo, &dispc_cinfo);
111 r = dss_set_clock_div(&dss_cinfo);
115 r = dispc_mgr_set_clock_div(dssdev->manager->id, &dispc_cinfo);
119 *fck = dss_cinfo.fck;
120 *lck_div = dispc_cinfo.lck_div;
121 *pck_div = dispc_cinfo.pck_div;
126 static int dpi_set_mode(struct omap_dss_device *dssdev)
128 struct omap_video_timings *t = &dssdev->panel.timings;
129 int lck_div = 0, pck_div = 0;
130 unsigned long fck = 0;
134 dispc_mgr_set_pol_freq(dssdev->manager->id, dssdev->panel.config,
135 dssdev->panel.acbi, dssdev->panel.acb);
137 if (dpi_use_dsi_pll(dssdev))
138 r = dpi_set_dsi_clk(dssdev, t->pixel_clock * 1000, &fck,
141 r = dpi_set_dispc_clk(dssdev, t->pixel_clock * 1000, &fck,
146 pck = fck / lck_div / pck_div / 1000;
148 if (pck != t->pixel_clock) {
149 DSSWARN("Could not find exact pixel clock. "
150 "Requested %d kHz, got %lu kHz\n",
151 t->pixel_clock, pck);
153 t->pixel_clock = pck;
156 dss_mgr_set_timings(dssdev->manager, t);
161 static void dpi_basic_init(struct omap_dss_device *dssdev)
165 is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
167 dispc_mgr_set_io_pad_mode(DSS_IO_PAD_MODE_BYPASS);
168 dispc_mgr_enable_stallmode(dssdev->manager->id, false);
170 dispc_mgr_set_lcd_display_type(dssdev->manager->id, is_tft ?
171 OMAP_DSS_LCD_DISPLAY_TFT : OMAP_DSS_LCD_DISPLAY_STN);
172 dispc_mgr_set_tft_data_lines(dssdev->manager->id,
173 dssdev->phy.dpi.data_lines);
176 int omapdss_dpi_display_enable(struct omap_dss_device *dssdev)
180 if (cpu_is_omap34xx() && !dpi.vdds_dsi_reg) {
181 DSSERR("no VDSS_DSI regulator\n");
185 if (dssdev->manager == NULL) {
186 DSSERR("failed to enable display: no manager\n");
190 r = omap_dss_start_device(dssdev);
192 DSSERR("failed to start device\n");
196 if (cpu_is_omap34xx()) {
197 r = regulator_enable(dpi.vdds_dsi_reg);
202 r = dispc_runtime_get();
206 dpi_basic_init(dssdev);
208 if (dpi_use_dsi_pll(dssdev)) {
209 r = dsi_runtime_get(dpi.dsidev);
213 r = dsi_pll_init(dpi.dsidev, 0, 1);
215 goto err_dsi_pll_init;
218 r = dpi_set_mode(dssdev);
224 r = dss_mgr_enable(dssdev->manager);
232 if (dpi_use_dsi_pll(dssdev))
233 dsi_pll_uninit(dpi.dsidev, true);
235 if (dpi_use_dsi_pll(dssdev))
236 dsi_runtime_put(dpi.dsidev);
240 if (cpu_is_omap34xx())
241 regulator_disable(dpi.vdds_dsi_reg);
243 omap_dss_stop_device(dssdev);
247 EXPORT_SYMBOL(omapdss_dpi_display_enable);
249 void omapdss_dpi_display_disable(struct omap_dss_device *dssdev)
251 dss_mgr_disable(dssdev->manager);
253 if (dpi_use_dsi_pll(dssdev)) {
254 dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
255 dsi_pll_uninit(dpi.dsidev, true);
256 dsi_runtime_put(dpi.dsidev);
261 if (cpu_is_omap34xx())
262 regulator_disable(dpi.vdds_dsi_reg);
264 omap_dss_stop_device(dssdev);
266 EXPORT_SYMBOL(omapdss_dpi_display_disable);
268 void dpi_set_timings(struct omap_dss_device *dssdev,
269 struct omap_video_timings *timings)
273 DSSDBG("dpi_set_timings\n");
274 dssdev->panel.timings = *timings;
275 if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) {
276 r = dispc_runtime_get();
280 dpi_set_mode(dssdev);
284 dss_mgr_set_timings(dssdev->manager, timings);
287 EXPORT_SYMBOL(dpi_set_timings);
289 int dpi_check_timings(struct omap_dss_device *dssdev,
290 struct omap_video_timings *timings)
293 int lck_div, pck_div;
296 struct dispc_clock_info dispc_cinfo;
298 if (dss_mgr_check_timings(dssdev->manager, timings))
301 if (timings->pixel_clock == 0)
304 if (dpi_use_dsi_pll(dssdev)) {
305 struct dsi_clock_info dsi_cinfo;
306 r = dsi_pll_calc_clock_div_pck(dpi.dsidev,
307 timings->pixel_clock * 1000,
308 &dsi_cinfo, &dispc_cinfo);
313 fck = dsi_cinfo.dsi_pll_hsdiv_dispc_clk;
315 struct dss_clock_info dss_cinfo;
316 r = dss_calc_clock_div(timings->pixel_clock * 1000,
317 &dss_cinfo, &dispc_cinfo);
325 lck_div = dispc_cinfo.lck_div;
326 pck_div = dispc_cinfo.pck_div;
328 pck = fck / lck_div / pck_div / 1000;
330 timings->pixel_clock = pck;
334 EXPORT_SYMBOL(dpi_check_timings);
336 static int __init dpi_init_display(struct omap_dss_device *dssdev)
338 DSSDBG("init_display\n");
340 if (cpu_is_omap34xx() && dpi.vdds_dsi_reg == NULL) {
341 struct regulator *vdds_dsi;
343 vdds_dsi = dss_get_vdds_dsi();
345 if (IS_ERR(vdds_dsi)) {
346 DSSERR("can't get VDDS_DSI regulator\n");
347 return PTR_ERR(vdds_dsi);
350 dpi.vdds_dsi_reg = vdds_dsi;
353 if (dpi_use_dsi_pll(dssdev)) {
354 enum omap_dss_clk_source dispc_fclk_src =
355 dssdev->clocks.dispc.dispc_fclk_src;
356 dpi.dsidev = dpi_get_dsidev(dispc_fclk_src);
362 static void __init dpi_probe_pdata(struct platform_device *pdev)
364 struct omap_dss_board_info *pdata = pdev->dev.platform_data;
367 for (i = 0; i < pdata->num_devices; ++i) {
368 struct omap_dss_device *dssdev = pdata->devices[i];
370 if (dssdev->type != OMAP_DISPLAY_TYPE_DPI)
373 r = dpi_init_display(dssdev);
375 DSSERR("device %s init failed: %d\n", dssdev->name, r);
379 r = omap_dss_register_device(dssdev, &pdev->dev, i);
381 DSSERR("device %s register failed: %d\n",
386 static int __init omap_dpi_probe(struct platform_device *pdev)
388 dpi_probe_pdata(pdev);
393 static int __exit omap_dpi_remove(struct platform_device *pdev)
395 omap_dss_unregister_child_devices(&pdev->dev);
400 static struct platform_driver omap_dpi_driver = {
401 .remove = __exit_p(omap_dpi_remove),
403 .name = "omapdss_dpi",
404 .owner = THIS_MODULE,
408 int __init dpi_init_platform_driver(void)
410 return platform_driver_probe(&omap_dpi_driver, omap_dpi_probe);
413 void __exit dpi_uninit_platform_driver(void)
415 platform_driver_unregister(&omap_dpi_driver);