2 * linux/drivers/video/omap2/dss/dpi.c
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * Some code and ideas taken from drivers/video/omap/ driver
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
23 #define DSS_SUBSYS_NAME "DPI"
25 #include <linux/kernel.h>
26 #include <linux/delay.h>
27 #include <linux/export.h>
28 #include <linux/err.h>
29 #include <linux/errno.h>
30 #include <linux/platform_device.h>
31 #include <linux/regulator/consumer.h>
33 #include <video/omapdss.h>
39 struct regulator *vdds_dsi_reg;
40 struct platform_device *dsidev;
43 static struct platform_device *dpi_get_dsidev(enum omap_dss_clk_source clk)
47 dsi_module = clk == OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC ? 0 : 1;
49 return dsi_get_dsidev_from_id(dsi_module);
52 static bool dpi_use_dsi_pll(struct omap_dss_device *dssdev)
54 if (dssdev->clocks.dispc.dispc_fclk_src ==
55 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC ||
56 dssdev->clocks.dispc.dispc_fclk_src ==
57 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC ||
58 dssdev->clocks.dispc.channel.lcd_clk_src ==
59 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC ||
60 dssdev->clocks.dispc.channel.lcd_clk_src ==
61 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC)
67 static int dpi_set_dsi_clk(struct omap_dss_device *dssdev, bool is_tft,
68 unsigned long pck_req, unsigned long *fck, int *lck_div,
71 struct dsi_clock_info dsi_cinfo;
72 struct dispc_clock_info dispc_cinfo;
75 r = dsi_pll_calc_clock_div_pck(dpi.dsidev, is_tft, pck_req,
76 &dsi_cinfo, &dispc_cinfo);
80 r = dsi_pll_set_clock_div(dpi.dsidev, &dsi_cinfo);
84 dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src);
86 r = dispc_mgr_set_clock_div(dssdev->manager->id, &dispc_cinfo);
88 dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
92 *fck = dsi_cinfo.dsi_pll_hsdiv_dispc_clk;
93 *lck_div = dispc_cinfo.lck_div;
94 *pck_div = dispc_cinfo.pck_div;
99 static int dpi_set_dispc_clk(struct omap_dss_device *dssdev, bool is_tft,
100 unsigned long pck_req, unsigned long *fck, int *lck_div,
103 struct dss_clock_info dss_cinfo;
104 struct dispc_clock_info dispc_cinfo;
107 r = dss_calc_clock_div(is_tft, pck_req, &dss_cinfo, &dispc_cinfo);
111 r = dss_set_clock_div(&dss_cinfo);
115 r = dispc_mgr_set_clock_div(dssdev->manager->id, &dispc_cinfo);
119 *fck = dss_cinfo.fck;
120 *lck_div = dispc_cinfo.lck_div;
121 *pck_div = dispc_cinfo.pck_div;
126 static int dpi_set_mode(struct omap_dss_device *dssdev)
128 struct omap_video_timings *t = &dssdev->panel.timings;
129 int lck_div = 0, pck_div = 0;
130 unsigned long fck = 0;
135 dispc_mgr_set_pol_freq(dssdev->manager->id, dssdev->panel.config,
136 dssdev->panel.acbi, dssdev->panel.acb);
138 is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
140 if (dpi_use_dsi_pll(dssdev))
141 r = dpi_set_dsi_clk(dssdev, is_tft, t->pixel_clock * 1000,
142 &fck, &lck_div, &pck_div);
144 r = dpi_set_dispc_clk(dssdev, is_tft, t->pixel_clock * 1000,
145 &fck, &lck_div, &pck_div);
149 pck = fck / lck_div / pck_div / 1000;
151 if (pck != t->pixel_clock) {
152 DSSWARN("Could not find exact pixel clock. "
153 "Requested %d kHz, got %lu kHz\n",
154 t->pixel_clock, pck);
156 t->pixel_clock = pck;
159 dispc_mgr_set_lcd_timings(dssdev->manager->id, t);
164 static void dpi_basic_init(struct omap_dss_device *dssdev)
168 is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
170 dispc_mgr_set_io_pad_mode(DSS_IO_PAD_MODE_BYPASS);
171 dispc_mgr_enable_stallmode(dssdev->manager->id, false);
173 dispc_mgr_set_lcd_display_type(dssdev->manager->id, is_tft ?
174 OMAP_DSS_LCD_DISPLAY_TFT : OMAP_DSS_LCD_DISPLAY_STN);
175 dispc_mgr_set_tft_data_lines(dssdev->manager->id,
176 dssdev->phy.dpi.data_lines);
179 int omapdss_dpi_display_enable(struct omap_dss_device *dssdev)
183 if (cpu_is_omap34xx() && !dpi.vdds_dsi_reg) {
184 DSSERR("no VDSS_DSI regulator\n");
188 if (dssdev->manager == NULL) {
189 DSSERR("failed to enable display: no manager\n");
193 r = omap_dss_start_device(dssdev);
195 DSSERR("failed to start device\n");
199 if (cpu_is_omap34xx()) {
200 r = regulator_enable(dpi.vdds_dsi_reg);
205 r = dss_runtime_get();
209 r = dispc_runtime_get();
213 dpi_basic_init(dssdev);
215 if (dpi_use_dsi_pll(dssdev)) {
216 r = dsi_runtime_get(dpi.dsidev);
220 r = dsi_pll_init(dpi.dsidev, 0, 1);
222 goto err_dsi_pll_init;
225 r = dpi_set_mode(dssdev);
231 r = dss_mgr_enable(dssdev->manager);
239 if (dpi_use_dsi_pll(dssdev))
240 dsi_pll_uninit(dpi.dsidev, true);
242 if (dpi_use_dsi_pll(dssdev))
243 dsi_runtime_put(dpi.dsidev);
249 if (cpu_is_omap34xx())
250 regulator_disable(dpi.vdds_dsi_reg);
252 omap_dss_stop_device(dssdev);
256 EXPORT_SYMBOL(omapdss_dpi_display_enable);
258 void omapdss_dpi_display_disable(struct omap_dss_device *dssdev)
260 dss_mgr_disable(dssdev->manager);
262 if (dpi_use_dsi_pll(dssdev)) {
263 dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
264 dsi_pll_uninit(dpi.dsidev, true);
265 dsi_runtime_put(dpi.dsidev);
271 if (cpu_is_omap34xx())
272 regulator_disable(dpi.vdds_dsi_reg);
274 omap_dss_stop_device(dssdev);
276 EXPORT_SYMBOL(omapdss_dpi_display_disable);
278 void dpi_set_timings(struct omap_dss_device *dssdev,
279 struct omap_video_timings *timings)
283 DSSDBG("dpi_set_timings\n");
284 dssdev->panel.timings = *timings;
285 if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) {
286 r = dss_runtime_get();
290 r = dispc_runtime_get();
296 dpi_set_mode(dssdev);
297 dispc_mgr_go(dssdev->manager->id);
303 EXPORT_SYMBOL(dpi_set_timings);
305 int dpi_check_timings(struct omap_dss_device *dssdev,
306 struct omap_video_timings *timings)
310 int lck_div, pck_div;
313 struct dispc_clock_info dispc_cinfo;
315 if (!dispc_lcd_timings_ok(timings))
318 if (timings->pixel_clock == 0)
321 is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
323 if (dpi_use_dsi_pll(dssdev)) {
324 struct dsi_clock_info dsi_cinfo;
325 r = dsi_pll_calc_clock_div_pck(dpi.dsidev, is_tft,
326 timings->pixel_clock * 1000,
327 &dsi_cinfo, &dispc_cinfo);
332 fck = dsi_cinfo.dsi_pll_hsdiv_dispc_clk;
334 struct dss_clock_info dss_cinfo;
335 r = dss_calc_clock_div(is_tft, timings->pixel_clock * 1000,
336 &dss_cinfo, &dispc_cinfo);
344 lck_div = dispc_cinfo.lck_div;
345 pck_div = dispc_cinfo.pck_div;
347 pck = fck / lck_div / pck_div / 1000;
349 timings->pixel_clock = pck;
353 EXPORT_SYMBOL(dpi_check_timings);
355 int dpi_init_display(struct omap_dss_device *dssdev)
357 DSSDBG("init_display\n");
359 if (cpu_is_omap34xx() && dpi.vdds_dsi_reg == NULL) {
360 struct regulator *vdds_dsi;
362 vdds_dsi = dss_get_vdds_dsi();
364 if (IS_ERR(vdds_dsi)) {
365 DSSERR("can't get VDDS_DSI regulator\n");
366 return PTR_ERR(vdds_dsi);
369 dpi.vdds_dsi_reg = vdds_dsi;
372 if (dpi_use_dsi_pll(dssdev)) {
373 enum omap_dss_clk_source dispc_fclk_src =
374 dssdev->clocks.dispc.dispc_fclk_src;
375 dpi.dsidev = dpi_get_dsidev(dispc_fclk_src);