2 * linux/drivers/video/omap2/dss/dsi.c
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #define DSS_SUBSYS_NAME "DSI"
22 #include <linux/kernel.h>
24 #include <linux/clk.h>
25 #include <linux/device.h>
26 #include <linux/err.h>
27 #include <linux/interrupt.h>
28 #include <linux/delay.h>
29 #include <linux/mutex.h>
30 #include <linux/module.h>
31 #include <linux/semaphore.h>
32 #include <linux/seq_file.h>
33 #include <linux/platform_device.h>
34 #include <linux/regulator/consumer.h>
35 #include <linux/wait.h>
36 #include <linux/workqueue.h>
37 #include <linux/sched.h>
38 #include <linux/slab.h>
39 #include <linux/debugfs.h>
40 #include <linux/pm_runtime.h>
42 #include <video/omapdss.h>
43 #include <video/mipi_display.h>
44 #include <plat/clock.h>
47 #include "dss_features.h"
49 /*#define VERBOSE_IRQ*/
50 #define DSI_CATCH_MISSING_TE
52 struct dsi_reg { u16 idx; };
54 #define DSI_REG(idx) ((const struct dsi_reg) { idx })
56 #define DSI_SZ_REGS SZ_1K
57 /* DSI Protocol Engine */
59 #define DSI_REVISION DSI_REG(0x0000)
60 #define DSI_SYSCONFIG DSI_REG(0x0010)
61 #define DSI_SYSSTATUS DSI_REG(0x0014)
62 #define DSI_IRQSTATUS DSI_REG(0x0018)
63 #define DSI_IRQENABLE DSI_REG(0x001C)
64 #define DSI_CTRL DSI_REG(0x0040)
65 #define DSI_GNQ DSI_REG(0x0044)
66 #define DSI_COMPLEXIO_CFG1 DSI_REG(0x0048)
67 #define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(0x004C)
68 #define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(0x0050)
69 #define DSI_CLK_CTRL DSI_REG(0x0054)
70 #define DSI_TIMING1 DSI_REG(0x0058)
71 #define DSI_TIMING2 DSI_REG(0x005C)
72 #define DSI_VM_TIMING1 DSI_REG(0x0060)
73 #define DSI_VM_TIMING2 DSI_REG(0x0064)
74 #define DSI_VM_TIMING3 DSI_REG(0x0068)
75 #define DSI_CLK_TIMING DSI_REG(0x006C)
76 #define DSI_TX_FIFO_VC_SIZE DSI_REG(0x0070)
77 #define DSI_RX_FIFO_VC_SIZE DSI_REG(0x0074)
78 #define DSI_COMPLEXIO_CFG2 DSI_REG(0x0078)
79 #define DSI_RX_FIFO_VC_FULLNESS DSI_REG(0x007C)
80 #define DSI_VM_TIMING4 DSI_REG(0x0080)
81 #define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(0x0084)
82 #define DSI_VM_TIMING5 DSI_REG(0x0088)
83 #define DSI_VM_TIMING6 DSI_REG(0x008C)
84 #define DSI_VM_TIMING7 DSI_REG(0x0090)
85 #define DSI_STOPCLK_TIMING DSI_REG(0x0094)
86 #define DSI_VC_CTRL(n) DSI_REG(0x0100 + (n * 0x20))
87 #define DSI_VC_TE(n) DSI_REG(0x0104 + (n * 0x20))
88 #define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(0x0108 + (n * 0x20))
89 #define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(0x010C + (n * 0x20))
90 #define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(0x0110 + (n * 0x20))
91 #define DSI_VC_IRQSTATUS(n) DSI_REG(0x0118 + (n * 0x20))
92 #define DSI_VC_IRQENABLE(n) DSI_REG(0x011C + (n * 0x20))
96 #define DSI_DSIPHY_CFG0 DSI_REG(0x200 + 0x0000)
97 #define DSI_DSIPHY_CFG1 DSI_REG(0x200 + 0x0004)
98 #define DSI_DSIPHY_CFG2 DSI_REG(0x200 + 0x0008)
99 #define DSI_DSIPHY_CFG5 DSI_REG(0x200 + 0x0014)
100 #define DSI_DSIPHY_CFG10 DSI_REG(0x200 + 0x0028)
102 /* DSI_PLL_CTRL_SCP */
104 #define DSI_PLL_CONTROL DSI_REG(0x300 + 0x0000)
105 #define DSI_PLL_STATUS DSI_REG(0x300 + 0x0004)
106 #define DSI_PLL_GO DSI_REG(0x300 + 0x0008)
107 #define DSI_PLL_CONFIGURATION1 DSI_REG(0x300 + 0x000C)
108 #define DSI_PLL_CONFIGURATION2 DSI_REG(0x300 + 0x0010)
110 #define REG_GET(dsidev, idx, start, end) \
111 FLD_GET(dsi_read_reg(dsidev, idx), start, end)
113 #define REG_FLD_MOD(dsidev, idx, val, start, end) \
114 dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end))
116 /* Global interrupts */
117 #define DSI_IRQ_VC0 (1 << 0)
118 #define DSI_IRQ_VC1 (1 << 1)
119 #define DSI_IRQ_VC2 (1 << 2)
120 #define DSI_IRQ_VC3 (1 << 3)
121 #define DSI_IRQ_WAKEUP (1 << 4)
122 #define DSI_IRQ_RESYNC (1 << 5)
123 #define DSI_IRQ_PLL_LOCK (1 << 7)
124 #define DSI_IRQ_PLL_UNLOCK (1 << 8)
125 #define DSI_IRQ_PLL_RECALL (1 << 9)
126 #define DSI_IRQ_COMPLEXIO_ERR (1 << 10)
127 #define DSI_IRQ_HS_TX_TIMEOUT (1 << 14)
128 #define DSI_IRQ_LP_RX_TIMEOUT (1 << 15)
129 #define DSI_IRQ_TE_TRIGGER (1 << 16)
130 #define DSI_IRQ_ACK_TRIGGER (1 << 17)
131 #define DSI_IRQ_SYNC_LOST (1 << 18)
132 #define DSI_IRQ_LDO_POWER_GOOD (1 << 19)
133 #define DSI_IRQ_TA_TIMEOUT (1 << 20)
134 #define DSI_IRQ_ERROR_MASK \
135 (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
136 DSI_IRQ_TA_TIMEOUT | DSI_IRQ_SYNC_LOST)
137 #define DSI_IRQ_CHANNEL_MASK 0xf
139 /* Virtual channel interrupts */
140 #define DSI_VC_IRQ_CS (1 << 0)
141 #define DSI_VC_IRQ_ECC_CORR (1 << 1)
142 #define DSI_VC_IRQ_PACKET_SENT (1 << 2)
143 #define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3)
144 #define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4)
145 #define DSI_VC_IRQ_BTA (1 << 5)
146 #define DSI_VC_IRQ_ECC_NO_CORR (1 << 6)
147 #define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7)
148 #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
149 #define DSI_VC_IRQ_ERROR_MASK \
150 (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
151 DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
152 DSI_VC_IRQ_FIFO_TX_UDF)
154 /* ComplexIO interrupts */
155 #define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0)
156 #define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1)
157 #define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2)
158 #define DSI_CIO_IRQ_ERRSYNCESC4 (1 << 3)
159 #define DSI_CIO_IRQ_ERRSYNCESC5 (1 << 4)
160 #define DSI_CIO_IRQ_ERRESC1 (1 << 5)
161 #define DSI_CIO_IRQ_ERRESC2 (1 << 6)
162 #define DSI_CIO_IRQ_ERRESC3 (1 << 7)
163 #define DSI_CIO_IRQ_ERRESC4 (1 << 8)
164 #define DSI_CIO_IRQ_ERRESC5 (1 << 9)
165 #define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10)
166 #define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11)
167 #define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12)
168 #define DSI_CIO_IRQ_ERRCONTROL4 (1 << 13)
169 #define DSI_CIO_IRQ_ERRCONTROL5 (1 << 14)
170 #define DSI_CIO_IRQ_STATEULPS1 (1 << 15)
171 #define DSI_CIO_IRQ_STATEULPS2 (1 << 16)
172 #define DSI_CIO_IRQ_STATEULPS3 (1 << 17)
173 #define DSI_CIO_IRQ_STATEULPS4 (1 << 18)
174 #define DSI_CIO_IRQ_STATEULPS5 (1 << 19)
175 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20)
176 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21)
177 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22)
178 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23)
179 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24)
180 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25)
181 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_4 (1 << 26)
182 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_4 (1 << 27)
183 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_5 (1 << 28)
184 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_5 (1 << 29)
185 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30)
186 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31)
187 #define DSI_CIO_IRQ_ERROR_MASK \
188 (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \
189 DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \
190 DSI_CIO_IRQ_ERRSYNCESC5 | \
191 DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \
192 DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \
193 DSI_CIO_IRQ_ERRESC5 | \
194 DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \
195 DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \
196 DSI_CIO_IRQ_ERRCONTROL5 | \
197 DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \
198 DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \
199 DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \
200 DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \
201 DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5)
203 typedef void (*omap_dsi_isr_t) (void *arg, u32 mask);
205 #define DSI_MAX_NR_ISRS 2
206 #define DSI_MAX_NR_LANES 5
208 enum dsi_lane_function {
217 struct dsi_lane_config {
218 enum dsi_lane_function function;
222 struct dsi_isr_data {
230 DSI_FIFO_SIZE_32 = 1,
231 DSI_FIFO_SIZE_64 = 2,
232 DSI_FIFO_SIZE_96 = 3,
233 DSI_FIFO_SIZE_128 = 4,
237 DSI_VC_SOURCE_L4 = 0,
241 struct dsi_irq_stats {
242 unsigned long last_reset;
244 unsigned dsi_irqs[32];
245 unsigned vc_irqs[4][32];
246 unsigned cio_irqs[32];
249 struct dsi_isr_tables {
250 struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS];
251 struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS];
252 struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS];
256 struct platform_device *pdev;
264 int (*enable_pads)(int dsi_id, unsigned lane_mask);
265 void (*disable_pads)(int dsi_id, unsigned lane_mask);
267 struct dsi_clock_info current_cinfo;
269 bool vdds_dsi_enabled;
270 struct regulator *vdds_dsi_reg;
273 enum dsi_vc_source source;
274 struct omap_dss_device *dssdev;
275 enum fifo_size fifo_size;
280 struct semaphore bus_lock;
285 struct dsi_isr_tables isr_tables;
286 /* space for a copy used by the interrupt handler */
287 struct dsi_isr_tables isr_tables_copy;
291 unsigned update_bytes;
297 void (*framedone_callback)(int, void *);
298 void *framedone_data;
300 struct delayed_work framedone_timeout_work;
302 #ifdef DSI_CATCH_MISSING_TE
303 struct timer_list te_timer;
306 unsigned long cache_req_pck;
307 unsigned long cache_clk_freq;
308 struct dsi_clock_info cache_cinfo;
311 spinlock_t errors_lock;
313 ktime_t perf_setup_time;
314 ktime_t perf_start_time;
319 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
320 spinlock_t irq_stats_lock;
321 struct dsi_irq_stats irq_stats;
323 /* DSI PLL Parameter Ranges */
324 unsigned long regm_max, regn_max;
325 unsigned long regm_dispc_max, regm_dsi_max;
326 unsigned long fint_min, fint_max;
327 unsigned long lpdiv_max;
329 unsigned num_lanes_supported;
331 struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
332 unsigned num_lanes_used;
334 unsigned scp_clk_refcount;
337 struct dsi_packet_sent_handler_data {
338 struct platform_device *dsidev;
339 struct completion *completion;
342 static struct platform_device *dsi_pdev_map[MAX_NUM_DSI];
345 static bool dsi_perf;
346 module_param(dsi_perf, bool, 0644);
349 static inline struct dsi_data *dsi_get_dsidrv_data(struct platform_device *dsidev)
351 return dev_get_drvdata(&dsidev->dev);
354 static inline struct platform_device *dsi_get_dsidev_from_dssdev(struct omap_dss_device *dssdev)
356 return dsi_pdev_map[dssdev->phy.dsi.module];
359 struct platform_device *dsi_get_dsidev_from_id(int module)
361 return dsi_pdev_map[module];
364 static inline int dsi_get_dsidev_id(struct platform_device *dsidev)
369 static inline void dsi_write_reg(struct platform_device *dsidev,
370 const struct dsi_reg idx, u32 val)
372 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
374 __raw_writel(val, dsi->base + idx.idx);
377 static inline u32 dsi_read_reg(struct platform_device *dsidev,
378 const struct dsi_reg idx)
380 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
382 return __raw_readl(dsi->base + idx.idx);
385 void dsi_bus_lock(struct omap_dss_device *dssdev)
387 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
388 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
390 down(&dsi->bus_lock);
392 EXPORT_SYMBOL(dsi_bus_lock);
394 void dsi_bus_unlock(struct omap_dss_device *dssdev)
396 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
397 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
401 EXPORT_SYMBOL(dsi_bus_unlock);
403 static bool dsi_bus_is_locked(struct platform_device *dsidev)
405 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
407 return dsi->bus_lock.count == 0;
410 static void dsi_completion_handler(void *data, u32 mask)
412 complete((struct completion *)data);
415 static inline int wait_for_bit_change(struct platform_device *dsidev,
416 const struct dsi_reg idx, int bitnum, int value)
418 unsigned long timeout;
422 /* first busyloop to see if the bit changes right away */
425 if (REG_GET(dsidev, idx, bitnum, bitnum) == value)
429 /* then loop for 500ms, sleeping for 1ms in between */
430 timeout = jiffies + msecs_to_jiffies(500);
431 while (time_before(jiffies, timeout)) {
432 if (REG_GET(dsidev, idx, bitnum, bitnum) == value)
435 wait = ns_to_ktime(1000 * 1000);
436 set_current_state(TASK_UNINTERRUPTIBLE);
437 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
443 u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
446 case OMAP_DSS_DSI_FMT_RGB888:
447 case OMAP_DSS_DSI_FMT_RGB666:
449 case OMAP_DSS_DSI_FMT_RGB666_PACKED:
451 case OMAP_DSS_DSI_FMT_RGB565:
459 static void dsi_perf_mark_setup(struct platform_device *dsidev)
461 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
462 dsi->perf_setup_time = ktime_get();
465 static void dsi_perf_mark_start(struct platform_device *dsidev)
467 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
468 dsi->perf_start_time = ktime_get();
471 static void dsi_perf_show(struct platform_device *dsidev, const char *name)
473 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
474 ktime_t t, setup_time, trans_time;
476 u32 setup_us, trans_us, total_us;
483 setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time);
484 setup_us = (u32)ktime_to_us(setup_time);
488 trans_time = ktime_sub(t, dsi->perf_start_time);
489 trans_us = (u32)ktime_to_us(trans_time);
493 total_us = setup_us + trans_us;
495 total_bytes = dsi->update_bytes;
497 printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), "
498 "%u bytes, %u kbytes/sec\n",
503 1000*1000 / total_us,
505 total_bytes * 1000 / total_us);
508 static inline void dsi_perf_mark_setup(struct platform_device *dsidev)
512 static inline void dsi_perf_mark_start(struct platform_device *dsidev)
516 static inline void dsi_perf_show(struct platform_device *dsidev,
522 static void print_irq_status(u32 status)
528 if ((status & ~DSI_IRQ_CHANNEL_MASK) == 0)
531 printk(KERN_DEBUG "DSI IRQ: 0x%x: ", status);
534 if (status & DSI_IRQ_##x) \
560 static void print_irq_status_vc(int channel, u32 status)
566 if ((status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
569 printk(KERN_DEBUG "DSI VC(%d) IRQ 0x%x: ", channel, status);
572 if (status & DSI_VC_IRQ_##x) \
589 static void print_irq_status_cio(u32 status)
594 printk(KERN_DEBUG "DSI CIO IRQ 0x%x: ", status);
597 if (status & DSI_CIO_IRQ_##x) \
611 PIS(ERRCONTENTIONLP0_1);
612 PIS(ERRCONTENTIONLP1_1);
613 PIS(ERRCONTENTIONLP0_2);
614 PIS(ERRCONTENTIONLP1_2);
615 PIS(ERRCONTENTIONLP0_3);
616 PIS(ERRCONTENTIONLP1_3);
617 PIS(ULPSACTIVENOT_ALL0);
618 PIS(ULPSACTIVENOT_ALL1);
624 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
625 static void dsi_collect_irq_stats(struct platform_device *dsidev, u32 irqstatus,
626 u32 *vcstatus, u32 ciostatus)
628 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
631 spin_lock(&dsi->irq_stats_lock);
633 dsi->irq_stats.irq_count++;
634 dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs);
636 for (i = 0; i < 4; ++i)
637 dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]);
639 dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs);
641 spin_unlock(&dsi->irq_stats_lock);
644 #define dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus)
647 static int debug_irq;
649 static void dsi_handle_irq_errors(struct platform_device *dsidev, u32 irqstatus,
650 u32 *vcstatus, u32 ciostatus)
652 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
655 if (irqstatus & DSI_IRQ_ERROR_MASK) {
656 DSSERR("DSI error, irqstatus %x\n", irqstatus);
657 print_irq_status(irqstatus);
658 spin_lock(&dsi->errors_lock);
659 dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK;
660 spin_unlock(&dsi->errors_lock);
661 } else if (debug_irq) {
662 print_irq_status(irqstatus);
665 for (i = 0; i < 4; ++i) {
666 if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) {
667 DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
669 print_irq_status_vc(i, vcstatus[i]);
670 } else if (debug_irq) {
671 print_irq_status_vc(i, vcstatus[i]);
675 if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) {
676 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
677 print_irq_status_cio(ciostatus);
678 } else if (debug_irq) {
679 print_irq_status_cio(ciostatus);
683 static void dsi_call_isrs(struct dsi_isr_data *isr_array,
684 unsigned isr_array_size, u32 irqstatus)
686 struct dsi_isr_data *isr_data;
689 for (i = 0; i < isr_array_size; i++) {
690 isr_data = &isr_array[i];
691 if (isr_data->isr && isr_data->mask & irqstatus)
692 isr_data->isr(isr_data->arg, irqstatus);
696 static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables,
697 u32 irqstatus, u32 *vcstatus, u32 ciostatus)
701 dsi_call_isrs(isr_tables->isr_table,
702 ARRAY_SIZE(isr_tables->isr_table),
705 for (i = 0; i < 4; ++i) {
706 if (vcstatus[i] == 0)
708 dsi_call_isrs(isr_tables->isr_table_vc[i],
709 ARRAY_SIZE(isr_tables->isr_table_vc[i]),
714 dsi_call_isrs(isr_tables->isr_table_cio,
715 ARRAY_SIZE(isr_tables->isr_table_cio),
719 static irqreturn_t omap_dsi_irq_handler(int irq, void *arg)
721 struct platform_device *dsidev;
722 struct dsi_data *dsi;
723 u32 irqstatus, vcstatus[4], ciostatus;
726 dsidev = (struct platform_device *) arg;
727 dsi = dsi_get_dsidrv_data(dsidev);
729 spin_lock(&dsi->irq_lock);
731 irqstatus = dsi_read_reg(dsidev, DSI_IRQSTATUS);
733 /* IRQ is not for us */
735 spin_unlock(&dsi->irq_lock);
739 dsi_write_reg(dsidev, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
740 /* flush posted write */
741 dsi_read_reg(dsidev, DSI_IRQSTATUS);
743 for (i = 0; i < 4; ++i) {
744 if ((irqstatus & (1 << i)) == 0) {
749 vcstatus[i] = dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
751 dsi_write_reg(dsidev, DSI_VC_IRQSTATUS(i), vcstatus[i]);
752 /* flush posted write */
753 dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
756 if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
757 ciostatus = dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
759 dsi_write_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
760 /* flush posted write */
761 dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
766 #ifdef DSI_CATCH_MISSING_TE
767 if (irqstatus & DSI_IRQ_TE_TRIGGER)
768 del_timer(&dsi->te_timer);
771 /* make a copy and unlock, so that isrs can unregister
773 memcpy(&dsi->isr_tables_copy, &dsi->isr_tables,
774 sizeof(dsi->isr_tables));
776 spin_unlock(&dsi->irq_lock);
778 dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus);
780 dsi_handle_irq_errors(dsidev, irqstatus, vcstatus, ciostatus);
782 dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus);
787 /* dsi->irq_lock has to be locked by the caller */
788 static void _omap_dsi_configure_irqs(struct platform_device *dsidev,
789 struct dsi_isr_data *isr_array,
790 unsigned isr_array_size, u32 default_mask,
791 const struct dsi_reg enable_reg,
792 const struct dsi_reg status_reg)
794 struct dsi_isr_data *isr_data;
801 for (i = 0; i < isr_array_size; i++) {
802 isr_data = &isr_array[i];
804 if (isr_data->isr == NULL)
807 mask |= isr_data->mask;
810 old_mask = dsi_read_reg(dsidev, enable_reg);
811 /* clear the irqstatus for newly enabled irqs */
812 dsi_write_reg(dsidev, status_reg, (mask ^ old_mask) & mask);
813 dsi_write_reg(dsidev, enable_reg, mask);
815 /* flush posted writes */
816 dsi_read_reg(dsidev, enable_reg);
817 dsi_read_reg(dsidev, status_reg);
820 /* dsi->irq_lock has to be locked by the caller */
821 static void _omap_dsi_set_irqs(struct platform_device *dsidev)
823 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
824 u32 mask = DSI_IRQ_ERROR_MASK;
825 #ifdef DSI_CATCH_MISSING_TE
826 mask |= DSI_IRQ_TE_TRIGGER;
828 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table,
829 ARRAY_SIZE(dsi->isr_tables.isr_table), mask,
830 DSI_IRQENABLE, DSI_IRQSTATUS);
833 /* dsi->irq_lock has to be locked by the caller */
834 static void _omap_dsi_set_irqs_vc(struct platform_device *dsidev, int vc)
836 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
838 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_vc[vc],
839 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]),
840 DSI_VC_IRQ_ERROR_MASK,
841 DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc));
844 /* dsi->irq_lock has to be locked by the caller */
845 static void _omap_dsi_set_irqs_cio(struct platform_device *dsidev)
847 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
849 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_cio,
850 ARRAY_SIZE(dsi->isr_tables.isr_table_cio),
851 DSI_CIO_IRQ_ERROR_MASK,
852 DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS);
855 static void _dsi_initialize_irq(struct platform_device *dsidev)
857 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
861 spin_lock_irqsave(&dsi->irq_lock, flags);
863 memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables));
865 _omap_dsi_set_irqs(dsidev);
866 for (vc = 0; vc < 4; ++vc)
867 _omap_dsi_set_irqs_vc(dsidev, vc);
868 _omap_dsi_set_irqs_cio(dsidev);
870 spin_unlock_irqrestore(&dsi->irq_lock, flags);
873 static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
874 struct dsi_isr_data *isr_array, unsigned isr_array_size)
876 struct dsi_isr_data *isr_data;
882 /* check for duplicate entry and find a free slot */
884 for (i = 0; i < isr_array_size; i++) {
885 isr_data = &isr_array[i];
887 if (isr_data->isr == isr && isr_data->arg == arg &&
888 isr_data->mask == mask) {
892 if (isr_data->isr == NULL && free_idx == -1)
899 isr_data = &isr_array[free_idx];
902 isr_data->mask = mask;
907 static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
908 struct dsi_isr_data *isr_array, unsigned isr_array_size)
910 struct dsi_isr_data *isr_data;
913 for (i = 0; i < isr_array_size; i++) {
914 isr_data = &isr_array[i];
915 if (isr_data->isr != isr || isr_data->arg != arg ||
916 isr_data->mask != mask)
919 isr_data->isr = NULL;
920 isr_data->arg = NULL;
929 static int dsi_register_isr(struct platform_device *dsidev, omap_dsi_isr_t isr,
932 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
936 spin_lock_irqsave(&dsi->irq_lock, flags);
938 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table,
939 ARRAY_SIZE(dsi->isr_tables.isr_table));
942 _omap_dsi_set_irqs(dsidev);
944 spin_unlock_irqrestore(&dsi->irq_lock, flags);
949 static int dsi_unregister_isr(struct platform_device *dsidev,
950 omap_dsi_isr_t isr, void *arg, u32 mask)
952 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
956 spin_lock_irqsave(&dsi->irq_lock, flags);
958 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table,
959 ARRAY_SIZE(dsi->isr_tables.isr_table));
962 _omap_dsi_set_irqs(dsidev);
964 spin_unlock_irqrestore(&dsi->irq_lock, flags);
969 static int dsi_register_isr_vc(struct platform_device *dsidev, int channel,
970 omap_dsi_isr_t isr, void *arg, u32 mask)
972 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
976 spin_lock_irqsave(&dsi->irq_lock, flags);
978 r = _dsi_register_isr(isr, arg, mask,
979 dsi->isr_tables.isr_table_vc[channel],
980 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
983 _omap_dsi_set_irqs_vc(dsidev, channel);
985 spin_unlock_irqrestore(&dsi->irq_lock, flags);
990 static int dsi_unregister_isr_vc(struct platform_device *dsidev, int channel,
991 omap_dsi_isr_t isr, void *arg, u32 mask)
993 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
997 spin_lock_irqsave(&dsi->irq_lock, flags);
999 r = _dsi_unregister_isr(isr, arg, mask,
1000 dsi->isr_tables.isr_table_vc[channel],
1001 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
1004 _omap_dsi_set_irqs_vc(dsidev, channel);
1006 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1011 static int dsi_register_isr_cio(struct platform_device *dsidev,
1012 omap_dsi_isr_t isr, void *arg, u32 mask)
1014 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1015 unsigned long flags;
1018 spin_lock_irqsave(&dsi->irq_lock, flags);
1020 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1021 ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1024 _omap_dsi_set_irqs_cio(dsidev);
1026 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1031 static int dsi_unregister_isr_cio(struct platform_device *dsidev,
1032 omap_dsi_isr_t isr, void *arg, u32 mask)
1034 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1035 unsigned long flags;
1038 spin_lock_irqsave(&dsi->irq_lock, flags);
1040 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1041 ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1044 _omap_dsi_set_irqs_cio(dsidev);
1046 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1051 static u32 dsi_get_errors(struct platform_device *dsidev)
1053 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1054 unsigned long flags;
1056 spin_lock_irqsave(&dsi->errors_lock, flags);
1059 spin_unlock_irqrestore(&dsi->errors_lock, flags);
1063 int dsi_runtime_get(struct platform_device *dsidev)
1066 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1068 DSSDBG("dsi_runtime_get\n");
1070 r = pm_runtime_get_sync(&dsi->pdev->dev);
1072 return r < 0 ? r : 0;
1075 void dsi_runtime_put(struct platform_device *dsidev)
1077 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1080 DSSDBG("dsi_runtime_put\n");
1082 r = pm_runtime_put_sync(&dsi->pdev->dev);
1086 /* source clock for DSI PLL. this could also be PCLKFREE */
1087 static inline void dsi_enable_pll_clock(struct platform_device *dsidev,
1090 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1093 clk_enable(dsi->sys_clk);
1095 clk_disable(dsi->sys_clk);
1097 if (enable && dsi->pll_locked) {
1098 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1)
1099 DSSERR("cannot lock PLL when enabling clocks\n");
1104 static void _dsi_print_reset_status(struct platform_device *dsidev)
1112 /* A dummy read using the SCP interface to any DSIPHY register is
1113 * required after DSIPHY reset to complete the reset of the DSI complex
1115 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
1117 printk(KERN_DEBUG "DSI resets: ");
1119 l = dsi_read_reg(dsidev, DSI_PLL_STATUS);
1120 printk("PLL (%d) ", FLD_GET(l, 0, 0));
1122 l = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1);
1123 printk("CIO (%d) ", FLD_GET(l, 29, 29));
1125 if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) {
1135 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
1136 printk("PHY (%x%x%x, %d, %d, %d)\n",
1142 FLD_GET(l, 31, 31));
1145 #define _dsi_print_reset_status(x)
1148 static inline int dsi_if_enable(struct platform_device *dsidev, bool enable)
1150 DSSDBG("dsi_if_enable(%d)\n", enable);
1152 enable = enable ? 1 : 0;
1153 REG_FLD_MOD(dsidev, DSI_CTRL, enable, 0, 0); /* IF_EN */
1155 if (wait_for_bit_change(dsidev, DSI_CTRL, 0, enable) != enable) {
1156 DSSERR("Failed to set dsi_if_enable to %d\n", enable);
1163 unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev)
1165 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1167 return dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk;
1170 static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct platform_device *dsidev)
1172 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1174 return dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk;
1177 static unsigned long dsi_get_txbyteclkhs(struct platform_device *dsidev)
1179 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1181 return dsi->current_cinfo.clkin4ddr / 16;
1184 static unsigned long dsi_fclk_rate(struct platform_device *dsidev)
1187 int dsi_module = dsi_get_dsidev_id(dsidev);
1188 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1190 if (dss_get_dsi_clk_source(dsi_module) == OMAP_DSS_CLK_SRC_FCK) {
1191 /* DSI FCLK source is DSS_CLK_FCK */
1192 r = clk_get_rate(dsi->dss_clk);
1194 /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */
1195 r = dsi_get_pll_hsdiv_dsi_rate(dsidev);
1201 static int dsi_set_lp_clk_divisor(struct omap_dss_device *dssdev)
1203 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
1204 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1205 unsigned long dsi_fclk;
1206 unsigned lp_clk_div;
1207 unsigned long lp_clk;
1209 lp_clk_div = dssdev->clocks.dsi.lp_clk_div;
1211 if (lp_clk_div == 0 || lp_clk_div > dsi->lpdiv_max)
1214 dsi_fclk = dsi_fclk_rate(dsidev);
1216 lp_clk = dsi_fclk / 2 / lp_clk_div;
1218 DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk);
1219 dsi->current_cinfo.lp_clk = lp_clk;
1220 dsi->current_cinfo.lp_clk_div = lp_clk_div;
1222 /* LP_CLK_DIVISOR */
1223 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, lp_clk_div, 12, 0);
1225 /* LP_RX_SYNCHRO_ENABLE */
1226 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21);
1231 static void dsi_enable_scp_clk(struct platform_device *dsidev)
1233 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1235 if (dsi->scp_clk_refcount++ == 0)
1236 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */
1239 static void dsi_disable_scp_clk(struct platform_device *dsidev)
1241 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1243 WARN_ON(dsi->scp_clk_refcount == 0);
1244 if (--dsi->scp_clk_refcount == 0)
1245 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */
1248 enum dsi_pll_power_state {
1249 DSI_PLL_POWER_OFF = 0x0,
1250 DSI_PLL_POWER_ON_HSCLK = 0x1,
1251 DSI_PLL_POWER_ON_ALL = 0x2,
1252 DSI_PLL_POWER_ON_DIV = 0x3,
1255 static int dsi_pll_power(struct platform_device *dsidev,
1256 enum dsi_pll_power_state state)
1260 /* DSI-PLL power command 0x3 is not working */
1261 if (dss_has_feature(FEAT_DSI_PLL_PWR_BUG) &&
1262 state == DSI_PLL_POWER_ON_DIV)
1263 state = DSI_PLL_POWER_ON_ALL;
1266 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, state, 31, 30);
1268 /* PLL_PWR_STATUS */
1269 while (FLD_GET(dsi_read_reg(dsidev, DSI_CLK_CTRL), 29, 28) != state) {
1271 DSSERR("Failed to set DSI PLL power mode to %d\n",
1281 /* calculate clock rates using dividers in cinfo */
1282 static int dsi_calc_clock_rates(struct platform_device *dsidev,
1283 struct dsi_clock_info *cinfo)
1285 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1287 if (cinfo->regn == 0 || cinfo->regn > dsi->regn_max)
1290 if (cinfo->regm == 0 || cinfo->regm > dsi->regm_max)
1293 if (cinfo->regm_dispc > dsi->regm_dispc_max)
1296 if (cinfo->regm_dsi > dsi->regm_dsi_max)
1299 cinfo->clkin = clk_get_rate(dsi->sys_clk);
1300 cinfo->fint = cinfo->clkin / cinfo->regn;
1302 if (cinfo->fint > dsi->fint_max || cinfo->fint < dsi->fint_min)
1305 cinfo->clkin4ddr = 2 * cinfo->regm * cinfo->fint;
1307 if (cinfo->clkin4ddr > 1800 * 1000 * 1000)
1310 if (cinfo->regm_dispc > 0)
1311 cinfo->dsi_pll_hsdiv_dispc_clk =
1312 cinfo->clkin4ddr / cinfo->regm_dispc;
1314 cinfo->dsi_pll_hsdiv_dispc_clk = 0;
1316 if (cinfo->regm_dsi > 0)
1317 cinfo->dsi_pll_hsdiv_dsi_clk =
1318 cinfo->clkin4ddr / cinfo->regm_dsi;
1320 cinfo->dsi_pll_hsdiv_dsi_clk = 0;
1325 int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev, bool is_tft,
1326 unsigned long req_pck, struct dsi_clock_info *dsi_cinfo,
1327 struct dispc_clock_info *dispc_cinfo)
1329 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1330 struct dsi_clock_info cur, best;
1331 struct dispc_clock_info best_dispc;
1332 int min_fck_per_pck;
1334 unsigned long dss_sys_clk, max_dss_fck;
1336 dss_sys_clk = clk_get_rate(dsi->sys_clk);
1338 max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
1340 if (req_pck == dsi->cache_req_pck &&
1341 dsi->cache_cinfo.clkin == dss_sys_clk) {
1342 DSSDBG("DSI clock info found from cache\n");
1343 *dsi_cinfo = dsi->cache_cinfo;
1344 dispc_find_clk_divs(is_tft, req_pck,
1345 dsi_cinfo->dsi_pll_hsdiv_dispc_clk, dispc_cinfo);
1349 min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
1351 if (min_fck_per_pck &&
1352 req_pck * min_fck_per_pck > max_dss_fck) {
1353 DSSERR("Requested pixel clock not possible with the current "
1354 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
1355 "the constraint off.\n");
1356 min_fck_per_pck = 0;
1359 DSSDBG("dsi_pll_calc\n");
1362 memset(&best, 0, sizeof(best));
1363 memset(&best_dispc, 0, sizeof(best_dispc));
1365 memset(&cur, 0, sizeof(cur));
1366 cur.clkin = dss_sys_clk;
1368 /* 0.75MHz < Fint = clkin / regn < 2.1MHz */
1369 /* To reduce PLL lock time, keep Fint high (around 2 MHz) */
1370 for (cur.regn = 1; cur.regn < dsi->regn_max; ++cur.regn) {
1371 cur.fint = cur.clkin / cur.regn;
1373 if (cur.fint > dsi->fint_max || cur.fint < dsi->fint_min)
1376 /* DSIPHY(MHz) = (2 * regm / regn) * clkin */
1377 for (cur.regm = 1; cur.regm < dsi->regm_max; ++cur.regm) {
1380 a = 2 * cur.regm * (cur.clkin/1000);
1382 cur.clkin4ddr = a / b * 1000;
1384 if (cur.clkin4ddr > 1800 * 1000 * 1000)
1387 /* dsi_pll_hsdiv_dispc_clk(MHz) =
1388 * DSIPHY(MHz) / regm_dispc < 173MHz/186Mhz */
1389 for (cur.regm_dispc = 1; cur.regm_dispc <
1390 dsi->regm_dispc_max; ++cur.regm_dispc) {
1391 struct dispc_clock_info cur_dispc;
1392 cur.dsi_pll_hsdiv_dispc_clk =
1393 cur.clkin4ddr / cur.regm_dispc;
1395 /* this will narrow down the search a bit,
1396 * but still give pixclocks below what was
1398 if (cur.dsi_pll_hsdiv_dispc_clk < req_pck)
1401 if (cur.dsi_pll_hsdiv_dispc_clk > max_dss_fck)
1404 if (min_fck_per_pck &&
1405 cur.dsi_pll_hsdiv_dispc_clk <
1406 req_pck * min_fck_per_pck)
1411 dispc_find_clk_divs(is_tft, req_pck,
1412 cur.dsi_pll_hsdiv_dispc_clk,
1415 if (abs(cur_dispc.pck - req_pck) <
1416 abs(best_dispc.pck - req_pck)) {
1418 best_dispc = cur_dispc;
1420 if (cur_dispc.pck == req_pck)
1428 if (min_fck_per_pck) {
1429 DSSERR("Could not find suitable clock settings.\n"
1430 "Turning FCK/PCK constraint off and"
1432 min_fck_per_pck = 0;
1436 DSSERR("Could not find suitable clock settings.\n");
1441 /* dsi_pll_hsdiv_dsi_clk (regm_dsi) is not used */
1443 best.dsi_pll_hsdiv_dsi_clk = 0;
1448 *dispc_cinfo = best_dispc;
1450 dsi->cache_req_pck = req_pck;
1451 dsi->cache_clk_freq = 0;
1452 dsi->cache_cinfo = best;
1457 int dsi_pll_set_clock_div(struct platform_device *dsidev,
1458 struct dsi_clock_info *cinfo)
1460 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1464 u8 regn_start, regn_end, regm_start, regm_end;
1465 u8 regm_dispc_start, regm_dispc_end, regm_dsi_start, regm_dsi_end;
1469 dsi->current_cinfo.clkin = cinfo->clkin;
1470 dsi->current_cinfo.fint = cinfo->fint;
1471 dsi->current_cinfo.clkin4ddr = cinfo->clkin4ddr;
1472 dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk =
1473 cinfo->dsi_pll_hsdiv_dispc_clk;
1474 dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk =
1475 cinfo->dsi_pll_hsdiv_dsi_clk;
1477 dsi->current_cinfo.regn = cinfo->regn;
1478 dsi->current_cinfo.regm = cinfo->regm;
1479 dsi->current_cinfo.regm_dispc = cinfo->regm_dispc;
1480 dsi->current_cinfo.regm_dsi = cinfo->regm_dsi;
1482 DSSDBG("DSI Fint %ld\n", cinfo->fint);
1484 DSSDBG("clkin rate %ld\n", cinfo->clkin);
1486 /* DSIPHY == CLKIN4DDR */
1487 DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu = %lu\n",
1493 DSSDBG("Data rate on 1 DSI lane %ld Mbps\n",
1494 cinfo->clkin4ddr / 1000 / 1000 / 2);
1496 DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4);
1498 DSSDBG("regm_dispc = %d, %s (%s) = %lu\n", cinfo->regm_dispc,
1499 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
1500 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
1501 cinfo->dsi_pll_hsdiv_dispc_clk);
1502 DSSDBG("regm_dsi = %d, %s (%s) = %lu\n", cinfo->regm_dsi,
1503 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
1504 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
1505 cinfo->dsi_pll_hsdiv_dsi_clk);
1507 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGN, ®n_start, ®n_end);
1508 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM, ®m_start, ®m_end);
1509 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DISPC, ®m_dispc_start,
1511 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DSI, ®m_dsi_start,
1514 /* DSI_PLL_AUTOMODE = manual */
1515 REG_FLD_MOD(dsidev, DSI_PLL_CONTROL, 0, 0, 0);
1517 l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION1);
1518 l = FLD_MOD(l, 1, 0, 0); /* DSI_PLL_STOPMODE */
1520 l = FLD_MOD(l, cinfo->regn - 1, regn_start, regn_end);
1522 l = FLD_MOD(l, cinfo->regm, regm_start, regm_end);
1524 l = FLD_MOD(l, cinfo->regm_dispc > 0 ? cinfo->regm_dispc - 1 : 0,
1525 regm_dispc_start, regm_dispc_end);
1526 /* DSIPROTO_CLOCK_DIV */
1527 l = FLD_MOD(l, cinfo->regm_dsi > 0 ? cinfo->regm_dsi - 1 : 0,
1528 regm_dsi_start, regm_dsi_end);
1529 dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION1, l);
1531 BUG_ON(cinfo->fint < dsi->fint_min || cinfo->fint > dsi->fint_max);
1533 if (dss_has_feature(FEAT_DSI_PLL_FREQSEL)) {
1534 f = cinfo->fint < 1000000 ? 0x3 :
1535 cinfo->fint < 1250000 ? 0x4 :
1536 cinfo->fint < 1500000 ? 0x5 :
1537 cinfo->fint < 1750000 ? 0x6 :
1541 l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2);
1543 if (dss_has_feature(FEAT_DSI_PLL_FREQSEL))
1544 l = FLD_MOD(l, f, 4, 1); /* DSI_PLL_FREQSEL */
1545 l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
1546 l = FLD_MOD(l, 0, 14, 14); /* DSIPHY_CLKINEN */
1547 l = FLD_MOD(l, 1, 20, 20); /* DSI_HSDIVBYPASS */
1548 dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l);
1550 REG_FLD_MOD(dsidev, DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */
1552 if (wait_for_bit_change(dsidev, DSI_PLL_GO, 0, 0) != 0) {
1553 DSSERR("dsi pll go bit not going down.\n");
1558 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1) {
1559 DSSERR("cannot lock PLL\n");
1564 dsi->pll_locked = 1;
1566 l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2);
1567 l = FLD_MOD(l, 0, 0, 0); /* DSI_PLL_IDLE */
1568 l = FLD_MOD(l, 0, 5, 5); /* DSI_PLL_PLLLPMODE */
1569 l = FLD_MOD(l, 0, 6, 6); /* DSI_PLL_LOWCURRSTBY */
1570 l = FLD_MOD(l, 0, 7, 7); /* DSI_PLL_TIGHTPHASELOCK */
1571 l = FLD_MOD(l, 0, 8, 8); /* DSI_PLL_DRIFTGUARDEN */
1572 l = FLD_MOD(l, 0, 10, 9); /* DSI_PLL_LOCKSEL */
1573 l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
1574 l = FLD_MOD(l, 1, 14, 14); /* DSIPHY_CLKINEN */
1575 l = FLD_MOD(l, 0, 15, 15); /* DSI_BYPASSEN */
1576 l = FLD_MOD(l, 1, 16, 16); /* DSS_CLOCK_EN */
1577 l = FLD_MOD(l, 0, 17, 17); /* DSS_CLOCK_PWDN */
1578 l = FLD_MOD(l, 1, 18, 18); /* DSI_PROTO_CLOCK_EN */
1579 l = FLD_MOD(l, 0, 19, 19); /* DSI_PROTO_CLOCK_PWDN */
1580 l = FLD_MOD(l, 0, 20, 20); /* DSI_HSDIVBYPASS */
1581 dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l);
1583 DSSDBG("PLL config done\n");
1588 int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk,
1591 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1593 enum dsi_pll_power_state pwstate;
1595 DSSDBG("PLL init\n");
1597 if (dsi->vdds_dsi_reg == NULL) {
1598 struct regulator *vdds_dsi;
1600 vdds_dsi = regulator_get(&dsi->pdev->dev, "vdds_dsi");
1602 if (IS_ERR(vdds_dsi)) {
1603 DSSERR("can't get VDDS_DSI regulator\n");
1604 return PTR_ERR(vdds_dsi);
1607 dsi->vdds_dsi_reg = vdds_dsi;
1610 dsi_enable_pll_clock(dsidev, 1);
1612 * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4.
1614 dsi_enable_scp_clk(dsidev);
1616 if (!dsi->vdds_dsi_enabled) {
1617 r = regulator_enable(dsi->vdds_dsi_reg);
1620 dsi->vdds_dsi_enabled = true;
1623 /* XXX PLL does not come out of reset without this... */
1624 dispc_pck_free_enable(1);
1626 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 0, 1) != 1) {
1627 DSSERR("PLL not coming out of reset.\n");
1629 dispc_pck_free_enable(0);
1633 /* XXX ... but if left on, we get problems when planes do not
1634 * fill the whole display. No idea about this */
1635 dispc_pck_free_enable(0);
1637 if (enable_hsclk && enable_hsdiv)
1638 pwstate = DSI_PLL_POWER_ON_ALL;
1639 else if (enable_hsclk)
1640 pwstate = DSI_PLL_POWER_ON_HSCLK;
1641 else if (enable_hsdiv)
1642 pwstate = DSI_PLL_POWER_ON_DIV;
1644 pwstate = DSI_PLL_POWER_OFF;
1646 r = dsi_pll_power(dsidev, pwstate);
1651 DSSDBG("PLL init done\n");
1655 if (dsi->vdds_dsi_enabled) {
1656 regulator_disable(dsi->vdds_dsi_reg);
1657 dsi->vdds_dsi_enabled = false;
1660 dsi_disable_scp_clk(dsidev);
1661 dsi_enable_pll_clock(dsidev, 0);
1665 void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes)
1667 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1669 dsi->pll_locked = 0;
1670 dsi_pll_power(dsidev, DSI_PLL_POWER_OFF);
1671 if (disconnect_lanes) {
1672 WARN_ON(!dsi->vdds_dsi_enabled);
1673 regulator_disable(dsi->vdds_dsi_reg);
1674 dsi->vdds_dsi_enabled = false;
1677 dsi_disable_scp_clk(dsidev);
1678 dsi_enable_pll_clock(dsidev, 0);
1680 DSSDBG("PLL uninit done\n");
1683 static void dsi_dump_dsidev_clocks(struct platform_device *dsidev,
1686 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1687 struct dsi_clock_info *cinfo = &dsi->current_cinfo;
1688 enum omap_dss_clk_source dispc_clk_src, dsi_clk_src;
1689 int dsi_module = dsi_get_dsidev_id(dsidev);
1691 dispc_clk_src = dss_get_dispc_clk_source();
1692 dsi_clk_src = dss_get_dsi_clk_source(dsi_module);
1694 if (dsi_runtime_get(dsidev))
1697 seq_printf(s, "- DSI%d PLL -\n", dsi_module + 1);
1699 seq_printf(s, "dsi pll clkin\t%lu\n", cinfo->clkin);
1701 seq_printf(s, "Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn);
1703 seq_printf(s, "CLKIN4DDR\t%-16luregm %u\n",
1704 cinfo->clkin4ddr, cinfo->regm);
1706 seq_printf(s, "DSI_PLL_HSDIV_DISPC (%s)\t%-16luregm_dispc %u\t(%s)\n",
1707 dss_feat_get_clk_source_name(dsi_module == 0 ?
1708 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC :
1709 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC),
1710 cinfo->dsi_pll_hsdiv_dispc_clk,
1712 dispc_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1715 seq_printf(s, "DSI_PLL_HSDIV_DSI (%s)\t%-16luregm_dsi %u\t(%s)\n",
1716 dss_feat_get_clk_source_name(dsi_module == 0 ?
1717 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI :
1718 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI),
1719 cinfo->dsi_pll_hsdiv_dsi_clk,
1721 dsi_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1724 seq_printf(s, "- DSI%d -\n", dsi_module + 1);
1726 seq_printf(s, "dsi fclk source = %s (%s)\n",
1727 dss_get_generic_clk_source_name(dsi_clk_src),
1728 dss_feat_get_clk_source_name(dsi_clk_src));
1730 seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsidev));
1732 seq_printf(s, "DDR_CLK\t\t%lu\n",
1733 cinfo->clkin4ddr / 4);
1735 seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsidev));
1737 seq_printf(s, "LP_CLK\t\t%lu\n", cinfo->lp_clk);
1739 dsi_runtime_put(dsidev);
1742 void dsi_dump_clocks(struct seq_file *s)
1744 struct platform_device *dsidev;
1747 for (i = 0; i < MAX_NUM_DSI; i++) {
1748 dsidev = dsi_get_dsidev_from_id(i);
1750 dsi_dump_dsidev_clocks(dsidev, s);
1754 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
1755 static void dsi_dump_dsidev_irqs(struct platform_device *dsidev,
1758 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1759 unsigned long flags;
1760 struct dsi_irq_stats stats;
1761 int dsi_module = dsi_get_dsidev_id(dsidev);
1763 spin_lock_irqsave(&dsi->irq_stats_lock, flags);
1765 stats = dsi->irq_stats;
1766 memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats));
1767 dsi->irq_stats.last_reset = jiffies;
1769 spin_unlock_irqrestore(&dsi->irq_stats_lock, flags);
1771 seq_printf(s, "period %u ms\n",
1772 jiffies_to_msecs(jiffies - stats.last_reset));
1774 seq_printf(s, "irqs %d\n", stats.irq_count);
1776 seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]);
1778 seq_printf(s, "-- DSI%d interrupts --\n", dsi_module + 1);
1794 PIS(LDO_POWER_GOOD);
1799 seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
1800 stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
1801 stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
1802 stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
1803 stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);
1805 seq_printf(s, "-- VC interrupts --\n");
1814 PIS(PP_BUSY_CHANGE);
1818 seq_printf(s, "%-20s %10d\n", #x, \
1819 stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);
1821 seq_printf(s, "-- CIO interrupts --\n");
1834 PIS(ERRCONTENTIONLP0_1);
1835 PIS(ERRCONTENTIONLP1_1);
1836 PIS(ERRCONTENTIONLP0_2);
1837 PIS(ERRCONTENTIONLP1_2);
1838 PIS(ERRCONTENTIONLP0_3);
1839 PIS(ERRCONTENTIONLP1_3);
1840 PIS(ULPSACTIVENOT_ALL0);
1841 PIS(ULPSACTIVENOT_ALL1);
1845 static void dsi1_dump_irqs(struct seq_file *s)
1847 struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
1849 dsi_dump_dsidev_irqs(dsidev, s);
1852 static void dsi2_dump_irqs(struct seq_file *s)
1854 struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
1856 dsi_dump_dsidev_irqs(dsidev, s);
1859 void dsi_create_debugfs_files_irq(struct dentry *debugfs_dir,
1860 const struct file_operations *debug_fops)
1862 struct platform_device *dsidev;
1864 dsidev = dsi_get_dsidev_from_id(0);
1866 debugfs_create_file("dsi1_irqs", S_IRUGO, debugfs_dir,
1867 &dsi1_dump_irqs, debug_fops);
1869 dsidev = dsi_get_dsidev_from_id(1);
1871 debugfs_create_file("dsi2_irqs", S_IRUGO, debugfs_dir,
1872 &dsi2_dump_irqs, debug_fops);
1876 static void dsi_dump_dsidev_regs(struct platform_device *dsidev,
1879 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsidev, r))
1881 if (dsi_runtime_get(dsidev))
1883 dsi_enable_scp_clk(dsidev);
1885 DUMPREG(DSI_REVISION);
1886 DUMPREG(DSI_SYSCONFIG);
1887 DUMPREG(DSI_SYSSTATUS);
1888 DUMPREG(DSI_IRQSTATUS);
1889 DUMPREG(DSI_IRQENABLE);
1891 DUMPREG(DSI_COMPLEXIO_CFG1);
1892 DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
1893 DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
1894 DUMPREG(DSI_CLK_CTRL);
1895 DUMPREG(DSI_TIMING1);
1896 DUMPREG(DSI_TIMING2);
1897 DUMPREG(DSI_VM_TIMING1);
1898 DUMPREG(DSI_VM_TIMING2);
1899 DUMPREG(DSI_VM_TIMING3);
1900 DUMPREG(DSI_CLK_TIMING);
1901 DUMPREG(DSI_TX_FIFO_VC_SIZE);
1902 DUMPREG(DSI_RX_FIFO_VC_SIZE);
1903 DUMPREG(DSI_COMPLEXIO_CFG2);
1904 DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
1905 DUMPREG(DSI_VM_TIMING4);
1906 DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
1907 DUMPREG(DSI_VM_TIMING5);
1908 DUMPREG(DSI_VM_TIMING6);
1909 DUMPREG(DSI_VM_TIMING7);
1910 DUMPREG(DSI_STOPCLK_TIMING);
1912 DUMPREG(DSI_VC_CTRL(0));
1913 DUMPREG(DSI_VC_TE(0));
1914 DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
1915 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
1916 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
1917 DUMPREG(DSI_VC_IRQSTATUS(0));
1918 DUMPREG(DSI_VC_IRQENABLE(0));
1920 DUMPREG(DSI_VC_CTRL(1));
1921 DUMPREG(DSI_VC_TE(1));
1922 DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
1923 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
1924 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
1925 DUMPREG(DSI_VC_IRQSTATUS(1));
1926 DUMPREG(DSI_VC_IRQENABLE(1));
1928 DUMPREG(DSI_VC_CTRL(2));
1929 DUMPREG(DSI_VC_TE(2));
1930 DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
1931 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
1932 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
1933 DUMPREG(DSI_VC_IRQSTATUS(2));
1934 DUMPREG(DSI_VC_IRQENABLE(2));
1936 DUMPREG(DSI_VC_CTRL(3));
1937 DUMPREG(DSI_VC_TE(3));
1938 DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
1939 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
1940 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
1941 DUMPREG(DSI_VC_IRQSTATUS(3));
1942 DUMPREG(DSI_VC_IRQENABLE(3));
1944 DUMPREG(DSI_DSIPHY_CFG0);
1945 DUMPREG(DSI_DSIPHY_CFG1);
1946 DUMPREG(DSI_DSIPHY_CFG2);
1947 DUMPREG(DSI_DSIPHY_CFG5);
1949 DUMPREG(DSI_PLL_CONTROL);
1950 DUMPREG(DSI_PLL_STATUS);
1951 DUMPREG(DSI_PLL_GO);
1952 DUMPREG(DSI_PLL_CONFIGURATION1);
1953 DUMPREG(DSI_PLL_CONFIGURATION2);
1955 dsi_disable_scp_clk(dsidev);
1956 dsi_runtime_put(dsidev);
1960 static void dsi1_dump_regs(struct seq_file *s)
1962 struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
1964 dsi_dump_dsidev_regs(dsidev, s);
1967 static void dsi2_dump_regs(struct seq_file *s)
1969 struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
1971 dsi_dump_dsidev_regs(dsidev, s);
1974 void dsi_create_debugfs_files_reg(struct dentry *debugfs_dir,
1975 const struct file_operations *debug_fops)
1977 struct platform_device *dsidev;
1979 dsidev = dsi_get_dsidev_from_id(0);
1981 debugfs_create_file("dsi1_regs", S_IRUGO, debugfs_dir,
1982 &dsi1_dump_regs, debug_fops);
1984 dsidev = dsi_get_dsidev_from_id(1);
1986 debugfs_create_file("dsi2_regs", S_IRUGO, debugfs_dir,
1987 &dsi2_dump_regs, debug_fops);
1989 enum dsi_cio_power_state {
1990 DSI_COMPLEXIO_POWER_OFF = 0x0,
1991 DSI_COMPLEXIO_POWER_ON = 0x1,
1992 DSI_COMPLEXIO_POWER_ULPS = 0x2,
1995 static int dsi_cio_power(struct platform_device *dsidev,
1996 enum dsi_cio_power_state state)
2001 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG1, state, 28, 27);
2004 while (FLD_GET(dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1),
2007 DSSERR("failed to set complexio power state to "
2017 static unsigned dsi_get_line_buf_size(struct platform_device *dsidev)
2021 /* line buffer on OMAP3 is 1024 x 24bits */
2022 /* XXX: for some reason using full buffer size causes
2023 * considerable TX slowdown with update sizes that fill the
2025 if (!dss_has_feature(FEAT_DSI_GNQ))
2028 val = REG_GET(dsidev, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */
2032 return 512 * 3; /* 512x24 bits */
2034 return 682 * 3; /* 682x24 bits */
2036 return 853 * 3; /* 853x24 bits */
2038 return 1024 * 3; /* 1024x24 bits */
2040 return 1194 * 3; /* 1194x24 bits */
2042 return 1365 * 3; /* 1365x24 bits */
2048 static int dsi_parse_lane_config(struct omap_dss_device *dssdev)
2050 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2051 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2052 u8 lanes[DSI_MAX_NR_LANES];
2053 u8 polarities[DSI_MAX_NR_LANES];
2056 static const enum dsi_lane_function functions[] = {
2064 lanes[0] = dssdev->phy.dsi.clk_lane;
2065 lanes[1] = dssdev->phy.dsi.data1_lane;
2066 lanes[2] = dssdev->phy.dsi.data2_lane;
2067 lanes[3] = dssdev->phy.dsi.data3_lane;
2068 lanes[4] = dssdev->phy.dsi.data4_lane;
2069 polarities[0] = dssdev->phy.dsi.clk_pol;
2070 polarities[1] = dssdev->phy.dsi.data1_pol;
2071 polarities[2] = dssdev->phy.dsi.data2_pol;
2072 polarities[3] = dssdev->phy.dsi.data3_pol;
2073 polarities[4] = dssdev->phy.dsi.data4_pol;
2077 for (i = 0; i < dsi->num_lanes_supported; ++i)
2078 dsi->lanes[i].function = DSI_LANE_UNUSED;
2080 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2083 if (lanes[i] == DSI_LANE_UNUSED)
2088 if (num >= dsi->num_lanes_supported)
2091 if (dsi->lanes[num].function != DSI_LANE_UNUSED)
2094 dsi->lanes[num].function = functions[i];
2095 dsi->lanes[num].polarity = polarities[i];
2099 if (num_lanes < 2 || num_lanes > dsi->num_lanes_supported)
2102 dsi->num_lanes_used = num_lanes;
2107 static int dsi_set_lane_config(struct omap_dss_device *dssdev)
2109 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2110 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2111 static const u8 offsets[] = { 0, 4, 8, 12, 16 };
2112 static const enum dsi_lane_function functions[] = {
2122 r = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1);
2124 for (i = 0; i < dsi->num_lanes_used; ++i) {
2125 unsigned offset = offsets[i];
2126 unsigned polarity, lane_number;
2129 for (t = 0; t < dsi->num_lanes_supported; ++t)
2130 if (dsi->lanes[t].function == functions[i])
2133 if (t == dsi->num_lanes_supported)
2137 polarity = dsi->lanes[t].polarity;
2139 r = FLD_MOD(r, lane_number + 1, offset + 2, offset);
2140 r = FLD_MOD(r, polarity, offset + 3, offset + 3);
2143 /* clear the unused lanes */
2144 for (; i < dsi->num_lanes_supported; ++i) {
2145 unsigned offset = offsets[i];
2147 r = FLD_MOD(r, 0, offset + 2, offset);
2148 r = FLD_MOD(r, 0, offset + 3, offset + 3);
2151 dsi_write_reg(dsidev, DSI_COMPLEXIO_CFG1, r);
2156 static inline unsigned ns2ddr(struct platform_device *dsidev, unsigned ns)
2158 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2160 /* convert time in ns to ddr ticks, rounding up */
2161 unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4;
2162 return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000;
2165 static inline unsigned ddr2ns(struct platform_device *dsidev, unsigned ddr)
2167 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2169 unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4;
2170 return ddr * 1000 * 1000 / (ddr_clk / 1000);
2173 static void dsi_cio_timings(struct platform_device *dsidev)
2176 u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
2177 u32 tlpx_half, tclk_trail, tclk_zero;
2180 /* calculate timings */
2182 /* 1 * DDR_CLK = 2 * UI */
2184 /* min 40ns + 4*UI max 85ns + 6*UI */
2185 ths_prepare = ns2ddr(dsidev, 70) + 2;
2187 /* min 145ns + 10*UI */
2188 ths_prepare_ths_zero = ns2ddr(dsidev, 175) + 2;
2190 /* min max(8*UI, 60ns+4*UI) */
2191 ths_trail = ns2ddr(dsidev, 60) + 5;
2194 ths_exit = ns2ddr(dsidev, 145);
2197 tlpx_half = ns2ddr(dsidev, 25);
2200 tclk_trail = ns2ddr(dsidev, 60) + 2;
2202 /* min 38ns, max 95ns */
2203 tclk_prepare = ns2ddr(dsidev, 65);
2205 /* min tclk-prepare + tclk-zero = 300ns */
2206 tclk_zero = ns2ddr(dsidev, 260);
2208 DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
2209 ths_prepare, ddr2ns(dsidev, ths_prepare),
2210 ths_prepare_ths_zero, ddr2ns(dsidev, ths_prepare_ths_zero));
2211 DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
2212 ths_trail, ddr2ns(dsidev, ths_trail),
2213 ths_exit, ddr2ns(dsidev, ths_exit));
2215 DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
2216 "tclk_zero %u (%uns)\n",
2217 tlpx_half, ddr2ns(dsidev, tlpx_half),
2218 tclk_trail, ddr2ns(dsidev, tclk_trail),
2219 tclk_zero, ddr2ns(dsidev, tclk_zero));
2220 DSSDBG("tclk_prepare %u (%uns)\n",
2221 tclk_prepare, ddr2ns(dsidev, tclk_prepare));
2223 /* program timings */
2225 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
2226 r = FLD_MOD(r, ths_prepare, 31, 24);
2227 r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
2228 r = FLD_MOD(r, ths_trail, 15, 8);
2229 r = FLD_MOD(r, ths_exit, 7, 0);
2230 dsi_write_reg(dsidev, DSI_DSIPHY_CFG0, r);
2232 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
2233 r = FLD_MOD(r, tlpx_half, 22, 16);
2234 r = FLD_MOD(r, tclk_trail, 15, 8);
2235 r = FLD_MOD(r, tclk_zero, 7, 0);
2236 dsi_write_reg(dsidev, DSI_DSIPHY_CFG1, r);
2238 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
2239 r = FLD_MOD(r, tclk_prepare, 7, 0);
2240 dsi_write_reg(dsidev, DSI_DSIPHY_CFG2, r);
2243 /* lane masks have lane 0 at lsb. mask_p for positive lines, n for negative */
2244 static void dsi_cio_enable_lane_override(struct omap_dss_device *dssdev,
2245 unsigned mask_p, unsigned mask_n)
2247 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2248 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2251 u8 lptxscp_start = dsi->num_lanes_supported == 3 ? 22 : 26;
2255 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2256 unsigned p = dsi->lanes[i].polarity;
2258 if (mask_p & (1 << i))
2259 l |= 1 << (i * 2 + (p ? 0 : 1));
2261 if (mask_n & (1 << i))
2262 l |= 1 << (i * 2 + (p ? 1 : 0));
2266 * Bits in REGLPTXSCPDAT4TO0DXDY:
2274 /* Set the lane override configuration */
2276 /* REGLPTXSCPDAT4TO0DXDY */
2277 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, l, lptxscp_start, 17);
2279 /* Enable lane override */
2282 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 1, 27, 27);
2285 static void dsi_cio_disable_lane_override(struct platform_device *dsidev)
2287 /* Disable lane override */
2288 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */
2289 /* Reset the lane override configuration */
2290 /* REGLPTXSCPDAT4TO0DXDY */
2291 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 22, 17);
2294 static int dsi_cio_wait_tx_clk_esc_reset(struct omap_dss_device *dssdev)
2296 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2297 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2299 bool in_use[DSI_MAX_NR_LANES];
2300 static const u8 offsets_old[] = { 28, 27, 26 };
2301 static const u8 offsets_new[] = { 24, 25, 26, 27, 28 };
2304 if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC))
2305 offsets = offsets_old;
2307 offsets = offsets_new;
2309 for (i = 0; i < dsi->num_lanes_supported; ++i)
2310 in_use[i] = dsi->lanes[i].function != DSI_LANE_UNUSED;
2317 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2320 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2321 if (!in_use[i] || (l & (1 << offsets[i])))
2325 if (ok == dsi->num_lanes_supported)
2329 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2330 if (!in_use[i] || (l & (1 << offsets[i])))
2333 DSSERR("CIO TXCLKESC%d domain not coming " \
2334 "out of reset\n", i);
2343 /* return bitmask of enabled lanes, lane0 being the lsb */
2344 static unsigned dsi_get_lane_mask(struct omap_dss_device *dssdev)
2346 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2347 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2351 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2352 if (dsi->lanes[i].function != DSI_LANE_UNUSED)
2359 static int dsi_cio_init(struct omap_dss_device *dssdev)
2361 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2362 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2368 r = dsi->enable_pads(dsidev->id, dsi_get_lane_mask(dssdev));
2372 dsi_enable_scp_clk(dsidev);
2374 /* A dummy read using the SCP interface to any DSIPHY register is
2375 * required after DSIPHY reset to complete the reset of the DSI complex
2377 dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2379 if (wait_for_bit_change(dsidev, DSI_DSIPHY_CFG5, 30, 1) != 1) {
2380 DSSERR("CIO SCP Clock domain not coming out of reset.\n");
2382 goto err_scp_clk_dom;
2385 r = dsi_set_lane_config(dssdev);
2387 goto err_scp_clk_dom;
2389 /* set TX STOP MODE timer to maximum for this operation */
2390 l = dsi_read_reg(dsidev, DSI_TIMING1);
2391 l = FLD_MOD(l, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2392 l = FLD_MOD(l, 1, 14, 14); /* STOP_STATE_X16_IO */
2393 l = FLD_MOD(l, 1, 13, 13); /* STOP_STATE_X4_IO */
2394 l = FLD_MOD(l, 0x1fff, 12, 0); /* STOP_STATE_COUNTER_IO */
2395 dsi_write_reg(dsidev, DSI_TIMING1, l);
2397 if (dsi->ulps_enabled) {
2401 DSSDBG("manual ulps exit\n");
2403 /* ULPS is exited by Mark-1 state for 1ms, followed by
2404 * stop state. DSS HW cannot do this via the normal
2405 * ULPS exit sequence, as after reset the DSS HW thinks
2406 * that we are not in ULPS mode, and refuses to send the
2407 * sequence. So we need to send the ULPS exit sequence
2408 * manually by setting positive lines high and negative lines
2414 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2415 if (dsi->lanes[i].function == DSI_LANE_UNUSED)
2420 dsi_cio_enable_lane_override(dssdev, mask_p, 0);
2423 r = dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ON);
2427 if (wait_for_bit_change(dsidev, DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
2428 DSSERR("CIO PWR clock domain not coming out of reset.\n");
2430 goto err_cio_pwr_dom;
2433 dsi_if_enable(dsidev, true);
2434 dsi_if_enable(dsidev, false);
2435 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
2437 r = dsi_cio_wait_tx_clk_esc_reset(dssdev);
2439 goto err_tx_clk_esc_rst;
2441 if (dsi->ulps_enabled) {
2442 /* Keep Mark-1 state for 1ms (as per DSI spec) */
2443 ktime_t wait = ns_to_ktime(1000 * 1000);
2444 set_current_state(TASK_UNINTERRUPTIBLE);
2445 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
2447 /* Disable the override. The lanes should be set to Mark-11
2448 * state by the HW */
2449 dsi_cio_disable_lane_override(dsidev);
2452 /* FORCE_TX_STOP_MODE_IO */
2453 REG_FLD_MOD(dsidev, DSI_TIMING1, 0, 15, 15);
2455 dsi_cio_timings(dsidev);
2457 if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
2458 /* DDR_CLK_ALWAYS_ON */
2459 REG_FLD_MOD(dsidev, DSI_CLK_CTRL,
2460 dssdev->panel.dsi_vm_data.ddr_clk_always_on, 13, 13);
2463 dsi->ulps_enabled = false;
2465 DSSDBG("CIO init done\n");
2470 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */
2472 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2474 if (dsi->ulps_enabled)
2475 dsi_cio_disable_lane_override(dsidev);
2477 dsi_disable_scp_clk(dsidev);
2478 dsi->disable_pads(dsidev->id, dsi_get_lane_mask(dssdev));
2482 static void dsi_cio_uninit(struct omap_dss_device *dssdev)
2484 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2485 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2487 /* DDR_CLK_ALWAYS_ON */
2488 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13);
2490 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2491 dsi_disable_scp_clk(dsidev);
2492 dsi->disable_pads(dsidev->id, dsi_get_lane_mask(dssdev));
2495 static void dsi_config_tx_fifo(struct platform_device *dsidev,
2496 enum fifo_size size1, enum fifo_size size2,
2497 enum fifo_size size3, enum fifo_size size4)
2499 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2504 dsi->vc[0].fifo_size = size1;
2505 dsi->vc[1].fifo_size = size2;
2506 dsi->vc[2].fifo_size = size3;
2507 dsi->vc[3].fifo_size = size4;
2509 for (i = 0; i < 4; i++) {
2511 int size = dsi->vc[i].fifo_size;
2513 if (add + size > 4) {
2514 DSSERR("Illegal FIFO configuration\n");
2518 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2520 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
2524 dsi_write_reg(dsidev, DSI_TX_FIFO_VC_SIZE, r);
2527 static void dsi_config_rx_fifo(struct platform_device *dsidev,
2528 enum fifo_size size1, enum fifo_size size2,
2529 enum fifo_size size3, enum fifo_size size4)
2531 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2536 dsi->vc[0].fifo_size = size1;
2537 dsi->vc[1].fifo_size = size2;
2538 dsi->vc[2].fifo_size = size3;
2539 dsi->vc[3].fifo_size = size4;
2541 for (i = 0; i < 4; i++) {
2543 int size = dsi->vc[i].fifo_size;
2545 if (add + size > 4) {
2546 DSSERR("Illegal FIFO configuration\n");
2550 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2552 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
2556 dsi_write_reg(dsidev, DSI_RX_FIFO_VC_SIZE, r);
2559 static int dsi_force_tx_stop_mode_io(struct platform_device *dsidev)
2563 r = dsi_read_reg(dsidev, DSI_TIMING1);
2564 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2565 dsi_write_reg(dsidev, DSI_TIMING1, r);
2567 if (wait_for_bit_change(dsidev, DSI_TIMING1, 15, 0) != 0) {
2568 DSSERR("TX_STOP bit not going down\n");
2575 static bool dsi_vc_is_enabled(struct platform_device *dsidev, int channel)
2577 return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0);
2580 static void dsi_packet_sent_handler_vp(void *data, u32 mask)
2582 struct dsi_packet_sent_handler_data *vp_data =
2583 (struct dsi_packet_sent_handler_data *) data;
2584 struct dsi_data *dsi = dsi_get_dsidrv_data(vp_data->dsidev);
2585 const int channel = dsi->update_channel;
2586 u8 bit = dsi->te_enabled ? 30 : 31;
2588 if (REG_GET(vp_data->dsidev, DSI_VC_TE(channel), bit, bit) == 0)
2589 complete(vp_data->completion);
2592 static int dsi_sync_vc_vp(struct platform_device *dsidev, int channel)
2594 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2595 DECLARE_COMPLETION_ONSTACK(completion);
2596 struct dsi_packet_sent_handler_data vp_data = { dsidev, &completion };
2600 bit = dsi->te_enabled ? 30 : 31;
2602 r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2603 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2607 /* Wait for completion only if TE_EN/TE_START is still set */
2608 if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit)) {
2609 if (wait_for_completion_timeout(&completion,
2610 msecs_to_jiffies(10)) == 0) {
2611 DSSERR("Failed to complete previous frame transfer\n");
2617 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2618 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2622 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2623 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2628 static void dsi_packet_sent_handler_l4(void *data, u32 mask)
2630 struct dsi_packet_sent_handler_data *l4_data =
2631 (struct dsi_packet_sent_handler_data *) data;
2632 struct dsi_data *dsi = dsi_get_dsidrv_data(l4_data->dsidev);
2633 const int channel = dsi->update_channel;
2635 if (REG_GET(l4_data->dsidev, DSI_VC_CTRL(channel), 5, 5) == 0)
2636 complete(l4_data->completion);
2639 static int dsi_sync_vc_l4(struct platform_device *dsidev, int channel)
2641 DECLARE_COMPLETION_ONSTACK(completion);
2642 struct dsi_packet_sent_handler_data l4_data = { dsidev, &completion };
2645 r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2646 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2650 /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */
2651 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) {
2652 if (wait_for_completion_timeout(&completion,
2653 msecs_to_jiffies(10)) == 0) {
2654 DSSERR("Failed to complete previous l4 transfer\n");
2660 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2661 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2665 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2666 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2671 static int dsi_sync_vc(struct platform_device *dsidev, int channel)
2673 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2675 WARN_ON(!dsi_bus_is_locked(dsidev));
2677 WARN_ON(in_interrupt());
2679 if (!dsi_vc_is_enabled(dsidev, channel))
2682 switch (dsi->vc[channel].source) {
2683 case DSI_VC_SOURCE_VP:
2684 return dsi_sync_vc_vp(dsidev, channel);
2685 case DSI_VC_SOURCE_L4:
2686 return dsi_sync_vc_l4(dsidev, channel);
2692 static int dsi_vc_enable(struct platform_device *dsidev, int channel,
2695 DSSDBG("dsi_vc_enable channel %d, enable %d\n",
2698 enable = enable ? 1 : 0;
2700 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 0, 0);
2702 if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel),
2703 0, enable) != enable) {
2704 DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
2711 static void dsi_vc_initial_config(struct platform_device *dsidev, int channel)
2715 DSSDBGF("%d", channel);
2717 r = dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
2719 if (FLD_GET(r, 15, 15)) /* VC_BUSY */
2720 DSSERR("VC(%d) busy when trying to configure it!\n",
2723 r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
2724 r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */
2725 r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
2726 r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
2727 r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
2728 r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
2729 r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
2730 if (dss_has_feature(FEAT_DSI_VC_OCP_WIDTH))
2731 r = FLD_MOD(r, 3, 11, 10); /* OCP_WIDTH = 32 bit */
2733 r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
2734 r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
2736 dsi_write_reg(dsidev, DSI_VC_CTRL(channel), r);
2739 static int dsi_vc_config_source(struct platform_device *dsidev, int channel,
2740 enum dsi_vc_source source)
2742 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2744 if (dsi->vc[channel].source == source)
2747 DSSDBGF("%d", channel);
2749 dsi_sync_vc(dsidev, channel);
2751 dsi_vc_enable(dsidev, channel, 0);
2754 if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 15, 0) != 0) {
2755 DSSERR("vc(%d) busy when trying to config for VP\n", channel);
2759 /* SOURCE, 0 = L4, 1 = video port */
2760 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), source, 1, 1);
2762 /* DCS_CMD_ENABLE */
2763 if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
2764 bool enable = source == DSI_VC_SOURCE_VP;
2765 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 30, 30);
2768 dsi_vc_enable(dsidev, channel, 1);
2770 dsi->vc[channel].source = source;
2775 void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
2778 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2780 DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
2782 WARN_ON(!dsi_bus_is_locked(dsidev));
2784 dsi_vc_enable(dsidev, channel, 0);
2785 dsi_if_enable(dsidev, 0);
2787 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 9, 9);
2789 dsi_vc_enable(dsidev, channel, 1);
2790 dsi_if_enable(dsidev, 1);
2792 dsi_force_tx_stop_mode_io(dsidev);
2794 /* start the DDR clock by sending a NULL packet */
2795 if (dssdev->panel.dsi_vm_data.ddr_clk_always_on && enable)
2796 dsi_vc_send_null(dssdev, channel);
2798 EXPORT_SYMBOL(omapdss_dsi_vc_enable_hs);
2800 static void dsi_vc_flush_long_data(struct platform_device *dsidev, int channel)
2802 while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2804 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2805 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
2809 (val >> 24) & 0xff);
2813 static void dsi_show_rx_ack_with_err(u16 err)
2815 DSSERR("\tACK with ERROR (%#x):\n", err);
2817 DSSERR("\t\tSoT Error\n");
2819 DSSERR("\t\tSoT Sync Error\n");
2821 DSSERR("\t\tEoT Sync Error\n");
2823 DSSERR("\t\tEscape Mode Entry Command Error\n");
2825 DSSERR("\t\tLP Transmit Sync Error\n");
2827 DSSERR("\t\tHS Receive Timeout Error\n");
2829 DSSERR("\t\tFalse Control Error\n");
2831 DSSERR("\t\t(reserved7)\n");
2833 DSSERR("\t\tECC Error, single-bit (corrected)\n");
2835 DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
2836 if (err & (1 << 10))
2837 DSSERR("\t\tChecksum Error\n");
2838 if (err & (1 << 11))
2839 DSSERR("\t\tData type not recognized\n");
2840 if (err & (1 << 12))
2841 DSSERR("\t\tInvalid VC ID\n");
2842 if (err & (1 << 13))
2843 DSSERR("\t\tInvalid Transmission Length\n");
2844 if (err & (1 << 14))
2845 DSSERR("\t\t(reserved14)\n");
2846 if (err & (1 << 15))
2847 DSSERR("\t\tDSI Protocol Violation\n");
2850 static u16 dsi_vc_flush_receive_data(struct platform_device *dsidev,
2853 /* RX_FIFO_NOT_EMPTY */
2854 while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2857 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2858 DSSERR("\trawval %#08x\n", val);
2859 dt = FLD_GET(val, 5, 0);
2860 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
2861 u16 err = FLD_GET(val, 23, 8);
2862 dsi_show_rx_ack_with_err(err);
2863 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE) {
2864 DSSERR("\tDCS short response, 1 byte: %#x\n",
2865 FLD_GET(val, 23, 8));
2866 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE) {
2867 DSSERR("\tDCS short response, 2 byte: %#x\n",
2868 FLD_GET(val, 23, 8));
2869 } else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) {
2870 DSSERR("\tDCS long response, len %d\n",
2871 FLD_GET(val, 23, 8));
2872 dsi_vc_flush_long_data(dsidev, channel);
2874 DSSERR("\tunknown datatype 0x%02x\n", dt);
2880 static int dsi_vc_send_bta(struct platform_device *dsidev, int channel)
2882 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2884 if (dsi->debug_write || dsi->debug_read)
2885 DSSDBG("dsi_vc_send_bta %d\n", channel);
2887 WARN_ON(!dsi_bus_is_locked(dsidev));
2889 /* RX_FIFO_NOT_EMPTY */
2890 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2891 DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
2892 dsi_vc_flush_receive_data(dsidev, channel);
2895 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
2897 /* flush posted write */
2898 dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
2903 int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel)
2905 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2906 DECLARE_COMPLETION_ONSTACK(completion);
2910 r = dsi_register_isr_vc(dsidev, channel, dsi_completion_handler,
2911 &completion, DSI_VC_IRQ_BTA);
2915 r = dsi_register_isr(dsidev, dsi_completion_handler, &completion,
2916 DSI_IRQ_ERROR_MASK);
2920 r = dsi_vc_send_bta(dsidev, channel);
2924 if (wait_for_completion_timeout(&completion,
2925 msecs_to_jiffies(500)) == 0) {
2926 DSSERR("Failed to receive BTA\n");
2931 err = dsi_get_errors(dsidev);
2933 DSSERR("Error while sending BTA: %x\n", err);
2938 dsi_unregister_isr(dsidev, dsi_completion_handler, &completion,
2939 DSI_IRQ_ERROR_MASK);
2941 dsi_unregister_isr_vc(dsidev, channel, dsi_completion_handler,
2942 &completion, DSI_VC_IRQ_BTA);
2946 EXPORT_SYMBOL(dsi_vc_send_bta_sync);
2948 static inline void dsi_vc_write_long_header(struct platform_device *dsidev,
2949 int channel, u8 data_type, u16 len, u8 ecc)
2951 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2955 WARN_ON(!dsi_bus_is_locked(dsidev));
2957 data_id = data_type | dsi->vc[channel].vc_id << 6;
2959 val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
2960 FLD_VAL(ecc, 31, 24);
2962 dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_HEADER(channel), val);
2965 static inline void dsi_vc_write_long_payload(struct platform_device *dsidev,
2966 int channel, u8 b1, u8 b2, u8 b3, u8 b4)
2970 val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0;
2972 /* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
2973 b1, b2, b3, b4, val); */
2975 dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
2978 static int dsi_vc_send_long(struct platform_device *dsidev, int channel,
2979 u8 data_type, u8 *data, u16 len, u8 ecc)
2982 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2988 if (dsi->debug_write)
2989 DSSDBG("dsi_vc_send_long, %d bytes\n", len);
2992 if (dsi->vc[channel].fifo_size * 32 * 4 < len + 4) {
2993 DSSERR("unable to send long packet: packet too long.\n");
2997 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
2999 dsi_vc_write_long_header(dsidev, channel, data_type, len, ecc);
3002 for (i = 0; i < len >> 2; i++) {
3003 if (dsi->debug_write)
3004 DSSDBG("\tsending full packet %d\n", i);
3011 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, b4);
3016 b1 = 0; b2 = 0; b3 = 0;
3018 if (dsi->debug_write)
3019 DSSDBG("\tsending remainder bytes %d\n", i);
3036 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, 0);
3042 static int dsi_vc_send_short(struct platform_device *dsidev, int channel,
3043 u8 data_type, u16 data, u8 ecc)
3045 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3049 WARN_ON(!dsi_bus_is_locked(dsidev));
3051 if (dsi->debug_write)
3052 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
3054 data_type, data & 0xff, (data >> 8) & 0xff);
3056 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
3058 if (FLD_GET(dsi_read_reg(dsidev, DSI_VC_CTRL(channel)), 16, 16)) {
3059 DSSERR("ERROR FIFO FULL, aborting transfer\n");
3063 data_id = data_type | dsi->vc[channel].vc_id << 6;
3065 r = (data_id << 0) | (data << 8) | (ecc << 24);
3067 dsi_write_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel), r);
3072 int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel)
3074 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3076 return dsi_vc_send_long(dsidev, channel, MIPI_DSI_NULL_PACKET, NULL,
3079 EXPORT_SYMBOL(dsi_vc_send_null);
3081 static int dsi_vc_write_nosync_common(struct omap_dss_device *dssdev,
3082 int channel, u8 *data, int len, enum dss_dsi_content_type type)
3084 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3088 BUG_ON(type == DSS_DSI_CONTENT_DCS);
3089 r = dsi_vc_send_short(dsidev, channel,
3090 MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM, 0, 0);
3091 } else if (len == 1) {
3092 r = dsi_vc_send_short(dsidev, channel,
3093 type == DSS_DSI_CONTENT_GENERIC ?
3094 MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM :
3095 MIPI_DSI_DCS_SHORT_WRITE, data[0], 0);
3096 } else if (len == 2) {
3097 r = dsi_vc_send_short(dsidev, channel,
3098 type == DSS_DSI_CONTENT_GENERIC ?
3099 MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM :
3100 MIPI_DSI_DCS_SHORT_WRITE_PARAM,
3101 data[0] | (data[1] << 8), 0);
3103 r = dsi_vc_send_long(dsidev, channel,
3104 type == DSS_DSI_CONTENT_GENERIC ?
3105 MIPI_DSI_GENERIC_LONG_WRITE :
3106 MIPI_DSI_DCS_LONG_WRITE, data, len, 0);
3112 int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
3115 return dsi_vc_write_nosync_common(dssdev, channel, data, len,
3116 DSS_DSI_CONTENT_DCS);
3118 EXPORT_SYMBOL(dsi_vc_dcs_write_nosync);
3120 int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel,
3123 return dsi_vc_write_nosync_common(dssdev, channel, data, len,
3124 DSS_DSI_CONTENT_GENERIC);
3126 EXPORT_SYMBOL(dsi_vc_generic_write_nosync);
3128 static int dsi_vc_write_common(struct omap_dss_device *dssdev, int channel,
3129 u8 *data, int len, enum dss_dsi_content_type type)
3131 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3134 r = dsi_vc_write_nosync_common(dssdev, channel, data, len, type);
3138 r = dsi_vc_send_bta_sync(dssdev, channel);
3142 /* RX_FIFO_NOT_EMPTY */
3143 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
3144 DSSERR("rx fifo not empty after write, dumping data:\n");
3145 dsi_vc_flush_receive_data(dsidev, channel);
3152 DSSERR("dsi_vc_write_common(ch %d, cmd 0x%02x, len %d) failed\n",
3153 channel, data[0], len);
3157 int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
3160 return dsi_vc_write_common(dssdev, channel, data, len,
3161 DSS_DSI_CONTENT_DCS);
3163 EXPORT_SYMBOL(dsi_vc_dcs_write);
3165 int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data,
3168 return dsi_vc_write_common(dssdev, channel, data, len,
3169 DSS_DSI_CONTENT_GENERIC);
3171 EXPORT_SYMBOL(dsi_vc_generic_write);
3173 int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd)
3175 return dsi_vc_dcs_write(dssdev, channel, &dcs_cmd, 1);
3177 EXPORT_SYMBOL(dsi_vc_dcs_write_0);
3179 int dsi_vc_generic_write_0(struct omap_dss_device *dssdev, int channel)
3181 return dsi_vc_generic_write(dssdev, channel, NULL, 0);
3183 EXPORT_SYMBOL(dsi_vc_generic_write_0);
3185 int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3191 return dsi_vc_dcs_write(dssdev, channel, buf, 2);
3193 EXPORT_SYMBOL(dsi_vc_dcs_write_1);
3195 int dsi_vc_generic_write_1(struct omap_dss_device *dssdev, int channel,
3198 return dsi_vc_generic_write(dssdev, channel, ¶m, 1);
3200 EXPORT_SYMBOL(dsi_vc_generic_write_1);
3202 int dsi_vc_generic_write_2(struct omap_dss_device *dssdev, int channel,
3203 u8 param1, u8 param2)
3208 return dsi_vc_generic_write(dssdev, channel, buf, 2);
3210 EXPORT_SYMBOL(dsi_vc_generic_write_2);
3212 static int dsi_vc_dcs_send_read_request(struct omap_dss_device *dssdev,
3213 int channel, u8 dcs_cmd)
3215 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3216 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3219 if (dsi->debug_read)
3220 DSSDBG("dsi_vc_dcs_send_read_request(ch%d, dcs_cmd %x)\n",
3223 r = dsi_vc_send_short(dsidev, channel, MIPI_DSI_DCS_READ, dcs_cmd, 0);
3225 DSSERR("dsi_vc_dcs_send_read_request(ch %d, cmd 0x%02x)"
3226 " failed\n", channel, dcs_cmd);
3233 static int dsi_vc_generic_send_read_request(struct omap_dss_device *dssdev,
3234 int channel, u8 *reqdata, int reqlen)
3236 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3237 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3242 if (dsi->debug_read)
3243 DSSDBG("dsi_vc_generic_send_read_request(ch %d, reqlen %d)\n",
3247 data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM;
3249 } else if (reqlen == 1) {
3250 data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM;
3252 } else if (reqlen == 2) {
3253 data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM;
3254 data = reqdata[0] | (reqdata[1] << 8);
3259 r = dsi_vc_send_short(dsidev, channel, data_type, data, 0);
3261 DSSERR("dsi_vc_generic_send_read_request(ch %d, reqlen %d)"
3262 " failed\n", channel, reqlen);
3269 static int dsi_vc_read_rx_fifo(struct platform_device *dsidev, int channel,
3270 u8 *buf, int buflen, enum dss_dsi_content_type type)
3272 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3277 /* RX_FIFO_NOT_EMPTY */
3278 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20) == 0) {
3279 DSSERR("RX fifo empty when trying to read.\n");
3284 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
3285 if (dsi->debug_read)
3286 DSSDBG("\theader: %08x\n", val);
3287 dt = FLD_GET(val, 5, 0);
3288 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
3289 u16 err = FLD_GET(val, 23, 8);
3290 dsi_show_rx_ack_with_err(err);
3294 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3295 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE :
3296 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE)) {
3297 u8 data = FLD_GET(val, 15, 8);
3298 if (dsi->debug_read)
3299 DSSDBG("\t%s short response, 1 byte: %02x\n",
3300 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3311 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3312 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE :
3313 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE)) {
3314 u16 data = FLD_GET(val, 23, 8);
3315 if (dsi->debug_read)
3316 DSSDBG("\t%s short response, 2 byte: %04x\n",
3317 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3325 buf[0] = data & 0xff;
3326 buf[1] = (data >> 8) & 0xff;
3329 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3330 MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE :
3331 MIPI_DSI_RX_DCS_LONG_READ_RESPONSE)) {
3333 int len = FLD_GET(val, 23, 8);
3334 if (dsi->debug_read)
3335 DSSDBG("\t%s long response, len %d\n",
3336 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3344 /* two byte checksum ends the packet, not included in len */
3345 for (w = 0; w < len + 2;) {
3347 val = dsi_read_reg(dsidev,
3348 DSI_VC_SHORT_PACKET_HEADER(channel));
3349 if (dsi->debug_read)
3350 DSSDBG("\t\t%02x %02x %02x %02x\n",
3354 (val >> 24) & 0xff);
3356 for (b = 0; b < 4; ++b) {
3358 buf[w] = (val >> (b * 8)) & 0xff;
3359 /* we discard the 2 byte checksum */
3366 DSSERR("\tunknown datatype 0x%02x\n", dt);
3373 DSSERR("dsi_vc_read_rx_fifo(ch %d type %s) failed\n", channel,
3374 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : "DCS");
3379 int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3380 u8 *buf, int buflen)
3382 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3385 r = dsi_vc_dcs_send_read_request(dssdev, channel, dcs_cmd);
3389 r = dsi_vc_send_bta_sync(dssdev, channel);
3393 r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
3394 DSS_DSI_CONTENT_DCS);
3405 DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", channel, dcs_cmd);
3408 EXPORT_SYMBOL(dsi_vc_dcs_read);
3410 static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int channel,
3411 u8 *reqdata, int reqlen, u8 *buf, int buflen)
3413 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3416 r = dsi_vc_generic_send_read_request(dssdev, channel, reqdata, reqlen);
3420 r = dsi_vc_send_bta_sync(dssdev, channel);
3424 r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
3425 DSS_DSI_CONTENT_GENERIC);
3437 int dsi_vc_generic_read_0(struct omap_dss_device *dssdev, int channel, u8 *buf,
3442 r = dsi_vc_generic_read(dssdev, channel, NULL, 0, buf, buflen);
3444 DSSERR("dsi_vc_generic_read_0(ch %d) failed\n", channel);
3450 EXPORT_SYMBOL(dsi_vc_generic_read_0);
3452 int dsi_vc_generic_read_1(struct omap_dss_device *dssdev, int channel, u8 param,
3453 u8 *buf, int buflen)
3457 r = dsi_vc_generic_read(dssdev, channel, ¶m, 1, buf, buflen);
3459 DSSERR("dsi_vc_generic_read_1(ch %d) failed\n", channel);
3465 EXPORT_SYMBOL(dsi_vc_generic_read_1);
3467 int dsi_vc_generic_read_2(struct omap_dss_device *dssdev, int channel,
3468 u8 param1, u8 param2, u8 *buf, int buflen)
3473 reqdata[0] = param1;
3474 reqdata[1] = param2;
3476 r = dsi_vc_generic_read(dssdev, channel, reqdata, 2, buf, buflen);
3478 DSSERR("dsi_vc_generic_read_2(ch %d) failed\n", channel);
3484 EXPORT_SYMBOL(dsi_vc_generic_read_2);
3486 int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
3489 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3491 return dsi_vc_send_short(dsidev, channel,
3492 MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0);
3494 EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size);
3496 static int dsi_enter_ulps(struct platform_device *dsidev)
3498 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3499 DECLARE_COMPLETION_ONSTACK(completion);
3505 WARN_ON(!dsi_bus_is_locked(dsidev));
3507 WARN_ON(dsi->ulps_enabled);
3509 if (dsi->ulps_enabled)
3512 /* DDR_CLK_ALWAYS_ON */
3513 if (REG_GET(dsidev, DSI_CLK_CTRL, 13, 13)) {
3514 dsi_if_enable(dsidev, 0);
3515 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13);
3516 dsi_if_enable(dsidev, 1);
3519 dsi_sync_vc(dsidev, 0);
3520 dsi_sync_vc(dsidev, 1);
3521 dsi_sync_vc(dsidev, 2);
3522 dsi_sync_vc(dsidev, 3);
3524 dsi_force_tx_stop_mode_io(dsidev);
3526 dsi_vc_enable(dsidev, 0, false);
3527 dsi_vc_enable(dsidev, 1, false);
3528 dsi_vc_enable(dsidev, 2, false);
3529 dsi_vc_enable(dsidev, 3, false);
3531 if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 16, 16)) { /* HS_BUSY */
3532 DSSERR("HS busy when enabling ULPS\n");
3536 if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 17, 17)) { /* LP_BUSY */
3537 DSSERR("LP busy when enabling ULPS\n");
3541 r = dsi_register_isr_cio(dsidev, dsi_completion_handler, &completion,
3542 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3548 for (i = 0; i < dsi->num_lanes_supported; ++i) {
3549 if (dsi->lanes[i].function == DSI_LANE_UNUSED)
3553 /* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */
3554 /* LANEx_ULPS_SIG2 */
3555 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, mask, 9, 5);
3557 /* flush posted write and wait for SCP interface to finish the write */
3558 dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
3560 if (wait_for_completion_timeout(&completion,
3561 msecs_to_jiffies(1000)) == 0) {
3562 DSSERR("ULPS enable timeout\n");
3567 dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3568 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3570 /* Reset LANEx_ULPS_SIG2 */
3571 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, 0, 9, 5);
3573 /* flush posted write and wait for SCP interface to finish the write */
3574 dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
3576 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ULPS);
3578 dsi_if_enable(dsidev, false);
3580 dsi->ulps_enabled = true;
3585 dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3586 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3590 static void dsi_set_lp_rx_timeout(struct platform_device *dsidev,
3591 unsigned ticks, bool x4, bool x16)
3594 unsigned long total_ticks;
3597 BUG_ON(ticks > 0x1fff);
3599 /* ticks in DSI_FCK */
3600 fck = dsi_fclk_rate(dsidev);
3602 r = dsi_read_reg(dsidev, DSI_TIMING2);
3603 r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */
3604 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */
3605 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */
3606 r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */
3607 dsi_write_reg(dsidev, DSI_TIMING2, r);
3609 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3611 DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3613 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3614 (total_ticks * 1000) / (fck / 1000 / 1000));
3617 static void dsi_set_ta_timeout(struct platform_device *dsidev, unsigned ticks,
3621 unsigned long total_ticks;
3624 BUG_ON(ticks > 0x1fff);
3626 /* ticks in DSI_FCK */
3627 fck = dsi_fclk_rate(dsidev);
3629 r = dsi_read_reg(dsidev, DSI_TIMING1);
3630 r = FLD_MOD(r, 1, 31, 31); /* TA_TO */
3631 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */
3632 r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */
3633 r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */
3634 dsi_write_reg(dsidev, DSI_TIMING1, r);
3636 total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1);
3638 DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n",
3640 ticks, x8 ? " x8" : "", x16 ? " x16" : "",
3641 (total_ticks * 1000) / (fck / 1000 / 1000));
3644 static void dsi_set_stop_state_counter(struct platform_device *dsidev,
3645 unsigned ticks, bool x4, bool x16)
3648 unsigned long total_ticks;
3651 BUG_ON(ticks > 0x1fff);
3653 /* ticks in DSI_FCK */
3654 fck = dsi_fclk_rate(dsidev);
3656 r = dsi_read_reg(dsidev, DSI_TIMING1);
3657 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
3658 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */
3659 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */
3660 r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */
3661 dsi_write_reg(dsidev, DSI_TIMING1, r);
3663 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3665 DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n",
3667 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3668 (total_ticks * 1000) / (fck / 1000 / 1000));
3671 static void dsi_set_hs_tx_timeout(struct platform_device *dsidev,
3672 unsigned ticks, bool x4, bool x16)
3675 unsigned long total_ticks;
3678 BUG_ON(ticks > 0x1fff);
3680 /* ticks in TxByteClkHS */
3681 fck = dsi_get_txbyteclkhs(dsidev);
3683 r = dsi_read_reg(dsidev, DSI_TIMING2);
3684 r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */
3685 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */
3686 r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */
3687 r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */
3688 dsi_write_reg(dsidev, DSI_TIMING2, r);
3690 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3692 DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3694 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3695 (total_ticks * 1000) / (fck / 1000 / 1000));
3698 static void dsi_config_vp_num_line_buffers(struct omap_dss_device *dssdev)
3700 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3701 int num_line_buffers;
3703 if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
3704 int bpp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt);
3705 unsigned line_buf_size = dsi_get_line_buf_size(dsidev);
3706 struct omap_video_timings *timings = &dssdev->panel.timings;
3708 * Don't use line buffers if width is greater than the video
3709 * port's line buffer size
3711 if (line_buf_size <= timings->x_res * bpp / 8)
3712 num_line_buffers = 0;
3714 num_line_buffers = 2;
3716 /* Use maximum number of line buffers in command mode */
3717 num_line_buffers = 2;
3721 REG_FLD_MOD(dsidev, DSI_CTRL, num_line_buffers, 13, 12);
3724 static void dsi_config_vp_sync_events(struct omap_dss_device *dssdev)
3726 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3727 int de_pol = dssdev->panel.dsi_vm_data.vp_de_pol;
3728 int hsync_pol = dssdev->panel.dsi_vm_data.vp_hsync_pol;
3729 int vsync_pol = dssdev->panel.dsi_vm_data.vp_vsync_pol;
3730 bool vsync_end = dssdev->panel.dsi_vm_data.vp_vsync_end;
3731 bool hsync_end = dssdev->panel.dsi_vm_data.vp_hsync_end;
3734 r = dsi_read_reg(dsidev, DSI_CTRL);
3735 r = FLD_MOD(r, de_pol, 9, 9); /* VP_DE_POL */
3736 r = FLD_MOD(r, hsync_pol, 10, 10); /* VP_HSYNC_POL */
3737 r = FLD_MOD(r, vsync_pol, 11, 11); /* VP_VSYNC_POL */
3738 r = FLD_MOD(r, 1, 15, 15); /* VP_VSYNC_START */
3739 r = FLD_MOD(r, vsync_end, 16, 16); /* VP_VSYNC_END */
3740 r = FLD_MOD(r, 1, 17, 17); /* VP_HSYNC_START */
3741 r = FLD_MOD(r, hsync_end, 18, 18); /* VP_HSYNC_END */
3742 dsi_write_reg(dsidev, DSI_CTRL, r);
3745 static void dsi_config_blanking_modes(struct omap_dss_device *dssdev)
3747 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3748 int blanking_mode = dssdev->panel.dsi_vm_data.blanking_mode;
3749 int hfp_blanking_mode = dssdev->panel.dsi_vm_data.hfp_blanking_mode;
3750 int hbp_blanking_mode = dssdev->panel.dsi_vm_data.hbp_blanking_mode;
3751 int hsa_blanking_mode = dssdev->panel.dsi_vm_data.hsa_blanking_mode;
3755 * 0 = TX FIFO packets sent or LPS in corresponding blanking periods
3756 * 1 = Long blanking packets are sent in corresponding blanking periods
3758 r = dsi_read_reg(dsidev, DSI_CTRL);
3759 r = FLD_MOD(r, blanking_mode, 20, 20); /* BLANKING_MODE */
3760 r = FLD_MOD(r, hfp_blanking_mode, 21, 21); /* HFP_BLANKING */
3761 r = FLD_MOD(r, hbp_blanking_mode, 22, 22); /* HBP_BLANKING */
3762 r = FLD_MOD(r, hsa_blanking_mode, 23, 23); /* HSA_BLANKING */
3763 dsi_write_reg(dsidev, DSI_CTRL, r);
3766 static int dsi_proto_config(struct omap_dss_device *dssdev)
3768 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3772 dsi_config_tx_fifo(dsidev, DSI_FIFO_SIZE_32,
3777 dsi_config_rx_fifo(dsidev, DSI_FIFO_SIZE_32,
3782 /* XXX what values for the timeouts? */
3783 dsi_set_stop_state_counter(dsidev, 0x1000, false, false);
3784 dsi_set_ta_timeout(dsidev, 0x1fff, true, true);
3785 dsi_set_lp_rx_timeout(dsidev, 0x1fff, true, true);
3786 dsi_set_hs_tx_timeout(dsidev, 0x1fff, true, true);
3788 switch (dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt)) {
3802 r = dsi_read_reg(dsidev, DSI_CTRL);
3803 r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */
3804 r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */
3805 r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */
3806 r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/
3807 r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
3808 r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */
3809 r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */
3810 r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */
3811 if (!dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
3812 r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */
3813 /* DCS_CMD_CODE, 1=start, 0=continue */
3814 r = FLD_MOD(r, 0, 25, 25);
3817 dsi_write_reg(dsidev, DSI_CTRL, r);
3819 dsi_config_vp_num_line_buffers(dssdev);
3821 if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
3822 dsi_config_vp_sync_events(dssdev);
3823 dsi_config_blanking_modes(dssdev);
3826 dsi_vc_initial_config(dsidev, 0);
3827 dsi_vc_initial_config(dsidev, 1);
3828 dsi_vc_initial_config(dsidev, 2);
3829 dsi_vc_initial_config(dsidev, 3);
3834 static void dsi_proto_timings(struct omap_dss_device *dssdev)
3836 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3837 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3838 unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail;
3839 unsigned tclk_pre, tclk_post;
3840 unsigned ths_prepare, ths_prepare_ths_zero, ths_zero;
3841 unsigned ths_trail, ths_exit;
3842 unsigned ddr_clk_pre, ddr_clk_post;
3843 unsigned enter_hs_mode_lat, exit_hs_mode_lat;
3845 int ndl = dsi->num_lanes_used - 1;
3848 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
3849 ths_prepare = FLD_GET(r, 31, 24);
3850 ths_prepare_ths_zero = FLD_GET(r, 23, 16);
3851 ths_zero = ths_prepare_ths_zero - ths_prepare;
3852 ths_trail = FLD_GET(r, 15, 8);
3853 ths_exit = FLD_GET(r, 7, 0);
3855 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
3856 tlpx = FLD_GET(r, 22, 16) * 2;
3857 tclk_trail = FLD_GET(r, 15, 8);
3858 tclk_zero = FLD_GET(r, 7, 0);
3860 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
3861 tclk_prepare = FLD_GET(r, 7, 0);
3865 /* min 60ns + 52*UI */
3866 tclk_post = ns2ddr(dsidev, 60) + 26;
3868 ths_eot = DIV_ROUND_UP(4, ndl);
3870 ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
3872 ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot;
3874 BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
3875 BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);
3877 r = dsi_read_reg(dsidev, DSI_CLK_TIMING);
3878 r = FLD_MOD(r, ddr_clk_pre, 15, 8);
3879 r = FLD_MOD(r, ddr_clk_post, 7, 0);
3880 dsi_write_reg(dsidev, DSI_CLK_TIMING, r);
3882 DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
3886 enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) +
3887 DIV_ROUND_UP(ths_prepare, 4) +
3888 DIV_ROUND_UP(ths_zero + 3, 4);
3890 exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;
3892 r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
3893 FLD_VAL(exit_hs_mode_lat, 15, 0);
3894 dsi_write_reg(dsidev, DSI_VM_TIMING7, r);
3896 DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
3897 enter_hs_mode_lat, exit_hs_mode_lat);
3899 if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
3900 /* TODO: Implement a video mode check_timings function */
3901 int hsa = dssdev->panel.dsi_vm_data.hsa;
3902 int hfp = dssdev->panel.dsi_vm_data.hfp;
3903 int hbp = dssdev->panel.dsi_vm_data.hbp;
3904 int vsa = dssdev->panel.dsi_vm_data.vsa;
3905 int vfp = dssdev->panel.dsi_vm_data.vfp;
3906 int vbp = dssdev->panel.dsi_vm_data.vbp;
3907 int window_sync = dssdev->panel.dsi_vm_data.window_sync;
3908 bool hsync_end = dssdev->panel.dsi_vm_data.vp_hsync_end;
3909 struct omap_video_timings *timings = &dssdev->panel.timings;
3910 int bpp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt);
3911 int tl, t_he, width_bytes;
3914 ((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0;
3916 width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8);
3918 /* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */
3919 tl = DIV_ROUND_UP(4, ndl) + (hsync_end ? hsa : 0) + t_he + hfp +
3920 DIV_ROUND_UP(width_bytes + 6, ndl) + hbp;
3922 DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp,
3923 hfp, hsync_end ? hsa : 0, tl);
3924 DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp, vfp,
3925 vsa, timings->y_res);
3927 r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
3928 r = FLD_MOD(r, hbp, 11, 0); /* HBP */
3929 r = FLD_MOD(r, hfp, 23, 12); /* HFP */
3930 r = FLD_MOD(r, hsync_end ? hsa : 0, 31, 24); /* HSA */
3931 dsi_write_reg(dsidev, DSI_VM_TIMING1, r);
3933 r = dsi_read_reg(dsidev, DSI_VM_TIMING2);
3934 r = FLD_MOD(r, vbp, 7, 0); /* VBP */
3935 r = FLD_MOD(r, vfp, 15, 8); /* VFP */
3936 r = FLD_MOD(r, vsa, 23, 16); /* VSA */
3937 r = FLD_MOD(r, window_sync, 27, 24); /* WINDOW_SYNC */
3938 dsi_write_reg(dsidev, DSI_VM_TIMING2, r);
3940 r = dsi_read_reg(dsidev, DSI_VM_TIMING3);
3941 r = FLD_MOD(r, timings->y_res, 14, 0); /* VACT */
3942 r = FLD_MOD(r, tl, 31, 16); /* TL */
3943 dsi_write_reg(dsidev, DSI_VM_TIMING3, r);
3947 int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel)
3949 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3950 int bpp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt);
3955 if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
3956 switch (dssdev->panel.dsi_pix_fmt) {
3957 case OMAP_DSS_DSI_FMT_RGB888:
3958 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24;
3960 case OMAP_DSS_DSI_FMT_RGB666:
3961 data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
3963 case OMAP_DSS_DSI_FMT_RGB666_PACKED:
3964 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18;
3966 case OMAP_DSS_DSI_FMT_RGB565:
3967 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16;
3973 dsi_if_enable(dsidev, false);
3974 dsi_vc_enable(dsidev, channel, false);
3976 /* MODE, 1 = video mode */
3977 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 4, 4);
3979 word_count = DIV_ROUND_UP(dssdev->panel.timings.x_res * bpp, 8);
3981 dsi_vc_write_long_header(dsidev, channel, data_type,
3984 dsi_vc_enable(dsidev, channel, true);
3985 dsi_if_enable(dsidev, true);
3988 r = dss_mgr_enable(dssdev->manager);
3990 if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
3991 dsi_if_enable(dsidev, false);
3992 dsi_vc_enable(dsidev, channel, false);
4000 EXPORT_SYMBOL(dsi_enable_video_output);
4002 void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel)
4004 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4006 if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
4007 dsi_if_enable(dsidev, false);
4008 dsi_vc_enable(dsidev, channel, false);
4010 /* MODE, 0 = command mode */
4011 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 0, 4, 4);
4013 dsi_vc_enable(dsidev, channel, true);
4014 dsi_if_enable(dsidev, true);
4017 dss_mgr_disable(dssdev->manager);
4019 EXPORT_SYMBOL(dsi_disable_video_output);
4021 static void dsi_update_screen_dispc(struct omap_dss_device *dssdev,
4024 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4025 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4030 unsigned packet_payload;
4031 unsigned packet_len;
4034 const unsigned channel = dsi->update_channel;
4035 const unsigned line_buf_size = dsi_get_line_buf_size(dsidev);
4037 DSSDBG("dsi_update_screen_dispc(%dx%d)\n", w, h);
4039 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_VP);
4041 bytespp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt) / 8;
4042 bytespl = w * bytespp;
4043 bytespf = bytespl * h;
4045 /* NOTE: packet_payload has to be equal to N * bytespl, where N is
4046 * number of lines in a packet. See errata about VP_CLK_RATIO */
4048 if (bytespf < line_buf_size)
4049 packet_payload = bytespf;
4051 packet_payload = (line_buf_size) / bytespl * bytespl;
4053 packet_len = packet_payload + 1; /* 1 byte for DCS cmd */
4054 total_len = (bytespf / packet_payload) * packet_len;
4056 if (bytespf % packet_payload)
4057 total_len += (bytespf % packet_payload) + 1;
4059 l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
4060 dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
4062 dsi_vc_write_long_header(dsidev, channel, MIPI_DSI_DCS_LONG_WRITE,
4065 if (dsi->te_enabled)
4066 l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
4068 l = FLD_MOD(l, 1, 31, 31); /* TE_START */
4069 dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
4071 /* We put SIDLEMODE to no-idle for the duration of the transfer,
4072 * because DSS interrupts are not capable of waking up the CPU and the
4073 * framedone interrupt could be delayed for quite a long time. I think
4074 * the same goes for any DSS interrupts, but for some reason I have not
4075 * seen the problem anywhere else than here.
4077 dispc_disable_sidle();
4079 dsi_perf_mark_start(dsidev);
4081 r = schedule_delayed_work(&dsi->framedone_timeout_work,
4082 msecs_to_jiffies(250));
4085 dss_mgr_start_update(dssdev->manager);
4087 if (dsi->te_enabled) {
4088 /* disable LP_RX_TO, so that we can receive TE. Time to wait
4089 * for TE is longer than the timer allows */
4090 REG_FLD_MOD(dsidev, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
4092 dsi_vc_send_bta(dsidev, channel);
4094 #ifdef DSI_CATCH_MISSING_TE
4095 mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250));
4100 #ifdef DSI_CATCH_MISSING_TE
4101 static void dsi_te_timeout(unsigned long arg)
4103 DSSERR("TE not received for 250ms!\n");
4107 static void dsi_handle_framedone(struct platform_device *dsidev, int error)
4109 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4111 /* SIDLEMODE back to smart-idle */
4112 dispc_enable_sidle();
4114 if (dsi->te_enabled) {
4115 /* enable LP_RX_TO again after the TE */
4116 REG_FLD_MOD(dsidev, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
4119 dsi->framedone_callback(error, dsi->framedone_data);
4122 dsi_perf_show(dsidev, "DISPC");
4125 static void dsi_framedone_timeout_work_callback(struct work_struct *work)
4127 struct dsi_data *dsi = container_of(work, struct dsi_data,
4128 framedone_timeout_work.work);
4129 /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after
4130 * 250ms which would conflict with this timeout work. What should be
4131 * done is first cancel the transfer on the HW, and then cancel the
4132 * possibly scheduled framedone work. However, cancelling the transfer
4133 * on the HW is buggy, and would probably require resetting the whole
4136 DSSERR("Framedone not received for 250ms!\n");
4138 dsi_handle_framedone(dsi->pdev, -ETIMEDOUT);
4141 static void dsi_framedone_irq_callback(void *data, u32 mask)
4143 struct omap_dss_device *dssdev = (struct omap_dss_device *) data;
4144 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4145 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4147 /* Note: We get FRAMEDONE when DISPC has finished sending pixels and
4148 * turns itself off. However, DSI still has the pixels in its buffers,
4149 * and is sending the data.
4152 __cancel_delayed_work(&dsi->framedone_timeout_work);
4154 dsi_handle_framedone(dsidev, 0);
4156 #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
4157 dispc_fake_vsync_irq();
4161 int omap_dsi_update(struct omap_dss_device *dssdev, int channel,
4162 void (*callback)(int, void *), void *data)
4164 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4165 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4168 dsi_perf_mark_setup(dsidev);
4170 dsi->update_channel = channel;
4172 dsi->framedone_callback = callback;
4173 dsi->framedone_data = data;
4175 dssdev->driver->get_resolution(dssdev, &dw, &dh);
4178 dsi->update_bytes = dw * dh *
4179 dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt) / 8;
4181 dsi_update_screen_dispc(dssdev, dw, dh);
4185 EXPORT_SYMBOL(omap_dsi_update);
4189 static int dsi_display_init_dispc(struct omap_dss_device *dssdev)
4193 if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) {
4196 struct omap_video_timings timings = {
4205 dssdev->driver->get_resolution(dssdev, &dw, &dh);
4209 irq = dssdev->manager->id == OMAP_DSS_CHANNEL_LCD ?
4210 DISPC_IRQ_FRAMEDONE : DISPC_IRQ_FRAMEDONE2;
4212 r = omap_dispc_register_isr(dsi_framedone_irq_callback,
4213 (void *) dssdev, irq);
4215 DSSERR("can't get FRAMEDONE irq\n");
4219 dispc_mgr_enable_stallmode(dssdev->manager->id, true);
4220 dispc_mgr_enable_fifohandcheck(dssdev->manager->id, 1);
4222 dispc_mgr_set_lcd_timings(dssdev->manager->id, &timings);
4224 dispc_mgr_enable_stallmode(dssdev->manager->id, false);
4225 dispc_mgr_enable_fifohandcheck(dssdev->manager->id, 0);
4227 dispc_mgr_set_lcd_timings(dssdev->manager->id,
4228 &dssdev->panel.timings);
4231 dispc_mgr_set_lcd_display_type(dssdev->manager->id,
4232 OMAP_DSS_LCD_DISPLAY_TFT);
4233 dispc_mgr_set_tft_data_lines(dssdev->manager->id,
4234 dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt));
4238 static void dsi_display_uninit_dispc(struct omap_dss_device *dssdev)
4240 if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) {
4243 irq = dssdev->manager->id == OMAP_DSS_CHANNEL_LCD ?
4244 DISPC_IRQ_FRAMEDONE : DISPC_IRQ_FRAMEDONE2;
4246 omap_dispc_unregister_isr(dsi_framedone_irq_callback,
4247 (void *) dssdev, irq);
4251 static int dsi_configure_dsi_clocks(struct omap_dss_device *dssdev)
4253 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4254 struct dsi_clock_info cinfo;
4257 cinfo.regn = dssdev->clocks.dsi.regn;
4258 cinfo.regm = dssdev->clocks.dsi.regm;
4259 cinfo.regm_dispc = dssdev->clocks.dsi.regm_dispc;
4260 cinfo.regm_dsi = dssdev->clocks.dsi.regm_dsi;
4261 r = dsi_calc_clock_rates(dsidev, &cinfo);
4263 DSSERR("Failed to calc dsi clocks\n");
4267 r = dsi_pll_set_clock_div(dsidev, &cinfo);
4269 DSSERR("Failed to set dsi clocks\n");
4276 static int dsi_configure_dispc_clocks(struct omap_dss_device *dssdev)
4278 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4279 struct dispc_clock_info dispc_cinfo;
4281 unsigned long long fck;
4283 fck = dsi_get_pll_hsdiv_dispc_rate(dsidev);
4285 dispc_cinfo.lck_div = dssdev->clocks.dispc.channel.lck_div;
4286 dispc_cinfo.pck_div = dssdev->clocks.dispc.channel.pck_div;
4288 r = dispc_calc_clock_rates(fck, &dispc_cinfo);
4290 DSSERR("Failed to calc dispc clocks\n");
4294 r = dispc_mgr_set_clock_div(dssdev->manager->id, &dispc_cinfo);
4296 DSSERR("Failed to set dispc clocks\n");
4303 static int dsi_display_init_dsi(struct omap_dss_device *dssdev)
4305 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4306 int dsi_module = dsi_get_dsidev_id(dsidev);
4309 r = dsi_parse_lane_config(dssdev);
4311 DSSERR("illegal lane config");
4315 r = dsi_pll_init(dsidev, true, true);
4319 r = dsi_configure_dsi_clocks(dssdev);
4323 dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src);
4324 dss_select_dsi_clk_source(dsi_module, dssdev->clocks.dsi.dsi_fclk_src);
4325 dss_select_lcd_clk_source(dssdev->manager->id,
4326 dssdev->clocks.dispc.channel.lcd_clk_src);
4330 r = dsi_configure_dispc_clocks(dssdev);
4334 r = dsi_cio_init(dssdev);
4338 _dsi_print_reset_status(dsidev);
4340 dsi_proto_timings(dssdev);
4341 dsi_set_lp_clk_divisor(dssdev);
4344 _dsi_print_reset_status(dsidev);
4346 r = dsi_proto_config(dssdev);
4350 /* enable interface */
4351 dsi_vc_enable(dsidev, 0, 1);
4352 dsi_vc_enable(dsidev, 1, 1);
4353 dsi_vc_enable(dsidev, 2, 1);
4354 dsi_vc_enable(dsidev, 3, 1);
4355 dsi_if_enable(dsidev, 1);
4356 dsi_force_tx_stop_mode_io(dsidev);
4360 dsi_cio_uninit(dssdev);
4362 dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
4363 dss_select_dsi_clk_source(dsi_module, OMAP_DSS_CLK_SRC_FCK);
4364 dss_select_lcd_clk_source(dssdev->manager->id, OMAP_DSS_CLK_SRC_FCK);
4367 dsi_pll_uninit(dsidev, true);
4372 static void dsi_display_uninit_dsi(struct omap_dss_device *dssdev,
4373 bool disconnect_lanes, bool enter_ulps)
4375 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4376 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4377 int dsi_module = dsi_get_dsidev_id(dsidev);
4379 if (enter_ulps && !dsi->ulps_enabled)
4380 dsi_enter_ulps(dsidev);
4382 /* disable interface */
4383 dsi_if_enable(dsidev, 0);
4384 dsi_vc_enable(dsidev, 0, 0);
4385 dsi_vc_enable(dsidev, 1, 0);
4386 dsi_vc_enable(dsidev, 2, 0);
4387 dsi_vc_enable(dsidev, 3, 0);
4389 dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
4390 dss_select_dsi_clk_source(dsi_module, OMAP_DSS_CLK_SRC_FCK);
4391 dss_select_lcd_clk_source(dssdev->manager->id, OMAP_DSS_CLK_SRC_FCK);
4392 dsi_cio_uninit(dssdev);
4393 dsi_pll_uninit(dsidev, disconnect_lanes);
4396 int omapdss_dsi_display_enable(struct omap_dss_device *dssdev)
4398 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4399 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4402 DSSDBG("dsi_display_enable\n");
4404 WARN_ON(!dsi_bus_is_locked(dsidev));
4406 mutex_lock(&dsi->lock);
4408 if (dssdev->manager == NULL) {
4409 DSSERR("failed to enable display: no manager\n");
4414 r = omap_dss_start_device(dssdev);
4416 DSSERR("failed to start device\n");
4420 r = dsi_runtime_get(dsidev);
4424 dsi_enable_pll_clock(dsidev, 1);
4426 _dsi_initialize_irq(dsidev);
4428 r = dsi_display_init_dispc(dssdev);
4430 goto err_init_dispc;
4432 r = dsi_display_init_dsi(dssdev);
4436 mutex_unlock(&dsi->lock);
4441 dsi_display_uninit_dispc(dssdev);
4443 dsi_enable_pll_clock(dsidev, 0);
4444 dsi_runtime_put(dsidev);
4446 omap_dss_stop_device(dssdev);
4448 mutex_unlock(&dsi->lock);
4449 DSSDBG("dsi_display_enable FAILED\n");
4452 EXPORT_SYMBOL(omapdss_dsi_display_enable);
4454 void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
4455 bool disconnect_lanes, bool enter_ulps)
4457 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4458 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4460 DSSDBG("dsi_display_disable\n");
4462 WARN_ON(!dsi_bus_is_locked(dsidev));
4464 mutex_lock(&dsi->lock);
4466 dsi_sync_vc(dsidev, 0);
4467 dsi_sync_vc(dsidev, 1);
4468 dsi_sync_vc(dsidev, 2);
4469 dsi_sync_vc(dsidev, 3);
4471 dsi_display_uninit_dispc(dssdev);
4473 dsi_display_uninit_dsi(dssdev, disconnect_lanes, enter_ulps);
4475 dsi_runtime_put(dsidev);
4476 dsi_enable_pll_clock(dsidev, 0);
4478 omap_dss_stop_device(dssdev);
4480 mutex_unlock(&dsi->lock);
4482 EXPORT_SYMBOL(omapdss_dsi_display_disable);
4484 int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable)
4486 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4487 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4489 dsi->te_enabled = enable;
4492 EXPORT_SYMBOL(omapdss_dsi_enable_te);
4494 int dsi_init_display(struct omap_dss_device *dssdev)
4496 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4497 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4499 DSSDBG("DSI init\n");
4501 if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) {
4502 dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE |
4503 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM;
4506 if (dsi->vdds_dsi_reg == NULL) {
4507 struct regulator *vdds_dsi;
4509 vdds_dsi = regulator_get(&dsi->pdev->dev, "vdds_dsi");
4511 if (IS_ERR(vdds_dsi)) {
4512 DSSERR("can't get VDDS_DSI regulator\n");
4513 return PTR_ERR(vdds_dsi);
4516 dsi->vdds_dsi_reg = vdds_dsi;
4522 int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel)
4524 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4525 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4528 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
4529 if (!dsi->vc[i].dssdev) {
4530 dsi->vc[i].dssdev = dssdev;
4536 DSSERR("cannot get VC for display %s", dssdev->name);
4539 EXPORT_SYMBOL(omap_dsi_request_vc);
4541 int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id)
4543 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4544 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4546 if (vc_id < 0 || vc_id > 3) {
4547 DSSERR("VC ID out of range\n");
4551 if (channel < 0 || channel > 3) {
4552 DSSERR("Virtual Channel out of range\n");
4556 if (dsi->vc[channel].dssdev != dssdev) {
4557 DSSERR("Virtual Channel not allocated to display %s\n",
4562 dsi->vc[channel].vc_id = vc_id;
4566 EXPORT_SYMBOL(omap_dsi_set_vc_id);
4568 void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel)
4570 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4571 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4573 if ((channel >= 0 && channel <= 3) &&
4574 dsi->vc[channel].dssdev == dssdev) {
4575 dsi->vc[channel].dssdev = NULL;
4576 dsi->vc[channel].vc_id = 0;
4579 EXPORT_SYMBOL(omap_dsi_release_vc);
4581 void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev)
4583 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 7, 1) != 1)
4584 DSSERR("%s (%s) not active\n",
4585 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
4586 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC));
4589 void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev)
4591 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 8, 1) != 1)
4592 DSSERR("%s (%s) not active\n",
4593 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
4594 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI));
4597 static void dsi_calc_clock_param_ranges(struct platform_device *dsidev)
4599 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4601 dsi->regn_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGN);
4602 dsi->regm_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM);
4603 dsi->regm_dispc_max =
4604 dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DISPC);
4605 dsi->regm_dsi_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DSI);
4606 dsi->fint_min = dss_feat_get_param_min(FEAT_PARAM_DSIPLL_FINT);
4607 dsi->fint_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_FINT);
4608 dsi->lpdiv_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV);
4611 static int dsi_get_clocks(struct platform_device *dsidev)
4613 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4616 clk = clk_get(&dsidev->dev, "fck");
4618 DSSERR("can't get fck\n");
4619 return PTR_ERR(clk);
4624 clk = clk_get(&dsidev->dev, "sys_clk");
4626 DSSERR("can't get sys_clk\n");
4627 clk_put(dsi->dss_clk);
4628 dsi->dss_clk = NULL;
4629 return PTR_ERR(clk);
4637 static void dsi_put_clocks(struct platform_device *dsidev)
4639 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4642 clk_put(dsi->dss_clk);
4644 clk_put(dsi->sys_clk);
4647 /* DSI1 HW IP initialisation */
4648 static int omap_dsihw_probe(struct platform_device *dsidev)
4650 struct omap_display_platform_data *dss_plat_data;
4651 struct omap_dss_board_info *board_info;
4653 int r, i, dsi_module = dsi_get_dsidev_id(dsidev);
4654 struct resource *dsi_mem;
4655 struct dsi_data *dsi;
4657 dsi = devm_kzalloc(&dsidev->dev, sizeof(*dsi), GFP_KERNEL);
4662 dsi_pdev_map[dsi_module] = dsidev;
4663 dev_set_drvdata(&dsidev->dev, dsi);
4665 dss_plat_data = dsidev->dev.platform_data;
4666 board_info = dss_plat_data->board_data;
4667 dsi->enable_pads = board_info->dsi_enable_pads;
4668 dsi->disable_pads = board_info->dsi_disable_pads;
4670 spin_lock_init(&dsi->irq_lock);
4671 spin_lock_init(&dsi->errors_lock);
4674 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
4675 spin_lock_init(&dsi->irq_stats_lock);
4676 dsi->irq_stats.last_reset = jiffies;
4679 mutex_init(&dsi->lock);
4680 sema_init(&dsi->bus_lock, 1);
4682 INIT_DELAYED_WORK_DEFERRABLE(&dsi->framedone_timeout_work,
4683 dsi_framedone_timeout_work_callback);
4685 #ifdef DSI_CATCH_MISSING_TE
4686 init_timer(&dsi->te_timer);
4687 dsi->te_timer.function = dsi_te_timeout;
4688 dsi->te_timer.data = 0;
4690 dsi_mem = platform_get_resource(dsi->pdev, IORESOURCE_MEM, 0);
4692 DSSERR("can't get IORESOURCE_MEM DSI\n");
4696 dsi->base = devm_ioremap(&dsidev->dev, dsi_mem->start,
4697 resource_size(dsi_mem));
4699 DSSERR("can't ioremap DSI\n");
4703 dsi->irq = platform_get_irq(dsi->pdev, 0);
4705 DSSERR("platform_get_irq failed\n");
4709 r = devm_request_irq(&dsidev->dev, dsi->irq, omap_dsi_irq_handler,
4710 IRQF_SHARED, dev_name(&dsidev->dev), dsi->pdev);
4712 DSSERR("request_irq failed\n");
4716 /* DSI VCs initialization */
4717 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
4718 dsi->vc[i].source = DSI_VC_SOURCE_L4;
4719 dsi->vc[i].dssdev = NULL;
4720 dsi->vc[i].vc_id = 0;
4723 dsi_calc_clock_param_ranges(dsidev);
4725 r = dsi_get_clocks(dsidev);
4729 pm_runtime_enable(&dsidev->dev);
4731 r = dsi_runtime_get(dsidev);
4733 goto err_runtime_get;
4735 rev = dsi_read_reg(dsidev, DSI_REVISION);
4736 dev_dbg(&dsidev->dev, "OMAP DSI rev %d.%d\n",
4737 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
4739 /* DSI on OMAP3 doesn't have register DSI_GNQ, set number
4740 * of data to 3 by default */
4741 if (dss_has_feature(FEAT_DSI_GNQ))
4743 dsi->num_lanes_supported = 1 + REG_GET(dsidev, DSI_GNQ, 11, 9);
4745 dsi->num_lanes_supported = 3;
4747 dsi_runtime_put(dsidev);
4752 pm_runtime_disable(&dsidev->dev);
4753 dsi_put_clocks(dsidev);
4757 static int omap_dsihw_remove(struct platform_device *dsidev)
4759 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4761 WARN_ON(dsi->scp_clk_refcount > 0);
4763 pm_runtime_disable(&dsidev->dev);
4765 dsi_put_clocks(dsidev);
4767 if (dsi->vdds_dsi_reg != NULL) {
4768 if (dsi->vdds_dsi_enabled) {
4769 regulator_disable(dsi->vdds_dsi_reg);
4770 dsi->vdds_dsi_enabled = false;
4773 regulator_put(dsi->vdds_dsi_reg);
4774 dsi->vdds_dsi_reg = NULL;
4780 static int dsi_runtime_suspend(struct device *dev)
4782 dispc_runtime_put();
4788 static int dsi_runtime_resume(struct device *dev)
4792 r = dss_runtime_get();
4796 r = dispc_runtime_get();
4808 static const struct dev_pm_ops dsi_pm_ops = {
4809 .runtime_suspend = dsi_runtime_suspend,
4810 .runtime_resume = dsi_runtime_resume,
4813 static struct platform_driver omap_dsihw_driver = {
4814 .probe = omap_dsihw_probe,
4815 .remove = omap_dsihw_remove,
4817 .name = "omapdss_dsi",
4818 .owner = THIS_MODULE,
4823 int dsi_init_platform_driver(void)
4825 return platform_driver_register(&omap_dsihw_driver);
4828 void dsi_uninit_platform_driver(void)
4830 return platform_driver_unregister(&omap_dsihw_driver);