drivers/video/omap2/dss/dsi.c

   1 /*
   2  * linux/drivers/video/omap2/dss/dsi.c
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 as published by
   9  * the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #define DSS_SUBSYS_NAME "DSI"
  21
  22 #include <linux/kernel.h>
  23 #include <linux/io.h>
  24 #include <linux/clk.h>
  25 #include <linux/device.h>
  26 #include <linux/err.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/delay.h>
  29 #include <linux/mutex.h>
  30 #include <linux/module.h>
  31 #include <linux/semaphore.h>
  32 #include <linux/seq_file.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/regulator/consumer.h>
  35 #include <linux/wait.h>
  36 #include <linux/workqueue.h>
  37 #include <linux/sched.h>
  38 #include <linux/slab.h>
  39 #include <linux/debugfs.h>
  40 #include <linux/pm_runtime.h>
  41
  42 #include <video/omapdss.h>
  43 #include <video/mipi_display.h>
  44 #include <plat/clock.h>
  45
  46 #include "dss.h"
  47 #include "dss_features.h"
  48
  49 /*#define VERBOSE_IRQ*/
  50 #define DSI_CATCH_MISSING_TE
  51
  52 struct dsi_reg { u16 idx; };
  53
  54 #define DSI_REG(idx)            ((const struct dsi_reg) { idx })
  55
  56 #define DSI_SZ_REGS             SZ_1K
  57 /* DSI Protocol Engine */
  58
  59 #define DSI_REVISION                    DSI_REG(0x0000)
  60 #define DSI_SYSCONFIG                   DSI_REG(0x0010)
  61 #define DSI_SYSSTATUS                   DSI_REG(0x0014)
  62 #define DSI_IRQSTATUS                   DSI_REG(0x0018)
  63 #define DSI_IRQENABLE                   DSI_REG(0x001C)
  64 #define DSI_CTRL                        DSI_REG(0x0040)
  65 #define DSI_GNQ                         DSI_REG(0x0044)
  66 #define DSI_COMPLEXIO_CFG1              DSI_REG(0x0048)
  67 #define DSI_COMPLEXIO_IRQ_STATUS        DSI_REG(0x004C)
  68 #define DSI_COMPLEXIO_IRQ_ENABLE        DSI_REG(0x0050)
  69 #define DSI_CLK_CTRL                    DSI_REG(0x0054)
  70 #define DSI_TIMING1                     DSI_REG(0x0058)
  71 #define DSI_TIMING2                     DSI_REG(0x005C)
  72 #define DSI_VM_TIMING1                  DSI_REG(0x0060)
  73 #define DSI_VM_TIMING2                  DSI_REG(0x0064)
  74 #define DSI_VM_TIMING3                  DSI_REG(0x0068)
  75 #define DSI_CLK_TIMING                  DSI_REG(0x006C)
  76 #define DSI_TX_FIFO_VC_SIZE             DSI_REG(0x0070)
  77 #define DSI_RX_FIFO_VC_SIZE             DSI_REG(0x0074)
  78 #define DSI_COMPLEXIO_CFG2              DSI_REG(0x0078)
  79 #define DSI_RX_FIFO_VC_FULLNESS         DSI_REG(0x007C)
  80 #define DSI_VM_TIMING4                  DSI_REG(0x0080)
  81 #define DSI_TX_FIFO_VC_EMPTINESS        DSI_REG(0x0084)
  82 #define DSI_VM_TIMING5                  DSI_REG(0x0088)
  83 #define DSI_VM_TIMING6                  DSI_REG(0x008C)
  84 #define DSI_VM_TIMING7                  DSI_REG(0x0090)
  85 #define DSI_STOPCLK_TIMING              DSI_REG(0x0094)
  86 #define DSI_VC_CTRL(n)                  DSI_REG(0x0100 + (n * 0x20))
  87 #define DSI_VC_TE(n)                    DSI_REG(0x0104 + (n * 0x20))
  88 #define DSI_VC_LONG_PACKET_HEADER(n)    DSI_REG(0x0108 + (n * 0x20))
  89 #define DSI_VC_LONG_PACKET_PAYLOAD(n)   DSI_REG(0x010C + (n * 0x20))
  90 #define DSI_VC_SHORT_PACKET_HEADER(n)   DSI_REG(0x0110 + (n * 0x20))
  91 #define DSI_VC_IRQSTATUS(n)             DSI_REG(0x0118 + (n * 0x20))
  92 #define DSI_VC_IRQENABLE(n)             DSI_REG(0x011C + (n * 0x20))
  93
  94 /* DSIPHY_SCP */
  95
  96 #define DSI_DSIPHY_CFG0                 DSI_REG(0x200 + 0x0000)
  97 #define DSI_DSIPHY_CFG1                 DSI_REG(0x200 + 0x0004)
  98 #define DSI_DSIPHY_CFG2                 DSI_REG(0x200 + 0x0008)
  99 #define DSI_DSIPHY_CFG5                 DSI_REG(0x200 + 0x0014)
 100 #define DSI_DSIPHY_CFG10                DSI_REG(0x200 + 0x0028)
 101
 102 /* DSI_PLL_CTRL_SCP */
 103
 104 #define DSI_PLL_CONTROL                 DSI_REG(0x300 + 0x0000)
 105 #define DSI_PLL_STATUS                  DSI_REG(0x300 + 0x0004)
 106 #define DSI_PLL_GO                      DSI_REG(0x300 + 0x0008)
 107 #define DSI_PLL_CONFIGURATION1          DSI_REG(0x300 + 0x000C)
 108 #define DSI_PLL_CONFIGURATION2          DSI_REG(0x300 + 0x0010)
 109
 110 #define REG_GET(dsidev, idx, start, end) \
 111         FLD_GET(dsi_read_reg(dsidev, idx), start, end)
 112
 113 #define REG_FLD_MOD(dsidev, idx, val, start, end) \
 114         dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end))
 115
 116 /* Global interrupts */
 117 #define DSI_IRQ_VC0             (1 << 0)
 118 #define DSI_IRQ_VC1             (1 << 1)
 119 #define DSI_IRQ_VC2             (1 << 2)
 120 #define DSI_IRQ_VC3             (1 << 3)
 121 #define DSI_IRQ_WAKEUP          (1 << 4)
 122 #define DSI_IRQ_RESYNC          (1 << 5)
 123 #define DSI_IRQ_PLL_LOCK        (1 << 7)
 124 #define DSI_IRQ_PLL_UNLOCK      (1 << 8)
 125 #define DSI_IRQ_PLL_RECALL      (1 << 9)
 126 #define DSI_IRQ_COMPLEXIO_ERR   (1 << 10)
 127 #define DSI_IRQ_HS_TX_TIMEOUT   (1 << 14)
 128 #define DSI_IRQ_LP_RX_TIMEOUT   (1 << 15)
 129 #define DSI_IRQ_TE_TRIGGER      (1 << 16)
 130 #define DSI_IRQ_ACK_TRIGGER     (1 << 17)
 131 #define DSI_IRQ_SYNC_LOST       (1 << 18)
 132 #define DSI_IRQ_LDO_POWER_GOOD  (1 << 19)
 133 #define DSI_IRQ_TA_TIMEOUT      (1 << 20)
 134 #define DSI_IRQ_ERROR_MASK \
 135         (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
 136         DSI_IRQ_TA_TIMEOUT | DSI_IRQ_SYNC_LOST)
 137 #define DSI_IRQ_CHANNEL_MASK    0xf
 138
 139 /* Virtual channel interrupts */
 140 #define DSI_VC_IRQ_CS           (1 << 0)
 141 #define DSI_VC_IRQ_ECC_CORR     (1 << 1)
 142 #define DSI_VC_IRQ_PACKET_SENT  (1 << 2)
 143 #define DSI_VC_IRQ_FIFO_TX_OVF  (1 << 3)
 144 #define DSI_VC_IRQ_FIFO_RX_OVF  (1 << 4)
 145 #define DSI_VC_IRQ_BTA          (1 << 5)
 146 #define DSI_VC_IRQ_ECC_NO_CORR  (1 << 6)
 147 #define DSI_VC_IRQ_FIFO_TX_UDF  (1 << 7)
 148 #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
 149 #define DSI_VC_IRQ_ERROR_MASK \
 150         (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
 151         DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
 152         DSI_VC_IRQ_FIFO_TX_UDF)
 153
 154 /* ComplexIO interrupts */
 155 #define DSI_CIO_IRQ_ERRSYNCESC1         (1 << 0)
 156 #define DSI_CIO_IRQ_ERRSYNCESC2         (1 << 1)
 157 #define DSI_CIO_IRQ_ERRSYNCESC3         (1 << 2)
 158 #define DSI_CIO_IRQ_ERRSYNCESC4         (1 << 3)
 159 #define DSI_CIO_IRQ_ERRSYNCESC5         (1 << 4)
 160 #define DSI_CIO_IRQ_ERRESC1             (1 << 5)
 161 #define DSI_CIO_IRQ_ERRESC2             (1 << 6)
 162 #define DSI_CIO_IRQ_ERRESC3             (1 << 7)
 163 #define DSI_CIO_IRQ_ERRESC4             (1 << 8)
 164 #define DSI_CIO_IRQ_ERRESC5             (1 << 9)
 165 #define DSI_CIO_IRQ_ERRCONTROL1         (1 << 10)
 166 #define DSI_CIO_IRQ_ERRCONTROL2         (1 << 11)
 167 #define DSI_CIO_IRQ_ERRCONTROL3         (1 << 12)
 168 #define DSI_CIO_IRQ_ERRCONTROL4         (1 << 13)
 169 #define DSI_CIO_IRQ_ERRCONTROL5         (1 << 14)
 170 #define DSI_CIO_IRQ_STATEULPS1          (1 << 15)
 171 #define DSI_CIO_IRQ_STATEULPS2          (1 << 16)
 172 #define DSI_CIO_IRQ_STATEULPS3          (1 << 17)
 173 #define DSI_CIO_IRQ_STATEULPS4          (1 << 18)
 174 #define DSI_CIO_IRQ_STATEULPS5          (1 << 19)
 175 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1  (1 << 20)
 176 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1  (1 << 21)
 177 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2  (1 << 22)
 178 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2  (1 << 23)
 179 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3  (1 << 24)
 180 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3  (1 << 25)
 181 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_4  (1 << 26)
 182 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_4  (1 << 27)
 183 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_5  (1 << 28)
 184 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_5  (1 << 29)
 185 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0  (1 << 30)
 186 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1  (1 << 31)
 187 #define DSI_CIO_IRQ_ERROR_MASK \
 188         (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \
 189          DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \
 190          DSI_CIO_IRQ_ERRSYNCESC5 | \
 191          DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \
 192          DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \
 193          DSI_CIO_IRQ_ERRESC5 | \
 194          DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \
 195          DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \
 196          DSI_CIO_IRQ_ERRCONTROL5 | \
 197          DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \
 198          DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \
 199          DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \
 200          DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \
 201          DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5)
 202
 203 typedef void (*omap_dsi_isr_t) (void *arg, u32 mask);
 204
 205 #define DSI_MAX_NR_ISRS                2
 206 #define DSI_MAX_NR_LANES        5
 207
 208 enum dsi_lane_function {
 209         DSI_LANE_UNUSED = 0,
 210         DSI_LANE_CLK,
 211         DSI_LANE_DATA1,
 212         DSI_LANE_DATA2,
 213         DSI_LANE_DATA3,
 214         DSI_LANE_DATA4,
 215 };
 216
 217 struct dsi_lane_config {
 218         enum dsi_lane_function function;
 219         u8 polarity;
 220 };
 221
 222 struct dsi_isr_data {
 223         omap_dsi_isr_t  isr;
 224         void            *arg;
 225         u32             mask;
 226 };
 227
 228 enum fifo_size {
 229         DSI_FIFO_SIZE_0         = 0,
 230         DSI_FIFO_SIZE_32        = 1,
 231         DSI_FIFO_SIZE_64        = 2,
 232         DSI_FIFO_SIZE_96        = 3,
 233         DSI_FIFO_SIZE_128       = 4,
 234 };
 235
 236 enum dsi_vc_source {
 237         DSI_VC_SOURCE_L4 = 0,
 238         DSI_VC_SOURCE_VP,
 239 };
 240
 241 struct dsi_irq_stats {
 242         unsigned long last_reset;
 243         unsigned irq_count;
 244         unsigned dsi_irqs[32];
 245         unsigned vc_irqs[4][32];
 246         unsigned cio_irqs[32];
 247 };
 248
 249 struct dsi_isr_tables {
 250         struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS];
 251         struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS];
 252         struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS];
 253 };
 254
 255 struct dsi_data {
 256         struct platform_device *pdev;
 257         void __iomem    *base;
 258
 259         int irq;
 260
 261         struct clk *dss_clk;
 262         struct clk *sys_clk;
 263
 264         int (*enable_pads)(int dsi_id, unsigned lane_mask);
 265         void (*disable_pads)(int dsi_id, unsigned lane_mask);
 266
 267         struct dsi_clock_info current_cinfo;
 268
 269         bool vdds_dsi_enabled;
 270         struct regulator *vdds_dsi_reg;
 271
 272         struct {
 273                 enum dsi_vc_source source;
 274                 struct omap_dss_device *dssdev;
 275                 enum fifo_size fifo_size;
 276                 int vc_id;
 277         } vc[4];
 278
 279         struct mutex lock;
 280         struct semaphore bus_lock;
 281
 282         unsigned pll_locked;
 283
 284         spinlock_t irq_lock;
 285         struct dsi_isr_tables isr_tables;
 286         /* space for a copy used by the interrupt handler */
 287         struct dsi_isr_tables isr_tables_copy;
 288
 289         int update_channel;
 290 #ifdef DEBUG
 291         unsigned update_bytes;
 292 #endif
 293
 294         bool te_enabled;
 295         bool ulps_enabled;
 296
 297         void (*framedone_callback)(int, void *);
 298         void *framedone_data;
 299
 300         struct delayed_work framedone_timeout_work;
 301
 302 #ifdef DSI_CATCH_MISSING_TE
 303         struct timer_list te_timer;
 304 #endif
 305
 306         unsigned long cache_req_pck;
 307         unsigned long cache_clk_freq;
 308         struct dsi_clock_info cache_cinfo;
 309
 310         u32             errors;
 311         spinlock_t      errors_lock;
 312 #ifdef DEBUG
 313         ktime_t perf_setup_time;
 314         ktime_t perf_start_time;
 315 #endif
 316         int debug_read;
 317         int debug_write;
 318
 319 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
 320         spinlock_t irq_stats_lock;
 321         struct dsi_irq_stats irq_stats;
 322 #endif
 323         /* DSI PLL Parameter Ranges */
 324         unsigned long regm_max, regn_max;
 325         unsigned long  regm_dispc_max, regm_dsi_max;
 326         unsigned long  fint_min, fint_max;
 327         unsigned long lpdiv_max;
 328
 329         unsigned num_lanes_supported;
 330
 331         struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
 332         unsigned num_lanes_used;
 333
 334         unsigned scp_clk_refcount;
 335 };
 336
 337 struct dsi_packet_sent_handler_data {
 338         struct platform_device *dsidev;
 339         struct completion *completion;
 340 };
 341
 342 static struct platform_device *dsi_pdev_map[MAX_NUM_DSI];
 343
 344 #ifdef DEBUG
 345 static bool dsi_perf;
 346 module_param(dsi_perf, bool, 0644);
 347 #endif
 348
 349 static inline struct dsi_data *dsi_get_dsidrv_data(struct platform_device *dsidev)
 350 {
 351         return dev_get_drvdata(&dsidev->dev);
 352 }
 353
 354 static inline struct platform_device *dsi_get_dsidev_from_dssdev(struct omap_dss_device *dssdev)
 355 {
 356         return dsi_pdev_map[dssdev->phy.dsi.module];
 357 }
 358
 359 struct platform_device *dsi_get_dsidev_from_id(int module)
 360 {
 361         return dsi_pdev_map[module];
 362 }
 363
 364 static inline int dsi_get_dsidev_id(struct platform_device *dsidev)
 365 {
 366         return dsidev->id;
 367 }
 368
 369 static inline void dsi_write_reg(struct platform_device *dsidev,
 370                 const struct dsi_reg idx, u32 val)
 371 {
 372         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 373
 374         __raw_writel(val, dsi->base + idx.idx);
 375 }
 376
 377 static inline u32 dsi_read_reg(struct platform_device *dsidev,
 378                 const struct dsi_reg idx)
 379 {
 380         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 381
 382         return __raw_readl(dsi->base + idx.idx);
 383 }
 384
 385 void dsi_bus_lock(struct omap_dss_device *dssdev)
 386 {
 387         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
 388         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 389
 390         down(&dsi->bus_lock);
 391 }
 392 EXPORT_SYMBOL(dsi_bus_lock);
 393
 394 void dsi_bus_unlock(struct omap_dss_device *dssdev)
 395 {
 396         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
 397         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 398
 399         up(&dsi->bus_lock);
 400 }
 401 EXPORT_SYMBOL(dsi_bus_unlock);
 402
 403 static bool dsi_bus_is_locked(struct platform_device *dsidev)
 404 {
 405         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 406
 407         return dsi->bus_lock.count == 0;
 408 }
 409
 410 static void dsi_completion_handler(void *data, u32 mask)
 411 {
 412         complete((struct completion *)data);
 413 }
 414
 415 static inline int wait_for_bit_change(struct platform_device *dsidev,
 416                 const struct dsi_reg idx, int bitnum, int value)
 417 {
 418         unsigned long timeout;
 419         ktime_t wait;
 420         int t;
 421
 422         /* first busyloop to see if the bit changes right away */
 423         t = 100;
 424         while (t-- > 0) {
 425                 if (REG_GET(dsidev, idx, bitnum, bitnum) == value)
 426                         return value;
 427         }
 428
 429         /* then loop for 500ms, sleeping for 1ms in between */
 430         timeout = jiffies + msecs_to_jiffies(500);
 431         while (time_before(jiffies, timeout)) {
 432                 if (REG_GET(dsidev, idx, bitnum, bitnum) == value)
 433                         return value;
 434
 435                 wait = ns_to_ktime(1000 * 1000);
 436                 set_current_state(TASK_UNINTERRUPTIBLE);
 437                 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
 438         }
 439
 440         return !value;
 441 }
 442
 443 u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
 444 {
 445         switch (fmt) {
 446         case OMAP_DSS_DSI_FMT_RGB888:
 447         case OMAP_DSS_DSI_FMT_RGB666:
 448                 return 24;
 449         case OMAP_DSS_DSI_FMT_RGB666_PACKED:
 450                 return 18;
 451         case OMAP_DSS_DSI_FMT_RGB565:
 452                 return 16;
 453         default:
 454                 BUG();
 455         }
 456 }
 457
 458 #ifdef DEBUG
 459 static void dsi_perf_mark_setup(struct platform_device *dsidev)
 460 {
 461         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 462         dsi->perf_setup_time = ktime_get();
 463 }
 464
 465 static void dsi_perf_mark_start(struct platform_device *dsidev)
 466 {
 467         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 468         dsi->perf_start_time = ktime_get();
 469 }
 470
 471 static void dsi_perf_show(struct platform_device *dsidev, const char *name)
 472 {
 473         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 474         ktime_t t, setup_time, trans_time;
 475         u32 total_bytes;
 476         u32 setup_us, trans_us, total_us;
 477
 478         if (!dsi_perf)
 479                 return;
 480
 481         t = ktime_get();
 482
 483         setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time);
 484         setup_us = (u32)ktime_to_us(setup_time);
 485         if (setup_us == 0)
 486                 setup_us = 1;
 487
 488         trans_time = ktime_sub(t, dsi->perf_start_time);
 489         trans_us = (u32)ktime_to_us(trans_time);
 490         if (trans_us == 0)
 491                 trans_us = 1;
 492
 493         total_us = setup_us + trans_us;
 494
 495         total_bytes = dsi->update_bytes;
 496
 497         printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), "
 498                         "%u bytes, %u kbytes/sec\n",
 499                         name,
 500                         setup_us,
 501                         trans_us,
 502                         total_us,
 503                         1000*1000 / total_us,
 504                         total_bytes,
 505                         total_bytes * 1000 / total_us);
 506 }
 507 #else
 508 static inline void dsi_perf_mark_setup(struct platform_device *dsidev)
 509 {
 510 }
 511
 512 static inline void dsi_perf_mark_start(struct platform_device *dsidev)
 513 {
 514 }
 515
 516 static inline void dsi_perf_show(struct platform_device *dsidev,
 517                 const char *name)
 518 {
 519 }
 520 #endif
 521
 522 static void print_irq_status(u32 status)
 523 {
 524         if (status == 0)
 525                 return;
 526
 527 #ifndef VERBOSE_IRQ
 528         if ((status & ~DSI_IRQ_CHANNEL_MASK) == 0)
 529                 return;
 530 #endif
 531         printk(KERN_DEBUG "DSI IRQ: 0x%x: ", status);
 532
 533 #define PIS(x) \
 534         if (status & DSI_IRQ_##x) \
 535                 printk(#x " ");
 536 #ifdef VERBOSE_IRQ
 537         PIS(VC0);
 538         PIS(VC1);
 539         PIS(VC2);
 540         PIS(VC3);
 541 #endif
 542         PIS(WAKEUP);
 543         PIS(RESYNC);
 544         PIS(PLL_LOCK);
 545         PIS(PLL_UNLOCK);
 546         PIS(PLL_RECALL);
 547         PIS(COMPLEXIO_ERR);
 548         PIS(HS_TX_TIMEOUT);
 549         PIS(LP_RX_TIMEOUT);
 550         PIS(TE_TRIGGER);
 551         PIS(ACK_TRIGGER);
 552         PIS(SYNC_LOST);
 553         PIS(LDO_POWER_GOOD);
 554         PIS(TA_TIMEOUT);
 555 #undef PIS
 556
 557         printk("\n");
 558 }
 559
 560 static void print_irq_status_vc(int channel, u32 status)
 561 {
 562         if (status == 0)
 563                 return;
 564
 565 #ifndef VERBOSE_IRQ
 566         if ((status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
 567                 return;
 568 #endif
 569         printk(KERN_DEBUG "DSI VC(%d) IRQ 0x%x: ", channel, status);
 570
 571 #define PIS(x) \
 572         if (status & DSI_VC_IRQ_##x) \
 573                 printk(#x " ");
 574         PIS(CS);
 575         PIS(ECC_CORR);
 576 #ifdef VERBOSE_IRQ
 577         PIS(PACKET_SENT);
 578 #endif
 579         PIS(FIFO_TX_OVF);
 580         PIS(FIFO_RX_OVF);
 581         PIS(BTA);
 582         PIS(ECC_NO_CORR);
 583         PIS(FIFO_TX_UDF);
 584         PIS(PP_BUSY_CHANGE);
 585 #undef PIS
 586         printk("\n");
 587 }
 588
 589 static void print_irq_status_cio(u32 status)
 590 {
 591         if (status == 0)
 592                 return;
 593
 594         printk(KERN_DEBUG "DSI CIO IRQ 0x%x: ", status);
 595
 596 #define PIS(x) \
 597         if (status & DSI_CIO_IRQ_##x) \
 598                 printk(#x " ");
 599         PIS(ERRSYNCESC1);
 600         PIS(ERRSYNCESC2);
 601         PIS(ERRSYNCESC3);
 602         PIS(ERRESC1);
 603         PIS(ERRESC2);
 604         PIS(ERRESC3);
 605         PIS(ERRCONTROL1);
 606         PIS(ERRCONTROL2);
 607         PIS(ERRCONTROL3);
 608         PIS(STATEULPS1);
 609         PIS(STATEULPS2);
 610         PIS(STATEULPS3);
 611         PIS(ERRCONTENTIONLP0_1);
 612         PIS(ERRCONTENTIONLP1_1);
 613         PIS(ERRCONTENTIONLP0_2);
 614         PIS(ERRCONTENTIONLP1_2);
 615         PIS(ERRCONTENTIONLP0_3);
 616         PIS(ERRCONTENTIONLP1_3);
 617         PIS(ULPSACTIVENOT_ALL0);
 618         PIS(ULPSACTIVENOT_ALL1);
 619 #undef PIS
 620
 621         printk("\n");
 622 }
 623
 624 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
 625 static void dsi_collect_irq_stats(struct platform_device *dsidev, u32 irqstatus,
 626                 u32 *vcstatus, u32 ciostatus)
 627 {
 628         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 629         int i;
 630
 631         spin_lock(&dsi->irq_stats_lock);
 632
 633         dsi->irq_stats.irq_count++;
 634         dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs);
 635
 636         for (i = 0; i < 4; ++i)
 637                 dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]);
 638
 639         dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs);
 640
 641         spin_unlock(&dsi->irq_stats_lock);
 642 }
 643 #else
 644 #define dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus)
 645 #endif
 646
 647 static int debug_irq;
 648
 649 static void dsi_handle_irq_errors(struct platform_device *dsidev, u32 irqstatus,
 650                 u32 *vcstatus, u32 ciostatus)
 651 {
 652         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 653         int i;
 654
 655         if (irqstatus & DSI_IRQ_ERROR_MASK) {
 656                 DSSERR("DSI error, irqstatus %x\n", irqstatus);
 657                 print_irq_status(irqstatus);
 658                 spin_lock(&dsi->errors_lock);
 659                 dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK;
 660                 spin_unlock(&dsi->errors_lock);
 661         } else if (debug_irq) {
 662                 print_irq_status(irqstatus);
 663         }
 664
 665         for (i = 0; i < 4; ++i) {
 666                 if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) {
 667                         DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
 668                                        i, vcstatus[i]);
 669                         print_irq_status_vc(i, vcstatus[i]);
 670                 } else if (debug_irq) {
 671                         print_irq_status_vc(i, vcstatus[i]);
 672                 }
 673         }
 674
 675         if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) {
 676                 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
 677                 print_irq_status_cio(ciostatus);
 678         } else if (debug_irq) {
 679                 print_irq_status_cio(ciostatus);
 680         }
 681 }
 682
 683 static void dsi_call_isrs(struct dsi_isr_data *isr_array,
 684                 unsigned isr_array_size, u32 irqstatus)
 685 {
 686         struct dsi_isr_data *isr_data;
 687         int i;
 688
 689         for (i = 0; i < isr_array_size; i++) {
 690                 isr_data = &isr_array[i];
 691                 if (isr_data->isr && isr_data->mask & irqstatus)
 692                         isr_data->isr(isr_data->arg, irqstatus);
 693         }
 694 }
 695
 696 static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables,
 697                 u32 irqstatus, u32 *vcstatus, u32 ciostatus)
 698 {
 699         int i;
 700
 701         dsi_call_isrs(isr_tables->isr_table,
 702                         ARRAY_SIZE(isr_tables->isr_table),
 703                         irqstatus);
 704
 705         for (i = 0; i < 4; ++i) {
 706                 if (vcstatus[i] == 0)
 707                         continue;
 708                 dsi_call_isrs(isr_tables->isr_table_vc[i],
 709                                 ARRAY_SIZE(isr_tables->isr_table_vc[i]),
 710                                 vcstatus[i]);
 711         }
 712
 713         if (ciostatus != 0)
 714                 dsi_call_isrs(isr_tables->isr_table_cio,
 715                                 ARRAY_SIZE(isr_tables->isr_table_cio),
 716                                 ciostatus);
 717 }
 718
 719 static irqreturn_t omap_dsi_irq_handler(int irq, void *arg)
 720 {
 721         struct platform_device *dsidev;
 722         struct dsi_data *dsi;
 723         u32 irqstatus, vcstatus[4], ciostatus;
 724         int i;
 725
 726         dsidev = (struct platform_device *) arg;
 727         dsi = dsi_get_dsidrv_data(dsidev);
 728
 729         spin_lock(&dsi->irq_lock);
 730
 731         irqstatus = dsi_read_reg(dsidev, DSI_IRQSTATUS);
 732
 733         /* IRQ is not for us */
 734         if (!irqstatus) {
 735                 spin_unlock(&dsi->irq_lock);
 736                 return IRQ_NONE;
 737         }
 738
 739         dsi_write_reg(dsidev, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
 740         /* flush posted write */
 741         dsi_read_reg(dsidev, DSI_IRQSTATUS);
 742
 743         for (i = 0; i < 4; ++i) {
 744                 if ((irqstatus & (1 << i)) == 0) {
 745                         vcstatus[i] = 0;
 746                         continue;
 747                 }
 748
 749                 vcstatus[i] = dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
 750
 751                 dsi_write_reg(dsidev, DSI_VC_IRQSTATUS(i), vcstatus[i]);
 752                 /* flush posted write */
 753                 dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
 754         }
 755
 756         if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
 757                 ciostatus = dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
 758
 759                 dsi_write_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
 760                 /* flush posted write */
 761                 dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
 762         } else {
 763                 ciostatus = 0;
 764         }
 765
 766 #ifdef DSI_CATCH_MISSING_TE
 767         if (irqstatus & DSI_IRQ_TE_TRIGGER)
 768                 del_timer(&dsi->te_timer);
 769 #endif
 770
 771         /* make a copy and unlock, so that isrs can unregister
 772          * themselves */
 773         memcpy(&dsi->isr_tables_copy, &dsi->isr_tables,
 774                 sizeof(dsi->isr_tables));
 775
 776         spin_unlock(&dsi->irq_lock);
 777
 778         dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus);
 779
 780         dsi_handle_irq_errors(dsidev, irqstatus, vcstatus, ciostatus);
 781
 782         dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus);
 783
 784         return IRQ_HANDLED;
 785 }
 786
 787 /* dsi->irq_lock has to be locked by the caller */
 788 static void _omap_dsi_configure_irqs(struct platform_device *dsidev,
 789                 struct dsi_isr_data *isr_array,
 790                 unsigned isr_array_size, u32 default_mask,
 791                 const struct dsi_reg enable_reg,
 792                 const struct dsi_reg status_reg)
 793 {
 794         struct dsi_isr_data *isr_data;
 795         u32 mask;
 796         u32 old_mask;
 797         int i;
 798
 799         mask = default_mask;
 800
 801         for (i = 0; i < isr_array_size; i++) {
 802                 isr_data = &isr_array[i];
 803
 804                 if (isr_data->isr == NULL)
 805                         continue;
 806
 807                 mask |= isr_data->mask;
 808         }
 809
 810         old_mask = dsi_read_reg(dsidev, enable_reg);
 811         /* clear the irqstatus for newly enabled irqs */
 812         dsi_write_reg(dsidev, status_reg, (mask ^ old_mask) & mask);
 813         dsi_write_reg(dsidev, enable_reg, mask);
 814
 815         /* flush posted writes */
 816         dsi_read_reg(dsidev, enable_reg);
 817         dsi_read_reg(dsidev, status_reg);
 818 }
 819
 820 /* dsi->irq_lock has to be locked by the caller */
 821 static void _omap_dsi_set_irqs(struct platform_device *dsidev)
 822 {
 823         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 824         u32 mask = DSI_IRQ_ERROR_MASK;
 825 #ifdef DSI_CATCH_MISSING_TE
 826         mask |= DSI_IRQ_TE_TRIGGER;
 827 #endif
 828         _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table,
 829                         ARRAY_SIZE(dsi->isr_tables.isr_table), mask,
 830                         DSI_IRQENABLE, DSI_IRQSTATUS);
 831 }
 832
 833 /* dsi->irq_lock has to be locked by the caller */
 834 static void _omap_dsi_set_irqs_vc(struct platform_device *dsidev, int vc)
 835 {
 836         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 837
 838         _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_vc[vc],
 839                         ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]),
 840                         DSI_VC_IRQ_ERROR_MASK,
 841                         DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc));
 842 }
 843
 844 /* dsi->irq_lock has to be locked by the caller */
 845 static void _omap_dsi_set_irqs_cio(struct platform_device *dsidev)
 846 {
 847         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 848
 849         _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_cio,
 850                         ARRAY_SIZE(dsi->isr_tables.isr_table_cio),
 851                         DSI_CIO_IRQ_ERROR_MASK,
 852                         DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS);
 853 }
 854
 855 static void _dsi_initialize_irq(struct platform_device *dsidev)
 856 {
 857         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 858         unsigned long flags;
 859         int vc;
 860
 861         spin_lock_irqsave(&dsi->irq_lock, flags);
 862
 863         memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables));
 864
 865         _omap_dsi_set_irqs(dsidev);
 866         for (vc = 0; vc < 4; ++vc)
 867                 _omap_dsi_set_irqs_vc(dsidev, vc);
 868         _omap_dsi_set_irqs_cio(dsidev);
 869
 870         spin_unlock_irqrestore(&dsi->irq_lock, flags);
 871 }
 872
 873 static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
 874                 struct dsi_isr_data *isr_array, unsigned isr_array_size)
 875 {
 876         struct dsi_isr_data *isr_data;
 877         int free_idx;
 878         int i;
 879
 880         BUG_ON(isr == NULL);
 881
 882         /* check for duplicate entry and find a free slot */
 883         free_idx = -1;
 884         for (i = 0; i < isr_array_size; i++) {
 885                 isr_data = &isr_array[i];
 886
 887                 if (isr_data->isr == isr && isr_data->arg == arg &&
 888                                 isr_data->mask == mask) {
 889                         return -EINVAL;
 890                 }
 891
 892                 if (isr_data->isr == NULL && free_idx == -1)
 893                         free_idx = i;
 894         }
 895
 896         if (free_idx == -1)
 897                 return -EBUSY;
 898
 899         isr_data = &isr_array[free_idx];
 900         isr_data->isr = isr;
 901         isr_data->arg = arg;
 902         isr_data->mask = mask;
 903
 904         return 0;
 905 }
 906
 907 static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
 908                 struct dsi_isr_data *isr_array, unsigned isr_array_size)
 909 {
 910         struct dsi_isr_data *isr_data;
 911         int i;
 912
 913         for (i = 0; i < isr_array_size; i++) {
 914                 isr_data = &isr_array[i];
 915                 if (isr_data->isr != isr || isr_data->arg != arg ||
 916                                 isr_data->mask != mask)
 917                         continue;
 918
 919                 isr_data->isr = NULL;
 920                 isr_data->arg = NULL;
 921                 isr_data->mask = 0;
 922
 923                 return 0;
 924         }
 925
 926         return -EINVAL;
 927 }
 928
 929 static int dsi_register_isr(struct platform_device *dsidev, omap_dsi_isr_t isr,
 930                 void *arg, u32 mask)
 931 {
 932         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 933         unsigned long flags;
 934         int r;
 935
 936         spin_lock_irqsave(&dsi->irq_lock, flags);
 937
 938         r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table,
 939                         ARRAY_SIZE(dsi->isr_tables.isr_table));
 940
 941         if (r == 0)
 942                 _omap_dsi_set_irqs(dsidev);
 943
 944         spin_unlock_irqrestore(&dsi->irq_lock, flags);
 945
 946         return r;
 947 }
 948
 949 static int dsi_unregister_isr(struct platform_device *dsidev,
 950                 omap_dsi_isr_t isr, void *arg, u32 mask)
 951 {
 952         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 953         unsigned long flags;
 954         int r;
 955
 956         spin_lock_irqsave(&dsi->irq_lock, flags);
 957
 958         r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table,
 959                         ARRAY_SIZE(dsi->isr_tables.isr_table));
 960
 961         if (r == 0)
 962                 _omap_dsi_set_irqs(dsidev);
 963
 964         spin_unlock_irqrestore(&dsi->irq_lock, flags);
 965
 966         return r;
 967 }
 968
 969 static int dsi_register_isr_vc(struct platform_device *dsidev, int channel,
 970                 omap_dsi_isr_t isr, void *arg, u32 mask)
 971 {
 972         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 973         unsigned long flags;
 974         int r;
 975
 976         spin_lock_irqsave(&dsi->irq_lock, flags);
 977
 978         r = _dsi_register_isr(isr, arg, mask,
 979                         dsi->isr_tables.isr_table_vc[channel],
 980                         ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
 981
 982         if (r == 0)
 983                 _omap_dsi_set_irqs_vc(dsidev, channel);
 984
 985         spin_unlock_irqrestore(&dsi->irq_lock, flags);
 986
 987         return r;
 988 }
 989
 990 static int dsi_unregister_isr_vc(struct platform_device *dsidev, int channel,
 991                 omap_dsi_isr_t isr, void *arg, u32 mask)
 992 {
 993         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 994         unsigned long flags;
 995         int r;
 996
 997         spin_lock_irqsave(&dsi->irq_lock, flags);
 998
 999         r = _dsi_unregister_isr(isr, arg, mask,
1000                         dsi->isr_tables.isr_table_vc[channel],
1001                         ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
1002
1003         if (r == 0)
1004                 _omap_dsi_set_irqs_vc(dsidev, channel);
1005
1006         spin_unlock_irqrestore(&dsi->irq_lock, flags);
1007
1008         return r;
1009 }
1010
1011 static int dsi_register_isr_cio(struct platform_device *dsidev,
1012                 omap_dsi_isr_t isr, void *arg, u32 mask)
1013 {
1014         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1015         unsigned long flags;
1016         int r;
1017
1018         spin_lock_irqsave(&dsi->irq_lock, flags);
1019
1020         r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1021                         ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1022
1023         if (r == 0)
1024                 _omap_dsi_set_irqs_cio(dsidev);
1025
1026         spin_unlock_irqrestore(&dsi->irq_lock, flags);
1027
1028         return r;
1029 }
1030
1031 static int dsi_unregister_isr_cio(struct platform_device *dsidev,
1032                 omap_dsi_isr_t isr, void *arg, u32 mask)
1033 {
1034         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1035         unsigned long flags;
1036         int r;
1037
1038         spin_lock_irqsave(&dsi->irq_lock, flags);
1039
1040         r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1041                         ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1042
1043         if (r == 0)
1044                 _omap_dsi_set_irqs_cio(dsidev);
1045
1046         spin_unlock_irqrestore(&dsi->irq_lock, flags);
1047
1048         return r;
1049 }
1050
1051 static u32 dsi_get_errors(struct platform_device *dsidev)
1052 {
1053         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1054         unsigned long flags;
1055         u32 e;
1056         spin_lock_irqsave(&dsi->errors_lock, flags);
1057         e = dsi->errors;
1058         dsi->errors = 0;
1059         spin_unlock_irqrestore(&dsi->errors_lock, flags);
1060         return e;
1061 }
1062
1063 int dsi_runtime_get(struct platform_device *dsidev)
1064 {
1065         int r;
1066         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1067
1068         DSSDBG("dsi_runtime_get\n");
1069
1070         r = pm_runtime_get_sync(&dsi->pdev->dev);
1071         WARN_ON(r < 0);
1072         return r < 0 ? r : 0;
1073 }
1074
1075 void dsi_runtime_put(struct platform_device *dsidev)
1076 {
1077         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1078         int r;
1079
1080         DSSDBG("dsi_runtime_put\n");
1081
1082         r = pm_runtime_put_sync(&dsi->pdev->dev);
1083         WARN_ON(r < 0);
1084 }
1085
1086 /* source clock for DSI PLL. this could also be PCLKFREE */
1087 static inline void dsi_enable_pll_clock(struct platform_device *dsidev,
1088                 bool enable)
1089 {
1090         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1091
1092         if (enable)
1093                 clk_enable(dsi->sys_clk);
1094         else
1095                 clk_disable(dsi->sys_clk);
1096
1097         if (enable && dsi->pll_locked) {
1098                 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1)
1099                         DSSERR("cannot lock PLL when enabling clocks\n");
1100         }
1101 }
1102
1103 #ifdef DEBUG
1104 static void _dsi_print_reset_status(struct platform_device *dsidev)
1105 {
1106         u32 l;
1107         int b0, b1, b2;
1108
1109         if (!dss_debug)
1110                 return;
1111
1112         /* A dummy read using the SCP interface to any DSIPHY register is
1113          * required after DSIPHY reset to complete the reset of the DSI complex
1114          * I/O. */
1115         l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
1116
1117         printk(KERN_DEBUG "DSI resets: ");
1118
1119         l = dsi_read_reg(dsidev, DSI_PLL_STATUS);
1120         printk("PLL (%d) ", FLD_GET(l, 0, 0));
1121
1122         l = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1);
1123         printk("CIO (%d) ", FLD_GET(l, 29, 29));
1124
1125         if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) {
1126                 b0 = 28;
1127                 b1 = 27;
1128                 b2 = 26;
1129         } else {
1130                 b0 = 24;
1131                 b1 = 25;
1132                 b2 = 26;
1133         }
1134
1135         l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
1136         printk("PHY (%x%x%x, %d, %d, %d)\n",
1137                         FLD_GET(l, b0, b0),
1138                         FLD_GET(l, b1, b1),
1139                         FLD_GET(l, b2, b2),
1140                         FLD_GET(l, 29, 29),
1141                         FLD_GET(l, 30, 30),
1142                         FLD_GET(l, 31, 31));
1143 }
1144 #else
1145 #define _dsi_print_reset_status(x)
1146 #endif
1147
1148 static inline int dsi_if_enable(struct platform_device *dsidev, bool enable)
1149 {
1150         DSSDBG("dsi_if_enable(%d)\n", enable);
1151
1152         enable = enable ? 1 : 0;
1153         REG_FLD_MOD(dsidev, DSI_CTRL, enable, 0, 0); /* IF_EN */
1154
1155         if (wait_for_bit_change(dsidev, DSI_CTRL, 0, enable) != enable) {
1156                         DSSERR("Failed to set dsi_if_enable to %d\n", enable);
1157                         return -EIO;
1158         }
1159
1160         return 0;
1161 }
1162
1163 unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev)
1164 {
1165         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1166
1167         return dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk;
1168 }
1169
1170 static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct platform_device *dsidev)
1171 {
1172         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1173
1174         return dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk;
1175 }
1176
1177 static unsigned long dsi_get_txbyteclkhs(struct platform_device *dsidev)
1178 {
1179         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1180
1181         return dsi->current_cinfo.clkin4ddr / 16;
1182 }
1183
1184 static unsigned long dsi_fclk_rate(struct platform_device *dsidev)
1185 {
1186         unsigned long r;
1187         int dsi_module = dsi_get_dsidev_id(dsidev);
1188         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1189
1190         if (dss_get_dsi_clk_source(dsi_module) == OMAP_DSS_CLK_SRC_FCK) {
1191                 /* DSI FCLK source is DSS_CLK_FCK */
1192                 r = clk_get_rate(dsi->dss_clk);
1193         } else {
1194                 /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */
1195                 r = dsi_get_pll_hsdiv_dsi_rate(dsidev);
1196         }
1197
1198         return r;
1199 }
1200
1201 static int dsi_set_lp_clk_divisor(struct omap_dss_device *dssdev)
1202 {
1203         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
1204         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1205         unsigned long dsi_fclk;
1206         unsigned lp_clk_div;
1207         unsigned long lp_clk;
1208
1209         lp_clk_div = dssdev->clocks.dsi.lp_clk_div;
1210
1211         if (lp_clk_div == 0 || lp_clk_div > dsi->lpdiv_max)
1212                 return -EINVAL;
1213
1214         dsi_fclk = dsi_fclk_rate(dsidev);
1215
1216         lp_clk = dsi_fclk / 2 / lp_clk_div;
1217
1218         DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk);
1219         dsi->current_cinfo.lp_clk = lp_clk;
1220         dsi->current_cinfo.lp_clk_div = lp_clk_div;
1221
1222         /* LP_CLK_DIVISOR */
1223         REG_FLD_MOD(dsidev, DSI_CLK_CTRL, lp_clk_div, 12, 0);
1224
1225         /* LP_RX_SYNCHRO_ENABLE */
1226         REG_FLD_MOD(dsidev, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21);
1227
1228         return 0;
1229 }
1230
1231 static void dsi_enable_scp_clk(struct platform_device *dsidev)
1232 {
1233         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1234
1235         if (dsi->scp_clk_refcount++ == 0)
1236                 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */
1237 }
1238
1239 static void dsi_disable_scp_clk(struct platform_device *dsidev)
1240 {
1241         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1242
1243         WARN_ON(dsi->scp_clk_refcount == 0);
1244         if (--dsi->scp_clk_refcount == 0)
1245                 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */
1246 }
1247
1248 enum dsi_pll_power_state {
1249         DSI_PLL_POWER_OFF       = 0x0,
1250         DSI_PLL_POWER_ON_HSCLK  = 0x1,
1251         DSI_PLL_POWER_ON_ALL    = 0x2,
1252         DSI_PLL_POWER_ON_DIV    = 0x3,
1253 };
1254
1255 static int dsi_pll_power(struct platform_device *dsidev,
1256                 enum dsi_pll_power_state state)
1257 {
1258         int t = 0;
1259
1260         /* DSI-PLL power command 0x3 is not working */
1261         if (dss_has_feature(FEAT_DSI_PLL_PWR_BUG) &&
1262                         state == DSI_PLL_POWER_ON_DIV)
1263                 state = DSI_PLL_POWER_ON_ALL;
1264
1265         /* PLL_PWR_CMD */
1266         REG_FLD_MOD(dsidev, DSI_CLK_CTRL, state, 31, 30);
1267
1268         /* PLL_PWR_STATUS */
1269         while (FLD_GET(dsi_read_reg(dsidev, DSI_CLK_CTRL), 29, 28) != state) {
1270                 if (++t > 1000) {
1271                         DSSERR("Failed to set DSI PLL power mode to %d\n",
1272                                         state);
1273                         return -ENODEV;
1274                 }
1275                 udelay(1);
1276         }
1277
1278         return 0;
1279 }
1280
1281 /* calculate clock rates using dividers in cinfo */
1282 static int dsi_calc_clock_rates(struct platform_device *dsidev,
1283                 struct dsi_clock_info *cinfo)
1284 {
1285         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1286
1287         if (cinfo->regn == 0 || cinfo->regn > dsi->regn_max)
1288                 return -EINVAL;
1289
1290         if (cinfo->regm == 0 || cinfo->regm > dsi->regm_max)
1291                 return -EINVAL;
1292
1293         if (cinfo->regm_dispc > dsi->regm_dispc_max)
1294                 return -EINVAL;
1295
1296         if (cinfo->regm_dsi > dsi->regm_dsi_max)
1297                 return -EINVAL;
1298
1299         cinfo->clkin = clk_get_rate(dsi->sys_clk);
1300         cinfo->fint = cinfo->clkin / cinfo->regn;
1301
1302         if (cinfo->fint > dsi->fint_max || cinfo->fint < dsi->fint_min)
1303                 return -EINVAL;
1304
1305         cinfo->clkin4ddr = 2 * cinfo->regm * cinfo->fint;
1306
1307         if (cinfo->clkin4ddr > 1800 * 1000 * 1000)
1308                 return -EINVAL;
1309
1310         if (cinfo->regm_dispc > 0)
1311                 cinfo->dsi_pll_hsdiv_dispc_clk =
1312                         cinfo->clkin4ddr / cinfo->regm_dispc;
1313         else
1314                 cinfo->dsi_pll_hsdiv_dispc_clk = 0;
1315
1316         if (cinfo->regm_dsi > 0)
1317                 cinfo->dsi_pll_hsdiv_dsi_clk =
1318                         cinfo->clkin4ddr / cinfo->regm_dsi;
1319         else
1320                 cinfo->dsi_pll_hsdiv_dsi_clk = 0;
1321
1322         return 0;
1323 }
1324
1325 int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev, bool is_tft,
1326                 unsigned long req_pck, struct dsi_clock_info *dsi_cinfo,
1327                 struct dispc_clock_info *dispc_cinfo)
1328 {
1329         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1330         struct dsi_clock_info cur, best;
1331         struct dispc_clock_info best_dispc;
1332         int min_fck_per_pck;
1333         int match = 0;
1334         unsigned long dss_sys_clk, max_dss_fck;
1335
1336         dss_sys_clk = clk_get_rate(dsi->sys_clk);
1337
1338         max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
1339
1340         if (req_pck == dsi->cache_req_pck &&
1341                         dsi->cache_cinfo.clkin == dss_sys_clk) {
1342                 DSSDBG("DSI clock info found from cache\n");
1343                 *dsi_cinfo = dsi->cache_cinfo;
1344                 dispc_find_clk_divs(is_tft, req_pck,
1345                         dsi_cinfo->dsi_pll_hsdiv_dispc_clk, dispc_cinfo);
1346                 return 0;
1347         }
1348
1349         min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
1350
1351         if (min_fck_per_pck &&
1352                 req_pck * min_fck_per_pck > max_dss_fck) {
1353                 DSSERR("Requested pixel clock not possible with the current "
1354                                 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
1355                                 "the constraint off.\n");
1356                 min_fck_per_pck = 0;
1357         }
1358
1359         DSSDBG("dsi_pll_calc\n");
1360
1361 retry:
1362         memset(&best, 0, sizeof(best));
1363         memset(&best_dispc, 0, sizeof(best_dispc));
1364
1365         memset(&cur, 0, sizeof(cur));
1366         cur.clkin = dss_sys_clk;
1367
1368         /* 0.75MHz < Fint = clkin / regn < 2.1MHz */
1369         /* To reduce PLL lock time, keep Fint high (around 2 MHz) */
1370         for (cur.regn = 1; cur.regn < dsi->regn_max; ++cur.regn) {
1371                 cur.fint = cur.clkin / cur.regn;
1372
1373                 if (cur.fint > dsi->fint_max || cur.fint < dsi->fint_min)
1374                         continue;
1375
1376                 /* DSIPHY(MHz) = (2 * regm / regn) * clkin */
1377                 for (cur.regm = 1; cur.regm < dsi->regm_max; ++cur.regm) {
1378                         unsigned long a, b;
1379
1380                         a = 2 * cur.regm * (cur.clkin/1000);
1381                         b = cur.regn;
1382                         cur.clkin4ddr = a / b * 1000;
1383
1384                         if (cur.clkin4ddr > 1800 * 1000 * 1000)
1385                                 break;
1386
1387                         /* dsi_pll_hsdiv_dispc_clk(MHz) =
1388                          * DSIPHY(MHz) / regm_dispc  < 173MHz/186Mhz */
1389                         for (cur.regm_dispc = 1; cur.regm_dispc <
1390                                         dsi->regm_dispc_max; ++cur.regm_dispc) {
1391                                 struct dispc_clock_info cur_dispc;
1392                                 cur.dsi_pll_hsdiv_dispc_clk =
1393                                         cur.clkin4ddr / cur.regm_dispc;
1394
1395                                 /* this will narrow down the search a bit,
1396                                  * but still give pixclocks below what was
1397                                  * requested */
1398                                 if (cur.dsi_pll_hsdiv_dispc_clk  < req_pck)
1399                                         break;
1400
1401                                 if (cur.dsi_pll_hsdiv_dispc_clk > max_dss_fck)
1402                                         continue;
1403
1404                                 if (min_fck_per_pck &&
1405                                         cur.dsi_pll_hsdiv_dispc_clk <
1406                                                 req_pck * min_fck_per_pck)
1407                                         continue;
1408
1409                                 match = 1;
1410
1411                                 dispc_find_clk_divs(is_tft, req_pck,
1412                                                 cur.dsi_pll_hsdiv_dispc_clk,
1413                                                 &cur_dispc);
1414
1415                                 if (abs(cur_dispc.pck - req_pck) <
1416                                                 abs(best_dispc.pck - req_pck)) {
1417                                         best = cur;
1418                                         best_dispc = cur_dispc;
1419
1420                                         if (cur_dispc.pck == req_pck)
1421                                                 goto found;
1422                                 }
1423                         }
1424                 }
1425         }
1426 found:
1427         if (!match) {
1428                 if (min_fck_per_pck) {
1429                         DSSERR("Could not find suitable clock settings.\n"
1430                                         "Turning FCK/PCK constraint off and"
1431                                         "trying again.\n");
1432                         min_fck_per_pck = 0;
1433                         goto retry;
1434                 }
1435
1436                 DSSERR("Could not find suitable clock settings.\n");
1437
1438                 return -EINVAL;
1439         }
1440
1441         /* dsi_pll_hsdiv_dsi_clk (regm_dsi) is not used */
1442         best.regm_dsi = 0;
1443         best.dsi_pll_hsdiv_dsi_clk = 0;
1444
1445         if (dsi_cinfo)
1446                 *dsi_cinfo = best;
1447         if (dispc_cinfo)
1448                 *dispc_cinfo = best_dispc;
1449
1450         dsi->cache_req_pck = req_pck;
1451         dsi->cache_clk_freq = 0;
1452         dsi->cache_cinfo = best;
1453
1454         return 0;
1455 }
1456
1457 int dsi_pll_set_clock_div(struct platform_device *dsidev,
1458                 struct dsi_clock_info *cinfo)
1459 {
1460         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1461         int r = 0;
1462         u32 l;
1463         int f = 0;
1464         u8 regn_start, regn_end, regm_start, regm_end;
1465         u8 regm_dispc_start, regm_dispc_end, regm_dsi_start, regm_dsi_end;
1466
1467         DSSDBGF();
1468
1469         dsi->current_cinfo.clkin = cinfo->clkin;
1470         dsi->current_cinfo.fint = cinfo->fint;
1471         dsi->current_cinfo.clkin4ddr = cinfo->clkin4ddr;
1472         dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk =
1473                         cinfo->dsi_pll_hsdiv_dispc_clk;
1474         dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk =
1475                         cinfo->dsi_pll_hsdiv_dsi_clk;
1476
1477         dsi->current_cinfo.regn = cinfo->regn;
1478         dsi->current_cinfo.regm = cinfo->regm;
1479         dsi->current_cinfo.regm_dispc = cinfo->regm_dispc;
1480         dsi->current_cinfo.regm_dsi = cinfo->regm_dsi;
1481
1482         DSSDBG("DSI Fint %ld\n", cinfo->fint);
1483
1484         DSSDBG("clkin rate %ld\n", cinfo->clkin);
1485
1486         /* DSIPHY == CLKIN4DDR */
1487         DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu = %lu\n",
1488                         cinfo->regm,
1489                         cinfo->regn,
1490                         cinfo->clkin,
1491                         cinfo->clkin4ddr);
1492
1493         DSSDBG("Data rate on 1 DSI lane %ld Mbps\n",
1494                         cinfo->clkin4ddr / 1000 / 1000 / 2);
1495
1496         DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4);
1497
1498         DSSDBG("regm_dispc = %d, %s (%s) = %lu\n", cinfo->regm_dispc,
1499                 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
1500                 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
1501                 cinfo->dsi_pll_hsdiv_dispc_clk);
1502         DSSDBG("regm_dsi = %d, %s (%s) = %lu\n", cinfo->regm_dsi,
1503                 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
1504                 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
1505                 cinfo->dsi_pll_hsdiv_dsi_clk);
1506
1507         dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGN, &regn_start, &regn_end);
1508         dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM, &regm_start, &regm_end);
1509         dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DISPC, &regm_dispc_start,
1510                         &regm_dispc_end);
1511         dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DSI, &regm_dsi_start,
1512                         &regm_dsi_end);
1513
1514         /* DSI_PLL_AUTOMODE = manual */
1515         REG_FLD_MOD(dsidev, DSI_PLL_CONTROL, 0, 0, 0);
1516
1517         l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION1);
1518         l = FLD_MOD(l, 1, 0, 0);                /* DSI_PLL_STOPMODE */
1519         /* DSI_PLL_REGN */
1520         l = FLD_MOD(l, cinfo->regn - 1, regn_start, regn_end);
1521         /* DSI_PLL_REGM */
1522         l = FLD_MOD(l, cinfo->regm, regm_start, regm_end);
1523         /* DSI_CLOCK_DIV */
1524         l = FLD_MOD(l, cinfo->regm_dispc > 0 ? cinfo->regm_dispc - 1 : 0,
1525                         regm_dispc_start, regm_dispc_end);
1526         /* DSIPROTO_CLOCK_DIV */
1527         l = FLD_MOD(l, cinfo->regm_dsi > 0 ? cinfo->regm_dsi - 1 : 0,
1528                         regm_dsi_start, regm_dsi_end);
1529         dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION1, l);
1530
1531         BUG_ON(cinfo->fint < dsi->fint_min || cinfo->fint > dsi->fint_max);
1532
1533         if (dss_has_feature(FEAT_DSI_PLL_FREQSEL)) {
1534                 f = cinfo->fint < 1000000 ? 0x3 :
1535                         cinfo->fint < 1250000 ? 0x4 :
1536                         cinfo->fint < 1500000 ? 0x5 :
1537                         cinfo->fint < 1750000 ? 0x6 :
1538                         0x7;
1539         }
1540
1541         l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2);
1542
1543         if (dss_has_feature(FEAT_DSI_PLL_FREQSEL))
1544                 l = FLD_MOD(l, f, 4, 1);        /* DSI_PLL_FREQSEL */
1545         l = FLD_MOD(l, 1, 13, 13);              /* DSI_PLL_REFEN */
1546         l = FLD_MOD(l, 0, 14, 14);              /* DSIPHY_CLKINEN */
1547         l = FLD_MOD(l, 1, 20, 20);              /* DSI_HSDIVBYPASS */
1548         dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l);
1549
1550         REG_FLD_MOD(dsidev, DSI_PLL_GO, 1, 0, 0);       /* DSI_PLL_GO */
1551
1552         if (wait_for_bit_change(dsidev, DSI_PLL_GO, 0, 0) != 0) {
1553                 DSSERR("dsi pll go bit not going down.\n");
1554                 r = -EIO;
1555                 goto err;
1556         }
1557
1558         if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1) {
1559                 DSSERR("cannot lock PLL\n");
1560                 r = -EIO;
1561                 goto err;
1562         }
1563
1564         dsi->pll_locked = 1;
1565
1566         l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2);
1567         l = FLD_MOD(l, 0, 0, 0);        /* DSI_PLL_IDLE */
1568         l = FLD_MOD(l, 0, 5, 5);        /* DSI_PLL_PLLLPMODE */
1569         l = FLD_MOD(l, 0, 6, 6);        /* DSI_PLL_LOWCURRSTBY */
1570         l = FLD_MOD(l, 0, 7, 7);        /* DSI_PLL_TIGHTPHASELOCK */
1571         l = FLD_MOD(l, 0, 8, 8);        /* DSI_PLL_DRIFTGUARDEN */
1572         l = FLD_MOD(l, 0, 10, 9);       /* DSI_PLL_LOCKSEL */
1573         l = FLD_MOD(l, 1, 13, 13);      /* DSI_PLL_REFEN */
1574         l = FLD_MOD(l, 1, 14, 14);      /* DSIPHY_CLKINEN */
1575         l = FLD_MOD(l, 0, 15, 15);      /* DSI_BYPASSEN */
1576         l = FLD_MOD(l, 1, 16, 16);      /* DSS_CLOCK_EN */
1577         l = FLD_MOD(l, 0, 17, 17);      /* DSS_CLOCK_PWDN */
1578         l = FLD_MOD(l, 1, 18, 18);      /* DSI_PROTO_CLOCK_EN */
1579         l = FLD_MOD(l, 0, 19, 19);      /* DSI_PROTO_CLOCK_PWDN */
1580         l = FLD_MOD(l, 0, 20, 20);      /* DSI_HSDIVBYPASS */
1581         dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l);
1582
1583         DSSDBG("PLL config done\n");
1584 err:
1585         return r;
1586 }
1587
1588 int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk,
1589                 bool enable_hsdiv)
1590 {
1591         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1592         int r = 0;
1593         enum dsi_pll_power_state pwstate;
1594
1595         DSSDBG("PLL init\n");
1596
1597         if (dsi->vdds_dsi_reg == NULL) {
1598                 struct regulator *vdds_dsi;
1599
1600                 vdds_dsi = regulator_get(&dsi->pdev->dev, "vdds_dsi");
1601
1602                 if (IS_ERR(vdds_dsi)) {
1603                         DSSERR("can't get VDDS_DSI regulator\n");
1604                         return PTR_ERR(vdds_dsi);
1605                 }
1606
1607                 dsi->vdds_dsi_reg = vdds_dsi;
1608         }
1609
1610         dsi_enable_pll_clock(dsidev, 1);
1611         /*
1612          * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4.
1613          */
1614         dsi_enable_scp_clk(dsidev);
1615
1616         if (!dsi->vdds_dsi_enabled) {
1617                 r = regulator_enable(dsi->vdds_dsi_reg);
1618                 if (r)
1619                         goto err0;
1620                 dsi->vdds_dsi_enabled = true;
1621         }
1622
1623         /* XXX PLL does not come out of reset without this... */
1624         dispc_pck_free_enable(1);
1625
1626         if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 0, 1) != 1) {
1627                 DSSERR("PLL not coming out of reset.\n");
1628                 r = -ENODEV;
1629                 dispc_pck_free_enable(0);
1630                 goto err1;
1631         }
1632
1633         /* XXX ... but if left on, we get problems when planes do not
1634          * fill the whole display. No idea about this */
1635         dispc_pck_free_enable(0);
1636
1637         if (enable_hsclk && enable_hsdiv)
1638                 pwstate = DSI_PLL_POWER_ON_ALL;
1639         else if (enable_hsclk)
1640                 pwstate = DSI_PLL_POWER_ON_HSCLK;
1641         else if (enable_hsdiv)
1642                 pwstate = DSI_PLL_POWER_ON_DIV;
1643         else
1644                 pwstate = DSI_PLL_POWER_OFF;
1645
1646         r = dsi_pll_power(dsidev, pwstate);
1647
1648         if (r)
1649                 goto err1;
1650
1651         DSSDBG("PLL init done\n");
1652
1653         return 0;
1654 err1:
1655         if (dsi->vdds_dsi_enabled) {
1656                 regulator_disable(dsi->vdds_dsi_reg);
1657                 dsi->vdds_dsi_enabled = false;
1658         }
1659 err0:
1660         dsi_disable_scp_clk(dsidev);
1661         dsi_enable_pll_clock(dsidev, 0);
1662         return r;
1663 }
1664
1665 void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes)
1666 {
1667         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1668
1669         dsi->pll_locked = 0;
1670         dsi_pll_power(dsidev, DSI_PLL_POWER_OFF);
1671         if (disconnect_lanes) {
1672                 WARN_ON(!dsi->vdds_dsi_enabled);
1673                 regulator_disable(dsi->vdds_dsi_reg);
1674                 dsi->vdds_dsi_enabled = false;
1675         }
1676
1677         dsi_disable_scp_clk(dsidev);
1678         dsi_enable_pll_clock(dsidev, 0);
1679
1680         DSSDBG("PLL uninit done\n");
1681 }
1682
1683 static void dsi_dump_dsidev_clocks(struct platform_device *dsidev,
1684                 struct seq_file *s)
1685 {
1686         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1687         struct dsi_clock_info *cinfo = &dsi->current_cinfo;
1688         enum omap_dss_clk_source dispc_clk_src, dsi_clk_src;
1689         int dsi_module = dsi_get_dsidev_id(dsidev);
1690
1691         dispc_clk_src = dss_get_dispc_clk_source();
1692         dsi_clk_src = dss_get_dsi_clk_source(dsi_module);
1693
1694         if (dsi_runtime_get(dsidev))
1695                 return;
1696
1697         seq_printf(s,   "- DSI%d PLL -\n", dsi_module + 1);
1698
1699         seq_printf(s,   "dsi pll clkin\t%lu\n", cinfo->clkin);
1700
1701         seq_printf(s,   "Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn);
1702
1703         seq_printf(s,   "CLKIN4DDR\t%-16luregm %u\n",
1704                         cinfo->clkin4ddr, cinfo->regm);
1705
1706         seq_printf(s,   "DSI_PLL_HSDIV_DISPC (%s)\t%-16luregm_dispc %u\t(%s)\n",
1707                         dss_feat_get_clk_source_name(dsi_module == 0 ?
1708                                 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC :
1709                                 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC),
1710                         cinfo->dsi_pll_hsdiv_dispc_clk,
1711                         cinfo->regm_dispc,
1712                         dispc_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1713                         "off" : "on");
1714
1715         seq_printf(s,   "DSI_PLL_HSDIV_DSI (%s)\t%-16luregm_dsi %u\t(%s)\n",
1716                         dss_feat_get_clk_source_name(dsi_module == 0 ?
1717                                 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI :
1718                                 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI),
1719                         cinfo->dsi_pll_hsdiv_dsi_clk,
1720                         cinfo->regm_dsi,
1721                         dsi_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1722                         "off" : "on");
1723
1724         seq_printf(s,   "- DSI%d -\n", dsi_module + 1);
1725
1726         seq_printf(s,   "dsi fclk source = %s (%s)\n",
1727                         dss_get_generic_clk_source_name(dsi_clk_src),
1728                         dss_feat_get_clk_source_name(dsi_clk_src));
1729
1730         seq_printf(s,   "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsidev));
1731
1732         seq_printf(s,   "DDR_CLK\t\t%lu\n",
1733                         cinfo->clkin4ddr / 4);
1734
1735         seq_printf(s,   "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsidev));
1736
1737         seq_printf(s,   "LP_CLK\t\t%lu\n", cinfo->lp_clk);
1738
1739         dsi_runtime_put(dsidev);
1740 }
1741
1742 void dsi_dump_clocks(struct seq_file *s)
1743 {
1744         struct platform_device *dsidev;
1745         int i;
1746
1747         for  (i = 0; i < MAX_NUM_DSI; i++) {
1748                 dsidev = dsi_get_dsidev_from_id(i);
1749                 if (dsidev)
1750                         dsi_dump_dsidev_clocks(dsidev, s);
1751         }
1752 }
1753
1754 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
1755 static void dsi_dump_dsidev_irqs(struct platform_device *dsidev,
1756                 struct seq_file *s)
1757 {
1758         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1759         unsigned long flags;
1760         struct dsi_irq_stats stats;
1761         int dsi_module = dsi_get_dsidev_id(dsidev);
1762
1763         spin_lock_irqsave(&dsi->irq_stats_lock, flags);
1764
1765         stats = dsi->irq_stats;
1766         memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats));
1767         dsi->irq_stats.last_reset = jiffies;
1768
1769         spin_unlock_irqrestore(&dsi->irq_stats_lock, flags);
1770
1771         seq_printf(s, "period %u ms\n",
1772                         jiffies_to_msecs(jiffies - stats.last_reset));
1773
1774         seq_printf(s, "irqs %d\n", stats.irq_count);
1775 #define PIS(x) \
1776         seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]);
1777
1778         seq_printf(s, "-- DSI%d interrupts --\n", dsi_module + 1);
1779         PIS(VC0);
1780         PIS(VC1);
1781         PIS(VC2);
1782         PIS(VC3);
1783         PIS(WAKEUP);
1784         PIS(RESYNC);
1785         PIS(PLL_LOCK);
1786         PIS(PLL_UNLOCK);
1787         PIS(PLL_RECALL);
1788         PIS(COMPLEXIO_ERR);
1789         PIS(HS_TX_TIMEOUT);
1790         PIS(LP_RX_TIMEOUT);
1791         PIS(TE_TRIGGER);
1792         PIS(ACK_TRIGGER);
1793         PIS(SYNC_LOST);
1794         PIS(LDO_POWER_GOOD);
1795         PIS(TA_TIMEOUT);
1796 #undef PIS
1797
1798 #define PIS(x) \
1799         seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
1800                         stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
1801                         stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
1802                         stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
1803                         stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);
1804
1805         seq_printf(s, "-- VC interrupts --\n");
1806         PIS(CS);
1807         PIS(ECC_CORR);
1808         PIS(PACKET_SENT);
1809         PIS(FIFO_TX_OVF);
1810         PIS(FIFO_RX_OVF);
1811         PIS(BTA);
1812         PIS(ECC_NO_CORR);
1813         PIS(FIFO_TX_UDF);
1814         PIS(PP_BUSY_CHANGE);
1815 #undef PIS
1816
1817 #define PIS(x) \
1818         seq_printf(s, "%-20s %10d\n", #x, \
1819                         stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);
1820
1821         seq_printf(s, "-- CIO interrupts --\n");
1822         PIS(ERRSYNCESC1);
1823         PIS(ERRSYNCESC2);
1824         PIS(ERRSYNCESC3);
1825         PIS(ERRESC1);
1826         PIS(ERRESC2);
1827         PIS(ERRESC3);
1828         PIS(ERRCONTROL1);
1829         PIS(ERRCONTROL2);
1830         PIS(ERRCONTROL3);
1831         PIS(STATEULPS1);
1832         PIS(STATEULPS2);
1833         PIS(STATEULPS3);
1834         PIS(ERRCONTENTIONLP0_1);
1835         PIS(ERRCONTENTIONLP1_1);
1836         PIS(ERRCONTENTIONLP0_2);
1837         PIS(ERRCONTENTIONLP1_2);
1838         PIS(ERRCONTENTIONLP0_3);
1839         PIS(ERRCONTENTIONLP1_3);
1840         PIS(ULPSACTIVENOT_ALL0);
1841         PIS(ULPSACTIVENOT_ALL1);
1842 #undef PIS
1843 }
1844
1845 static void dsi1_dump_irqs(struct seq_file *s)
1846 {
1847         struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
1848
1849         dsi_dump_dsidev_irqs(dsidev, s);
1850 }
1851
1852 static void dsi2_dump_irqs(struct seq_file *s)
1853 {
1854         struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
1855
1856         dsi_dump_dsidev_irqs(dsidev, s);
1857 }
1858
1859 void dsi_create_debugfs_files_irq(struct dentry *debugfs_dir,
1860                 const struct file_operations *debug_fops)
1861 {
1862         struct platform_device *dsidev;
1863
1864         dsidev = dsi_get_dsidev_from_id(0);
1865         if (dsidev)
1866                 debugfs_create_file("dsi1_irqs", S_IRUGO, debugfs_dir,
1867                         &dsi1_dump_irqs, debug_fops);
1868
1869         dsidev = dsi_get_dsidev_from_id(1);
1870         if (dsidev)
1871                 debugfs_create_file("dsi2_irqs", S_IRUGO, debugfs_dir,
1872                         &dsi2_dump_irqs, debug_fops);
1873 }
1874 #endif
1875
1876 static void dsi_dump_dsidev_regs(struct platform_device *dsidev,
1877                 struct seq_file *s)
1878 {
1879 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsidev, r))
1880
1881         if (dsi_runtime_get(dsidev))
1882                 return;
1883         dsi_enable_scp_clk(dsidev);
1884
1885         DUMPREG(DSI_REVISION);
1886         DUMPREG(DSI_SYSCONFIG);
1887         DUMPREG(DSI_SYSSTATUS);
1888         DUMPREG(DSI_IRQSTATUS);
1889         DUMPREG(DSI_IRQENABLE);
1890         DUMPREG(DSI_CTRL);
1891         DUMPREG(DSI_COMPLEXIO_CFG1);
1892         DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
1893         DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
1894         DUMPREG(DSI_CLK_CTRL);
1895         DUMPREG(DSI_TIMING1);
1896         DUMPREG(DSI_TIMING2);
1897         DUMPREG(DSI_VM_TIMING1);
1898         DUMPREG(DSI_VM_TIMING2);
1899         DUMPREG(DSI_VM_TIMING3);
1900         DUMPREG(DSI_CLK_TIMING);
1901         DUMPREG(DSI_TX_FIFO_VC_SIZE);
1902         DUMPREG(DSI_RX_FIFO_VC_SIZE);
1903         DUMPREG(DSI_COMPLEXIO_CFG2);
1904         DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
1905         DUMPREG(DSI_VM_TIMING4);
1906         DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
1907         DUMPREG(DSI_VM_TIMING5);
1908         DUMPREG(DSI_VM_TIMING6);
1909         DUMPREG(DSI_VM_TIMING7);
1910         DUMPREG(DSI_STOPCLK_TIMING);
1911
1912         DUMPREG(DSI_VC_CTRL(0));
1913         DUMPREG(DSI_VC_TE(0));
1914         DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
1915         DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
1916         DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
1917         DUMPREG(DSI_VC_IRQSTATUS(0));
1918         DUMPREG(DSI_VC_IRQENABLE(0));
1919
1920         DUMPREG(DSI_VC_CTRL(1));
1921         DUMPREG(DSI_VC_TE(1));
1922         DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
1923         DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
1924         DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
1925         DUMPREG(DSI_VC_IRQSTATUS(1));
1926         DUMPREG(DSI_VC_IRQENABLE(1));
1927
1928         DUMPREG(DSI_VC_CTRL(2));
1929         DUMPREG(DSI_VC_TE(2));
1930         DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
1931         DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
1932         DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
1933         DUMPREG(DSI_VC_IRQSTATUS(2));
1934         DUMPREG(DSI_VC_IRQENABLE(2));
1935
1936         DUMPREG(DSI_VC_CTRL(3));
1937         DUMPREG(DSI_VC_TE(3));
1938         DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
1939         DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
1940         DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
1941         DUMPREG(DSI_VC_IRQSTATUS(3));
1942         DUMPREG(DSI_VC_IRQENABLE(3));
1943
1944         DUMPREG(DSI_DSIPHY_CFG0);
1945         DUMPREG(DSI_DSIPHY_CFG1);
1946         DUMPREG(DSI_DSIPHY_CFG2);
1947         DUMPREG(DSI_DSIPHY_CFG5);
1948
1949         DUMPREG(DSI_PLL_CONTROL);
1950         DUMPREG(DSI_PLL_STATUS);
1951         DUMPREG(DSI_PLL_GO);
1952         DUMPREG(DSI_PLL_CONFIGURATION1);
1953         DUMPREG(DSI_PLL_CONFIGURATION2);
1954
1955         dsi_disable_scp_clk(dsidev);
1956         dsi_runtime_put(dsidev);
1957 #undef DUMPREG
1958 }
1959
1960 static void dsi1_dump_regs(struct seq_file *s)
1961 {
1962         struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
1963
1964         dsi_dump_dsidev_regs(dsidev, s);
1965 }
1966
1967 static void dsi2_dump_regs(struct seq_file *s)
1968 {
1969         struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
1970
1971         dsi_dump_dsidev_regs(dsidev, s);
1972 }
1973
1974 void dsi_create_debugfs_files_reg(struct dentry *debugfs_dir,
1975                 const struct file_operations *debug_fops)
1976 {
1977         struct platform_device *dsidev;
1978
1979         dsidev = dsi_get_dsidev_from_id(0);
1980         if (dsidev)
1981                 debugfs_create_file("dsi1_regs", S_IRUGO, debugfs_dir,
1982                         &dsi1_dump_regs, debug_fops);
1983
1984         dsidev = dsi_get_dsidev_from_id(1);
1985         if (dsidev)
1986                 debugfs_create_file("dsi2_regs", S_IRUGO, debugfs_dir,
1987                         &dsi2_dump_regs, debug_fops);
1988 }
1989 enum dsi_cio_power_state {
1990         DSI_COMPLEXIO_POWER_OFF         = 0x0,
1991         DSI_COMPLEXIO_POWER_ON          = 0x1,
1992         DSI_COMPLEXIO_POWER_ULPS        = 0x2,
1993 };
1994
1995 static int dsi_cio_power(struct platform_device *dsidev,
1996                 enum dsi_cio_power_state state)
1997 {
1998         int t = 0;
1999
2000         /* PWR_CMD */
2001         REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG1, state, 28, 27);
2002
2003         /* PWR_STATUS */
2004         while (FLD_GET(dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1),
2005                         26, 25) != state) {
2006                 if (++t > 1000) {
2007                         DSSERR("failed to set complexio power state to "
2008                                         "%d\n", state);
2009                         return -ENODEV;
2010                 }
2011                 udelay(1);
2012         }
2013
2014         return 0;
2015 }
2016
2017 static unsigned dsi_get_line_buf_size(struct platform_device *dsidev)
2018 {
2019         int val;
2020
2021         /* line buffer on OMAP3 is 1024 x 24bits */
2022         /* XXX: for some reason using full buffer size causes
2023          * considerable TX slowdown with update sizes that fill the
2024          * whole buffer */
2025         if (!dss_has_feature(FEAT_DSI_GNQ))
2026                 return 1023 * 3;
2027
2028         val = REG_GET(dsidev, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */
2029
2030         switch (val) {
2031         case 1:
2032                 return 512 * 3;         /* 512x24 bits */
2033         case 2:
2034                 return 682 * 3;         /* 682x24 bits */
2035         case 3:
2036                 return 853 * 3;         /* 853x24 bits */
2037         case 4:
2038                 return 1024 * 3;        /* 1024x24 bits */
2039         case 5:
2040                 return 1194 * 3;        /* 1194x24 bits */
2041         case 6:
2042                 return 1365 * 3;        /* 1365x24 bits */
2043         default:
2044                 BUG();
2045         }
2046 }
2047
2048 static int dsi_parse_lane_config(struct omap_dss_device *dssdev)
2049 {
2050         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2051         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2052         u8 lanes[DSI_MAX_NR_LANES];
2053         u8 polarities[DSI_MAX_NR_LANES];
2054         int num_lanes, i;
2055
2056         static const enum dsi_lane_function functions[] = {
2057                 DSI_LANE_CLK,
2058                 DSI_LANE_DATA1,
2059                 DSI_LANE_DATA2,
2060                 DSI_LANE_DATA3,
2061                 DSI_LANE_DATA4,
2062         };
2063
2064         lanes[0] = dssdev->phy.dsi.clk_lane;
2065         lanes[1] = dssdev->phy.dsi.data1_lane;
2066         lanes[2] = dssdev->phy.dsi.data2_lane;
2067         lanes[3] = dssdev->phy.dsi.data3_lane;
2068         lanes[4] = dssdev->phy.dsi.data4_lane;
2069         polarities[0] = dssdev->phy.dsi.clk_pol;
2070         polarities[1] = dssdev->phy.dsi.data1_pol;
2071         polarities[2] = dssdev->phy.dsi.data2_pol;
2072         polarities[3] = dssdev->phy.dsi.data3_pol;
2073         polarities[4] = dssdev->phy.dsi.data4_pol;
2074
2075         num_lanes = 0;
2076
2077         for (i = 0; i < dsi->num_lanes_supported; ++i)
2078                 dsi->lanes[i].function = DSI_LANE_UNUSED;
2079
2080         for (i = 0; i < dsi->num_lanes_supported; ++i) {
2081                 int num;
2082
2083                 if (lanes[i] == DSI_LANE_UNUSED)
2084                         break;
2085
2086                 num = lanes[i] - 1;
2087
2088                 if (num >= dsi->num_lanes_supported)
2089                         return -EINVAL;
2090
2091                 if (dsi->lanes[num].function != DSI_LANE_UNUSED)
2092                         return -EINVAL;
2093
2094                 dsi->lanes[num].function = functions[i];
2095                 dsi->lanes[num].polarity = polarities[i];
2096                 num_lanes++;
2097         }
2098
2099         if (num_lanes < 2 || num_lanes > dsi->num_lanes_supported)
2100                 return -EINVAL;
2101
2102         dsi->num_lanes_used = num_lanes;
2103
2104         return 0;
2105 }
2106
2107 static int dsi_set_lane_config(struct omap_dss_device *dssdev)
2108 {
2109         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2110         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2111         static const u8 offsets[] = { 0, 4, 8, 12, 16 };
2112         static const enum dsi_lane_function functions[] = {
2113                 DSI_LANE_CLK,
2114                 DSI_LANE_DATA1,
2115                 DSI_LANE_DATA2,
2116                 DSI_LANE_DATA3,
2117                 DSI_LANE_DATA4,
2118         };
2119         u32 r;
2120         int i;
2121
2122         r = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1);
2123
2124         for (i = 0; i < dsi->num_lanes_used; ++i) {
2125                 unsigned offset = offsets[i];
2126                 unsigned polarity, lane_number;
2127                 unsigned t;
2128
2129                 for (t = 0; t < dsi->num_lanes_supported; ++t)
2130                         if (dsi->lanes[t].function == functions[i])
2131                                 break;
2132
2133                 if (t == dsi->num_lanes_supported)
2134                         return -EINVAL;
2135
2136                 lane_number = t;
2137                 polarity = dsi->lanes[t].polarity;
2138
2139                 r = FLD_MOD(r, lane_number + 1, offset + 2, offset);
2140                 r = FLD_MOD(r, polarity, offset + 3, offset + 3);
2141         }
2142
2143         /* clear the unused lanes */
2144         for (; i < dsi->num_lanes_supported; ++i) {
2145                 unsigned offset = offsets[i];
2146
2147                 r = FLD_MOD(r, 0, offset + 2, offset);
2148                 r = FLD_MOD(r, 0, offset + 3, offset + 3);
2149         }
2150
2151         dsi_write_reg(dsidev, DSI_COMPLEXIO_CFG1, r);
2152
2153         return 0;
2154 }
2155
2156 static inline unsigned ns2ddr(struct platform_device *dsidev, unsigned ns)
2157 {
2158         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2159
2160         /* convert time in ns to ddr ticks, rounding up */
2161         unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4;
2162         return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000;
2163 }
2164
2165 static inline unsigned ddr2ns(struct platform_device *dsidev, unsigned ddr)
2166 {
2167         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2168
2169         unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4;
2170         return ddr * 1000 * 1000 / (ddr_clk / 1000);
2171 }
2172
2173 static void dsi_cio_timings(struct platform_device *dsidev)
2174 {
2175         u32 r;
2176         u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
2177         u32 tlpx_half, tclk_trail, tclk_zero;
2178         u32 tclk_prepare;
2179
2180         /* calculate timings */
2181
2182         /* 1 * DDR_CLK = 2 * UI */
2183
2184         /* min 40ns + 4*UI      max 85ns + 6*UI */
2185         ths_prepare = ns2ddr(dsidev, 70) + 2;
2186
2187         /* min 145ns + 10*UI */
2188         ths_prepare_ths_zero = ns2ddr(dsidev, 175) + 2;
2189
2190         /* min max(8*UI, 60ns+4*UI) */
2191         ths_trail = ns2ddr(dsidev, 60) + 5;
2192
2193         /* min 100ns */
2194         ths_exit = ns2ddr(dsidev, 145);
2195
2196         /* tlpx min 50n */
2197         tlpx_half = ns2ddr(dsidev, 25);
2198
2199         /* min 60ns */
2200         tclk_trail = ns2ddr(dsidev, 60) + 2;
2201
2202         /* min 38ns, max 95ns */
2203         tclk_prepare = ns2ddr(dsidev, 65);
2204
2205         /* min tclk-prepare + tclk-zero = 300ns */
2206         tclk_zero = ns2ddr(dsidev, 260);
2207
2208         DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
2209                 ths_prepare, ddr2ns(dsidev, ths_prepare),
2210                 ths_prepare_ths_zero, ddr2ns(dsidev, ths_prepare_ths_zero));
2211         DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
2212                         ths_trail, ddr2ns(dsidev, ths_trail),
2213                         ths_exit, ddr2ns(dsidev, ths_exit));
2214
2215         DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
2216                         "tclk_zero %u (%uns)\n",
2217                         tlpx_half, ddr2ns(dsidev, tlpx_half),
2218                         tclk_trail, ddr2ns(dsidev, tclk_trail),
2219                         tclk_zero, ddr2ns(dsidev, tclk_zero));
2220         DSSDBG("tclk_prepare %u (%uns)\n",
2221                         tclk_prepare, ddr2ns(dsidev, tclk_prepare));
2222
2223         /* program timings */
2224
2225         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
2226         r = FLD_MOD(r, ths_prepare, 31, 24);
2227         r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
2228         r = FLD_MOD(r, ths_trail, 15, 8);
2229         r = FLD_MOD(r, ths_exit, 7, 0);
2230         dsi_write_reg(dsidev, DSI_DSIPHY_CFG0, r);
2231
2232         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
2233         r = FLD_MOD(r, tlpx_half, 22, 16);
2234         r = FLD_MOD(r, tclk_trail, 15, 8);
2235         r = FLD_MOD(r, tclk_zero, 7, 0);
2236         dsi_write_reg(dsidev, DSI_DSIPHY_CFG1, r);
2237
2238         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
2239         r = FLD_MOD(r, tclk_prepare, 7, 0);
2240         dsi_write_reg(dsidev, DSI_DSIPHY_CFG2, r);
2241 }
2242
2243 /* lane masks have lane 0 at lsb. mask_p for positive lines, n for negative */
2244 static void dsi_cio_enable_lane_override(struct omap_dss_device *dssdev,
2245                 unsigned mask_p, unsigned mask_n)
2246 {
2247         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2248         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2249         int i;
2250         u32 l;
2251         u8 lptxscp_start = dsi->num_lanes_supported == 3 ? 22 : 26;
2252
2253         l = 0;
2254
2255         for (i = 0; i < dsi->num_lanes_supported; ++i) {
2256                 unsigned p = dsi->lanes[i].polarity;
2257
2258                 if (mask_p & (1 << i))
2259                         l |= 1 << (i * 2 + (p ? 0 : 1));
2260
2261                 if (mask_n & (1 << i))
2262                         l |= 1 << (i * 2 + (p ? 1 : 0));
2263         }
2264
2265         /*
2266          * Bits in REGLPTXSCPDAT4TO0DXDY:
2267          * 17: DY0 18: DX0
2268          * 19: DY1 20: DX1
2269          * 21: DY2 22: DX2
2270          * 23: DY3 24: DX3
2271          * 25: DY4 26: DX4
2272          */
2273
2274         /* Set the lane override configuration */
2275
2276         /* REGLPTXSCPDAT4TO0DXDY */
2277         REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, l, lptxscp_start, 17);
2278
2279         /* Enable lane override */
2280
2281         /* ENLPTXSCPDAT */
2282         REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 1, 27, 27);
2283 }
2284
2285 static void dsi_cio_disable_lane_override(struct platform_device *dsidev)
2286 {
2287         /* Disable lane override */
2288         REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */
2289         /* Reset the lane override configuration */
2290         /* REGLPTXSCPDAT4TO0DXDY */
2291         REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 22, 17);
2292 }
2293
2294 static int dsi_cio_wait_tx_clk_esc_reset(struct omap_dss_device *dssdev)
2295 {
2296         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2297         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2298         int t, i;
2299         bool in_use[DSI_MAX_NR_LANES];
2300         static const u8 offsets_old[] = { 28, 27, 26 };
2301         static const u8 offsets_new[] = { 24, 25, 26, 27, 28 };
2302         const u8 *offsets;
2303
2304         if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC))
2305                 offsets = offsets_old;
2306         else
2307                 offsets = offsets_new;
2308
2309         for (i = 0; i < dsi->num_lanes_supported; ++i)
2310                 in_use[i] = dsi->lanes[i].function != DSI_LANE_UNUSED;
2311
2312         t = 100000;
2313         while (true) {
2314                 u32 l;
2315                 int ok;
2316
2317                 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2318
2319                 ok = 0;
2320                 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2321                         if (!in_use[i] || (l & (1 << offsets[i])))
2322                                 ok++;
2323                 }
2324
2325                 if (ok == dsi->num_lanes_supported)
2326                         break;
2327
2328                 if (--t == 0) {
2329                         for (i = 0; i < dsi->num_lanes_supported; ++i) {
2330                                 if (!in_use[i] || (l & (1 << offsets[i])))
2331                                         continue;
2332
2333                                 DSSERR("CIO TXCLKESC%d domain not coming " \
2334                                                 "out of reset\n", i);
2335                         }
2336                         return -EIO;
2337                 }
2338         }
2339
2340         return 0;
2341 }
2342
2343 /* return bitmask of enabled lanes, lane0 being the lsb */
2344 static unsigned dsi_get_lane_mask(struct omap_dss_device *dssdev)
2345 {
2346         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2347         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2348         unsigned mask = 0;
2349         int i;
2350
2351         for (i = 0; i < dsi->num_lanes_supported; ++i) {
2352                 if (dsi->lanes[i].function != DSI_LANE_UNUSED)
2353                         mask |= 1 << i;
2354         }
2355
2356         return mask;
2357 }
2358
2359 static int dsi_cio_init(struct omap_dss_device *dssdev)
2360 {
2361         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2362         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2363         int r;
2364         u32 l;
2365
2366         DSSDBGF();
2367
2368         r = dsi->enable_pads(dsidev->id, dsi_get_lane_mask(dssdev));
2369         if (r)
2370                 return r;
2371
2372         dsi_enable_scp_clk(dsidev);
2373
2374         /* A dummy read using the SCP interface to any DSIPHY register is
2375          * required after DSIPHY reset to complete the reset of the DSI complex
2376          * I/O. */
2377         dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2378
2379         if (wait_for_bit_change(dsidev, DSI_DSIPHY_CFG5, 30, 1) != 1) {
2380                 DSSERR("CIO SCP Clock domain not coming out of reset.\n");
2381                 r = -EIO;
2382                 goto err_scp_clk_dom;
2383         }
2384
2385         r = dsi_set_lane_config(dssdev);
2386         if (r)
2387                 goto err_scp_clk_dom;
2388
2389         /* set TX STOP MODE timer to maximum for this operation */
2390         l = dsi_read_reg(dsidev, DSI_TIMING1);
2391         l = FLD_MOD(l, 1, 15, 15);      /* FORCE_TX_STOP_MODE_IO */
2392         l = FLD_MOD(l, 1, 14, 14);      /* STOP_STATE_X16_IO */
2393         l = FLD_MOD(l, 1, 13, 13);      /* STOP_STATE_X4_IO */
2394         l = FLD_MOD(l, 0x1fff, 12, 0);  /* STOP_STATE_COUNTER_IO */
2395         dsi_write_reg(dsidev, DSI_TIMING1, l);
2396
2397         if (dsi->ulps_enabled) {
2398                 unsigned mask_p;
2399                 int i;
2400
2401                 DSSDBG("manual ulps exit\n");
2402
2403                 /* ULPS is exited by Mark-1 state for 1ms, followed by
2404                  * stop state. DSS HW cannot do this via the normal
2405                  * ULPS exit sequence, as after reset the DSS HW thinks
2406                  * that we are not in ULPS mode, and refuses to send the
2407                  * sequence. So we need to send the ULPS exit sequence
2408                  * manually by setting positive lines high and negative lines
2409                  * low for 1ms.
2410                  */
2411
2412                 mask_p = 0;
2413
2414                 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2415                         if (dsi->lanes[i].function == DSI_LANE_UNUSED)
2416                                 continue;
2417                         mask_p |= 1 << i;
2418                 }
2419
2420                 dsi_cio_enable_lane_override(dssdev, mask_p, 0);
2421         }
2422
2423         r = dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ON);
2424         if (r)
2425                 goto err_cio_pwr;
2426
2427         if (wait_for_bit_change(dsidev, DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
2428                 DSSERR("CIO PWR clock domain not coming out of reset.\n");
2429                 r = -ENODEV;
2430                 goto err_cio_pwr_dom;
2431         }
2432
2433         dsi_if_enable(dsidev, true);
2434         dsi_if_enable(dsidev, false);
2435         REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
2436
2437         r = dsi_cio_wait_tx_clk_esc_reset(dssdev);
2438         if (r)
2439                 goto err_tx_clk_esc_rst;
2440
2441         if (dsi->ulps_enabled) {
2442                 /* Keep Mark-1 state for 1ms (as per DSI spec) */
2443                 ktime_t wait = ns_to_ktime(1000 * 1000);
2444                 set_current_state(TASK_UNINTERRUPTIBLE);
2445                 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
2446
2447                 /* Disable the override. The lanes should be set to Mark-11
2448                  * state by the HW */
2449                 dsi_cio_disable_lane_override(dsidev);
2450         }
2451
2452         /* FORCE_TX_STOP_MODE_IO */
2453         REG_FLD_MOD(dsidev, DSI_TIMING1, 0, 15, 15);
2454
2455         dsi_cio_timings(dsidev);
2456
2457         if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
2458                 /* DDR_CLK_ALWAYS_ON */
2459                 REG_FLD_MOD(dsidev, DSI_CLK_CTRL,
2460                         dssdev->panel.dsi_vm_data.ddr_clk_always_on, 13, 13);
2461         }
2462
2463         dsi->ulps_enabled = false;
2464
2465         DSSDBG("CIO init done\n");
2466
2467         return 0;
2468
2469 err_tx_clk_esc_rst:
2470         REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */
2471 err_cio_pwr_dom:
2472         dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2473 err_cio_pwr:
2474         if (dsi->ulps_enabled)
2475                 dsi_cio_disable_lane_override(dsidev);
2476 err_scp_clk_dom:
2477         dsi_disable_scp_clk(dsidev);
2478         dsi->disable_pads(dsidev->id, dsi_get_lane_mask(dssdev));
2479         return r;
2480 }
2481
2482 static void dsi_cio_uninit(struct omap_dss_device *dssdev)
2483 {
2484         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2485         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2486
2487         /* DDR_CLK_ALWAYS_ON */
2488         REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13);
2489
2490         dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2491         dsi_disable_scp_clk(dsidev);
2492         dsi->disable_pads(dsidev->id, dsi_get_lane_mask(dssdev));
2493 }
2494
2495 static void dsi_config_tx_fifo(struct platform_device *dsidev,
2496                 enum fifo_size size1, enum fifo_size size2,
2497                 enum fifo_size size3, enum fifo_size size4)
2498 {
2499         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2500         u32 r = 0;
2501         int add = 0;
2502         int i;
2503
2504         dsi->vc[0].fifo_size = size1;
2505         dsi->vc[1].fifo_size = size2;
2506         dsi->vc[2].fifo_size = size3;
2507         dsi->vc[3].fifo_size = size4;
2508
2509         for (i = 0; i < 4; i++) {
2510                 u8 v;
2511                 int size = dsi->vc[i].fifo_size;
2512
2513                 if (add + size > 4) {
2514                         DSSERR("Illegal FIFO configuration\n");
2515                         BUG();
2516                 }
2517
2518                 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2519                 r |= v << (8 * i);
2520                 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
2521                 add += size;
2522         }
2523
2524         dsi_write_reg(dsidev, DSI_TX_FIFO_VC_SIZE, r);
2525 }
2526
2527 static void dsi_config_rx_fifo(struct platform_device *dsidev,
2528                 enum fifo_size size1, enum fifo_size size2,
2529                 enum fifo_size size3, enum fifo_size size4)
2530 {
2531         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2532         u32 r = 0;
2533         int add = 0;
2534         int i;
2535
2536         dsi->vc[0].fifo_size = size1;
2537         dsi->vc[1].fifo_size = size2;
2538         dsi->vc[2].fifo_size = size3;
2539         dsi->vc[3].fifo_size = size4;
2540
2541         for (i = 0; i < 4; i++) {
2542                 u8 v;
2543                 int size = dsi->vc[i].fifo_size;
2544
2545                 if (add + size > 4) {
2546                         DSSERR("Illegal FIFO configuration\n");
2547                         BUG();
2548                 }
2549
2550                 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2551                 r |= v << (8 * i);
2552                 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
2553                 add += size;
2554         }
2555
2556         dsi_write_reg(dsidev, DSI_RX_FIFO_VC_SIZE, r);
2557 }
2558
2559 static int dsi_force_tx_stop_mode_io(struct platform_device *dsidev)
2560 {
2561         u32 r;
2562
2563         r = dsi_read_reg(dsidev, DSI_TIMING1);
2564         r = FLD_MOD(r, 1, 15, 15);      /* FORCE_TX_STOP_MODE_IO */
2565         dsi_write_reg(dsidev, DSI_TIMING1, r);
2566
2567         if (wait_for_bit_change(dsidev, DSI_TIMING1, 15, 0) != 0) {
2568                 DSSERR("TX_STOP bit not going down\n");
2569                 return -EIO;
2570         }
2571
2572         return 0;
2573 }
2574
2575 static bool dsi_vc_is_enabled(struct platform_device *dsidev, int channel)
2576 {
2577         return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0);
2578 }
2579
2580 static void dsi_packet_sent_handler_vp(void *data, u32 mask)
2581 {
2582         struct dsi_packet_sent_handler_data *vp_data =
2583                 (struct dsi_packet_sent_handler_data *) data;
2584         struct dsi_data *dsi = dsi_get_dsidrv_data(vp_data->dsidev);
2585         const int channel = dsi->update_channel;
2586         u8 bit = dsi->te_enabled ? 30 : 31;
2587
2588         if (REG_GET(vp_data->dsidev, DSI_VC_TE(channel), bit, bit) == 0)
2589                 complete(vp_data->completion);
2590 }
2591
2592 static int dsi_sync_vc_vp(struct platform_device *dsidev, int channel)
2593 {
2594         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2595         DECLARE_COMPLETION_ONSTACK(completion);
2596         struct dsi_packet_sent_handler_data vp_data = { dsidev, &completion };
2597         int r = 0;
2598         u8 bit;
2599
2600         bit = dsi->te_enabled ? 30 : 31;
2601
2602         r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2603                 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2604         if (r)
2605                 goto err0;
2606
2607         /* Wait for completion only if TE_EN/TE_START is still set */
2608         if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit)) {
2609                 if (wait_for_completion_timeout(&completion,
2610                                 msecs_to_jiffies(10)) == 0) {
2611                         DSSERR("Failed to complete previous frame transfer\n");
2612                         r = -EIO;
2613                         goto err1;
2614                 }
2615         }
2616
2617         dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2618                 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2619
2620         return 0;
2621 err1:
2622         dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2623                 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2624 err0:
2625         return r;
2626 }
2627
2628 static void dsi_packet_sent_handler_l4(void *data, u32 mask)
2629 {
2630         struct dsi_packet_sent_handler_data *l4_data =
2631                 (struct dsi_packet_sent_handler_data *) data;
2632         struct dsi_data *dsi = dsi_get_dsidrv_data(l4_data->dsidev);
2633         const int channel = dsi->update_channel;
2634
2635         if (REG_GET(l4_data->dsidev, DSI_VC_CTRL(channel), 5, 5) == 0)
2636                 complete(l4_data->completion);
2637 }
2638
2639 static int dsi_sync_vc_l4(struct platform_device *dsidev, int channel)
2640 {
2641         DECLARE_COMPLETION_ONSTACK(completion);
2642         struct dsi_packet_sent_handler_data l4_data = { dsidev, &completion };
2643         int r = 0;
2644
2645         r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2646                 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2647         if (r)
2648                 goto err0;
2649
2650         /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */
2651         if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) {
2652                 if (wait_for_completion_timeout(&completion,
2653                                 msecs_to_jiffies(10)) == 0) {
2654                         DSSERR("Failed to complete previous l4 transfer\n");
2655                         r = -EIO;
2656                         goto err1;
2657                 }
2658         }
2659
2660         dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2661                 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2662
2663         return 0;
2664 err1:
2665         dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2666                 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2667 err0:
2668         return r;
2669 }
2670
2671 static int dsi_sync_vc(struct platform_device *dsidev, int channel)
2672 {
2673         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2674
2675         WARN_ON(!dsi_bus_is_locked(dsidev));
2676
2677         WARN_ON(in_interrupt());
2678
2679         if (!dsi_vc_is_enabled(dsidev, channel))
2680                 return 0;
2681
2682         switch (dsi->vc[channel].source) {
2683         case DSI_VC_SOURCE_VP:
2684                 return dsi_sync_vc_vp(dsidev, channel);
2685         case DSI_VC_SOURCE_L4:
2686                 return dsi_sync_vc_l4(dsidev, channel);
2687         default:
2688                 BUG();
2689         }
2690 }
2691
2692 static int dsi_vc_enable(struct platform_device *dsidev, int channel,
2693                 bool enable)
2694 {
2695         DSSDBG("dsi_vc_enable channel %d, enable %d\n",
2696                         channel, enable);
2697
2698         enable = enable ? 1 : 0;
2699
2700         REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 0, 0);
2701
2702         if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel),
2703                 0, enable) != enable) {
2704                         DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
2705                         return -EIO;
2706         }
2707
2708         return 0;
2709 }
2710
2711 static void dsi_vc_initial_config(struct platform_device *dsidev, int channel)
2712 {
2713         u32 r;
2714
2715         DSSDBGF("%d", channel);
2716
2717         r = dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
2718
2719         if (FLD_GET(r, 15, 15)) /* VC_BUSY */
2720                 DSSERR("VC(%d) busy when trying to configure it!\n",
2721                                 channel);
2722
2723         r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
2724         r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN  */
2725         r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
2726         r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
2727         r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
2728         r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
2729         r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
2730         if (dss_has_feature(FEAT_DSI_VC_OCP_WIDTH))
2731                 r = FLD_MOD(r, 3, 11, 10);      /* OCP_WIDTH = 32 bit */
2732
2733         r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
2734         r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
2735
2736         dsi_write_reg(dsidev, DSI_VC_CTRL(channel), r);
2737 }
2738
2739 static int dsi_vc_config_source(struct platform_device *dsidev, int channel,
2740                 enum dsi_vc_source source)
2741 {
2742         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2743
2744         if (dsi->vc[channel].source == source)
2745                 return 0;
2746
2747         DSSDBGF("%d", channel);
2748
2749         dsi_sync_vc(dsidev, channel);
2750
2751         dsi_vc_enable(dsidev, channel, 0);
2752
2753         /* VC_BUSY */
2754         if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 15, 0) != 0) {
2755                 DSSERR("vc(%d) busy when trying to config for VP\n", channel);
2756                 return -EIO;
2757         }
2758
2759         /* SOURCE, 0 = L4, 1 = video port */
2760         REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), source, 1, 1);
2761
2762         /* DCS_CMD_ENABLE */
2763         if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
2764                 bool enable = source == DSI_VC_SOURCE_VP;
2765                 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 30, 30);
2766         }
2767
2768         dsi_vc_enable(dsidev, channel, 1);
2769
2770         dsi->vc[channel].source = source;
2771
2772         return 0;
2773 }
2774
2775 void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
2776                 bool enable)
2777 {
2778         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2779
2780         DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
2781
2782         WARN_ON(!dsi_bus_is_locked(dsidev));
2783
2784         dsi_vc_enable(dsidev, channel, 0);
2785         dsi_if_enable(dsidev, 0);
2786
2787         REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 9, 9);
2788
2789         dsi_vc_enable(dsidev, channel, 1);
2790         dsi_if_enable(dsidev, 1);
2791
2792         dsi_force_tx_stop_mode_io(dsidev);
2793
2794         /* start the DDR clock by sending a NULL packet */
2795         if (dssdev->panel.dsi_vm_data.ddr_clk_always_on && enable)
2796                 dsi_vc_send_null(dssdev, channel);
2797 }
2798 EXPORT_SYMBOL(omapdss_dsi_vc_enable_hs);
2799
2800 static void dsi_vc_flush_long_data(struct platform_device *dsidev, int channel)
2801 {
2802         while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2803                 u32 val;
2804                 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2805                 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
2806                                 (val >> 0) & 0xff,
2807                                 (val >> 8) & 0xff,
2808                                 (val >> 16) & 0xff,
2809                                 (val >> 24) & 0xff);
2810         }
2811 }
2812
2813 static void dsi_show_rx_ack_with_err(u16 err)
2814 {
2815         DSSERR("\tACK with ERROR (%#x):\n", err);
2816         if (err & (1 << 0))
2817                 DSSERR("\t\tSoT Error\n");
2818         if (err & (1 << 1))
2819                 DSSERR("\t\tSoT Sync Error\n");
2820         if (err & (1 << 2))
2821                 DSSERR("\t\tEoT Sync Error\n");
2822         if (err & (1 << 3))
2823                 DSSERR("\t\tEscape Mode Entry Command Error\n");
2824         if (err & (1 << 4))
2825                 DSSERR("\t\tLP Transmit Sync Error\n");
2826         if (err & (1 << 5))
2827                 DSSERR("\t\tHS Receive Timeout Error\n");
2828         if (err & (1 << 6))
2829                 DSSERR("\t\tFalse Control Error\n");
2830         if (err & (1 << 7))
2831                 DSSERR("\t\t(reserved7)\n");
2832         if (err & (1 << 8))
2833                 DSSERR("\t\tECC Error, single-bit (corrected)\n");
2834         if (err & (1 << 9))
2835                 DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
2836         if (err & (1 << 10))
2837                 DSSERR("\t\tChecksum Error\n");
2838         if (err & (1 << 11))
2839                 DSSERR("\t\tData type not recognized\n");
2840         if (err & (1 << 12))
2841                 DSSERR("\t\tInvalid VC ID\n");
2842         if (err & (1 << 13))
2843                 DSSERR("\t\tInvalid Transmission Length\n");
2844         if (err & (1 << 14))
2845                 DSSERR("\t\t(reserved14)\n");
2846         if (err & (1 << 15))
2847                 DSSERR("\t\tDSI Protocol Violation\n");
2848 }
2849
2850 static u16 dsi_vc_flush_receive_data(struct platform_device *dsidev,
2851                 int channel)
2852 {
2853         /* RX_FIFO_NOT_EMPTY */
2854         while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2855                 u32 val;
2856                 u8 dt;
2857                 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2858                 DSSERR("\trawval %#08x\n", val);
2859                 dt = FLD_GET(val, 5, 0);
2860                 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
2861                         u16 err = FLD_GET(val, 23, 8);
2862                         dsi_show_rx_ack_with_err(err);
2863                 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE) {
2864                         DSSERR("\tDCS short response, 1 byte: %#x\n",
2865                                         FLD_GET(val, 23, 8));
2866                 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE) {
2867                         DSSERR("\tDCS short response, 2 byte: %#x\n",
2868                                         FLD_GET(val, 23, 8));
2869                 } else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) {
2870                         DSSERR("\tDCS long response, len %d\n",
2871                                         FLD_GET(val, 23, 8));
2872                         dsi_vc_flush_long_data(dsidev, channel);
2873                 } else {
2874                         DSSERR("\tunknown datatype 0x%02x\n", dt);
2875                 }
2876         }
2877         return 0;
2878 }
2879
2880 static int dsi_vc_send_bta(struct platform_device *dsidev, int channel)
2881 {
2882         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2883
2884         if (dsi->debug_write || dsi->debug_read)
2885                 DSSDBG("dsi_vc_send_bta %d\n", channel);
2886
2887         WARN_ON(!dsi_bus_is_locked(dsidev));
2888
2889         /* RX_FIFO_NOT_EMPTY */
2890         if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2891                 DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
2892                 dsi_vc_flush_receive_data(dsidev, channel);
2893         }
2894
2895         REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
2896
2897         /* flush posted write */
2898         dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
2899
2900         return 0;
2901 }
2902
2903 int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel)
2904 {
2905         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2906         DECLARE_COMPLETION_ONSTACK(completion);
2907         int r = 0;
2908         u32 err;
2909
2910         r = dsi_register_isr_vc(dsidev, channel, dsi_completion_handler,
2911                         &completion, DSI_VC_IRQ_BTA);
2912         if (r)
2913                 goto err0;
2914
2915         r = dsi_register_isr(dsidev, dsi_completion_handler, &completion,
2916                         DSI_IRQ_ERROR_MASK);
2917         if (r)
2918                 goto err1;
2919
2920         r = dsi_vc_send_bta(dsidev, channel);
2921         if (r)
2922                 goto err2;
2923
2924         if (wait_for_completion_timeout(&completion,
2925                                 msecs_to_jiffies(500)) == 0) {
2926                 DSSERR("Failed to receive BTA\n");
2927                 r = -EIO;
2928                 goto err2;
2929         }
2930
2931         err = dsi_get_errors(dsidev);
2932         if (err) {
2933                 DSSERR("Error while sending BTA: %x\n", err);
2934                 r = -EIO;
2935                 goto err2;
2936         }
2937 err2:
2938         dsi_unregister_isr(dsidev, dsi_completion_handler, &completion,
2939                         DSI_IRQ_ERROR_MASK);
2940 err1:
2941         dsi_unregister_isr_vc(dsidev, channel, dsi_completion_handler,
2942                         &completion, DSI_VC_IRQ_BTA);
2943 err0:
2944         return r;
2945 }
2946 EXPORT_SYMBOL(dsi_vc_send_bta_sync);
2947
2948 static inline void dsi_vc_write_long_header(struct platform_device *dsidev,
2949                 int channel, u8 data_type, u16 len, u8 ecc)
2950 {
2951         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2952         u32 val;
2953         u8 data_id;
2954
2955         WARN_ON(!dsi_bus_is_locked(dsidev));
2956
2957         data_id = data_type | dsi->vc[channel].vc_id << 6;
2958
2959         val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
2960                 FLD_VAL(ecc, 31, 24);
2961
2962         dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_HEADER(channel), val);
2963 }
2964
2965 static inline void dsi_vc_write_long_payload(struct platform_device *dsidev,
2966                 int channel, u8 b1, u8 b2, u8 b3, u8 b4)
2967 {
2968         u32 val;
2969
2970         val = b4 << 24 | b3 << 16 | b2 << 8  | b1 << 0;
2971
2972 /*      DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
2973                         b1, b2, b3, b4, val); */
2974
2975         dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
2976 }
2977
2978 static int dsi_vc_send_long(struct platform_device *dsidev, int channel,
2979                 u8 data_type, u8 *data, u16 len, u8 ecc)
2980 {
2981         /*u32 val; */
2982         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2983         int i;
2984         u8 *p;
2985         int r = 0;
2986         u8 b1, b2, b3, b4;
2987
2988         if (dsi->debug_write)
2989                 DSSDBG("dsi_vc_send_long, %d bytes\n", len);
2990
2991         /* len + header */
2992         if (dsi->vc[channel].fifo_size * 32 * 4 < len + 4) {
2993                 DSSERR("unable to send long packet: packet too long.\n");
2994                 return -EINVAL;
2995         }
2996
2997         dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
2998
2999         dsi_vc_write_long_header(dsidev, channel, data_type, len, ecc);
3000
3001         p = data;
3002         for (i = 0; i < len >> 2; i++) {
3003                 if (dsi->debug_write)
3004                         DSSDBG("\tsending full packet %d\n", i);
3005
3006                 b1 = *p++;
3007                 b2 = *p++;
3008                 b3 = *p++;
3009                 b4 = *p++;
3010
3011                 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, b4);
3012         }
3013
3014         i = len % 4;
3015         if (i) {
3016                 b1 = 0; b2 = 0; b3 = 0;
3017
3018                 if (dsi->debug_write)
3019                         DSSDBG("\tsending remainder bytes %d\n", i);
3020
3021                 switch (i) {
3022                 case 3:
3023                         b1 = *p++;
3024                         b2 = *p++;
3025                         b3 = *p++;
3026                         break;
3027                 case 2:
3028                         b1 = *p++;
3029                         b2 = *p++;
3030                         break;
3031                 case 1:
3032                         b1 = *p++;
3033                         break;
3034                 }
3035
3036                 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, 0);
3037         }
3038
3039         return r;
3040 }
3041
3042 static int dsi_vc_send_short(struct platform_device *dsidev, int channel,
3043                 u8 data_type, u16 data, u8 ecc)
3044 {
3045         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3046         u32 r;
3047         u8 data_id;
3048
3049         WARN_ON(!dsi_bus_is_locked(dsidev));
3050
3051         if (dsi->debug_write)
3052                 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
3053                                 channel,
3054                                 data_type, data & 0xff, (data >> 8) & 0xff);
3055
3056         dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
3057
3058         if (FLD_GET(dsi_read_reg(dsidev, DSI_VC_CTRL(channel)), 16, 16)) {
3059                 DSSERR("ERROR FIFO FULL, aborting transfer\n");
3060                 return -EINVAL;
3061         }
3062
3063         data_id = data_type | dsi->vc[channel].vc_id << 6;
3064
3065         r = (data_id << 0) | (data << 8) | (ecc << 24);
3066
3067         dsi_write_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel), r);
3068
3069         return 0;
3070 }
3071
3072 int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel)
3073 {
3074         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3075
3076         return dsi_vc_send_long(dsidev, channel, MIPI_DSI_NULL_PACKET, NULL,
3077                 0, 0);
3078 }
3079 EXPORT_SYMBOL(dsi_vc_send_null);
3080
3081 static int dsi_vc_write_nosync_common(struct omap_dss_device *dssdev,
3082                 int channel, u8 *data, int len, enum dss_dsi_content_type type)
3083 {
3084         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3085         int r;
3086
3087         if (len == 0) {
3088                 BUG_ON(type == DSS_DSI_CONTENT_DCS);
3089                 r = dsi_vc_send_short(dsidev, channel,
3090                                 MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM, 0, 0);
3091         } else if (len == 1) {
3092                 r = dsi_vc_send_short(dsidev, channel,
3093                                 type == DSS_DSI_CONTENT_GENERIC ?
3094                                 MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM :
3095                                 MIPI_DSI_DCS_SHORT_WRITE, data[0], 0);
3096         } else if (len == 2) {
3097                 r = dsi_vc_send_short(dsidev, channel,
3098                                 type == DSS_DSI_CONTENT_GENERIC ?
3099                                 MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM :
3100                                 MIPI_DSI_DCS_SHORT_WRITE_PARAM,
3101                                 data[0] | (data[1] << 8), 0);
3102         } else {
3103                 r = dsi_vc_send_long(dsidev, channel,
3104                                 type == DSS_DSI_CONTENT_GENERIC ?
3105                                 MIPI_DSI_GENERIC_LONG_WRITE :
3106                                 MIPI_DSI_DCS_LONG_WRITE, data, len, 0);
3107         }
3108
3109         return r;
3110 }
3111
3112 int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
3113                 u8 *data, int len)
3114 {
3115         return dsi_vc_write_nosync_common(dssdev, channel, data, len,
3116                         DSS_DSI_CONTENT_DCS);
3117 }
3118 EXPORT_SYMBOL(dsi_vc_dcs_write_nosync);
3119
3120 int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel,
3121                 u8 *data, int len)
3122 {
3123         return dsi_vc_write_nosync_common(dssdev, channel, data, len,
3124                         DSS_DSI_CONTENT_GENERIC);
3125 }
3126 EXPORT_SYMBOL(dsi_vc_generic_write_nosync);
3127
3128 static int dsi_vc_write_common(struct omap_dss_device *dssdev, int channel,
3129                 u8 *data, int len, enum dss_dsi_content_type type)
3130 {
3131         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3132         int r;
3133
3134         r = dsi_vc_write_nosync_common(dssdev, channel, data, len, type);
3135         if (r)
3136                 goto err;
3137
3138         r = dsi_vc_send_bta_sync(dssdev, channel);
3139         if (r)
3140                 goto err;
3141
3142         /* RX_FIFO_NOT_EMPTY */
3143         if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
3144                 DSSERR("rx fifo not empty after write, dumping data:\n");
3145                 dsi_vc_flush_receive_data(dsidev, channel);
3146                 r = -EIO;
3147                 goto err;
3148         }
3149
3150         return 0;
3151 err:
3152         DSSERR("dsi_vc_write_common(ch %d, cmd 0x%02x, len %d) failed\n",
3153                         channel, data[0], len);
3154         return r;
3155 }
3156
3157 int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
3158                 int len)
3159 {
3160         return dsi_vc_write_common(dssdev, channel, data, len,
3161                         DSS_DSI_CONTENT_DCS);
3162 }
3163 EXPORT_SYMBOL(dsi_vc_dcs_write);
3164
3165 int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data,
3166                 int len)
3167 {
3168         return dsi_vc_write_common(dssdev, channel, data, len,
3169                         DSS_DSI_CONTENT_GENERIC);
3170 }
3171 EXPORT_SYMBOL(dsi_vc_generic_write);
3172
3173 int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd)
3174 {
3175         return dsi_vc_dcs_write(dssdev, channel, &dcs_cmd, 1);
3176 }
3177 EXPORT_SYMBOL(dsi_vc_dcs_write_0);
3178
3179 int dsi_vc_generic_write_0(struct omap_dss_device *dssdev, int channel)
3180 {
3181         return dsi_vc_generic_write(dssdev, channel, NULL, 0);
3182 }
3183 EXPORT_SYMBOL(dsi_vc_generic_write_0);
3184
3185 int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3186                 u8 param)
3187 {
3188         u8 buf[2];
3189         buf[0] = dcs_cmd;
3190         buf[1] = param;
3191         return dsi_vc_dcs_write(dssdev, channel, buf, 2);
3192 }
3193 EXPORT_SYMBOL(dsi_vc_dcs_write_1);
3194
3195 int dsi_vc_generic_write_1(struct omap_dss_device *dssdev, int channel,
3196                 u8 param)
3197 {
3198         return dsi_vc_generic_write(dssdev, channel, &param, 1);
3199 }
3200 EXPORT_SYMBOL(dsi_vc_generic_write_1);
3201
3202 int dsi_vc_generic_write_2(struct omap_dss_device *dssdev, int channel,
3203                 u8 param1, u8 param2)
3204 {
3205         u8 buf[2];
3206         buf[0] = param1;
3207         buf[1] = param2;
3208         return dsi_vc_generic_write(dssdev, channel, buf, 2);
3209 }
3210 EXPORT_SYMBOL(dsi_vc_generic_write_2);
3211
3212 static int dsi_vc_dcs_send_read_request(struct omap_dss_device *dssdev,
3213                 int channel, u8 dcs_cmd)
3214 {
3215         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3216         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3217         int r;
3218
3219         if (dsi->debug_read)
3220                 DSSDBG("dsi_vc_dcs_send_read_request(ch%d, dcs_cmd %x)\n",
3221                         channel, dcs_cmd);
3222
3223         r = dsi_vc_send_short(dsidev, channel, MIPI_DSI_DCS_READ, dcs_cmd, 0);
3224         if (r) {
3225                 DSSERR("dsi_vc_dcs_send_read_request(ch %d, cmd 0x%02x)"
3226                         " failed\n", channel, dcs_cmd);
3227                 return r;
3228         }
3229
3230         return 0;
3231 }
3232
3233 static int dsi_vc_generic_send_read_request(struct omap_dss_device *dssdev,
3234                 int channel, u8 *reqdata, int reqlen)
3235 {
3236         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3237         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3238         u16 data;
3239         u8 data_type;
3240         int r;
3241
3242         if (dsi->debug_read)
3243                 DSSDBG("dsi_vc_generic_send_read_request(ch %d, reqlen %d)\n",
3244                         channel, reqlen);
3245
3246         if (reqlen == 0) {
3247                 data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM;
3248                 data = 0;
3249         } else if (reqlen == 1) {
3250                 data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM;
3251                 data = reqdata[0];
3252         } else if (reqlen == 2) {
3253                 data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM;
3254                 data = reqdata[0] | (reqdata[1] << 8);
3255         } else {
3256                 BUG();
3257         }
3258
3259         r = dsi_vc_send_short(dsidev, channel, data_type, data, 0);
3260         if (r) {
3261                 DSSERR("dsi_vc_generic_send_read_request(ch %d, reqlen %d)"
3262                         " failed\n", channel, reqlen);
3263                 return r;
3264         }
3265
3266         return 0;
3267 }
3268
3269 static int dsi_vc_read_rx_fifo(struct platform_device *dsidev, int channel,
3270                 u8 *buf, int buflen, enum dss_dsi_content_type type)
3271 {
3272         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3273         u32 val;
3274         u8 dt;
3275         int r;
3276
3277         /* RX_FIFO_NOT_EMPTY */
3278         if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20) == 0) {
3279                 DSSERR("RX fifo empty when trying to read.\n");
3280                 r = -EIO;
3281                 goto err;
3282         }
3283
3284         val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
3285         if (dsi->debug_read)
3286                 DSSDBG("\theader: %08x\n", val);
3287         dt = FLD_GET(val, 5, 0);
3288         if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
3289                 u16 err = FLD_GET(val, 23, 8);
3290                 dsi_show_rx_ack_with_err(err);
3291                 r = -EIO;
3292                 goto err;
3293
3294         } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3295                         MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE :
3296                         MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE)) {
3297                 u8 data = FLD_GET(val, 15, 8);
3298                 if (dsi->debug_read)
3299                         DSSDBG("\t%s short response, 1 byte: %02x\n",
3300                                 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3301                                 "DCS", data);
3302
3303                 if (buflen < 1) {
3304                         r = -EIO;
3305                         goto err;
3306                 }
3307
3308                 buf[0] = data;
3309
3310                 return 1;
3311         } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3312                         MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE :
3313                         MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE)) {
3314                 u16 data = FLD_GET(val, 23, 8);
3315                 if (dsi->debug_read)
3316                         DSSDBG("\t%s short response, 2 byte: %04x\n",
3317                                 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3318                                 "DCS", data);
3319
3320                 if (buflen < 2) {
3321                         r = -EIO;
3322                         goto err;
3323                 }
3324
3325                 buf[0] = data & 0xff;
3326                 buf[1] = (data >> 8) & 0xff;
3327
3328                 return 2;
3329         } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3330                         MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE :
3331                         MIPI_DSI_RX_DCS_LONG_READ_RESPONSE)) {
3332                 int w;
3333                 int len = FLD_GET(val, 23, 8);
3334                 if (dsi->debug_read)
3335                         DSSDBG("\t%s long response, len %d\n",
3336                                 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3337                                 "DCS", len);
3338
3339                 if (len > buflen) {
3340                         r = -EIO;
3341                         goto err;
3342                 }
3343
3344                 /* two byte checksum ends the packet, not included in len */
3345                 for (w = 0; w < len + 2;) {
3346                         int b;
3347                         val = dsi_read_reg(dsidev,
3348                                 DSI_VC_SHORT_PACKET_HEADER(channel));
3349                         if (dsi->debug_read)
3350                                 DSSDBG("\t\t%02x %02x %02x %02x\n",
3351                                                 (val >> 0) & 0xff,
3352                                                 (val >> 8) & 0xff,
3353                                                 (val >> 16) & 0xff,
3354                                                 (val >> 24) & 0xff);
3355
3356                         for (b = 0; b < 4; ++b) {
3357                                 if (w < len)
3358                                         buf[w] = (val >> (b * 8)) & 0xff;
3359                                 /* we discard the 2 byte checksum */
3360                                 ++w;
3361                         }
3362                 }
3363
3364                 return len;
3365         } else {
3366                 DSSERR("\tunknown datatype 0x%02x\n", dt);
3367                 r = -EIO;
3368                 goto err;
3369         }
3370
3371         BUG();
3372 err:
3373         DSSERR("dsi_vc_read_rx_fifo(ch %d type %s) failed\n", channel,
3374                 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : "DCS");
3375
3376         return r;
3377 }
3378
3379 int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3380                 u8 *buf, int buflen)
3381 {
3382         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3383         int r;
3384
3385         r = dsi_vc_dcs_send_read_request(dssdev, channel, dcs_cmd);
3386         if (r)
3387                 goto err;
3388
3389         r = dsi_vc_send_bta_sync(dssdev, channel);
3390         if (r)
3391                 goto err;
3392
3393         r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
3394                 DSS_DSI_CONTENT_DCS);
3395         if (r < 0)
3396                 goto err;
3397
3398         if (r != buflen) {
3399                 r = -EIO;
3400                 goto err;
3401         }
3402
3403         return 0;
3404 err:
3405         DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", channel, dcs_cmd);
3406         return r;
3407 }
3408 EXPORT_SYMBOL(dsi_vc_dcs_read);
3409
3410 static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int channel,
3411                 u8 *reqdata, int reqlen, u8 *buf, int buflen)
3412 {
3413         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3414         int r;
3415
3416         r = dsi_vc_generic_send_read_request(dssdev, channel, reqdata, reqlen);
3417         if (r)
3418                 return r;
3419
3420         r = dsi_vc_send_bta_sync(dssdev, channel);
3421         if (r)
3422                 return r;
3423
3424         r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
3425                 DSS_DSI_CONTENT_GENERIC);
3426         if (r < 0)
3427                 return r;
3428
3429         if (r != buflen) {
3430                 r = -EIO;
3431                 return r;
3432         }
3433
3434         return 0;
3435 }
3436
3437 int dsi_vc_generic_read_0(struct omap_dss_device *dssdev, int channel, u8 *buf,
3438                 int buflen)
3439 {
3440         int r;
3441
3442         r = dsi_vc_generic_read(dssdev, channel, NULL, 0, buf, buflen);
3443         if (r) {
3444                 DSSERR("dsi_vc_generic_read_0(ch %d) failed\n", channel);
3445                 return r;
3446         }
3447
3448         return 0;
3449 }
3450 EXPORT_SYMBOL(dsi_vc_generic_read_0);
3451
3452 int dsi_vc_generic_read_1(struct omap_dss_device *dssdev, int channel, u8 param,
3453                 u8 *buf, int buflen)
3454 {
3455         int r;
3456
3457         r = dsi_vc_generic_read(dssdev, channel, &param, 1, buf, buflen);
3458         if (r) {
3459                 DSSERR("dsi_vc_generic_read_1(ch %d) failed\n", channel);
3460                 return r;
3461         }
3462
3463         return 0;
3464 }
3465 EXPORT_SYMBOL(dsi_vc_generic_read_1);
3466
3467 int dsi_vc_generic_read_2(struct omap_dss_device *dssdev, int channel,
3468                 u8 param1, u8 param2, u8 *buf, int buflen)
3469 {
3470         int r;
3471         u8 reqdata[2];
3472
3473         reqdata[0] = param1;
3474         reqdata[1] = param2;
3475
3476         r = dsi_vc_generic_read(dssdev, channel, reqdata, 2, buf, buflen);
3477         if (r) {
3478                 DSSERR("dsi_vc_generic_read_2(ch %d) failed\n", channel);
3479                 return r;
3480         }
3481
3482         return 0;
3483 }
3484 EXPORT_SYMBOL(dsi_vc_generic_read_2);
3485
3486 int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
3487                 u16 len)
3488 {
3489         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3490
3491         return dsi_vc_send_short(dsidev, channel,
3492                         MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0);
3493 }
3494 EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size);
3495
3496 static int dsi_enter_ulps(struct platform_device *dsidev)
3497 {
3498         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3499         DECLARE_COMPLETION_ONSTACK(completion);
3500         int r, i;
3501         unsigned mask;
3502
3503         DSSDBGF();
3504
3505         WARN_ON(!dsi_bus_is_locked(dsidev));
3506
3507         WARN_ON(dsi->ulps_enabled);
3508
3509         if (dsi->ulps_enabled)
3510                 return 0;
3511
3512         /* DDR_CLK_ALWAYS_ON */
3513         if (REG_GET(dsidev, DSI_CLK_CTRL, 13, 13)) {
3514                 dsi_if_enable(dsidev, 0);
3515                 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13);
3516                 dsi_if_enable(dsidev, 1);
3517         }
3518
3519         dsi_sync_vc(dsidev, 0);
3520         dsi_sync_vc(dsidev, 1);
3521         dsi_sync_vc(dsidev, 2);
3522         dsi_sync_vc(dsidev, 3);
3523
3524         dsi_force_tx_stop_mode_io(dsidev);
3525
3526         dsi_vc_enable(dsidev, 0, false);
3527         dsi_vc_enable(dsidev, 1, false);
3528         dsi_vc_enable(dsidev, 2, false);
3529         dsi_vc_enable(dsidev, 3, false);
3530
3531         if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 16, 16)) {      /* HS_BUSY */
3532                 DSSERR("HS busy when enabling ULPS\n");
3533                 return -EIO;
3534         }
3535
3536         if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 17, 17)) {      /* LP_BUSY */
3537                 DSSERR("LP busy when enabling ULPS\n");
3538                 return -EIO;
3539         }
3540
3541         r = dsi_register_isr_cio(dsidev, dsi_completion_handler, &completion,
3542                         DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3543         if (r)
3544                 return r;
3545
3546         mask = 0;
3547
3548         for (i = 0; i < dsi->num_lanes_supported; ++i) {
3549                 if (dsi->lanes[i].function == DSI_LANE_UNUSED)
3550                         continue;
3551                 mask |= 1 << i;
3552         }
3553         /* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */
3554         /* LANEx_ULPS_SIG2 */
3555         REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, mask, 9, 5);
3556
3557         /* flush posted write and wait for SCP interface to finish the write */
3558         dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
3559
3560         if (wait_for_completion_timeout(&completion,
3561                                 msecs_to_jiffies(1000)) == 0) {
3562                 DSSERR("ULPS enable timeout\n");
3563                 r = -EIO;
3564                 goto err;
3565         }
3566
3567         dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3568                         DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3569
3570         /* Reset LANEx_ULPS_SIG2 */
3571         REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, 0, 9, 5);
3572
3573         /* flush posted write and wait for SCP interface to finish the write */
3574         dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
3575
3576         dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ULPS);
3577
3578         dsi_if_enable(dsidev, false);
3579
3580         dsi->ulps_enabled = true;
3581
3582         return 0;
3583
3584 err:
3585         dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3586                         DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3587         return r;
3588 }
3589
3590 static void dsi_set_lp_rx_timeout(struct platform_device *dsidev,
3591                 unsigned ticks, bool x4, bool x16)
3592 {
3593         unsigned long fck;
3594         unsigned long total_ticks;
3595         u32 r;
3596
3597         BUG_ON(ticks > 0x1fff);
3598
3599         /* ticks in DSI_FCK */
3600         fck = dsi_fclk_rate(dsidev);
3601
3602         r = dsi_read_reg(dsidev, DSI_TIMING2);
3603         r = FLD_MOD(r, 1, 15, 15);      /* LP_RX_TO */
3604         r = FLD_MOD(r, x16 ? 1 : 0, 14, 14);    /* LP_RX_TO_X16 */
3605         r = FLD_MOD(r, x4 ? 1 : 0, 13, 13);     /* LP_RX_TO_X4 */
3606         r = FLD_MOD(r, ticks, 12, 0);   /* LP_RX_COUNTER */
3607         dsi_write_reg(dsidev, DSI_TIMING2, r);
3608
3609         total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3610
3611         DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3612                         total_ticks,
3613                         ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3614                         (total_ticks * 1000) / (fck / 1000 / 1000));
3615 }
3616
3617 static void dsi_set_ta_timeout(struct platform_device *dsidev, unsigned ticks,
3618                 bool x8, bool x16)
3619 {
3620         unsigned long fck;
3621         unsigned long total_ticks;
3622         u32 r;
3623
3624         BUG_ON(ticks > 0x1fff);
3625
3626         /* ticks in DSI_FCK */
3627         fck = dsi_fclk_rate(dsidev);
3628
3629         r = dsi_read_reg(dsidev, DSI_TIMING1);
3630         r = FLD_MOD(r, 1, 31, 31);      /* TA_TO */
3631         r = FLD_MOD(r, x16 ? 1 : 0, 30, 30);    /* TA_TO_X16 */
3632         r = FLD_MOD(r, x8 ? 1 : 0, 29, 29);     /* TA_TO_X8 */
3633         r = FLD_MOD(r, ticks, 28, 16);  /* TA_TO_COUNTER */
3634         dsi_write_reg(dsidev, DSI_TIMING1, r);
3635
3636         total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1);
3637
3638         DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n",
3639                         total_ticks,
3640                         ticks, x8 ? " x8" : "", x16 ? " x16" : "",
3641                         (total_ticks * 1000) / (fck / 1000 / 1000));
3642 }
3643
3644 static void dsi_set_stop_state_counter(struct platform_device *dsidev,
3645                 unsigned ticks, bool x4, bool x16)
3646 {
3647         unsigned long fck;
3648         unsigned long total_ticks;
3649         u32 r;
3650
3651         BUG_ON(ticks > 0x1fff);
3652
3653         /* ticks in DSI_FCK */
3654         fck = dsi_fclk_rate(dsidev);
3655
3656         r = dsi_read_reg(dsidev, DSI_TIMING1);
3657         r = FLD_MOD(r, 1, 15, 15);      /* FORCE_TX_STOP_MODE_IO */
3658         r = FLD_MOD(r, x16 ? 1 : 0, 14, 14);    /* STOP_STATE_X16_IO */
3659         r = FLD_MOD(r, x4 ? 1 : 0, 13, 13);     /* STOP_STATE_X4_IO */
3660         r = FLD_MOD(r, ticks, 12, 0);   /* STOP_STATE_COUNTER_IO */
3661         dsi_write_reg(dsidev, DSI_TIMING1, r);
3662
3663         total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3664
3665         DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n",
3666                         total_ticks,
3667                         ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3668                         (total_ticks * 1000) / (fck / 1000 / 1000));
3669 }
3670
3671 static void dsi_set_hs_tx_timeout(struct platform_device *dsidev,
3672                 unsigned ticks, bool x4, bool x16)
3673 {
3674         unsigned long fck;
3675         unsigned long total_ticks;
3676         u32 r;
3677
3678         BUG_ON(ticks > 0x1fff);
3679
3680         /* ticks in TxByteClkHS */
3681         fck = dsi_get_txbyteclkhs(dsidev);
3682
3683         r = dsi_read_reg(dsidev, DSI_TIMING2);
3684         r = FLD_MOD(r, 1, 31, 31);      /* HS_TX_TO */
3685         r = FLD_MOD(r, x16 ? 1 : 0, 30, 30);    /* HS_TX_TO_X16 */
3686         r = FLD_MOD(r, x4 ? 1 : 0, 29, 29);     /* HS_TX_TO_X8 (4 really) */
3687         r = FLD_MOD(r, ticks, 28, 16);  /* HS_TX_TO_COUNTER */
3688         dsi_write_reg(dsidev, DSI_TIMING2, r);
3689
3690         total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3691
3692         DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3693                         total_ticks,
3694                         ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3695                         (total_ticks * 1000) / (fck / 1000 / 1000));
3696 }
3697
3698 static void dsi_config_vp_num_line_buffers(struct omap_dss_device *dssdev)
3699 {
3700         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3701         int num_line_buffers;
3702
3703         if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
3704                 int bpp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt);
3705                 unsigned line_buf_size = dsi_get_line_buf_size(dsidev);
3706                 struct omap_video_timings *timings = &dssdev->panel.timings;
3707                 /*
3708                  * Don't use line buffers if width is greater than the video
3709                  * port's line buffer size
3710                  */
3711                 if (line_buf_size <= timings->x_res * bpp / 8)
3712                         num_line_buffers = 0;
3713                 else
3714                         num_line_buffers = 2;
3715         } else {
3716                 /* Use maximum number of line buffers in command mode */
3717                 num_line_buffers = 2;
3718         }
3719
3720         /* LINE_BUFFER */
3721         REG_FLD_MOD(dsidev, DSI_CTRL, num_line_buffers, 13, 12);
3722 }
3723
3724 static void dsi_config_vp_sync_events(struct omap_dss_device *dssdev)
3725 {
3726         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3727         int de_pol = dssdev->panel.dsi_vm_data.vp_de_pol;
3728         int hsync_pol = dssdev->panel.dsi_vm_data.vp_hsync_pol;
3729         int vsync_pol = dssdev->panel.dsi_vm_data.vp_vsync_pol;
3730         bool vsync_end = dssdev->panel.dsi_vm_data.vp_vsync_end;
3731         bool hsync_end = dssdev->panel.dsi_vm_data.vp_hsync_end;
3732         u32 r;
3733
3734         r = dsi_read_reg(dsidev, DSI_CTRL);
3735         r = FLD_MOD(r, de_pol, 9, 9);           /* VP_DE_POL */
3736         r = FLD_MOD(r, hsync_pol, 10, 10);      /* VP_HSYNC_POL */
3737         r = FLD_MOD(r, vsync_pol, 11, 11);      /* VP_VSYNC_POL */
3738         r = FLD_MOD(r, 1, 15, 15);              /* VP_VSYNC_START */
3739         r = FLD_MOD(r, vsync_end, 16, 16);      /* VP_VSYNC_END */
3740         r = FLD_MOD(r, 1, 17, 17);              /* VP_HSYNC_START */
3741         r = FLD_MOD(r, hsync_end, 18, 18);      /* VP_HSYNC_END */
3742         dsi_write_reg(dsidev, DSI_CTRL, r);
3743 }
3744
3745 static void dsi_config_blanking_modes(struct omap_dss_device *dssdev)
3746 {
3747         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3748         int blanking_mode = dssdev->panel.dsi_vm_data.blanking_mode;
3749         int hfp_blanking_mode = dssdev->panel.dsi_vm_data.hfp_blanking_mode;
3750         int hbp_blanking_mode = dssdev->panel.dsi_vm_data.hbp_blanking_mode;
3751         int hsa_blanking_mode = dssdev->panel.dsi_vm_data.hsa_blanking_mode;
3752         u32 r;
3753
3754         /*
3755          * 0 = TX FIFO packets sent or LPS in corresponding blanking periods
3756          * 1 = Long blanking packets are sent in corresponding blanking periods
3757          */
3758         r = dsi_read_reg(dsidev, DSI_CTRL);
3759         r = FLD_MOD(r, blanking_mode, 20, 20);          /* BLANKING_MODE */
3760         r = FLD_MOD(r, hfp_blanking_mode, 21, 21);      /* HFP_BLANKING */
3761         r = FLD_MOD(r, hbp_blanking_mode, 22, 22);      /* HBP_BLANKING */
3762         r = FLD_MOD(r, hsa_blanking_mode, 23, 23);      /* HSA_BLANKING */
3763         dsi_write_reg(dsidev, DSI_CTRL, r);
3764 }
3765
3766 static int dsi_proto_config(struct omap_dss_device *dssdev)
3767 {
3768         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3769         u32 r;
3770         int buswidth = 0;
3771
3772         dsi_config_tx_fifo(dsidev, DSI_FIFO_SIZE_32,
3773                         DSI_FIFO_SIZE_32,
3774                         DSI_FIFO_SIZE_32,
3775                         DSI_FIFO_SIZE_32);
3776
3777         dsi_config_rx_fifo(dsidev, DSI_FIFO_SIZE_32,
3778                         DSI_FIFO_SIZE_32,
3779                         DSI_FIFO_SIZE_32,
3780                         DSI_FIFO_SIZE_32);
3781
3782         /* XXX what values for the timeouts? */
3783         dsi_set_stop_state_counter(dsidev, 0x1000, false, false);
3784         dsi_set_ta_timeout(dsidev, 0x1fff, true, true);
3785         dsi_set_lp_rx_timeout(dsidev, 0x1fff, true, true);
3786         dsi_set_hs_tx_timeout(dsidev, 0x1fff, true, true);
3787
3788         switch (dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt)) {
3789         case 16:
3790                 buswidth = 0;
3791                 break;
3792         case 18:
3793                 buswidth = 1;
3794                 break;
3795         case 24:
3796                 buswidth = 2;
3797                 break;
3798         default:
3799                 BUG();
3800         }
3801
3802         r = dsi_read_reg(dsidev, DSI_CTRL);
3803         r = FLD_MOD(r, 1, 1, 1);        /* CS_RX_EN */
3804         r = FLD_MOD(r, 1, 2, 2);        /* ECC_RX_EN */
3805         r = FLD_MOD(r, 1, 3, 3);        /* TX_FIFO_ARBITRATION */
3806         r = FLD_MOD(r, 1, 4, 4);        /* VP_CLK_RATIO, always 1, see errata*/
3807         r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
3808         r = FLD_MOD(r, 0, 8, 8);        /* VP_CLK_POL */
3809         r = FLD_MOD(r, 1, 14, 14);      /* TRIGGER_RESET_MODE */
3810         r = FLD_MOD(r, 1, 19, 19);      /* EOT_ENABLE */
3811         if (!dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
3812                 r = FLD_MOD(r, 1, 24, 24);      /* DCS_CMD_ENABLE */
3813                 /* DCS_CMD_CODE, 1=start, 0=continue */
3814                 r = FLD_MOD(r, 0, 25, 25);
3815         }
3816
3817         dsi_write_reg(dsidev, DSI_CTRL, r);
3818
3819         dsi_config_vp_num_line_buffers(dssdev);
3820
3821         if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
3822                 dsi_config_vp_sync_events(dssdev);
3823                 dsi_config_blanking_modes(dssdev);
3824         }
3825
3826         dsi_vc_initial_config(dsidev, 0);
3827         dsi_vc_initial_config(dsidev, 1);
3828         dsi_vc_initial_config(dsidev, 2);
3829         dsi_vc_initial_config(dsidev, 3);
3830
3831         return 0;
3832 }
3833
3834 static void dsi_proto_timings(struct omap_dss_device *dssdev)
3835 {
3836         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3837         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3838         unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail;
3839         unsigned tclk_pre, tclk_post;
3840         unsigned ths_prepare, ths_prepare_ths_zero, ths_zero;
3841         unsigned ths_trail, ths_exit;
3842         unsigned ddr_clk_pre, ddr_clk_post;
3843         unsigned enter_hs_mode_lat, exit_hs_mode_lat;
3844         unsigned ths_eot;
3845         int ndl = dsi->num_lanes_used - 1;
3846         u32 r;
3847
3848         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
3849         ths_prepare = FLD_GET(r, 31, 24);
3850         ths_prepare_ths_zero = FLD_GET(r, 23, 16);
3851         ths_zero = ths_prepare_ths_zero - ths_prepare;
3852         ths_trail = FLD_GET(r, 15, 8);
3853         ths_exit = FLD_GET(r, 7, 0);
3854
3855         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
3856         tlpx = FLD_GET(r, 22, 16) * 2;
3857         tclk_trail = FLD_GET(r, 15, 8);
3858         tclk_zero = FLD_GET(r, 7, 0);
3859
3860         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
3861         tclk_prepare = FLD_GET(r, 7, 0);
3862
3863         /* min 8*UI */
3864         tclk_pre = 20;
3865         /* min 60ns + 52*UI */
3866         tclk_post = ns2ddr(dsidev, 60) + 26;
3867
3868         ths_eot = DIV_ROUND_UP(4, ndl);
3869
3870         ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
3871                         4);
3872         ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot;
3873
3874         BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
3875         BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);
3876
3877         r = dsi_read_reg(dsidev, DSI_CLK_TIMING);
3878         r = FLD_MOD(r, ddr_clk_pre, 15, 8);
3879         r = FLD_MOD(r, ddr_clk_post, 7, 0);
3880         dsi_write_reg(dsidev, DSI_CLK_TIMING, r);
3881
3882         DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
3883                         ddr_clk_pre,
3884                         ddr_clk_post);
3885
3886         enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) +
3887                 DIV_ROUND_UP(ths_prepare, 4) +
3888                 DIV_ROUND_UP(ths_zero + 3, 4);
3889
3890         exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;
3891
3892         r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
3893                 FLD_VAL(exit_hs_mode_lat, 15, 0);
3894         dsi_write_reg(dsidev, DSI_VM_TIMING7, r);
3895
3896         DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
3897                         enter_hs_mode_lat, exit_hs_mode_lat);
3898
3899          if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
3900                 /* TODO: Implement a video mode check_timings function */
3901                 int hsa = dssdev->panel.dsi_vm_data.hsa;
3902                 int hfp = dssdev->panel.dsi_vm_data.hfp;
3903                 int hbp = dssdev->panel.dsi_vm_data.hbp;
3904                 int vsa = dssdev->panel.dsi_vm_data.vsa;
3905                 int vfp = dssdev->panel.dsi_vm_data.vfp;
3906                 int vbp = dssdev->panel.dsi_vm_data.vbp;
3907                 int window_sync = dssdev->panel.dsi_vm_data.window_sync;
3908                 bool hsync_end = dssdev->panel.dsi_vm_data.vp_hsync_end;
3909                 struct omap_video_timings *timings = &dssdev->panel.timings;
3910                 int bpp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt);
3911                 int tl, t_he, width_bytes;
3912
3913                 t_he = hsync_end ?
3914                         ((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0;
3915
3916                 width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8);
3917
3918                 /* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */
3919                 tl = DIV_ROUND_UP(4, ndl) + (hsync_end ? hsa : 0) + t_he + hfp +
3920                         DIV_ROUND_UP(width_bytes + 6, ndl) + hbp;
3921
3922                 DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp,
3923                         hfp, hsync_end ? hsa : 0, tl);
3924                 DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp, vfp,
3925                         vsa, timings->y_res);
3926
3927                 r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
3928                 r = FLD_MOD(r, hbp, 11, 0);     /* HBP */
3929                 r = FLD_MOD(r, hfp, 23, 12);    /* HFP */
3930                 r = FLD_MOD(r, hsync_end ? hsa : 0, 31, 24);    /* HSA */
3931                 dsi_write_reg(dsidev, DSI_VM_TIMING1, r);
3932
3933                 r = dsi_read_reg(dsidev, DSI_VM_TIMING2);
3934                 r = FLD_MOD(r, vbp, 7, 0);      /* VBP */
3935                 r = FLD_MOD(r, vfp, 15, 8);     /* VFP */
3936                 r = FLD_MOD(r, vsa, 23, 16);    /* VSA */
3937                 r = FLD_MOD(r, window_sync, 27, 24);    /* WINDOW_SYNC */
3938                 dsi_write_reg(dsidev, DSI_VM_TIMING2, r);
3939
3940                 r = dsi_read_reg(dsidev, DSI_VM_TIMING3);
3941                 r = FLD_MOD(r, timings->y_res, 14, 0);  /* VACT */
3942                 r = FLD_MOD(r, tl, 31, 16);             /* TL */
3943                 dsi_write_reg(dsidev, DSI_VM_TIMING3, r);
3944         }
3945 }
3946
3947 int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel)
3948 {
3949         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3950         int bpp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt);
3951         u8 data_type;
3952         u16 word_count;
3953         int r;
3954
3955         if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
3956                 switch (dssdev->panel.dsi_pix_fmt) {
3957                 case OMAP_DSS_DSI_FMT_RGB888:
3958                         data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24;
3959                         break;
3960                 case OMAP_DSS_DSI_FMT_RGB666:
3961                         data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
3962                         break;
3963                 case OMAP_DSS_DSI_FMT_RGB666_PACKED:
3964                         data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18;
3965                         break;
3966                 case OMAP_DSS_DSI_FMT_RGB565:
3967                         data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16;
3968                         break;
3969                 default:
3970                         BUG();
3971                 };
3972
3973                 dsi_if_enable(dsidev, false);
3974                 dsi_vc_enable(dsidev, channel, false);
3975
3976                 /* MODE, 1 = video mode */
3977                 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 4, 4);
3978
3979                 word_count = DIV_ROUND_UP(dssdev->panel.timings.x_res * bpp, 8);
3980
3981                 dsi_vc_write_long_header(dsidev, channel, data_type,
3982                                 word_count, 0);
3983
3984                 dsi_vc_enable(dsidev, channel, true);
3985                 dsi_if_enable(dsidev, true);
3986         }
3987
3988         r = dss_mgr_enable(dssdev->manager);
3989         if (r) {
3990                 if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
3991                         dsi_if_enable(dsidev, false);
3992                         dsi_vc_enable(dsidev, channel, false);
3993                 }
3994
3995                 return r;
3996         }
3997
3998         return 0;
3999 }
4000 EXPORT_SYMBOL(dsi_enable_video_output);
4001
4002 void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel)
4003 {
4004         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4005
4006         if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
4007                 dsi_if_enable(dsidev, false);
4008                 dsi_vc_enable(dsidev, channel, false);
4009
4010                 /* MODE, 0 = command mode */
4011                 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 0, 4, 4);
4012
4013                 dsi_vc_enable(dsidev, channel, true);
4014                 dsi_if_enable(dsidev, true);
4015         }
4016
4017         dss_mgr_disable(dssdev->manager);
4018 }
4019 EXPORT_SYMBOL(dsi_disable_video_output);
4020
4021 static void dsi_update_screen_dispc(struct omap_dss_device *dssdev,
4022                 u16 w, u16 h)
4023 {
4024         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4025         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4026         unsigned bytespp;
4027         unsigned bytespl;
4028         unsigned bytespf;
4029         unsigned total_len;
4030         unsigned packet_payload;
4031         unsigned packet_len;
4032         u32 l;
4033         int r;
4034         const unsigned channel = dsi->update_channel;
4035         const unsigned line_buf_size = dsi_get_line_buf_size(dsidev);
4036
4037         DSSDBG("dsi_update_screen_dispc(%dx%d)\n", w, h);
4038
4039         dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_VP);
4040
4041         bytespp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt) / 8;
4042         bytespl = w * bytespp;
4043         bytespf = bytespl * h;
4044
4045         /* NOTE: packet_payload has to be equal to N * bytespl, where N is
4046          * number of lines in a packet.  See errata about VP_CLK_RATIO */
4047
4048         if (bytespf < line_buf_size)
4049                 packet_payload = bytespf;
4050         else
4051                 packet_payload = (line_buf_size) / bytespl * bytespl;
4052
4053         packet_len = packet_payload + 1;        /* 1 byte for DCS cmd */
4054         total_len = (bytespf / packet_payload) * packet_len;
4055
4056         if (bytespf % packet_payload)
4057                 total_len += (bytespf % packet_payload) + 1;
4058
4059         l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
4060         dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
4061
4062         dsi_vc_write_long_header(dsidev, channel, MIPI_DSI_DCS_LONG_WRITE,
4063                 packet_len, 0);
4064
4065         if (dsi->te_enabled)
4066                 l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
4067         else
4068                 l = FLD_MOD(l, 1, 31, 31); /* TE_START */
4069         dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
4070
4071         /* We put SIDLEMODE to no-idle for the duration of the transfer,
4072          * because DSS interrupts are not capable of waking up the CPU and the
4073          * framedone interrupt could be delayed for quite a long time. I think
4074          * the same goes for any DSS interrupts, but for some reason I have not
4075          * seen the problem anywhere else than here.
4076          */
4077         dispc_disable_sidle();
4078
4079         dsi_perf_mark_start(dsidev);
4080
4081         r = schedule_delayed_work(&dsi->framedone_timeout_work,
4082                 msecs_to_jiffies(250));
4083         BUG_ON(r == 0);
4084
4085         dss_mgr_start_update(dssdev->manager);
4086
4087         if (dsi->te_enabled) {
4088                 /* disable LP_RX_TO, so that we can receive TE.  Time to wait
4089                  * for TE is longer than the timer allows */
4090                 REG_FLD_MOD(dsidev, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
4091
4092                 dsi_vc_send_bta(dsidev, channel);
4093
4094 #ifdef DSI_CATCH_MISSING_TE
4095                 mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250));
4096 #endif
4097         }
4098 }
4099
4100 #ifdef DSI_CATCH_MISSING_TE
4101 static void dsi_te_timeout(unsigned long arg)
4102 {
4103         DSSERR("TE not received for 250ms!\n");
4104 }
4105 #endif
4106
4107 static void dsi_handle_framedone(struct platform_device *dsidev, int error)
4108 {
4109         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4110
4111         /* SIDLEMODE back to smart-idle */
4112         dispc_enable_sidle();
4113
4114         if (dsi->te_enabled) {
4115                 /* enable LP_RX_TO again after the TE */
4116                 REG_FLD_MOD(dsidev, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
4117         }
4118
4119         dsi->framedone_callback(error, dsi->framedone_data);
4120
4121         if (!error)
4122                 dsi_perf_show(dsidev, "DISPC");
4123 }
4124
4125 static void dsi_framedone_timeout_work_callback(struct work_struct *work)
4126 {
4127         struct dsi_data *dsi = container_of(work, struct dsi_data,
4128                         framedone_timeout_work.work);
4129         /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after
4130          * 250ms which would conflict with this timeout work. What should be
4131          * done is first cancel the transfer on the HW, and then cancel the
4132          * possibly scheduled framedone work. However, cancelling the transfer
4133          * on the HW is buggy, and would probably require resetting the whole
4134          * DSI */
4135
4136         DSSERR("Framedone not received for 250ms!\n");
4137
4138         dsi_handle_framedone(dsi->pdev, -ETIMEDOUT);
4139 }
4140
4141 static void dsi_framedone_irq_callback(void *data, u32 mask)
4142 {
4143         struct omap_dss_device *dssdev = (struct omap_dss_device *) data;
4144         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4145         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4146
4147         /* Note: We get FRAMEDONE when DISPC has finished sending pixels and
4148          * turns itself off. However, DSI still has the pixels in its buffers,
4149          * and is sending the data.
4150          */
4151
4152         __cancel_delayed_work(&dsi->framedone_timeout_work);
4153
4154         dsi_handle_framedone(dsidev, 0);
4155
4156 #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
4157         dispc_fake_vsync_irq();
4158 #endif
4159 }
4160
4161 int omap_dsi_update(struct omap_dss_device *dssdev, int channel,
4162                 void (*callback)(int, void *), void *data)
4163 {
4164         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4165         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4166         u16 dw, dh;
4167
4168         dsi_perf_mark_setup(dsidev);
4169
4170         dsi->update_channel = channel;
4171
4172         dsi->framedone_callback = callback;
4173         dsi->framedone_data = data;
4174
4175         dssdev->driver->get_resolution(dssdev, &dw, &dh);
4176
4177 #ifdef DEBUG
4178         dsi->update_bytes = dw * dh *
4179                 dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt) / 8;
4180 #endif
4181         dsi_update_screen_dispc(dssdev, dw, dh);
4182
4183         return 0;
4184 }
4185 EXPORT_SYMBOL(omap_dsi_update);
4186
4187 /* Display funcs */
4188
4189 static int dsi_display_init_dispc(struct omap_dss_device *dssdev)
4190 {
4191         int r;
4192
4193         if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) {
4194                 u16 dw, dh;
4195                 u32 irq;
4196                 struct omap_video_timings timings = {
4197                         .hsw            = 1,
4198                         .hfp            = 1,
4199                         .hbp            = 1,
4200                         .vsw            = 1,
4201                         .vfp            = 0,
4202                         .vbp            = 0,
4203                 };
4204
4205                 dssdev->driver->get_resolution(dssdev, &dw, &dh);
4206                 timings.x_res = dw;
4207                 timings.y_res = dh;
4208
4209                 irq = dssdev->manager->id == OMAP_DSS_CHANNEL_LCD ?
4210                         DISPC_IRQ_FRAMEDONE : DISPC_IRQ_FRAMEDONE2;
4211
4212                 r = omap_dispc_register_isr(dsi_framedone_irq_callback,
4213                         (void *) dssdev, irq);
4214                 if (r) {
4215                         DSSERR("can't get FRAMEDONE irq\n");
4216                         return r;
4217                 }
4218
4219                 dispc_mgr_enable_stallmode(dssdev->manager->id, true);
4220                 dispc_mgr_enable_fifohandcheck(dssdev->manager->id, 1);
4221
4222                 dispc_mgr_set_lcd_timings(dssdev->manager->id, &timings);
4223         } else {
4224                 dispc_mgr_enable_stallmode(dssdev->manager->id, false);
4225                 dispc_mgr_enable_fifohandcheck(dssdev->manager->id, 0);
4226
4227                 dispc_mgr_set_lcd_timings(dssdev->manager->id,
4228                         &dssdev->panel.timings);
4229         }
4230
4231                 dispc_mgr_set_lcd_display_type(dssdev->manager->id,
4232                         OMAP_DSS_LCD_DISPLAY_TFT);
4233                 dispc_mgr_set_tft_data_lines(dssdev->manager->id,
4234                         dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt));
4235         return 0;
4236 }
4237
4238 static void dsi_display_uninit_dispc(struct omap_dss_device *dssdev)
4239 {
4240         if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) {
4241                 u32 irq;
4242
4243                 irq = dssdev->manager->id == OMAP_DSS_CHANNEL_LCD ?
4244                         DISPC_IRQ_FRAMEDONE : DISPC_IRQ_FRAMEDONE2;
4245
4246                 omap_dispc_unregister_isr(dsi_framedone_irq_callback,
4247                         (void *) dssdev, irq);
4248         }
4249 }
4250
4251 static int dsi_configure_dsi_clocks(struct omap_dss_device *dssdev)
4252 {
4253         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4254         struct dsi_clock_info cinfo;
4255         int r;
4256
4257         cinfo.regn  = dssdev->clocks.dsi.regn;
4258         cinfo.regm  = dssdev->clocks.dsi.regm;
4259         cinfo.regm_dispc = dssdev->clocks.dsi.regm_dispc;
4260         cinfo.regm_dsi = dssdev->clocks.dsi.regm_dsi;
4261         r = dsi_calc_clock_rates(dsidev, &cinfo);
4262         if (r) {
4263                 DSSERR("Failed to calc dsi clocks\n");
4264                 return r;
4265         }
4266
4267         r = dsi_pll_set_clock_div(dsidev, &cinfo);
4268         if (r) {
4269                 DSSERR("Failed to set dsi clocks\n");
4270                 return r;
4271         }
4272
4273         return 0;
4274 }
4275
4276 static int dsi_configure_dispc_clocks(struct omap_dss_device *dssdev)
4277 {
4278         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4279         struct dispc_clock_info dispc_cinfo;
4280         int r;
4281         unsigned long long fck;
4282
4283         fck = dsi_get_pll_hsdiv_dispc_rate(dsidev);
4284
4285         dispc_cinfo.lck_div = dssdev->clocks.dispc.channel.lck_div;
4286         dispc_cinfo.pck_div = dssdev->clocks.dispc.channel.pck_div;
4287
4288         r = dispc_calc_clock_rates(fck, &dispc_cinfo);
4289         if (r) {
4290                 DSSERR("Failed to calc dispc clocks\n");
4291                 return r;
4292         }
4293
4294         r = dispc_mgr_set_clock_div(dssdev->manager->id, &dispc_cinfo);
4295         if (r) {
4296                 DSSERR("Failed to set dispc clocks\n");
4297                 return r;
4298         }
4299
4300         return 0;
4301 }
4302
4303 static int dsi_display_init_dsi(struct omap_dss_device *dssdev)
4304 {
4305         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4306         int dsi_module = dsi_get_dsidev_id(dsidev);
4307         int r;
4308
4309         r = dsi_parse_lane_config(dssdev);
4310         if (r) {
4311                 DSSERR("illegal lane config");
4312                 goto err0;
4313         }
4314
4315         r = dsi_pll_init(dsidev, true, true);
4316         if (r)
4317                 goto err0;
4318
4319         r = dsi_configure_dsi_clocks(dssdev);
4320         if (r)
4321                 goto err1;
4322
4323         dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src);
4324         dss_select_dsi_clk_source(dsi_module, dssdev->clocks.dsi.dsi_fclk_src);
4325         dss_select_lcd_clk_source(dssdev->manager->id,
4326                         dssdev->clocks.dispc.channel.lcd_clk_src);
4327
4328         DSSDBG("PLL OK\n");
4329
4330         r = dsi_configure_dispc_clocks(dssdev);
4331         if (r)
4332                 goto err2;
4333
4334         r = dsi_cio_init(dssdev);
4335         if (r)
4336                 goto err2;
4337
4338         _dsi_print_reset_status(dsidev);
4339
4340         dsi_proto_timings(dssdev);
4341         dsi_set_lp_clk_divisor(dssdev);
4342
4343         if (1)
4344                 _dsi_print_reset_status(dsidev);
4345
4346         r = dsi_proto_config(dssdev);
4347         if (r)
4348                 goto err3;
4349
4350         /* enable interface */
4351         dsi_vc_enable(dsidev, 0, 1);
4352         dsi_vc_enable(dsidev, 1, 1);
4353         dsi_vc_enable(dsidev, 2, 1);
4354         dsi_vc_enable(dsidev, 3, 1);
4355         dsi_if_enable(dsidev, 1);
4356         dsi_force_tx_stop_mode_io(dsidev);
4357
4358         return 0;
4359 err3:
4360         dsi_cio_uninit(dssdev);
4361 err2:
4362         dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
4363         dss_select_dsi_clk_source(dsi_module, OMAP_DSS_CLK_SRC_FCK);
4364         dss_select_lcd_clk_source(dssdev->manager->id, OMAP_DSS_CLK_SRC_FCK);
4365
4366 err1:
4367         dsi_pll_uninit(dsidev, true);
4368 err0:
4369         return r;
4370 }
4371
4372 static void dsi_display_uninit_dsi(struct omap_dss_device *dssdev,
4373                 bool disconnect_lanes, bool enter_ulps)
4374 {
4375         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4376         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4377         int dsi_module = dsi_get_dsidev_id(dsidev);
4378
4379         if (enter_ulps && !dsi->ulps_enabled)
4380                 dsi_enter_ulps(dsidev);
4381
4382         /* disable interface */
4383         dsi_if_enable(dsidev, 0);
4384         dsi_vc_enable(dsidev, 0, 0);
4385         dsi_vc_enable(dsidev, 1, 0);
4386         dsi_vc_enable(dsidev, 2, 0);
4387         dsi_vc_enable(dsidev, 3, 0);
4388
4389         dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
4390         dss_select_dsi_clk_source(dsi_module, OMAP_DSS_CLK_SRC_FCK);
4391         dss_select_lcd_clk_source(dssdev->manager->id, OMAP_DSS_CLK_SRC_FCK);
4392         dsi_cio_uninit(dssdev);
4393         dsi_pll_uninit(dsidev, disconnect_lanes);
4394 }
4395
4396 int omapdss_dsi_display_enable(struct omap_dss_device *dssdev)
4397 {
4398         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4399         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4400         int r = 0;
4401
4402         DSSDBG("dsi_display_enable\n");
4403
4404         WARN_ON(!dsi_bus_is_locked(dsidev));
4405
4406         mutex_lock(&dsi->lock);
4407
4408         if (dssdev->manager == NULL) {
4409                 DSSERR("failed to enable display: no manager\n");
4410                 r = -ENODEV;
4411                 goto err_start_dev;
4412         }
4413
4414         r = omap_dss_start_device(dssdev);
4415         if (r) {
4416                 DSSERR("failed to start device\n");
4417                 goto err_start_dev;
4418         }
4419
4420         r = dsi_runtime_get(dsidev);
4421         if (r)
4422                 goto err_get_dsi;
4423
4424         dsi_enable_pll_clock(dsidev, 1);
4425
4426         _dsi_initialize_irq(dsidev);
4427
4428         r = dsi_display_init_dispc(dssdev);
4429         if (r)
4430                 goto err_init_dispc;
4431
4432         r = dsi_display_init_dsi(dssdev);
4433         if (r)
4434                 goto err_init_dsi;
4435
4436         mutex_unlock(&dsi->lock);
4437
4438         return 0;
4439
4440 err_init_dsi:
4441         dsi_display_uninit_dispc(dssdev);
4442 err_init_dispc:
4443         dsi_enable_pll_clock(dsidev, 0);
4444         dsi_runtime_put(dsidev);
4445 err_get_dsi:
4446         omap_dss_stop_device(dssdev);
4447 err_start_dev:
4448         mutex_unlock(&dsi->lock);
4449         DSSDBG("dsi_display_enable FAILED\n");
4450         return r;
4451 }
4452 EXPORT_SYMBOL(omapdss_dsi_display_enable);
4453
4454 void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
4455                 bool disconnect_lanes, bool enter_ulps)
4456 {
4457         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4458         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4459
4460         DSSDBG("dsi_display_disable\n");
4461
4462         WARN_ON(!dsi_bus_is_locked(dsidev));
4463
4464         mutex_lock(&dsi->lock);
4465
4466         dsi_sync_vc(dsidev, 0);
4467         dsi_sync_vc(dsidev, 1);
4468         dsi_sync_vc(dsidev, 2);
4469         dsi_sync_vc(dsidev, 3);
4470
4471         dsi_display_uninit_dispc(dssdev);
4472
4473         dsi_display_uninit_dsi(dssdev, disconnect_lanes, enter_ulps);
4474
4475         dsi_runtime_put(dsidev);
4476         dsi_enable_pll_clock(dsidev, 0);
4477
4478         omap_dss_stop_device(dssdev);
4479
4480         mutex_unlock(&dsi->lock);
4481 }
4482 EXPORT_SYMBOL(omapdss_dsi_display_disable);
4483
4484 int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable)
4485 {
4486         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4487         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4488
4489         dsi->te_enabled = enable;
4490         return 0;
4491 }
4492 EXPORT_SYMBOL(omapdss_dsi_enable_te);
4493
4494 int dsi_init_display(struct omap_dss_device *dssdev)
4495 {
4496         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4497         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4498
4499         DSSDBG("DSI init\n");
4500
4501         if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) {
4502                 dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE |
4503                         OMAP_DSS_DISPLAY_CAP_TEAR_ELIM;
4504         }
4505
4506         if (dsi->vdds_dsi_reg == NULL) {
4507                 struct regulator *vdds_dsi;
4508
4509                 vdds_dsi = regulator_get(&dsi->pdev->dev, "vdds_dsi");
4510
4511                 if (IS_ERR(vdds_dsi)) {
4512                         DSSERR("can't get VDDS_DSI regulator\n");
4513                         return PTR_ERR(vdds_dsi);
4514                 }
4515
4516                 dsi->vdds_dsi_reg = vdds_dsi;
4517         }
4518
4519         return 0;
4520 }
4521
4522 int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel)
4523 {
4524         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4525         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4526         int i;
4527
4528         for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
4529                 if (!dsi->vc[i].dssdev) {
4530                         dsi->vc[i].dssdev = dssdev;
4531                         *channel = i;
4532                         return 0;
4533                 }
4534         }
4535
4536         DSSERR("cannot get VC for display %s", dssdev->name);
4537         return -ENOSPC;
4538 }
4539 EXPORT_SYMBOL(omap_dsi_request_vc);
4540
4541 int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id)
4542 {
4543         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4544         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4545
4546         if (vc_id < 0 || vc_id > 3) {
4547                 DSSERR("VC ID out of range\n");
4548                 return -EINVAL;
4549         }
4550
4551         if (channel < 0 || channel > 3) {
4552                 DSSERR("Virtual Channel out of range\n");
4553                 return -EINVAL;
4554         }
4555
4556         if (dsi->vc[channel].dssdev != dssdev) {
4557                 DSSERR("Virtual Channel not allocated to display %s\n",
4558                         dssdev->name);
4559                 return -EINVAL;
4560         }
4561
4562         dsi->vc[channel].vc_id = vc_id;
4563
4564         return 0;
4565 }
4566 EXPORT_SYMBOL(omap_dsi_set_vc_id);
4567
4568 void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel)
4569 {
4570         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4571         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4572
4573         if ((channel >= 0 && channel <= 3) &&
4574                 dsi->vc[channel].dssdev == dssdev) {
4575                 dsi->vc[channel].dssdev = NULL;
4576                 dsi->vc[channel].vc_id = 0;
4577         }
4578 }
4579 EXPORT_SYMBOL(omap_dsi_release_vc);
4580
4581 void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev)
4582 {
4583         if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 7, 1) != 1)
4584                 DSSERR("%s (%s) not active\n",
4585                         dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
4586                         dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC));
4587 }
4588
4589 void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev)
4590 {
4591         if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 8, 1) != 1)
4592                 DSSERR("%s (%s) not active\n",
4593                         dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
4594                         dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI));
4595 }
4596
4597 static void dsi_calc_clock_param_ranges(struct platform_device *dsidev)
4598 {
4599         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4600
4601         dsi->regn_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGN);
4602         dsi->regm_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM);
4603         dsi->regm_dispc_max =
4604                 dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DISPC);
4605         dsi->regm_dsi_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DSI);
4606         dsi->fint_min = dss_feat_get_param_min(FEAT_PARAM_DSIPLL_FINT);
4607         dsi->fint_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_FINT);
4608         dsi->lpdiv_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV);
4609 }
4610
4611 static int dsi_get_clocks(struct platform_device *dsidev)
4612 {
4613         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4614         struct clk *clk;
4615
4616         clk = clk_get(&dsidev->dev, "fck");
4617         if (IS_ERR(clk)) {
4618                 DSSERR("can't get fck\n");
4619                 return PTR_ERR(clk);
4620         }
4621
4622         dsi->dss_clk = clk;
4623
4624         clk = clk_get(&dsidev->dev, "sys_clk");
4625         if (IS_ERR(clk)) {
4626                 DSSERR("can't get sys_clk\n");
4627                 clk_put(dsi->dss_clk);
4628                 dsi->dss_clk = NULL;
4629                 return PTR_ERR(clk);
4630         }
4631
4632         dsi->sys_clk = clk;
4633
4634         return 0;
4635 }
4636
4637 static void dsi_put_clocks(struct platform_device *dsidev)
4638 {
4639         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4640
4641         if (dsi->dss_clk)
4642                 clk_put(dsi->dss_clk);
4643         if (dsi->sys_clk)
4644                 clk_put(dsi->sys_clk);
4645 }
4646
4647 /* DSI1 HW IP initialisation */
4648 static int omap_dsihw_probe(struct platform_device *dsidev)
4649 {
4650         struct omap_display_platform_data *dss_plat_data;
4651         struct omap_dss_board_info *board_info;
4652         u32 rev;
4653         int r, i, dsi_module = dsi_get_dsidev_id(dsidev);
4654         struct resource *dsi_mem;
4655         struct dsi_data *dsi;
4656
4657         dsi = devm_kzalloc(&dsidev->dev, sizeof(*dsi), GFP_KERNEL);
4658         if (!dsi)
4659                 return -ENOMEM;
4660
4661         dsi->pdev = dsidev;
4662         dsi_pdev_map[dsi_module] = dsidev;
4663         dev_set_drvdata(&dsidev->dev, dsi);
4664
4665         dss_plat_data = dsidev->dev.platform_data;
4666         board_info = dss_plat_data->board_data;
4667         dsi->enable_pads = board_info->dsi_enable_pads;
4668         dsi->disable_pads = board_info->dsi_disable_pads;
4669
4670         spin_lock_init(&dsi->irq_lock);
4671         spin_lock_init(&dsi->errors_lock);
4672         dsi->errors = 0;
4673
4674 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
4675         spin_lock_init(&dsi->irq_stats_lock);
4676         dsi->irq_stats.last_reset = jiffies;
4677 #endif
4678
4679         mutex_init(&dsi->lock);
4680         sema_init(&dsi->bus_lock, 1);
4681
4682         INIT_DELAYED_WORK_DEFERRABLE(&dsi->framedone_timeout_work,
4683                         dsi_framedone_timeout_work_callback);
4684
4685 #ifdef DSI_CATCH_MISSING_TE
4686         init_timer(&dsi->te_timer);
4687         dsi->te_timer.function = dsi_te_timeout;
4688         dsi->te_timer.data = 0;
4689 #endif
4690         dsi_mem = platform_get_resource(dsi->pdev, IORESOURCE_MEM, 0);
4691         if (!dsi_mem) {
4692                 DSSERR("can't get IORESOURCE_MEM DSI\n");
4693                 return -EINVAL;
4694         }
4695
4696         dsi->base = devm_ioremap(&dsidev->dev, dsi_mem->start,
4697                                  resource_size(dsi_mem));
4698         if (!dsi->base) {
4699                 DSSERR("can't ioremap DSI\n");
4700                 return -ENOMEM;
4701         }
4702
4703         dsi->irq = platform_get_irq(dsi->pdev, 0);
4704         if (dsi->irq < 0) {
4705                 DSSERR("platform_get_irq failed\n");
4706                 return -ENODEV;
4707         }
4708
4709         r = devm_request_irq(&dsidev->dev, dsi->irq, omap_dsi_irq_handler,
4710                              IRQF_SHARED, dev_name(&dsidev->dev), dsi->pdev);
4711         if (r < 0) {
4712                 DSSERR("request_irq failed\n");
4713                 return r;
4714         }
4715
4716         /* DSI VCs initialization */
4717         for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
4718                 dsi->vc[i].source = DSI_VC_SOURCE_L4;
4719                 dsi->vc[i].dssdev = NULL;
4720                 dsi->vc[i].vc_id = 0;
4721         }
4722
4723         dsi_calc_clock_param_ranges(dsidev);
4724
4725         r = dsi_get_clocks(dsidev);
4726         if (r)
4727                 return r;
4728
4729         pm_runtime_enable(&dsidev->dev);
4730
4731         r = dsi_runtime_get(dsidev);
4732         if (r)
4733                 goto err_runtime_get;
4734
4735         rev = dsi_read_reg(dsidev, DSI_REVISION);
4736         dev_dbg(&dsidev->dev, "OMAP DSI rev %d.%d\n",
4737                FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
4738
4739         /* DSI on OMAP3 doesn't have register DSI_GNQ, set number
4740          * of data to 3 by default */
4741         if (dss_has_feature(FEAT_DSI_GNQ))
4742                 /* NB_DATA_LANES */
4743                 dsi->num_lanes_supported = 1 + REG_GET(dsidev, DSI_GNQ, 11, 9);
4744         else
4745                 dsi->num_lanes_supported = 3;
4746
4747         dsi_runtime_put(dsidev);
4748
4749         return 0;
4750
4751 err_runtime_get:
4752         pm_runtime_disable(&dsidev->dev);
4753         dsi_put_clocks(dsidev);
4754         return r;
4755 }
4756
4757 static int omap_dsihw_remove(struct platform_device *dsidev)
4758 {
4759         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4760
4761         WARN_ON(dsi->scp_clk_refcount > 0);
4762
4763         pm_runtime_disable(&dsidev->dev);
4764
4765         dsi_put_clocks(dsidev);
4766
4767         if (dsi->vdds_dsi_reg != NULL) {
4768                 if (dsi->vdds_dsi_enabled) {
4769                         regulator_disable(dsi->vdds_dsi_reg);
4770                         dsi->vdds_dsi_enabled = false;
4771                 }
4772
4773                 regulator_put(dsi->vdds_dsi_reg);
4774                 dsi->vdds_dsi_reg = NULL;
4775         }
4776
4777         return 0;
4778 }
4779
4780 static int dsi_runtime_suspend(struct device *dev)
4781 {
4782         dispc_runtime_put();
4783         dss_runtime_put();
4784
4785         return 0;
4786 }
4787
4788 static int dsi_runtime_resume(struct device *dev)
4789 {
4790         int r;
4791
4792         r = dss_runtime_get();
4793         if (r)
4794                 goto err_get_dss;
4795
4796         r = dispc_runtime_get();
4797         if (r)
4798                 goto err_get_dispc;
4799
4800         return 0;
4801
4802 err_get_dispc:
4803         dss_runtime_put();
4804 err_get_dss:
4805         return r;
4806 }
4807
4808 static const struct dev_pm_ops dsi_pm_ops = {
4809         .runtime_suspend = dsi_runtime_suspend,
4810         .runtime_resume = dsi_runtime_resume,
4811 };
4812
4813 static struct platform_driver omap_dsihw_driver = {
4814         .probe          = omap_dsihw_probe,
4815         .remove         = omap_dsihw_remove,
4816         .driver         = {
4817                 .name   = "omapdss_dsi",
4818                 .owner  = THIS_MODULE,
4819                 .pm     = &dsi_pm_ops,
4820         },
4821 };
4822
4823 int dsi_init_platform_driver(void)
4824 {
4825         return platform_driver_register(&omap_dsihw_driver);
4826 }
4827
4828 void dsi_uninit_platform_driver(void)
4829 {
4830         return platform_driver_unregister(&omap_dsihw_driver);
4831 }