2 * linux/drivers/video/omap2/dss/dsi.c
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #define DSS_SUBSYS_NAME "DSI"
22 #include <linux/kernel.h>
24 #include <linux/clk.h>
25 #include <linux/device.h>
26 #include <linux/err.h>
27 #include <linux/interrupt.h>
28 #include <linux/delay.h>
29 #include <linux/mutex.h>
30 #include <linux/semaphore.h>
31 #include <linux/seq_file.h>
32 #include <linux/platform_device.h>
33 #include <linux/regulator/consumer.h>
34 #include <linux/wait.h>
35 #include <linux/workqueue.h>
37 #include <plat/display.h>
38 #include <plat/clock.h>
42 /*#define VERBOSE_IRQ*/
43 #define DSI_CATCH_MISSING_TE
45 struct dsi_reg { u16 idx; };
47 #define DSI_REG(idx) ((const struct dsi_reg) { idx })
49 #define DSI_SZ_REGS SZ_1K
50 /* DSI Protocol Engine */
52 #define DSI_REVISION DSI_REG(0x0000)
53 #define DSI_SYSCONFIG DSI_REG(0x0010)
54 #define DSI_SYSSTATUS DSI_REG(0x0014)
55 #define DSI_IRQSTATUS DSI_REG(0x0018)
56 #define DSI_IRQENABLE DSI_REG(0x001C)
57 #define DSI_CTRL DSI_REG(0x0040)
58 #define DSI_COMPLEXIO_CFG1 DSI_REG(0x0048)
59 #define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(0x004C)
60 #define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(0x0050)
61 #define DSI_CLK_CTRL DSI_REG(0x0054)
62 #define DSI_TIMING1 DSI_REG(0x0058)
63 #define DSI_TIMING2 DSI_REG(0x005C)
64 #define DSI_VM_TIMING1 DSI_REG(0x0060)
65 #define DSI_VM_TIMING2 DSI_REG(0x0064)
66 #define DSI_VM_TIMING3 DSI_REG(0x0068)
67 #define DSI_CLK_TIMING DSI_REG(0x006C)
68 #define DSI_TX_FIFO_VC_SIZE DSI_REG(0x0070)
69 #define DSI_RX_FIFO_VC_SIZE DSI_REG(0x0074)
70 #define DSI_COMPLEXIO_CFG2 DSI_REG(0x0078)
71 #define DSI_RX_FIFO_VC_FULLNESS DSI_REG(0x007C)
72 #define DSI_VM_TIMING4 DSI_REG(0x0080)
73 #define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(0x0084)
74 #define DSI_VM_TIMING5 DSI_REG(0x0088)
75 #define DSI_VM_TIMING6 DSI_REG(0x008C)
76 #define DSI_VM_TIMING7 DSI_REG(0x0090)
77 #define DSI_STOPCLK_TIMING DSI_REG(0x0094)
78 #define DSI_VC_CTRL(n) DSI_REG(0x0100 + (n * 0x20))
79 #define DSI_VC_TE(n) DSI_REG(0x0104 + (n * 0x20))
80 #define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(0x0108 + (n * 0x20))
81 #define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(0x010C + (n * 0x20))
82 #define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(0x0110 + (n * 0x20))
83 #define DSI_VC_IRQSTATUS(n) DSI_REG(0x0118 + (n * 0x20))
84 #define DSI_VC_IRQENABLE(n) DSI_REG(0x011C + (n * 0x20))
88 #define DSI_DSIPHY_CFG0 DSI_REG(0x200 + 0x0000)
89 #define DSI_DSIPHY_CFG1 DSI_REG(0x200 + 0x0004)
90 #define DSI_DSIPHY_CFG2 DSI_REG(0x200 + 0x0008)
91 #define DSI_DSIPHY_CFG5 DSI_REG(0x200 + 0x0014)
93 /* DSI_PLL_CTRL_SCP */
95 #define DSI_PLL_CONTROL DSI_REG(0x300 + 0x0000)
96 #define DSI_PLL_STATUS DSI_REG(0x300 + 0x0004)
97 #define DSI_PLL_GO DSI_REG(0x300 + 0x0008)
98 #define DSI_PLL_CONFIGURATION1 DSI_REG(0x300 + 0x000C)
99 #define DSI_PLL_CONFIGURATION2 DSI_REG(0x300 + 0x0010)
101 #define REG_GET(idx, start, end) \
102 FLD_GET(dsi_read_reg(idx), start, end)
104 #define REG_FLD_MOD(idx, val, start, end) \
105 dsi_write_reg(idx, FLD_MOD(dsi_read_reg(idx), val, start, end))
107 /* Global interrupts */
108 #define DSI_IRQ_VC0 (1 << 0)
109 #define DSI_IRQ_VC1 (1 << 1)
110 #define DSI_IRQ_VC2 (1 << 2)
111 #define DSI_IRQ_VC3 (1 << 3)
112 #define DSI_IRQ_WAKEUP (1 << 4)
113 #define DSI_IRQ_RESYNC (1 << 5)
114 #define DSI_IRQ_PLL_LOCK (1 << 7)
115 #define DSI_IRQ_PLL_UNLOCK (1 << 8)
116 #define DSI_IRQ_PLL_RECALL (1 << 9)
117 #define DSI_IRQ_COMPLEXIO_ERR (1 << 10)
118 #define DSI_IRQ_HS_TX_TIMEOUT (1 << 14)
119 #define DSI_IRQ_LP_RX_TIMEOUT (1 << 15)
120 #define DSI_IRQ_TE_TRIGGER (1 << 16)
121 #define DSI_IRQ_ACK_TRIGGER (1 << 17)
122 #define DSI_IRQ_SYNC_LOST (1 << 18)
123 #define DSI_IRQ_LDO_POWER_GOOD (1 << 19)
124 #define DSI_IRQ_TA_TIMEOUT (1 << 20)
125 #define DSI_IRQ_ERROR_MASK \
126 (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
128 #define DSI_IRQ_CHANNEL_MASK 0xf
130 /* Virtual channel interrupts */
131 #define DSI_VC_IRQ_CS (1 << 0)
132 #define DSI_VC_IRQ_ECC_CORR (1 << 1)
133 #define DSI_VC_IRQ_PACKET_SENT (1 << 2)
134 #define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3)
135 #define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4)
136 #define DSI_VC_IRQ_BTA (1 << 5)
137 #define DSI_VC_IRQ_ECC_NO_CORR (1 << 6)
138 #define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7)
139 #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
140 #define DSI_VC_IRQ_ERROR_MASK \
141 (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
142 DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
143 DSI_VC_IRQ_FIFO_TX_UDF)
145 /* ComplexIO interrupts */
146 #define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0)
147 #define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1)
148 #define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2)
149 #define DSI_CIO_IRQ_ERRESC1 (1 << 5)
150 #define DSI_CIO_IRQ_ERRESC2 (1 << 6)
151 #define DSI_CIO_IRQ_ERRESC3 (1 << 7)
152 #define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10)
153 #define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11)
154 #define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12)
155 #define DSI_CIO_IRQ_STATEULPS1 (1 << 15)
156 #define DSI_CIO_IRQ_STATEULPS2 (1 << 16)
157 #define DSI_CIO_IRQ_STATEULPS3 (1 << 17)
158 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20)
159 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21)
160 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22)
161 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23)
162 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24)
163 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25)
164 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30)
165 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31)
166 #define DSI_CIO_IRQ_ERROR_MASK \
167 (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \
168 DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \
169 DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRCONTROL1 | \
170 DSI_CIO_IRQ_ERRCONTROL2 | DSI_CIO_IRQ_ERRCONTROL3 | \
171 DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \
172 DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \
173 DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3)
175 #define DSI_DT_DCS_SHORT_WRITE_0 0x05
176 #define DSI_DT_DCS_SHORT_WRITE_1 0x15
177 #define DSI_DT_DCS_READ 0x06
178 #define DSI_DT_SET_MAX_RET_PKG_SIZE 0x37
179 #define DSI_DT_NULL_PACKET 0x09
180 #define DSI_DT_DCS_LONG_WRITE 0x39
182 #define DSI_DT_RX_ACK_WITH_ERR 0x02
183 #define DSI_DT_RX_DCS_LONG_READ 0x1c
184 #define DSI_DT_RX_SHORT_READ_1 0x21
185 #define DSI_DT_RX_SHORT_READ_2 0x22
187 #define FINT_MAX 2100000
188 #define FINT_MIN 750000
189 #define REGN_MAX (1 << 7)
190 #define REGM_MAX ((1 << 11) - 1)
191 #define REGM3_MAX (1 << 4)
192 #define REGM4_MAX (1 << 4)
193 #define LP_DIV_MAX ((1 << 13) - 1)
197 DSI_FIFO_SIZE_32 = 1,
198 DSI_FIFO_SIZE_64 = 2,
199 DSI_FIFO_SIZE_96 = 3,
200 DSI_FIFO_SIZE_128 = 4,
208 struct dsi_update_region {
210 struct omap_dss_device *device;
213 struct dsi_irq_stats {
214 unsigned long last_reset;
216 unsigned dsi_irqs[32];
217 unsigned vc_irqs[4][32];
218 unsigned cio_irqs[32];
223 struct platform_device *pdev;
226 struct dsi_clock_info current_cinfo;
228 struct regulator *vdds_dsi_reg;
231 enum dsi_vc_mode mode;
232 struct omap_dss_device *dssdev;
233 enum fifo_size fifo_size;
237 struct semaphore bus_lock;
241 struct completion bta_completion;
242 void (*bta_callback)(void);
245 struct dsi_update_region update_region;
249 struct workqueue_struct *workqueue;
251 void (*framedone_callback)(int, void *);
252 void *framedone_data;
254 struct delayed_work framedone_timeout_work;
256 #ifdef DSI_CATCH_MISSING_TE
257 struct timer_list te_timer;
260 unsigned long cache_req_pck;
261 unsigned long cache_clk_freq;
262 struct dsi_clock_info cache_cinfo;
265 spinlock_t errors_lock;
267 ktime_t perf_setup_time;
268 ktime_t perf_start_time;
273 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
274 spinlock_t irq_stats_lock;
275 struct dsi_irq_stats irq_stats;
280 static unsigned int dsi_perf;
281 module_param_named(dsi_perf, dsi_perf, bool, 0644);
284 static inline void dsi_write_reg(const struct dsi_reg idx, u32 val)
286 __raw_writel(val, dsi.base + idx.idx);
289 static inline u32 dsi_read_reg(const struct dsi_reg idx)
291 return __raw_readl(dsi.base + idx.idx);
295 void dsi_save_context(void)
299 void dsi_restore_context(void)
303 void dsi_bus_lock(void)
307 EXPORT_SYMBOL(dsi_bus_lock);
309 void dsi_bus_unlock(void)
313 EXPORT_SYMBOL(dsi_bus_unlock);
315 static bool dsi_bus_is_locked(void)
317 return dsi.bus_lock.count == 0;
320 static inline int wait_for_bit_change(const struct dsi_reg idx, int bitnum,
325 while (REG_GET(idx, bitnum, bitnum) != value) {
334 static void dsi_perf_mark_setup(void)
336 dsi.perf_setup_time = ktime_get();
339 static void dsi_perf_mark_start(void)
341 dsi.perf_start_time = ktime_get();
344 static void dsi_perf_show(const char *name)
346 ktime_t t, setup_time, trans_time;
348 u32 setup_us, trans_us, total_us;
355 setup_time = ktime_sub(dsi.perf_start_time, dsi.perf_setup_time);
356 setup_us = (u32)ktime_to_us(setup_time);
360 trans_time = ktime_sub(t, dsi.perf_start_time);
361 trans_us = (u32)ktime_to_us(trans_time);
365 total_us = setup_us + trans_us;
367 total_bytes = dsi.update_region.w *
368 dsi.update_region.h *
369 dsi.update_region.device->ctrl.pixel_size / 8;
371 printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), "
372 "%u bytes, %u kbytes/sec\n",
377 1000*1000 / total_us,
379 total_bytes * 1000 / total_us);
382 #define dsi_perf_mark_setup()
383 #define dsi_perf_mark_start()
384 #define dsi_perf_show(x)
387 static void print_irq_status(u32 status)
390 if ((status & ~DSI_IRQ_CHANNEL_MASK) == 0)
393 printk(KERN_DEBUG "DSI IRQ: 0x%x: ", status);
396 if (status & DSI_IRQ_##x) \
422 static void print_irq_status_vc(int channel, u32 status)
425 if ((status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
428 printk(KERN_DEBUG "DSI VC(%d) IRQ 0x%x: ", channel, status);
431 if (status & DSI_VC_IRQ_##x) \
448 static void print_irq_status_cio(u32 status)
450 printk(KERN_DEBUG "DSI CIO IRQ 0x%x: ", status);
453 if (status & DSI_CIO_IRQ_##x) \
467 PIS(ERRCONTENTIONLP0_1);
468 PIS(ERRCONTENTIONLP1_1);
469 PIS(ERRCONTENTIONLP0_2);
470 PIS(ERRCONTENTIONLP1_2);
471 PIS(ERRCONTENTIONLP0_3);
472 PIS(ERRCONTENTIONLP1_3);
473 PIS(ULPSACTIVENOT_ALL0);
474 PIS(ULPSACTIVENOT_ALL1);
480 static int debug_irq;
482 /* called from dss */
483 void dsi_irq_handler(void)
485 u32 irqstatus, vcstatus, ciostatus;
488 irqstatus = dsi_read_reg(DSI_IRQSTATUS);
490 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
491 spin_lock(&dsi.irq_stats_lock);
492 dsi.irq_stats.irq_count++;
493 dss_collect_irq_stats(irqstatus, dsi.irq_stats.dsi_irqs);
496 if (irqstatus & DSI_IRQ_ERROR_MASK) {
497 DSSERR("DSI error, irqstatus %x\n", irqstatus);
498 print_irq_status(irqstatus);
499 spin_lock(&dsi.errors_lock);
500 dsi.errors |= irqstatus & DSI_IRQ_ERROR_MASK;
501 spin_unlock(&dsi.errors_lock);
502 } else if (debug_irq) {
503 print_irq_status(irqstatus);
506 #ifdef DSI_CATCH_MISSING_TE
507 if (irqstatus & DSI_IRQ_TE_TRIGGER)
508 del_timer(&dsi.te_timer);
511 for (i = 0; i < 4; ++i) {
512 if ((irqstatus & (1<<i)) == 0)
515 vcstatus = dsi_read_reg(DSI_VC_IRQSTATUS(i));
517 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
518 dss_collect_irq_stats(vcstatus, dsi.irq_stats.vc_irqs[i]);
521 if (vcstatus & DSI_VC_IRQ_BTA) {
522 complete(&dsi.bta_completion);
524 if (dsi.bta_callback)
528 if (vcstatus & DSI_VC_IRQ_ERROR_MASK) {
529 DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
531 print_irq_status_vc(i, vcstatus);
532 } else if (debug_irq) {
533 print_irq_status_vc(i, vcstatus);
536 dsi_write_reg(DSI_VC_IRQSTATUS(i), vcstatus);
537 /* flush posted write */
538 dsi_read_reg(DSI_VC_IRQSTATUS(i));
541 if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
542 ciostatus = dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
544 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
545 dss_collect_irq_stats(ciostatus, dsi.irq_stats.cio_irqs);
548 dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
549 /* flush posted write */
550 dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
552 if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) {
553 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
554 print_irq_status_cio(ciostatus);
555 } else if (debug_irq) {
556 print_irq_status_cio(ciostatus);
560 dsi_write_reg(DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
561 /* flush posted write */
562 dsi_read_reg(DSI_IRQSTATUS);
564 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
565 spin_unlock(&dsi.irq_stats_lock);
570 static void _dsi_initialize_irq(void)
575 /* disable all interrupts */
576 dsi_write_reg(DSI_IRQENABLE, 0);
577 for (i = 0; i < 4; ++i)
578 dsi_write_reg(DSI_VC_IRQENABLE(i), 0);
579 dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE, 0);
581 /* clear interrupt status */
582 l = dsi_read_reg(DSI_IRQSTATUS);
583 dsi_write_reg(DSI_IRQSTATUS, l & ~DSI_IRQ_CHANNEL_MASK);
585 for (i = 0; i < 4; ++i) {
586 l = dsi_read_reg(DSI_VC_IRQSTATUS(i));
587 dsi_write_reg(DSI_VC_IRQSTATUS(i), l);
590 l = dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
591 dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS, l);
593 /* enable error irqs */
594 l = DSI_IRQ_ERROR_MASK;
595 #ifdef DSI_CATCH_MISSING_TE
596 l |= DSI_IRQ_TE_TRIGGER;
598 dsi_write_reg(DSI_IRQENABLE, l);
600 l = DSI_VC_IRQ_ERROR_MASK;
601 for (i = 0; i < 4; ++i)
602 dsi_write_reg(DSI_VC_IRQENABLE(i), l);
604 l = DSI_CIO_IRQ_ERROR_MASK;
605 dsi_write_reg(DSI_COMPLEXIO_IRQ_ENABLE, l);
608 static u32 dsi_get_errors(void)
612 spin_lock_irqsave(&dsi.errors_lock, flags);
615 spin_unlock_irqrestore(&dsi.errors_lock, flags);
619 static void dsi_vc_enable_bta_irq(int channel)
623 dsi_write_reg(DSI_VC_IRQSTATUS(channel), DSI_VC_IRQ_BTA);
625 l = dsi_read_reg(DSI_VC_IRQENABLE(channel));
627 dsi_write_reg(DSI_VC_IRQENABLE(channel), l);
630 static void dsi_vc_disable_bta_irq(int channel)
634 l = dsi_read_reg(DSI_VC_IRQENABLE(channel));
635 l &= ~DSI_VC_IRQ_BTA;
636 dsi_write_reg(DSI_VC_IRQENABLE(channel), l);
639 /* DSI func clock. this could also be DSI2_PLL_FCLK */
640 static inline void enable_clocks(bool enable)
643 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
645 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
648 /* source clock for DSI PLL. this could also be PCLKFREE */
649 static inline void dsi_enable_pll_clock(bool enable)
652 dss_clk_enable(DSS_CLK_SYSCK);
654 dss_clk_disable(DSS_CLK_SYSCK);
656 if (enable && dsi.pll_locked) {
657 if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1)
658 DSSERR("cannot lock PLL when enabling clocks\n");
663 static void _dsi_print_reset_status(void)
670 /* A dummy read using the SCP interface to any DSIPHY register is
671 * required after DSIPHY reset to complete the reset of the DSI complex
673 l = dsi_read_reg(DSI_DSIPHY_CFG5);
675 printk(KERN_DEBUG "DSI resets: ");
677 l = dsi_read_reg(DSI_PLL_STATUS);
678 printk("PLL (%d) ", FLD_GET(l, 0, 0));
680 l = dsi_read_reg(DSI_COMPLEXIO_CFG1);
681 printk("CIO (%d) ", FLD_GET(l, 29, 29));
683 l = dsi_read_reg(DSI_DSIPHY_CFG5);
684 printk("PHY (%x, %d, %d, %d)\n",
691 #define _dsi_print_reset_status()
694 static inline int dsi_if_enable(bool enable)
696 DSSDBG("dsi_if_enable(%d)\n", enable);
698 enable = enable ? 1 : 0;
699 REG_FLD_MOD(DSI_CTRL, enable, 0, 0); /* IF_EN */
701 if (wait_for_bit_change(DSI_CTRL, 0, enable) != enable) {
702 DSSERR("Failed to set dsi_if_enable to %d\n", enable);
709 unsigned long dsi_get_dsi1_pll_rate(void)
711 return dsi.current_cinfo.dsi1_pll_fclk;
714 static unsigned long dsi_get_dsi2_pll_rate(void)
716 return dsi.current_cinfo.dsi2_pll_fclk;
719 static unsigned long dsi_get_txbyteclkhs(void)
721 return dsi.current_cinfo.clkin4ddr / 16;
724 static unsigned long dsi_fclk_rate(void)
728 if (dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK) {
729 /* DSI FCLK source is DSS1_ALWON_FCK, which is dss1_fck */
730 r = dss_clk_get_rate(DSS_CLK_FCK);
732 /* DSI FCLK source is DSI2_PLL_FCLK */
733 r = dsi_get_dsi2_pll_rate();
739 static int dsi_set_lp_clk_divisor(struct omap_dss_device *dssdev)
741 unsigned long dsi_fclk;
743 unsigned long lp_clk;
745 lp_clk_div = dssdev->phy.dsi.div.lp_clk_div;
747 if (lp_clk_div == 0 || lp_clk_div > LP_DIV_MAX)
750 dsi_fclk = dsi_fclk_rate();
752 lp_clk = dsi_fclk / 2 / lp_clk_div;
754 DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk);
755 dsi.current_cinfo.lp_clk = lp_clk;
756 dsi.current_cinfo.lp_clk_div = lp_clk_div;
758 REG_FLD_MOD(DSI_CLK_CTRL, lp_clk_div, 12, 0); /* LP_CLK_DIVISOR */
760 REG_FLD_MOD(DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0,
761 21, 21); /* LP_RX_SYNCHRO_ENABLE */
767 enum dsi_pll_power_state {
768 DSI_PLL_POWER_OFF = 0x0,
769 DSI_PLL_POWER_ON_HSCLK = 0x1,
770 DSI_PLL_POWER_ON_ALL = 0x2,
771 DSI_PLL_POWER_ON_DIV = 0x3,
774 static int dsi_pll_power(enum dsi_pll_power_state state)
778 REG_FLD_MOD(DSI_CLK_CTRL, state, 31, 30); /* PLL_PWR_CMD */
781 while (FLD_GET(dsi_read_reg(DSI_CLK_CTRL), 29, 28) != state) {
783 DSSERR("Failed to set DSI PLL power mode to %d\n",
793 /* calculate clock rates using dividers in cinfo */
794 static int dsi_calc_clock_rates(struct omap_dss_device *dssdev,
795 struct dsi_clock_info *cinfo)
797 if (cinfo->regn == 0 || cinfo->regn > REGN_MAX)
800 if (cinfo->regm == 0 || cinfo->regm > REGM_MAX)
803 if (cinfo->regm3 > REGM3_MAX)
806 if (cinfo->regm4 > REGM4_MAX)
809 if (cinfo->use_dss2_fck) {
810 cinfo->clkin = dss_clk_get_rate(DSS_CLK_SYSCK);
811 /* XXX it is unclear if highfreq should be used
812 * with DSS2_FCK source also */
815 cinfo->clkin = dispc_pclk_rate(dssdev->manager->id);
817 if (cinfo->clkin < 32000000)
823 cinfo->fint = cinfo->clkin / (cinfo->regn * (cinfo->highfreq ? 2 : 1));
825 if (cinfo->fint > FINT_MAX || cinfo->fint < FINT_MIN)
828 cinfo->clkin4ddr = 2 * cinfo->regm * cinfo->fint;
830 if (cinfo->clkin4ddr > 1800 * 1000 * 1000)
833 if (cinfo->regm3 > 0)
834 cinfo->dsi1_pll_fclk = cinfo->clkin4ddr / cinfo->regm3;
836 cinfo->dsi1_pll_fclk = 0;
838 if (cinfo->regm4 > 0)
839 cinfo->dsi2_pll_fclk = cinfo->clkin4ddr / cinfo->regm4;
841 cinfo->dsi2_pll_fclk = 0;
846 int dsi_pll_calc_clock_div_pck(bool is_tft, unsigned long req_pck,
847 struct dsi_clock_info *dsi_cinfo,
848 struct dispc_clock_info *dispc_cinfo)
850 struct dsi_clock_info cur, best;
851 struct dispc_clock_info best_dispc;
854 unsigned long dss_clk_fck2;
856 dss_clk_fck2 = dss_clk_get_rate(DSS_CLK_SYSCK);
858 if (req_pck == dsi.cache_req_pck &&
859 dsi.cache_cinfo.clkin == dss_clk_fck2) {
860 DSSDBG("DSI clock info found from cache\n");
861 *dsi_cinfo = dsi.cache_cinfo;
862 dispc_find_clk_divs(is_tft, req_pck, dsi_cinfo->dsi1_pll_fclk,
867 min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
869 if (min_fck_per_pck &&
870 req_pck * min_fck_per_pck > DISPC_MAX_FCK) {
871 DSSERR("Requested pixel clock not possible with the current "
872 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
873 "the constraint off.\n");
877 DSSDBG("dsi_pll_calc\n");
880 memset(&best, 0, sizeof(best));
881 memset(&best_dispc, 0, sizeof(best_dispc));
883 memset(&cur, 0, sizeof(cur));
884 cur.clkin = dss_clk_fck2;
885 cur.use_dss2_fck = 1;
888 /* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */
889 /* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */
890 /* To reduce PLL lock time, keep Fint high (around 2 MHz) */
891 for (cur.regn = 1; cur.regn < REGN_MAX; ++cur.regn) {
892 if (cur.highfreq == 0)
893 cur.fint = cur.clkin / cur.regn;
895 cur.fint = cur.clkin / (2 * cur.regn);
897 if (cur.fint > FINT_MAX || cur.fint < FINT_MIN)
900 /* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */
901 for (cur.regm = 1; cur.regm < REGM_MAX; ++cur.regm) {
904 a = 2 * cur.regm * (cur.clkin/1000);
905 b = cur.regn * (cur.highfreq + 1);
906 cur.clkin4ddr = a / b * 1000;
908 if (cur.clkin4ddr > 1800 * 1000 * 1000)
911 /* DSI1_PLL_FCLK(MHz) = DSIPHY(MHz) / regm3 < 173MHz */
912 for (cur.regm3 = 1; cur.regm3 < REGM3_MAX;
914 struct dispc_clock_info cur_dispc;
915 cur.dsi1_pll_fclk = cur.clkin4ddr / cur.regm3;
917 /* this will narrow down the search a bit,
918 * but still give pixclocks below what was
920 if (cur.dsi1_pll_fclk < req_pck)
923 if (cur.dsi1_pll_fclk > DISPC_MAX_FCK)
926 if (min_fck_per_pck &&
928 req_pck * min_fck_per_pck)
933 dispc_find_clk_divs(is_tft, req_pck,
937 if (abs(cur_dispc.pck - req_pck) <
938 abs(best_dispc.pck - req_pck)) {
940 best_dispc = cur_dispc;
942 if (cur_dispc.pck == req_pck)
950 if (min_fck_per_pck) {
951 DSSERR("Could not find suitable clock settings.\n"
952 "Turning FCK/PCK constraint off and"
958 DSSERR("Could not find suitable clock settings.\n");
963 /* DSI2_PLL_FCLK (regm4) is not used */
965 best.dsi2_pll_fclk = 0;
970 *dispc_cinfo = best_dispc;
972 dsi.cache_req_pck = req_pck;
973 dsi.cache_clk_freq = 0;
974 dsi.cache_cinfo = best;
979 int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo)
987 dsi.current_cinfo.fint = cinfo->fint;
988 dsi.current_cinfo.clkin4ddr = cinfo->clkin4ddr;
989 dsi.current_cinfo.dsi1_pll_fclk = cinfo->dsi1_pll_fclk;
990 dsi.current_cinfo.dsi2_pll_fclk = cinfo->dsi2_pll_fclk;
992 dsi.current_cinfo.regn = cinfo->regn;
993 dsi.current_cinfo.regm = cinfo->regm;
994 dsi.current_cinfo.regm3 = cinfo->regm3;
995 dsi.current_cinfo.regm4 = cinfo->regm4;
997 DSSDBG("DSI Fint %ld\n", cinfo->fint);
999 DSSDBG("clkin (%s) rate %ld, highfreq %d\n",
1000 cinfo->use_dss2_fck ? "dss2_fck" : "pclkfree",
1004 /* DSIPHY == CLKIN4DDR */
1005 DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu / %d = %lu\n",
1009 cinfo->highfreq + 1,
1012 DSSDBG("Data rate on 1 DSI lane %ld Mbps\n",
1013 cinfo->clkin4ddr / 1000 / 1000 / 2);
1015 DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4);
1017 DSSDBG("regm3 = %d, dsi1_pll_fclk = %lu\n",
1018 cinfo->regm3, cinfo->dsi1_pll_fclk);
1019 DSSDBG("regm4 = %d, dsi2_pll_fclk = %lu\n",
1020 cinfo->regm4, cinfo->dsi2_pll_fclk);
1022 REG_FLD_MOD(DSI_PLL_CONTROL, 0, 0, 0); /* DSI_PLL_AUTOMODE = manual */
1024 l = dsi_read_reg(DSI_PLL_CONFIGURATION1);
1025 l = FLD_MOD(l, 1, 0, 0); /* DSI_PLL_STOPMODE */
1026 l = FLD_MOD(l, cinfo->regn - 1, 7, 1); /* DSI_PLL_REGN */
1027 l = FLD_MOD(l, cinfo->regm, 18, 8); /* DSI_PLL_REGM */
1028 l = FLD_MOD(l, cinfo->regm3 > 0 ? cinfo->regm3 - 1 : 0,
1029 22, 19); /* DSI_CLOCK_DIV */
1030 l = FLD_MOD(l, cinfo->regm4 > 0 ? cinfo->regm4 - 1 : 0,
1031 26, 23); /* DSIPROTO_CLOCK_DIV */
1032 dsi_write_reg(DSI_PLL_CONFIGURATION1, l);
1034 BUG_ON(cinfo->fint < 750000 || cinfo->fint > 2100000);
1035 if (cinfo->fint < 1000000)
1037 else if (cinfo->fint < 1250000)
1039 else if (cinfo->fint < 1500000)
1041 else if (cinfo->fint < 1750000)
1046 l = dsi_read_reg(DSI_PLL_CONFIGURATION2);
1047 l = FLD_MOD(l, f, 4, 1); /* DSI_PLL_FREQSEL */
1048 l = FLD_MOD(l, cinfo->use_dss2_fck ? 0 : 1,
1049 11, 11); /* DSI_PLL_CLKSEL */
1050 l = FLD_MOD(l, cinfo->highfreq,
1051 12, 12); /* DSI_PLL_HIGHFREQ */
1052 l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
1053 l = FLD_MOD(l, 0, 14, 14); /* DSIPHY_CLKINEN */
1054 l = FLD_MOD(l, 1, 20, 20); /* DSI_HSDIVBYPASS */
1055 dsi_write_reg(DSI_PLL_CONFIGURATION2, l);
1057 REG_FLD_MOD(DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */
1059 if (wait_for_bit_change(DSI_PLL_GO, 0, 0) != 0) {
1060 DSSERR("dsi pll go bit not going down.\n");
1065 if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1) {
1066 DSSERR("cannot lock PLL\n");
1073 l = dsi_read_reg(DSI_PLL_CONFIGURATION2);
1074 l = FLD_MOD(l, 0, 0, 0); /* DSI_PLL_IDLE */
1075 l = FLD_MOD(l, 0, 5, 5); /* DSI_PLL_PLLLPMODE */
1076 l = FLD_MOD(l, 0, 6, 6); /* DSI_PLL_LOWCURRSTBY */
1077 l = FLD_MOD(l, 0, 7, 7); /* DSI_PLL_TIGHTPHASELOCK */
1078 l = FLD_MOD(l, 0, 8, 8); /* DSI_PLL_DRIFTGUARDEN */
1079 l = FLD_MOD(l, 0, 10, 9); /* DSI_PLL_LOCKSEL */
1080 l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
1081 l = FLD_MOD(l, 1, 14, 14); /* DSIPHY_CLKINEN */
1082 l = FLD_MOD(l, 0, 15, 15); /* DSI_BYPASSEN */
1083 l = FLD_MOD(l, 1, 16, 16); /* DSS_CLOCK_EN */
1084 l = FLD_MOD(l, 0, 17, 17); /* DSS_CLOCK_PWDN */
1085 l = FLD_MOD(l, 1, 18, 18); /* DSI_PROTO_CLOCK_EN */
1086 l = FLD_MOD(l, 0, 19, 19); /* DSI_PROTO_CLOCK_PWDN */
1087 l = FLD_MOD(l, 0, 20, 20); /* DSI_HSDIVBYPASS */
1088 dsi_write_reg(DSI_PLL_CONFIGURATION2, l);
1090 DSSDBG("PLL config done\n");
1095 int dsi_pll_init(struct omap_dss_device *dssdev, bool enable_hsclk,
1099 enum dsi_pll_power_state pwstate;
1101 DSSDBG("PLL init\n");
1104 dsi_enable_pll_clock(1);
1106 r = regulator_enable(dsi.vdds_dsi_reg);
1110 /* XXX PLL does not come out of reset without this... */
1111 dispc_pck_free_enable(1);
1113 if (wait_for_bit_change(DSI_PLL_STATUS, 0, 1) != 1) {
1114 DSSERR("PLL not coming out of reset.\n");
1116 dispc_pck_free_enable(0);
1120 /* XXX ... but if left on, we get problems when planes do not
1121 * fill the whole display. No idea about this */
1122 dispc_pck_free_enable(0);
1124 if (enable_hsclk && enable_hsdiv)
1125 pwstate = DSI_PLL_POWER_ON_ALL;
1126 else if (enable_hsclk)
1127 pwstate = DSI_PLL_POWER_ON_HSCLK;
1128 else if (enable_hsdiv)
1129 pwstate = DSI_PLL_POWER_ON_DIV;
1131 pwstate = DSI_PLL_POWER_OFF;
1133 r = dsi_pll_power(pwstate);
1138 DSSDBG("PLL init done\n");
1142 regulator_disable(dsi.vdds_dsi_reg);
1145 dsi_enable_pll_clock(0);
1149 void dsi_pll_uninit(void)
1152 dsi_enable_pll_clock(0);
1155 dsi_pll_power(DSI_PLL_POWER_OFF);
1156 regulator_disable(dsi.vdds_dsi_reg);
1157 DSSDBG("PLL uninit done\n");
1160 void dsi_dump_clocks(struct seq_file *s)
1163 struct dsi_clock_info *cinfo = &dsi.current_cinfo;
1167 clksel = REG_GET(DSI_PLL_CONFIGURATION2, 11, 11);
1169 seq_printf(s, "- DSI PLL -\n");
1171 seq_printf(s, "dsi pll source = %s\n",
1173 "dss2_alwon_fclk" : "pclkfree");
1175 seq_printf(s, "Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn);
1177 seq_printf(s, "CLKIN4DDR\t%-16luregm %u\n",
1178 cinfo->clkin4ddr, cinfo->regm);
1180 seq_printf(s, "dsi1_pll_fck\t%-16luregm3 %u\t(%s)\n",
1181 cinfo->dsi1_pll_fclk,
1183 dss_get_dispc_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ?
1186 seq_printf(s, "dsi2_pll_fck\t%-16luregm4 %u\t(%s)\n",
1187 cinfo->dsi2_pll_fclk,
1189 dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ?
1192 seq_printf(s, "- DSI -\n");
1194 seq_printf(s, "dsi fclk source = %s\n",
1195 dss_get_dsi_clk_source() == DSS_SRC_DSS1_ALWON_FCLK ?
1196 "dss1_alwon_fclk" : "dsi2_pll_fclk");
1198 seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate());
1200 seq_printf(s, "DDR_CLK\t\t%lu\n",
1201 cinfo->clkin4ddr / 4);
1203 seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs());
1205 seq_printf(s, "LP_CLK\t\t%lu\n", cinfo->lp_clk);
1207 seq_printf(s, "VP_CLK\t\t%lu\n"
1209 dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD),
1210 dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD));
1215 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
1216 void dsi_dump_irqs(struct seq_file *s)
1218 unsigned long flags;
1219 struct dsi_irq_stats stats;
1221 spin_lock_irqsave(&dsi.irq_stats_lock, flags);
1223 stats = dsi.irq_stats;
1224 memset(&dsi.irq_stats, 0, sizeof(dsi.irq_stats));
1225 dsi.irq_stats.last_reset = jiffies;
1227 spin_unlock_irqrestore(&dsi.irq_stats_lock, flags);
1229 seq_printf(s, "period %u ms\n",
1230 jiffies_to_msecs(jiffies - stats.last_reset));
1232 seq_printf(s, "irqs %d\n", stats.irq_count);
1234 seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]);
1236 seq_printf(s, "-- DSI interrupts --\n");
1252 PIS(LDO_POWER_GOOD);
1257 seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
1258 stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
1259 stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
1260 stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
1261 stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);
1263 seq_printf(s, "-- VC interrupts --\n");
1272 PIS(PP_BUSY_CHANGE);
1276 seq_printf(s, "%-20s %10d\n", #x, \
1277 stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);
1279 seq_printf(s, "-- CIO interrupts --\n");
1292 PIS(ERRCONTENTIONLP0_1);
1293 PIS(ERRCONTENTIONLP1_1);
1294 PIS(ERRCONTENTIONLP0_2);
1295 PIS(ERRCONTENTIONLP1_2);
1296 PIS(ERRCONTENTIONLP0_3);
1297 PIS(ERRCONTENTIONLP1_3);
1298 PIS(ULPSACTIVENOT_ALL0);
1299 PIS(ULPSACTIVENOT_ALL1);
1304 void dsi_dump_regs(struct seq_file *s)
1306 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(r))
1308 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
1310 DUMPREG(DSI_REVISION);
1311 DUMPREG(DSI_SYSCONFIG);
1312 DUMPREG(DSI_SYSSTATUS);
1313 DUMPREG(DSI_IRQSTATUS);
1314 DUMPREG(DSI_IRQENABLE);
1316 DUMPREG(DSI_COMPLEXIO_CFG1);
1317 DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
1318 DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
1319 DUMPREG(DSI_CLK_CTRL);
1320 DUMPREG(DSI_TIMING1);
1321 DUMPREG(DSI_TIMING2);
1322 DUMPREG(DSI_VM_TIMING1);
1323 DUMPREG(DSI_VM_TIMING2);
1324 DUMPREG(DSI_VM_TIMING3);
1325 DUMPREG(DSI_CLK_TIMING);
1326 DUMPREG(DSI_TX_FIFO_VC_SIZE);
1327 DUMPREG(DSI_RX_FIFO_VC_SIZE);
1328 DUMPREG(DSI_COMPLEXIO_CFG2);
1329 DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
1330 DUMPREG(DSI_VM_TIMING4);
1331 DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
1332 DUMPREG(DSI_VM_TIMING5);
1333 DUMPREG(DSI_VM_TIMING6);
1334 DUMPREG(DSI_VM_TIMING7);
1335 DUMPREG(DSI_STOPCLK_TIMING);
1337 DUMPREG(DSI_VC_CTRL(0));
1338 DUMPREG(DSI_VC_TE(0));
1339 DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
1340 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
1341 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
1342 DUMPREG(DSI_VC_IRQSTATUS(0));
1343 DUMPREG(DSI_VC_IRQENABLE(0));
1345 DUMPREG(DSI_VC_CTRL(1));
1346 DUMPREG(DSI_VC_TE(1));
1347 DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
1348 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
1349 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
1350 DUMPREG(DSI_VC_IRQSTATUS(1));
1351 DUMPREG(DSI_VC_IRQENABLE(1));
1353 DUMPREG(DSI_VC_CTRL(2));
1354 DUMPREG(DSI_VC_TE(2));
1355 DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
1356 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
1357 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
1358 DUMPREG(DSI_VC_IRQSTATUS(2));
1359 DUMPREG(DSI_VC_IRQENABLE(2));
1361 DUMPREG(DSI_VC_CTRL(3));
1362 DUMPREG(DSI_VC_TE(3));
1363 DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
1364 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
1365 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
1366 DUMPREG(DSI_VC_IRQSTATUS(3));
1367 DUMPREG(DSI_VC_IRQENABLE(3));
1369 DUMPREG(DSI_DSIPHY_CFG0);
1370 DUMPREG(DSI_DSIPHY_CFG1);
1371 DUMPREG(DSI_DSIPHY_CFG2);
1372 DUMPREG(DSI_DSIPHY_CFG5);
1374 DUMPREG(DSI_PLL_CONTROL);
1375 DUMPREG(DSI_PLL_STATUS);
1376 DUMPREG(DSI_PLL_GO);
1377 DUMPREG(DSI_PLL_CONFIGURATION1);
1378 DUMPREG(DSI_PLL_CONFIGURATION2);
1380 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
1384 enum dsi_complexio_power_state {
1385 DSI_COMPLEXIO_POWER_OFF = 0x0,
1386 DSI_COMPLEXIO_POWER_ON = 0x1,
1387 DSI_COMPLEXIO_POWER_ULPS = 0x2,
1390 static int dsi_complexio_power(enum dsi_complexio_power_state state)
1395 REG_FLD_MOD(DSI_COMPLEXIO_CFG1, state, 28, 27);
1398 while (FLD_GET(dsi_read_reg(DSI_COMPLEXIO_CFG1), 26, 25) != state) {
1400 DSSERR("failed to set complexio power state to "
1410 static void dsi_complexio_config(struct omap_dss_device *dssdev)
1414 int clk_lane = dssdev->phy.dsi.clk_lane;
1415 int data1_lane = dssdev->phy.dsi.data1_lane;
1416 int data2_lane = dssdev->phy.dsi.data2_lane;
1417 int clk_pol = dssdev->phy.dsi.clk_pol;
1418 int data1_pol = dssdev->phy.dsi.data1_pol;
1419 int data2_pol = dssdev->phy.dsi.data2_pol;
1421 r = dsi_read_reg(DSI_COMPLEXIO_CFG1);
1422 r = FLD_MOD(r, clk_lane, 2, 0);
1423 r = FLD_MOD(r, clk_pol, 3, 3);
1424 r = FLD_MOD(r, data1_lane, 6, 4);
1425 r = FLD_MOD(r, data1_pol, 7, 7);
1426 r = FLD_MOD(r, data2_lane, 10, 8);
1427 r = FLD_MOD(r, data2_pol, 11, 11);
1428 dsi_write_reg(DSI_COMPLEXIO_CFG1, r);
1430 /* The configuration of the DSI complex I/O (number of data lanes,
1431 position, differential order) should not be changed while
1432 DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. In order for
1433 the hardware to take into account a new configuration of the complex
1434 I/O (done in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to
1435 follow this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1,
1436 then reset the DSS.DSI_CTRL[0] IF_EN to 0, then set
1437 DSS.DSI_CLK_CTRL[20] LP_CLK_ENABLE to 1 and finally set again the
1438 DSS.DSI_CTRL[0] IF_EN bit to 1. If the sequence is not followed, the
1439 DSI complex I/O configuration is unknown. */
1442 REG_FLD_MOD(DSI_CTRL, 1, 0, 0);
1443 REG_FLD_MOD(DSI_CTRL, 0, 0, 0);
1444 REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20);
1445 REG_FLD_MOD(DSI_CTRL, 1, 0, 0);
1449 static inline unsigned ns2ddr(unsigned ns)
1451 /* convert time in ns to ddr ticks, rounding up */
1452 unsigned long ddr_clk = dsi.current_cinfo.clkin4ddr / 4;
1453 return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000;
1456 static inline unsigned ddr2ns(unsigned ddr)
1458 unsigned long ddr_clk = dsi.current_cinfo.clkin4ddr / 4;
1459 return ddr * 1000 * 1000 / (ddr_clk / 1000);
1462 static void dsi_complexio_timings(void)
1465 u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
1466 u32 tlpx_half, tclk_trail, tclk_zero;
1469 /* calculate timings */
1471 /* 1 * DDR_CLK = 2 * UI */
1473 /* min 40ns + 4*UI max 85ns + 6*UI */
1474 ths_prepare = ns2ddr(70) + 2;
1476 /* min 145ns + 10*UI */
1477 ths_prepare_ths_zero = ns2ddr(175) + 2;
1479 /* min max(8*UI, 60ns+4*UI) */
1480 ths_trail = ns2ddr(60) + 5;
1483 ths_exit = ns2ddr(145);
1486 tlpx_half = ns2ddr(25);
1489 tclk_trail = ns2ddr(60) + 2;
1491 /* min 38ns, max 95ns */
1492 tclk_prepare = ns2ddr(65);
1494 /* min tclk-prepare + tclk-zero = 300ns */
1495 tclk_zero = ns2ddr(260);
1497 DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
1498 ths_prepare, ddr2ns(ths_prepare),
1499 ths_prepare_ths_zero, ddr2ns(ths_prepare_ths_zero));
1500 DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
1501 ths_trail, ddr2ns(ths_trail),
1502 ths_exit, ddr2ns(ths_exit));
1504 DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
1505 "tclk_zero %u (%uns)\n",
1506 tlpx_half, ddr2ns(tlpx_half),
1507 tclk_trail, ddr2ns(tclk_trail),
1508 tclk_zero, ddr2ns(tclk_zero));
1509 DSSDBG("tclk_prepare %u (%uns)\n",
1510 tclk_prepare, ddr2ns(tclk_prepare));
1512 /* program timings */
1514 r = dsi_read_reg(DSI_DSIPHY_CFG0);
1515 r = FLD_MOD(r, ths_prepare, 31, 24);
1516 r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
1517 r = FLD_MOD(r, ths_trail, 15, 8);
1518 r = FLD_MOD(r, ths_exit, 7, 0);
1519 dsi_write_reg(DSI_DSIPHY_CFG0, r);
1521 r = dsi_read_reg(DSI_DSIPHY_CFG1);
1522 r = FLD_MOD(r, tlpx_half, 22, 16);
1523 r = FLD_MOD(r, tclk_trail, 15, 8);
1524 r = FLD_MOD(r, tclk_zero, 7, 0);
1525 dsi_write_reg(DSI_DSIPHY_CFG1, r);
1527 r = dsi_read_reg(DSI_DSIPHY_CFG2);
1528 r = FLD_MOD(r, tclk_prepare, 7, 0);
1529 dsi_write_reg(DSI_DSIPHY_CFG2, r);
1533 static int dsi_complexio_init(struct omap_dss_device *dssdev)
1537 DSSDBG("dsi_complexio_init\n");
1539 /* CIO_CLK_ICG, enable L3 clk to CIO */
1540 REG_FLD_MOD(DSI_CLK_CTRL, 1, 14, 14);
1542 /* A dummy read using the SCP interface to any DSIPHY register is
1543 * required after DSIPHY reset to complete the reset of the DSI complex
1545 dsi_read_reg(DSI_DSIPHY_CFG5);
1547 if (wait_for_bit_change(DSI_DSIPHY_CFG5, 30, 1) != 1) {
1548 DSSERR("ComplexIO PHY not coming out of reset.\n");
1553 dsi_complexio_config(dssdev);
1555 r = dsi_complexio_power(DSI_COMPLEXIO_POWER_ON);
1560 if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
1561 DSSERR("ComplexIO not coming out of reset.\n");
1566 if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 21, 1) != 1) {
1567 DSSERR("ComplexIO LDO power down.\n");
1572 dsi_complexio_timings();
1575 The configuration of the DSI complex I/O (number of data lanes,
1576 position, differential order) should not be changed while
1577 DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. For the
1578 hardware to recognize a new configuration of the complex I/O (done
1579 in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to follow
1580 this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1, next
1581 reset the DSS.DSI_CTRL[0] IF_EN to 0, then set DSS.DSI_CLK_CTRL[20]
1582 LP_CLK_ENABLE to 1, and finally, set again the DSS.DSI_CTRL[0] IF_EN
1583 bit to 1. If the sequence is not followed, the DSi complex I/O
1584 configuration is undetermined.
1588 REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
1592 DSSDBG("CIO init done\n");
1597 static void dsi_complexio_uninit(void)
1599 dsi_complexio_power(DSI_COMPLEXIO_POWER_OFF);
1602 static int _dsi_wait_reset(void)
1606 while (REG_GET(DSI_SYSSTATUS, 0, 0) == 0) {
1608 DSSERR("soft reset failed\n");
1617 static int _dsi_reset(void)
1620 REG_FLD_MOD(DSI_SYSCONFIG, 1, 1, 1);
1621 return _dsi_wait_reset();
1624 static void dsi_reset_tx_fifo(int channel)
1629 /* set fifosize of the channel to 0, then return the old size */
1630 l = dsi_read_reg(DSI_TX_FIFO_VC_SIZE);
1632 mask = FLD_MASK((8 * channel) + 7, (8 * channel) + 4);
1633 dsi_write_reg(DSI_TX_FIFO_VC_SIZE, l & ~mask);
1635 dsi_write_reg(DSI_TX_FIFO_VC_SIZE, l);
1638 static void dsi_config_tx_fifo(enum fifo_size size1, enum fifo_size size2,
1639 enum fifo_size size3, enum fifo_size size4)
1645 dsi.vc[0].fifo_size = size1;
1646 dsi.vc[1].fifo_size = size2;
1647 dsi.vc[2].fifo_size = size3;
1648 dsi.vc[3].fifo_size = size4;
1650 for (i = 0; i < 4; i++) {
1652 int size = dsi.vc[i].fifo_size;
1654 if (add + size > 4) {
1655 DSSERR("Illegal FIFO configuration\n");
1659 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
1661 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
1665 dsi_write_reg(DSI_TX_FIFO_VC_SIZE, r);
1668 static void dsi_config_rx_fifo(enum fifo_size size1, enum fifo_size size2,
1669 enum fifo_size size3, enum fifo_size size4)
1675 dsi.vc[0].fifo_size = size1;
1676 dsi.vc[1].fifo_size = size2;
1677 dsi.vc[2].fifo_size = size3;
1678 dsi.vc[3].fifo_size = size4;
1680 for (i = 0; i < 4; i++) {
1682 int size = dsi.vc[i].fifo_size;
1684 if (add + size > 4) {
1685 DSSERR("Illegal FIFO configuration\n");
1689 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
1691 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
1695 dsi_write_reg(DSI_RX_FIFO_VC_SIZE, r);
1698 static int dsi_force_tx_stop_mode_io(void)
1702 r = dsi_read_reg(DSI_TIMING1);
1703 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
1704 dsi_write_reg(DSI_TIMING1, r);
1706 if (wait_for_bit_change(DSI_TIMING1, 15, 0) != 0) {
1707 DSSERR("TX_STOP bit not going down\n");
1714 static int dsi_vc_enable(int channel, bool enable)
1716 DSSDBG("dsi_vc_enable channel %d, enable %d\n",
1719 enable = enable ? 1 : 0;
1721 REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 0, 0);
1723 if (wait_for_bit_change(DSI_VC_CTRL(channel), 0, enable) != enable) {
1724 DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
1731 static void dsi_vc_initial_config(int channel)
1735 DSSDBGF("%d", channel);
1737 r = dsi_read_reg(DSI_VC_CTRL(channel));
1739 if (FLD_GET(r, 15, 15)) /* VC_BUSY */
1740 DSSERR("VC(%d) busy when trying to configure it!\n",
1743 r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
1744 r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */
1745 r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
1746 r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
1747 r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
1748 r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
1749 r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
1751 r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
1752 r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
1754 dsi_write_reg(DSI_VC_CTRL(channel), r);
1756 dsi.vc[channel].mode = DSI_VC_MODE_L4;
1759 static int dsi_vc_config_l4(int channel)
1761 if (dsi.vc[channel].mode == DSI_VC_MODE_L4)
1764 DSSDBGF("%d", channel);
1766 dsi_vc_enable(channel, 0);
1769 if (wait_for_bit_change(DSI_VC_CTRL(channel), 15, 0) != 0) {
1770 DSSERR("vc(%d) busy when trying to config for L4\n", channel);
1774 REG_FLD_MOD(DSI_VC_CTRL(channel), 0, 1, 1); /* SOURCE, 0 = L4 */
1776 dsi_vc_enable(channel, 1);
1778 dsi.vc[channel].mode = DSI_VC_MODE_L4;
1783 static int dsi_vc_config_vp(int channel)
1785 if (dsi.vc[channel].mode == DSI_VC_MODE_VP)
1788 DSSDBGF("%d", channel);
1790 dsi_vc_enable(channel, 0);
1793 if (wait_for_bit_change(DSI_VC_CTRL(channel), 15, 0) != 0) {
1794 DSSERR("vc(%d) busy when trying to config for VP\n", channel);
1798 REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 1, 1); /* SOURCE, 1 = video port */
1800 dsi_vc_enable(channel, 1);
1802 dsi.vc[channel].mode = DSI_VC_MODE_VP;
1808 void omapdss_dsi_vc_enable_hs(int channel, bool enable)
1810 DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
1812 WARN_ON(!dsi_bus_is_locked());
1814 dsi_vc_enable(channel, 0);
1817 REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 9, 9);
1819 dsi_vc_enable(channel, 1);
1822 dsi_force_tx_stop_mode_io();
1824 EXPORT_SYMBOL(omapdss_dsi_vc_enable_hs);
1826 static void dsi_vc_flush_long_data(int channel)
1828 while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
1830 val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
1831 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
1835 (val >> 24) & 0xff);
1839 static void dsi_show_rx_ack_with_err(u16 err)
1841 DSSERR("\tACK with ERROR (%#x):\n", err);
1843 DSSERR("\t\tSoT Error\n");
1845 DSSERR("\t\tSoT Sync Error\n");
1847 DSSERR("\t\tEoT Sync Error\n");
1849 DSSERR("\t\tEscape Mode Entry Command Error\n");
1851 DSSERR("\t\tLP Transmit Sync Error\n");
1853 DSSERR("\t\tHS Receive Timeout Error\n");
1855 DSSERR("\t\tFalse Control Error\n");
1857 DSSERR("\t\t(reserved7)\n");
1859 DSSERR("\t\tECC Error, single-bit (corrected)\n");
1861 DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
1862 if (err & (1 << 10))
1863 DSSERR("\t\tChecksum Error\n");
1864 if (err & (1 << 11))
1865 DSSERR("\t\tData type not recognized\n");
1866 if (err & (1 << 12))
1867 DSSERR("\t\tInvalid VC ID\n");
1868 if (err & (1 << 13))
1869 DSSERR("\t\tInvalid Transmission Length\n");
1870 if (err & (1 << 14))
1871 DSSERR("\t\t(reserved14)\n");
1872 if (err & (1 << 15))
1873 DSSERR("\t\tDSI Protocol Violation\n");
1876 static u16 dsi_vc_flush_receive_data(int channel)
1878 /* RX_FIFO_NOT_EMPTY */
1879 while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
1882 val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
1883 DSSERR("\trawval %#08x\n", val);
1884 dt = FLD_GET(val, 5, 0);
1885 if (dt == DSI_DT_RX_ACK_WITH_ERR) {
1886 u16 err = FLD_GET(val, 23, 8);
1887 dsi_show_rx_ack_with_err(err);
1888 } else if (dt == DSI_DT_RX_SHORT_READ_1) {
1889 DSSERR("\tDCS short response, 1 byte: %#x\n",
1890 FLD_GET(val, 23, 8));
1891 } else if (dt == DSI_DT_RX_SHORT_READ_2) {
1892 DSSERR("\tDCS short response, 2 byte: %#x\n",
1893 FLD_GET(val, 23, 8));
1894 } else if (dt == DSI_DT_RX_DCS_LONG_READ) {
1895 DSSERR("\tDCS long response, len %d\n",
1896 FLD_GET(val, 23, 8));
1897 dsi_vc_flush_long_data(channel);
1899 DSSERR("\tunknown datatype 0x%02x\n", dt);
1905 static int dsi_vc_send_bta(int channel)
1907 if (dsi.debug_write || dsi.debug_read)
1908 DSSDBG("dsi_vc_send_bta %d\n", channel);
1910 WARN_ON(!dsi_bus_is_locked());
1912 if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { /* RX_FIFO_NOT_EMPTY */
1913 DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
1914 dsi_vc_flush_receive_data(channel);
1917 REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
1922 int dsi_vc_send_bta_sync(int channel)
1927 INIT_COMPLETION(dsi.bta_completion);
1929 dsi_vc_enable_bta_irq(channel);
1931 r = dsi_vc_send_bta(channel);
1935 if (wait_for_completion_timeout(&dsi.bta_completion,
1936 msecs_to_jiffies(500)) == 0) {
1937 DSSERR("Failed to receive BTA\n");
1942 err = dsi_get_errors();
1944 DSSERR("Error while sending BTA: %x\n", err);
1949 dsi_vc_disable_bta_irq(channel);
1953 EXPORT_SYMBOL(dsi_vc_send_bta_sync);
1955 static inline void dsi_vc_write_long_header(int channel, u8 data_type,
1961 WARN_ON(!dsi_bus_is_locked());
1963 data_id = data_type | channel << 6;
1965 val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
1966 FLD_VAL(ecc, 31, 24);
1968 dsi_write_reg(DSI_VC_LONG_PACKET_HEADER(channel), val);
1971 static inline void dsi_vc_write_long_payload(int channel,
1972 u8 b1, u8 b2, u8 b3, u8 b4)
1976 val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0;
1978 /* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
1979 b1, b2, b3, b4, val); */
1981 dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
1984 static int dsi_vc_send_long(int channel, u8 data_type, u8 *data, u16 len,
1993 if (dsi.debug_write)
1994 DSSDBG("dsi_vc_send_long, %d bytes\n", len);
1997 if (dsi.vc[channel].fifo_size * 32 * 4 < len + 4) {
1998 DSSERR("unable to send long packet: packet too long.\n");
2002 dsi_vc_config_l4(channel);
2004 dsi_vc_write_long_header(channel, data_type, len, ecc);
2007 for (i = 0; i < len >> 2; i++) {
2008 if (dsi.debug_write)
2009 DSSDBG("\tsending full packet %d\n", i);
2016 dsi_vc_write_long_payload(channel, b1, b2, b3, b4);
2021 b1 = 0; b2 = 0; b3 = 0;
2023 if (dsi.debug_write)
2024 DSSDBG("\tsending remainder bytes %d\n", i);
2041 dsi_vc_write_long_payload(channel, b1, b2, b3, 0);
2047 static int dsi_vc_send_short(int channel, u8 data_type, u16 data, u8 ecc)
2052 WARN_ON(!dsi_bus_is_locked());
2054 if (dsi.debug_write)
2055 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
2057 data_type, data & 0xff, (data >> 8) & 0xff);
2059 dsi_vc_config_l4(channel);
2061 if (FLD_GET(dsi_read_reg(DSI_VC_CTRL(channel)), 16, 16)) {
2062 DSSERR("ERROR FIFO FULL, aborting transfer\n");
2066 data_id = data_type | channel << 6;
2068 r = (data_id << 0) | (data << 8) | (ecc << 24);
2070 dsi_write_reg(DSI_VC_SHORT_PACKET_HEADER(channel), r);
2075 int dsi_vc_send_null(int channel)
2077 u8 nullpkg[] = {0, 0, 0, 0};
2078 return dsi_vc_send_long(channel, DSI_DT_NULL_PACKET, nullpkg, 4, 0);
2080 EXPORT_SYMBOL(dsi_vc_send_null);
2082 int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len)
2089 r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_0,
2091 } else if (len == 2) {
2092 r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_1,
2093 data[0] | (data[1] << 8), 0);
2095 /* 0x39 = DCS Long Write */
2096 r = dsi_vc_send_long(channel, DSI_DT_DCS_LONG_WRITE,
2102 EXPORT_SYMBOL(dsi_vc_dcs_write_nosync);
2104 int dsi_vc_dcs_write(int channel, u8 *data, int len)
2108 r = dsi_vc_dcs_write_nosync(channel, data, len);
2112 r = dsi_vc_send_bta_sync(channel);
2116 if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { /* RX_FIFO_NOT_EMPTY */
2117 DSSERR("rx fifo not empty after write, dumping data:\n");
2118 dsi_vc_flush_receive_data(channel);
2125 DSSERR("dsi_vc_dcs_write(ch %d, cmd 0x%02x, len %d) failed\n",
2126 channel, data[0], len);
2129 EXPORT_SYMBOL(dsi_vc_dcs_write);
2131 int dsi_vc_dcs_write_0(int channel, u8 dcs_cmd)
2133 return dsi_vc_dcs_write(channel, &dcs_cmd, 1);
2135 EXPORT_SYMBOL(dsi_vc_dcs_write_0);
2137 int dsi_vc_dcs_write_1(int channel, u8 dcs_cmd, u8 param)
2142 return dsi_vc_dcs_write(channel, buf, 2);
2144 EXPORT_SYMBOL(dsi_vc_dcs_write_1);
2146 int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen)
2153 DSSDBG("dsi_vc_dcs_read(ch%d, dcs_cmd %x)\n", channel, dcs_cmd);
2155 r = dsi_vc_send_short(channel, DSI_DT_DCS_READ, dcs_cmd, 0);
2159 r = dsi_vc_send_bta_sync(channel);
2163 /* RX_FIFO_NOT_EMPTY */
2164 if (REG_GET(DSI_VC_CTRL(channel), 20, 20) == 0) {
2165 DSSERR("RX fifo empty when trying to read.\n");
2170 val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
2172 DSSDBG("\theader: %08x\n", val);
2173 dt = FLD_GET(val, 5, 0);
2174 if (dt == DSI_DT_RX_ACK_WITH_ERR) {
2175 u16 err = FLD_GET(val, 23, 8);
2176 dsi_show_rx_ack_with_err(err);
2180 } else if (dt == DSI_DT_RX_SHORT_READ_1) {
2181 u8 data = FLD_GET(val, 15, 8);
2183 DSSDBG("\tDCS short response, 1 byte: %02x\n", data);
2193 } else if (dt == DSI_DT_RX_SHORT_READ_2) {
2194 u16 data = FLD_GET(val, 23, 8);
2196 DSSDBG("\tDCS short response, 2 byte: %04x\n", data);
2203 buf[0] = data & 0xff;
2204 buf[1] = (data >> 8) & 0xff;
2207 } else if (dt == DSI_DT_RX_DCS_LONG_READ) {
2209 int len = FLD_GET(val, 23, 8);
2211 DSSDBG("\tDCS long response, len %d\n", len);
2218 /* two byte checksum ends the packet, not included in len */
2219 for (w = 0; w < len + 2;) {
2221 val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
2223 DSSDBG("\t\t%02x %02x %02x %02x\n",
2227 (val >> 24) & 0xff);
2229 for (b = 0; b < 4; ++b) {
2231 buf[w] = (val >> (b * 8)) & 0xff;
2232 /* we discard the 2 byte checksum */
2239 DSSERR("\tunknown datatype 0x%02x\n", dt);
2246 DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n",
2251 EXPORT_SYMBOL(dsi_vc_dcs_read);
2253 int dsi_vc_dcs_read_1(int channel, u8 dcs_cmd, u8 *data)
2257 r = dsi_vc_dcs_read(channel, dcs_cmd, data, 1);
2267 EXPORT_SYMBOL(dsi_vc_dcs_read_1);
2269 int dsi_vc_dcs_read_2(int channel, u8 dcs_cmd, u8 *data1, u8 *data2)
2274 r = dsi_vc_dcs_read(channel, dcs_cmd, buf, 2);
2287 EXPORT_SYMBOL(dsi_vc_dcs_read_2);
2289 int dsi_vc_set_max_rx_packet_size(int channel, u16 len)
2291 return dsi_vc_send_short(channel, DSI_DT_SET_MAX_RET_PKG_SIZE,
2294 EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size);
2296 static void dsi_set_lp_rx_timeout(unsigned ticks, bool x4, bool x16)
2299 unsigned long total_ticks;
2302 BUG_ON(ticks > 0x1fff);
2304 /* ticks in DSI_FCK */
2305 fck = dsi_fclk_rate();
2307 r = dsi_read_reg(DSI_TIMING2);
2308 r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */
2309 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */
2310 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */
2311 r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */
2312 dsi_write_reg(DSI_TIMING2, r);
2314 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
2316 DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n",
2318 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
2319 (total_ticks * 1000) / (fck / 1000 / 1000));
2322 static void dsi_set_ta_timeout(unsigned ticks, bool x8, bool x16)
2325 unsigned long total_ticks;
2328 BUG_ON(ticks > 0x1fff);
2330 /* ticks in DSI_FCK */
2331 fck = dsi_fclk_rate();
2333 r = dsi_read_reg(DSI_TIMING1);
2334 r = FLD_MOD(r, 1, 31, 31); /* TA_TO */
2335 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */
2336 r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */
2337 r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */
2338 dsi_write_reg(DSI_TIMING1, r);
2340 total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1);
2342 DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n",
2344 ticks, x8 ? " x8" : "", x16 ? " x16" : "",
2345 (total_ticks * 1000) / (fck / 1000 / 1000));
2348 static void dsi_set_stop_state_counter(unsigned ticks, bool x4, bool x16)
2351 unsigned long total_ticks;
2354 BUG_ON(ticks > 0x1fff);
2356 /* ticks in DSI_FCK */
2357 fck = dsi_fclk_rate();
2359 r = dsi_read_reg(DSI_TIMING1);
2360 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2361 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */
2362 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */
2363 r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */
2364 dsi_write_reg(DSI_TIMING1, r);
2366 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
2368 DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n",
2370 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
2371 (total_ticks * 1000) / (fck / 1000 / 1000));
2374 static void dsi_set_hs_tx_timeout(unsigned ticks, bool x4, bool x16)
2377 unsigned long total_ticks;
2380 BUG_ON(ticks > 0x1fff);
2382 /* ticks in TxByteClkHS */
2383 fck = dsi_get_txbyteclkhs();
2385 r = dsi_read_reg(DSI_TIMING2);
2386 r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */
2387 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */
2388 r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */
2389 r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */
2390 dsi_write_reg(DSI_TIMING2, r);
2392 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
2394 DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n",
2396 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
2397 (total_ticks * 1000) / (fck / 1000 / 1000));
2399 static int dsi_proto_config(struct omap_dss_device *dssdev)
2404 dsi_config_tx_fifo(DSI_FIFO_SIZE_32,
2409 dsi_config_rx_fifo(DSI_FIFO_SIZE_32,
2414 /* XXX what values for the timeouts? */
2415 dsi_set_stop_state_counter(0x1000, false, false);
2416 dsi_set_ta_timeout(0x1fff, true, true);
2417 dsi_set_lp_rx_timeout(0x1fff, true, true);
2418 dsi_set_hs_tx_timeout(0x1fff, true, true);
2420 switch (dssdev->ctrl.pixel_size) {
2434 r = dsi_read_reg(DSI_CTRL);
2435 r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */
2436 r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */
2437 r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */
2438 r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/
2439 r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
2440 r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */
2441 r = FLD_MOD(r, 2, 13, 12); /* LINE_BUFFER, 2 lines */
2442 r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */
2443 r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */
2444 r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */
2445 r = FLD_MOD(r, 0, 25, 25); /* DCS_CMD_CODE, 1=start, 0=continue */
2447 dsi_write_reg(DSI_CTRL, r);
2449 dsi_vc_initial_config(0);
2450 dsi_vc_initial_config(1);
2451 dsi_vc_initial_config(2);
2452 dsi_vc_initial_config(3);
2457 static void dsi_proto_timings(struct omap_dss_device *dssdev)
2459 unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail;
2460 unsigned tclk_pre, tclk_post;
2461 unsigned ths_prepare, ths_prepare_ths_zero, ths_zero;
2462 unsigned ths_trail, ths_exit;
2463 unsigned ddr_clk_pre, ddr_clk_post;
2464 unsigned enter_hs_mode_lat, exit_hs_mode_lat;
2468 r = dsi_read_reg(DSI_DSIPHY_CFG0);
2469 ths_prepare = FLD_GET(r, 31, 24);
2470 ths_prepare_ths_zero = FLD_GET(r, 23, 16);
2471 ths_zero = ths_prepare_ths_zero - ths_prepare;
2472 ths_trail = FLD_GET(r, 15, 8);
2473 ths_exit = FLD_GET(r, 7, 0);
2475 r = dsi_read_reg(DSI_DSIPHY_CFG1);
2476 tlpx = FLD_GET(r, 22, 16) * 2;
2477 tclk_trail = FLD_GET(r, 15, 8);
2478 tclk_zero = FLD_GET(r, 7, 0);
2480 r = dsi_read_reg(DSI_DSIPHY_CFG2);
2481 tclk_prepare = FLD_GET(r, 7, 0);
2485 /* min 60ns + 52*UI */
2486 tclk_post = ns2ddr(60) + 26;
2488 /* ths_eot is 2 for 2 datalanes and 4 for 1 datalane */
2489 if (dssdev->phy.dsi.data1_lane != 0 &&
2490 dssdev->phy.dsi.data2_lane != 0)
2495 ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
2497 ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot;
2499 BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
2500 BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);
2502 r = dsi_read_reg(DSI_CLK_TIMING);
2503 r = FLD_MOD(r, ddr_clk_pre, 15, 8);
2504 r = FLD_MOD(r, ddr_clk_post, 7, 0);
2505 dsi_write_reg(DSI_CLK_TIMING, r);
2507 DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
2511 enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) +
2512 DIV_ROUND_UP(ths_prepare, 4) +
2513 DIV_ROUND_UP(ths_zero + 3, 4);
2515 exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;
2517 r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
2518 FLD_VAL(exit_hs_mode_lat, 15, 0);
2519 dsi_write_reg(DSI_VM_TIMING7, r);
2521 DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
2522 enter_hs_mode_lat, exit_hs_mode_lat);
2526 #define DSI_DECL_VARS \
2527 int __dsi_cb = 0; u32 __dsi_cv = 0;
2529 #define DSI_FLUSH(ch) \
2530 if (__dsi_cb > 0) { \
2531 /*DSSDBG("sending long packet %#010x\n", __dsi_cv);*/ \
2532 dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(ch), __dsi_cv); \
2533 __dsi_cb = __dsi_cv = 0; \
2536 #define DSI_PUSH(ch, data) \
2538 __dsi_cv |= (data) << (__dsi_cb * 8); \
2539 /*DSSDBG("cv = %#010x, cb = %d\n", __dsi_cv, __dsi_cb);*/ \
2540 if (++__dsi_cb > 3) \
2544 static int dsi_update_screen_l4(struct omap_dss_device *dssdev,
2545 int x, int y, int w, int h)
2547 /* Note: supports only 24bit colors in 32bit container */
2549 int fifo_stalls = 0;
2550 int max_dsi_packet_size;
2551 int max_data_per_packet;
2552 int max_pixels_per_packet;
2554 int bytespp = dssdev->ctrl.pixel_size / 8;
2560 struct omap_overlay *ovl;
2564 DSSDBG("dsi_update_screen_l4 (%d,%d %dx%d)\n",
2567 ovl = dssdev->manager->overlays[0];
2569 if (ovl->info.color_mode != OMAP_DSS_COLOR_RGB24U)
2572 if (dssdev->ctrl.pixel_size != 24)
2575 scr_width = ovl->info.screen_width;
2576 data = ovl->info.vaddr;
2578 start_offset = scr_width * y + x;
2579 horiz_inc = scr_width - w;
2582 /* We need header(4) + DCSCMD(1) + pixels(numpix*bytespp) bytes
2585 /* When using CPU, max long packet size is TX buffer size */
2586 max_dsi_packet_size = dsi.vc[0].fifo_size * 32 * 4;
2588 /* we seem to get better perf if we divide the tx fifo to half,
2589 and while the other half is being sent, we fill the other half
2590 max_dsi_packet_size /= 2; */
2592 max_data_per_packet = max_dsi_packet_size - 4 - 1;
2594 max_pixels_per_packet = max_data_per_packet / bytespp;
2596 DSSDBG("max_pixels_per_packet %d\n", max_pixels_per_packet);
2598 pixels_left = w * h;
2600 DSSDBG("total pixels %d\n", pixels_left);
2602 data += start_offset;
2604 while (pixels_left > 0) {
2605 /* 0x2c = write_memory_start */
2606 /* 0x3c = write_memory_continue */
2607 u8 dcs_cmd = first ? 0x2c : 0x3c;
2613 /* using fifo not empty */
2614 /* TX_FIFO_NOT_EMPTY */
2615 while (FLD_GET(dsi_read_reg(DSI_VC_CTRL(0)), 5, 5)) {
2617 if (fifo_stalls > 0xfffff) {
2618 DSSERR("fifo stalls overflow, pixels left %d\n",
2626 /* using fifo emptiness */
2627 while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 <
2628 max_dsi_packet_size) {
2630 if (fifo_stalls > 0xfffff) {
2631 DSSERR("fifo stalls overflow, pixels left %d\n",
2638 while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 == 0) {
2640 if (fifo_stalls > 0xfffff) {
2641 DSSERR("fifo stalls overflow, pixels left %d\n",
2648 pixels = min(max_pixels_per_packet, pixels_left);
2650 pixels_left -= pixels;
2652 dsi_vc_write_long_header(0, DSI_DT_DCS_LONG_WRITE,
2653 1 + pixels * bytespp, 0);
2655 DSI_PUSH(0, dcs_cmd);
2657 while (pixels-- > 0) {
2658 u32 pix = __raw_readl(data++);
2660 DSI_PUSH(0, (pix >> 16) & 0xff);
2661 DSI_PUSH(0, (pix >> 8) & 0xff);
2662 DSI_PUSH(0, (pix >> 0) & 0xff);
2665 if (current_x == x+w) {
2677 static void dsi_update_screen_dispc(struct omap_dss_device *dssdev,
2678 u16 x, u16 y, u16 w, u16 h)
2684 unsigned packet_payload;
2685 unsigned packet_len;
2688 const unsigned channel = dsi.update_channel;
2689 /* line buffer is 1024 x 24bits */
2690 /* XXX: for some reason using full buffer size causes considerable TX
2691 * slowdown with update sizes that fill the whole buffer */
2692 const unsigned line_buf_size = 1023 * 3;
2694 DSSDBG("dsi_update_screen_dispc(%d,%d %dx%d)\n",
2697 dsi_vc_config_vp(channel);
2699 bytespp = dssdev->ctrl.pixel_size / 8;
2700 bytespl = w * bytespp;
2701 bytespf = bytespl * h;
2703 /* NOTE: packet_payload has to be equal to N * bytespl, where N is
2704 * number of lines in a packet. See errata about VP_CLK_RATIO */
2706 if (bytespf < line_buf_size)
2707 packet_payload = bytespf;
2709 packet_payload = (line_buf_size) / bytespl * bytespl;
2711 packet_len = packet_payload + 1; /* 1 byte for DCS cmd */
2712 total_len = (bytespf / packet_payload) * packet_len;
2714 if (bytespf % packet_payload)
2715 total_len += (bytespf % packet_payload) + 1;
2717 l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
2718 dsi_write_reg(DSI_VC_TE(channel), l);
2720 dsi_vc_write_long_header(channel, DSI_DT_DCS_LONG_WRITE, packet_len, 0);
2723 l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
2725 l = FLD_MOD(l, 1, 31, 31); /* TE_START */
2726 dsi_write_reg(DSI_VC_TE(channel), l);
2728 /* We put SIDLEMODE to no-idle for the duration of the transfer,
2729 * because DSS interrupts are not capable of waking up the CPU and the
2730 * framedone interrupt could be delayed for quite a long time. I think
2731 * the same goes for any DSS interrupts, but for some reason I have not
2732 * seen the problem anywhere else than here.
2734 dispc_disable_sidle();
2736 dsi_perf_mark_start();
2738 r = queue_delayed_work(dsi.workqueue, &dsi.framedone_timeout_work,
2739 msecs_to_jiffies(250));
2742 dss_start_update(dssdev);
2744 if (dsi.te_enabled) {
2745 /* disable LP_RX_TO, so that we can receive TE. Time to wait
2746 * for TE is longer than the timer allows */
2747 REG_FLD_MOD(DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
2749 dsi_vc_send_bta(channel);
2751 #ifdef DSI_CATCH_MISSING_TE
2752 mod_timer(&dsi.te_timer, jiffies + msecs_to_jiffies(250));
2757 #ifdef DSI_CATCH_MISSING_TE
2758 static void dsi_te_timeout(unsigned long arg)
2760 DSSERR("TE not received for 250ms!\n");
2764 static void dsi_handle_framedone(int error)
2766 const int channel = dsi.update_channel;
2768 cancel_delayed_work(&dsi.framedone_timeout_work);
2770 dsi_vc_disable_bta_irq(channel);
2772 /* SIDLEMODE back to smart-idle */
2773 dispc_enable_sidle();
2775 dsi.bta_callback = NULL;
2777 if (dsi.te_enabled) {
2778 /* enable LP_RX_TO again after the TE */
2779 REG_FLD_MOD(DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
2782 /* RX_FIFO_NOT_EMPTY */
2783 if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
2784 DSSERR("Received error during frame transfer:\n");
2785 dsi_vc_flush_receive_data(channel);
2790 dsi.framedone_callback(error, dsi.framedone_data);
2793 dsi_perf_show("DISPC");
2796 static void dsi_framedone_timeout_work_callback(struct work_struct *work)
2798 /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after
2799 * 250ms which would conflict with this timeout work. What should be
2800 * done is first cancel the transfer on the HW, and then cancel the
2801 * possibly scheduled framedone work. However, cancelling the transfer
2802 * on the HW is buggy, and would probably require resetting the whole
2805 DSSERR("Framedone not received for 250ms!\n");
2807 dsi_handle_framedone(-ETIMEDOUT);
2810 static void dsi_framedone_bta_callback(void)
2812 dsi_handle_framedone(0);
2814 #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
2815 dispc_fake_vsync_irq();
2819 static void dsi_framedone_irq_callback(void *data, u32 mask)
2821 const int channel = dsi.update_channel;
2824 /* Note: We get FRAMEDONE when DISPC has finished sending pixels and
2825 * turns itself off. However, DSI still has the pixels in its buffers,
2826 * and is sending the data.
2829 if (dsi.te_enabled) {
2830 /* enable LP_RX_TO again after the TE */
2831 REG_FLD_MOD(DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
2834 /* Send BTA after the frame. We need this for the TE to work, as TE
2835 * trigger is only sent for BTAs without preceding packet. Thus we need
2836 * to BTA after the pixel packets so that next BTA will cause TE
2839 * This is not needed when TE is not in use, but we do it anyway to
2840 * make sure that the transfer has been completed. It would be more
2841 * optimal, but more complex, to wait only just before starting next
2844 * Also, as there's no interrupt telling when the transfer has been
2845 * done and the channel could be reconfigured, the only way is to
2846 * busyloop until TE_SIZE is zero. With BTA we can do this
2850 dsi.bta_callback = dsi_framedone_bta_callback;
2854 dsi_vc_enable_bta_irq(channel);
2856 r = dsi_vc_send_bta(channel);
2858 DSSERR("BTA after framedone failed\n");
2859 dsi_handle_framedone(-EIO);
2863 int omap_dsi_prepare_update(struct omap_dss_device *dssdev,
2864 u16 *x, u16 *y, u16 *w, u16 *h,
2865 bool enlarge_update_area)
2869 dssdev->driver->get_resolution(dssdev, &dw, &dh);
2871 if (*x > dw || *y > dh)
2883 if (*w == 0 || *h == 0)
2886 dsi_perf_mark_setup();
2888 if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
2889 dss_setup_partial_planes(dssdev, x, y, w, h,
2890 enlarge_update_area);
2891 dispc_set_lcd_size(dssdev->manager->id, *w, *h);
2896 EXPORT_SYMBOL(omap_dsi_prepare_update);
2898 int omap_dsi_update(struct omap_dss_device *dssdev,
2900 u16 x, u16 y, u16 w, u16 h,
2901 void (*callback)(int, void *), void *data)
2903 dsi.update_channel = channel;
2905 /* OMAP DSS cannot send updates of odd widths.
2906 * omap_dsi_prepare_update() makes the widths even, but add a BUG_ON
2907 * here to make sure we catch erroneous updates. Otherwise we'll only
2908 * see rather obscure HW error happening, as DSS halts. */
2911 if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
2912 dsi.framedone_callback = callback;
2913 dsi.framedone_data = data;
2915 dsi.update_region.x = x;
2916 dsi.update_region.y = y;
2917 dsi.update_region.w = w;
2918 dsi.update_region.h = h;
2919 dsi.update_region.device = dssdev;
2921 dsi_update_screen_dispc(dssdev, x, y, w, h);
2925 r = dsi_update_screen_l4(dssdev, x, y, w, h);
2929 dsi_perf_show("L4");
2935 EXPORT_SYMBOL(omap_dsi_update);
2939 static int dsi_display_init_dispc(struct omap_dss_device *dssdev)
2943 r = omap_dispc_register_isr(dsi_framedone_irq_callback, NULL,
2944 DISPC_IRQ_FRAMEDONE);
2946 DSSERR("can't get FRAMEDONE irq\n");
2950 dispc_set_lcd_display_type(dssdev->manager->id,
2951 OMAP_DSS_LCD_DISPLAY_TFT);
2953 dispc_set_parallel_interface_mode(dssdev->manager->id,
2954 OMAP_DSS_PARALLELMODE_DSI);
2955 dispc_enable_fifohandcheck(dssdev->manager->id, 1);
2957 dispc_set_tft_data_lines(dssdev->manager->id, dssdev->ctrl.pixel_size);
2960 struct omap_video_timings timings = {
2969 dispc_set_lcd_timings(dssdev->manager->id, &timings);
2975 static void dsi_display_uninit_dispc(struct omap_dss_device *dssdev)
2977 omap_dispc_unregister_isr(dsi_framedone_irq_callback, NULL,
2978 DISPC_IRQ_FRAMEDONE);
2981 static int dsi_configure_dsi_clocks(struct omap_dss_device *dssdev)
2983 struct dsi_clock_info cinfo;
2986 /* we always use DSS2_FCK as input clock */
2987 cinfo.use_dss2_fck = true;
2988 cinfo.regn = dssdev->phy.dsi.div.regn;
2989 cinfo.regm = dssdev->phy.dsi.div.regm;
2990 cinfo.regm3 = dssdev->phy.dsi.div.regm3;
2991 cinfo.regm4 = dssdev->phy.dsi.div.regm4;
2992 r = dsi_calc_clock_rates(dssdev, &cinfo);
2994 DSSERR("Failed to calc dsi clocks\n");
2998 r = dsi_pll_set_clock_div(&cinfo);
3000 DSSERR("Failed to set dsi clocks\n");
3007 static int dsi_configure_dispc_clocks(struct omap_dss_device *dssdev)
3009 struct dispc_clock_info dispc_cinfo;
3011 unsigned long long fck;
3013 fck = dsi_get_dsi1_pll_rate();
3015 dispc_cinfo.lck_div = dssdev->phy.dsi.div.lck_div;
3016 dispc_cinfo.pck_div = dssdev->phy.dsi.div.pck_div;
3018 r = dispc_calc_clock_rates(fck, &dispc_cinfo);
3020 DSSERR("Failed to calc dispc clocks\n");
3024 r = dispc_set_clock_div(dssdev->manager->id, &dispc_cinfo);
3026 DSSERR("Failed to set dispc clocks\n");
3033 static int dsi_display_init_dsi(struct omap_dss_device *dssdev)
3037 _dsi_print_reset_status();
3039 r = dsi_pll_init(dssdev, true, true);
3043 r = dsi_configure_dsi_clocks(dssdev);
3047 dss_select_dispc_clk_source(DSS_SRC_DSI1_PLL_FCLK);
3048 dss_select_dsi_clk_source(DSS_SRC_DSI2_PLL_FCLK);
3052 r = dsi_configure_dispc_clocks(dssdev);
3056 r = dsi_complexio_init(dssdev);
3060 _dsi_print_reset_status();
3062 dsi_proto_timings(dssdev);
3063 dsi_set_lp_clk_divisor(dssdev);
3066 _dsi_print_reset_status();
3068 r = dsi_proto_config(dssdev);
3072 /* enable interface */
3073 dsi_vc_enable(0, 1);
3074 dsi_vc_enable(1, 1);
3075 dsi_vc_enable(2, 1);
3076 dsi_vc_enable(3, 1);
3078 dsi_force_tx_stop_mode_io();
3082 dsi_complexio_uninit();
3084 dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
3085 dss_select_dsi_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
3092 static void dsi_display_uninit_dsi(struct omap_dss_device *dssdev)
3094 /* disable interface */
3096 dsi_vc_enable(0, 0);
3097 dsi_vc_enable(1, 0);
3098 dsi_vc_enable(2, 0);
3099 dsi_vc_enable(3, 0);
3101 dss_select_dispc_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
3102 dss_select_dsi_clk_source(DSS_SRC_DSS1_ALWON_FCLK);
3103 dsi_complexio_uninit();
3107 static int dsi_core_init(void)
3110 REG_FLD_MOD(DSI_SYSCONFIG, 1, 0, 0);
3113 REG_FLD_MOD(DSI_SYSCONFIG, 1, 2, 2);
3115 /* SIDLEMODE smart-idle */
3116 REG_FLD_MOD(DSI_SYSCONFIG, 2, 4, 3);
3118 _dsi_initialize_irq();
3123 int omapdss_dsi_display_enable(struct omap_dss_device *dssdev)
3127 DSSDBG("dsi_display_enable\n");
3129 WARN_ON(!dsi_bus_is_locked());
3131 mutex_lock(&dsi.lock);
3133 r = omap_dss_start_device(dssdev);
3135 DSSERR("failed to start device\n");
3140 dsi_enable_pll_clock(1);
3148 r = dsi_display_init_dispc(dssdev);
3152 r = dsi_display_init_dsi(dssdev);
3156 mutex_unlock(&dsi.lock);
3161 dsi_display_uninit_dispc(dssdev);
3164 dsi_enable_pll_clock(0);
3165 omap_dss_stop_device(dssdev);
3167 mutex_unlock(&dsi.lock);
3168 DSSDBG("dsi_display_enable FAILED\n");
3171 EXPORT_SYMBOL(omapdss_dsi_display_enable);
3173 void omapdss_dsi_display_disable(struct omap_dss_device *dssdev)
3175 DSSDBG("dsi_display_disable\n");
3177 WARN_ON(!dsi_bus_is_locked());
3179 mutex_lock(&dsi.lock);
3181 dsi_display_uninit_dispc(dssdev);
3183 dsi_display_uninit_dsi(dssdev);
3186 dsi_enable_pll_clock(0);
3188 omap_dss_stop_device(dssdev);
3190 mutex_unlock(&dsi.lock);
3192 EXPORT_SYMBOL(omapdss_dsi_display_disable);
3194 int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable)
3196 dsi.te_enabled = enable;
3199 EXPORT_SYMBOL(omapdss_dsi_enable_te);
3201 void dsi_get_overlay_fifo_thresholds(enum omap_plane plane,
3202 u32 fifo_size, enum omap_burst_size *burst_size,
3203 u32 *fifo_low, u32 *fifo_high)
3205 unsigned burst_size_bytes;
3207 *burst_size = OMAP_DSS_BURST_16x32;
3208 burst_size_bytes = 16 * 32 / 8;
3210 *fifo_high = fifo_size - burst_size_bytes;
3211 *fifo_low = fifo_size - burst_size_bytes * 2;
3214 int dsi_init_display(struct omap_dss_device *dssdev)
3216 DSSDBG("DSI init\n");
3218 /* XXX these should be figured out dynamically */
3219 dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE |
3220 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM;
3222 dsi.vc[0].dssdev = dssdev;
3223 dsi.vc[1].dssdev = dssdev;
3225 if (dsi.vdds_dsi_reg == NULL) {
3226 struct regulator *vdds_dsi;
3228 vdds_dsi = regulator_get(&dsi.pdev->dev, "vdds_dsi");
3230 if (IS_ERR(vdds_dsi)) {
3231 DSSERR("can't get VDDS_DSI regulator\n");
3232 return PTR_ERR(vdds_dsi);
3235 dsi.vdds_dsi_reg = vdds_dsi;
3241 void dsi_wait_dsi1_pll_active(void)
3243 if (wait_for_bit_change(DSI_PLL_STATUS, 7, 1) != 1)
3244 DSSERR("DSI1 PLL clock not active\n");
3247 void dsi_wait_dsi2_pll_active(void)
3249 if (wait_for_bit_change(DSI_PLL_STATUS, 8, 1) != 1)
3250 DSSERR("DSI2 PLL clock not active\n");
3253 static int dsi_init(struct platform_device *pdev)
3257 struct resource *dsi_mem;
3259 spin_lock_init(&dsi.errors_lock);
3262 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3263 spin_lock_init(&dsi.irq_stats_lock);
3264 dsi.irq_stats.last_reset = jiffies;
3267 init_completion(&dsi.bta_completion);
3269 mutex_init(&dsi.lock);
3270 sema_init(&dsi.bus_lock, 1);
3272 dsi.workqueue = create_singlethread_workqueue("dsi");
3273 if (dsi.workqueue == NULL)
3276 INIT_DELAYED_WORK_DEFERRABLE(&dsi.framedone_timeout_work,
3277 dsi_framedone_timeout_work_callback);
3279 #ifdef DSI_CATCH_MISSING_TE
3280 init_timer(&dsi.te_timer);
3281 dsi.te_timer.function = dsi_te_timeout;
3282 dsi.te_timer.data = 0;
3284 dsi_mem = platform_get_resource(dsi.pdev, IORESOURCE_MEM, 0);
3286 DSSERR("can't get IORESOURCE_MEM DSI\n");
3290 dsi.base = ioremap(dsi_mem->start, resource_size(dsi_mem));
3292 DSSERR("can't ioremap DSI\n");
3299 rev = dsi_read_reg(DSI_REVISION);
3300 dev_dbg(&pdev->dev, "OMAP DSI rev %d.%d\n",
3301 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3307 destroy_workqueue(dsi.workqueue);
3311 static void dsi_exit(void)
3313 if (dsi.vdds_dsi_reg != NULL) {
3314 regulator_put(dsi.vdds_dsi_reg);
3315 dsi.vdds_dsi_reg = NULL;
3320 destroy_workqueue(dsi.workqueue);
3322 DSSDBG("omap_dsi_exit\n");
3325 /* DSI1 HW IP initialisation */
3326 static int omap_dsi1hw_probe(struct platform_device *pdev)
3332 DSSERR("Failed to initialize DSI\n");
3339 static int omap_dsi1hw_remove(struct platform_device *pdev)
3345 static struct platform_driver omap_dsi1hw_driver = {
3346 .probe = omap_dsi1hw_probe,
3347 .remove = omap_dsi1hw_remove,
3349 .name = "omapdss_dsi1",
3350 .owner = THIS_MODULE,
3354 int dsi_init_platform_driver(void)
3356 return platform_driver_register(&omap_dsi1hw_driver);
3359 void dsi_uninit_platform_driver(void)
3361 return platform_driver_unregister(&omap_dsi1hw_driver);