2 * linux/drivers/video/omap2/dss/dsi.c
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #define DSS_SUBSYS_NAME "DSI"
22 #include <linux/kernel.h>
24 #include <linux/clk.h>
25 #include <linux/device.h>
26 #include <linux/err.h>
27 #include <linux/interrupt.h>
28 #include <linux/delay.h>
29 #include <linux/mutex.h>
30 #include <linux/module.h>
31 #include <linux/semaphore.h>
32 #include <linux/seq_file.h>
33 #include <linux/platform_device.h>
34 #include <linux/regulator/consumer.h>
35 #include <linux/wait.h>
36 #include <linux/workqueue.h>
37 #include <linux/sched.h>
38 #include <linux/slab.h>
39 #include <linux/debugfs.h>
40 #include <linux/pm_runtime.h>
42 #include <video/omapdss.h>
43 #include <video/mipi_display.h>
46 #include "dss_features.h"
48 #define DSI_CATCH_MISSING_TE
50 struct dsi_reg { u16 idx; };
52 #define DSI_REG(idx) ((const struct dsi_reg) { idx })
54 #define DSI_SZ_REGS SZ_1K
55 /* DSI Protocol Engine */
57 #define DSI_REVISION DSI_REG(0x0000)
58 #define DSI_SYSCONFIG DSI_REG(0x0010)
59 #define DSI_SYSSTATUS DSI_REG(0x0014)
60 #define DSI_IRQSTATUS DSI_REG(0x0018)
61 #define DSI_IRQENABLE DSI_REG(0x001C)
62 #define DSI_CTRL DSI_REG(0x0040)
63 #define DSI_GNQ DSI_REG(0x0044)
64 #define DSI_COMPLEXIO_CFG1 DSI_REG(0x0048)
65 #define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(0x004C)
66 #define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(0x0050)
67 #define DSI_CLK_CTRL DSI_REG(0x0054)
68 #define DSI_TIMING1 DSI_REG(0x0058)
69 #define DSI_TIMING2 DSI_REG(0x005C)
70 #define DSI_VM_TIMING1 DSI_REG(0x0060)
71 #define DSI_VM_TIMING2 DSI_REG(0x0064)
72 #define DSI_VM_TIMING3 DSI_REG(0x0068)
73 #define DSI_CLK_TIMING DSI_REG(0x006C)
74 #define DSI_TX_FIFO_VC_SIZE DSI_REG(0x0070)
75 #define DSI_RX_FIFO_VC_SIZE DSI_REG(0x0074)
76 #define DSI_COMPLEXIO_CFG2 DSI_REG(0x0078)
77 #define DSI_RX_FIFO_VC_FULLNESS DSI_REG(0x007C)
78 #define DSI_VM_TIMING4 DSI_REG(0x0080)
79 #define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(0x0084)
80 #define DSI_VM_TIMING5 DSI_REG(0x0088)
81 #define DSI_VM_TIMING6 DSI_REG(0x008C)
82 #define DSI_VM_TIMING7 DSI_REG(0x0090)
83 #define DSI_STOPCLK_TIMING DSI_REG(0x0094)
84 #define DSI_VC_CTRL(n) DSI_REG(0x0100 + (n * 0x20))
85 #define DSI_VC_TE(n) DSI_REG(0x0104 + (n * 0x20))
86 #define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(0x0108 + (n * 0x20))
87 #define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(0x010C + (n * 0x20))
88 #define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(0x0110 + (n * 0x20))
89 #define DSI_VC_IRQSTATUS(n) DSI_REG(0x0118 + (n * 0x20))
90 #define DSI_VC_IRQENABLE(n) DSI_REG(0x011C + (n * 0x20))
94 #define DSI_DSIPHY_CFG0 DSI_REG(0x200 + 0x0000)
95 #define DSI_DSIPHY_CFG1 DSI_REG(0x200 + 0x0004)
96 #define DSI_DSIPHY_CFG2 DSI_REG(0x200 + 0x0008)
97 #define DSI_DSIPHY_CFG5 DSI_REG(0x200 + 0x0014)
98 #define DSI_DSIPHY_CFG10 DSI_REG(0x200 + 0x0028)
100 /* DSI_PLL_CTRL_SCP */
102 #define DSI_PLL_CONTROL DSI_REG(0x300 + 0x0000)
103 #define DSI_PLL_STATUS DSI_REG(0x300 + 0x0004)
104 #define DSI_PLL_GO DSI_REG(0x300 + 0x0008)
105 #define DSI_PLL_CONFIGURATION1 DSI_REG(0x300 + 0x000C)
106 #define DSI_PLL_CONFIGURATION2 DSI_REG(0x300 + 0x0010)
108 #define REG_GET(dsidev, idx, start, end) \
109 FLD_GET(dsi_read_reg(dsidev, idx), start, end)
111 #define REG_FLD_MOD(dsidev, idx, val, start, end) \
112 dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end))
114 /* Global interrupts */
115 #define DSI_IRQ_VC0 (1 << 0)
116 #define DSI_IRQ_VC1 (1 << 1)
117 #define DSI_IRQ_VC2 (1 << 2)
118 #define DSI_IRQ_VC3 (1 << 3)
119 #define DSI_IRQ_WAKEUP (1 << 4)
120 #define DSI_IRQ_RESYNC (1 << 5)
121 #define DSI_IRQ_PLL_LOCK (1 << 7)
122 #define DSI_IRQ_PLL_UNLOCK (1 << 8)
123 #define DSI_IRQ_PLL_RECALL (1 << 9)
124 #define DSI_IRQ_COMPLEXIO_ERR (1 << 10)
125 #define DSI_IRQ_HS_TX_TIMEOUT (1 << 14)
126 #define DSI_IRQ_LP_RX_TIMEOUT (1 << 15)
127 #define DSI_IRQ_TE_TRIGGER (1 << 16)
128 #define DSI_IRQ_ACK_TRIGGER (1 << 17)
129 #define DSI_IRQ_SYNC_LOST (1 << 18)
130 #define DSI_IRQ_LDO_POWER_GOOD (1 << 19)
131 #define DSI_IRQ_TA_TIMEOUT (1 << 20)
132 #define DSI_IRQ_ERROR_MASK \
133 (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
134 DSI_IRQ_TA_TIMEOUT | DSI_IRQ_SYNC_LOST)
135 #define DSI_IRQ_CHANNEL_MASK 0xf
137 /* Virtual channel interrupts */
138 #define DSI_VC_IRQ_CS (1 << 0)
139 #define DSI_VC_IRQ_ECC_CORR (1 << 1)
140 #define DSI_VC_IRQ_PACKET_SENT (1 << 2)
141 #define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3)
142 #define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4)
143 #define DSI_VC_IRQ_BTA (1 << 5)
144 #define DSI_VC_IRQ_ECC_NO_CORR (1 << 6)
145 #define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7)
146 #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
147 #define DSI_VC_IRQ_ERROR_MASK \
148 (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
149 DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
150 DSI_VC_IRQ_FIFO_TX_UDF)
152 /* ComplexIO interrupts */
153 #define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0)
154 #define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1)
155 #define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2)
156 #define DSI_CIO_IRQ_ERRSYNCESC4 (1 << 3)
157 #define DSI_CIO_IRQ_ERRSYNCESC5 (1 << 4)
158 #define DSI_CIO_IRQ_ERRESC1 (1 << 5)
159 #define DSI_CIO_IRQ_ERRESC2 (1 << 6)
160 #define DSI_CIO_IRQ_ERRESC3 (1 << 7)
161 #define DSI_CIO_IRQ_ERRESC4 (1 << 8)
162 #define DSI_CIO_IRQ_ERRESC5 (1 << 9)
163 #define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10)
164 #define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11)
165 #define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12)
166 #define DSI_CIO_IRQ_ERRCONTROL4 (1 << 13)
167 #define DSI_CIO_IRQ_ERRCONTROL5 (1 << 14)
168 #define DSI_CIO_IRQ_STATEULPS1 (1 << 15)
169 #define DSI_CIO_IRQ_STATEULPS2 (1 << 16)
170 #define DSI_CIO_IRQ_STATEULPS3 (1 << 17)
171 #define DSI_CIO_IRQ_STATEULPS4 (1 << 18)
172 #define DSI_CIO_IRQ_STATEULPS5 (1 << 19)
173 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20)
174 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21)
175 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22)
176 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23)
177 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24)
178 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25)
179 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_4 (1 << 26)
180 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_4 (1 << 27)
181 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_5 (1 << 28)
182 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_5 (1 << 29)
183 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30)
184 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31)
185 #define DSI_CIO_IRQ_ERROR_MASK \
186 (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \
187 DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \
188 DSI_CIO_IRQ_ERRSYNCESC5 | \
189 DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \
190 DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \
191 DSI_CIO_IRQ_ERRESC5 | \
192 DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \
193 DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \
194 DSI_CIO_IRQ_ERRCONTROL5 | \
195 DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \
196 DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \
197 DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \
198 DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \
199 DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5)
201 typedef void (*omap_dsi_isr_t) (void *arg, u32 mask);
203 static int dsi_display_init_dispc(struct platform_device *dsidev,
204 struct omap_overlay_manager *mgr);
205 static void dsi_display_uninit_dispc(struct platform_device *dsidev,
206 struct omap_overlay_manager *mgr);
208 #define DSI_MAX_NR_ISRS 2
209 #define DSI_MAX_NR_LANES 5
211 enum dsi_lane_function {
220 struct dsi_lane_config {
221 enum dsi_lane_function function;
225 struct dsi_isr_data {
233 DSI_FIFO_SIZE_32 = 1,
234 DSI_FIFO_SIZE_64 = 2,
235 DSI_FIFO_SIZE_96 = 3,
236 DSI_FIFO_SIZE_128 = 4,
240 DSI_VC_SOURCE_L4 = 0,
244 struct dsi_irq_stats {
245 unsigned long last_reset;
247 unsigned dsi_irqs[32];
248 unsigned vc_irqs[4][32];
249 unsigned cio_irqs[32];
252 struct dsi_isr_tables {
253 struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS];
254 struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS];
255 struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS];
258 struct dsi_clk_calc_ctx {
259 struct platform_device *dsidev;
263 const struct omap_dss_dsi_config *config;
265 unsigned long req_pck_min, req_pck_nom, req_pck_max;
269 struct dsi_clock_info dsi_cinfo;
270 struct dispc_clock_info dispc_cinfo;
272 struct omap_video_timings dispc_vm;
273 struct omap_dss_dsi_videomode_timings dsi_vm;
277 struct platform_device *pdev;
287 struct dispc_clock_info user_dispc_cinfo;
288 struct dsi_clock_info user_dsi_cinfo;
290 struct dsi_clock_info current_cinfo;
292 bool vdds_dsi_enabled;
293 struct regulator *vdds_dsi_reg;
296 enum dsi_vc_source source;
297 struct omap_dss_device *dssdev;
298 enum fifo_size fifo_size;
303 struct semaphore bus_lock;
308 struct dsi_isr_tables isr_tables;
309 /* space for a copy used by the interrupt handler */
310 struct dsi_isr_tables isr_tables_copy;
314 unsigned update_bytes;
320 void (*framedone_callback)(int, void *);
321 void *framedone_data;
323 struct delayed_work framedone_timeout_work;
325 #ifdef DSI_CATCH_MISSING_TE
326 struct timer_list te_timer;
329 unsigned long cache_req_pck;
330 unsigned long cache_clk_freq;
331 struct dsi_clock_info cache_cinfo;
334 spinlock_t errors_lock;
336 ktime_t perf_setup_time;
337 ktime_t perf_start_time;
342 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
343 spinlock_t irq_stats_lock;
344 struct dsi_irq_stats irq_stats;
346 /* DSI PLL Parameter Ranges */
347 unsigned long regm_max, regn_max;
348 unsigned long regm_dispc_max, regm_dsi_max;
349 unsigned long fint_min, fint_max;
350 unsigned long lpdiv_max;
352 unsigned num_lanes_supported;
353 unsigned line_buffer_size;
355 struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
356 unsigned num_lanes_used;
358 unsigned scp_clk_refcount;
360 struct dss_lcd_mgr_config mgr_config;
361 struct omap_video_timings timings;
362 enum omap_dss_dsi_pixel_format pix_fmt;
363 enum omap_dss_dsi_mode mode;
364 struct omap_dss_dsi_videomode_timings vm_timings;
366 struct omap_dss_output output;
369 struct dsi_packet_sent_handler_data {
370 struct platform_device *dsidev;
371 struct completion *completion;
375 static bool dsi_perf;
376 module_param(dsi_perf, bool, 0644);
379 static inline struct dsi_data *dsi_get_dsidrv_data(struct platform_device *dsidev)
381 return dev_get_drvdata(&dsidev->dev);
384 static inline struct platform_device *dsi_get_dsidev_from_dssdev(struct omap_dss_device *dssdev)
386 return dssdev->output->pdev;
389 struct platform_device *dsi_get_dsidev_from_id(int module)
391 struct omap_dss_output *out;
392 enum omap_dss_output_id id;
396 id = OMAP_DSS_OUTPUT_DSI1;
399 id = OMAP_DSS_OUTPUT_DSI2;
405 out = omap_dss_get_output(id);
407 return out ? out->pdev : NULL;
410 static inline void dsi_write_reg(struct platform_device *dsidev,
411 const struct dsi_reg idx, u32 val)
413 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
415 __raw_writel(val, dsi->base + idx.idx);
418 static inline u32 dsi_read_reg(struct platform_device *dsidev,
419 const struct dsi_reg idx)
421 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
423 return __raw_readl(dsi->base + idx.idx);
426 void dsi_bus_lock(struct omap_dss_device *dssdev)
428 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
429 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
431 down(&dsi->bus_lock);
433 EXPORT_SYMBOL(dsi_bus_lock);
435 void dsi_bus_unlock(struct omap_dss_device *dssdev)
437 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
438 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
442 EXPORT_SYMBOL(dsi_bus_unlock);
444 static bool dsi_bus_is_locked(struct platform_device *dsidev)
446 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
448 return dsi->bus_lock.count == 0;
451 static void dsi_completion_handler(void *data, u32 mask)
453 complete((struct completion *)data);
456 static inline int wait_for_bit_change(struct platform_device *dsidev,
457 const struct dsi_reg idx, int bitnum, int value)
459 unsigned long timeout;
463 /* first busyloop to see if the bit changes right away */
466 if (REG_GET(dsidev, idx, bitnum, bitnum) == value)
470 /* then loop for 500ms, sleeping for 1ms in between */
471 timeout = jiffies + msecs_to_jiffies(500);
472 while (time_before(jiffies, timeout)) {
473 if (REG_GET(dsidev, idx, bitnum, bitnum) == value)
476 wait = ns_to_ktime(1000 * 1000);
477 set_current_state(TASK_UNINTERRUPTIBLE);
478 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
484 u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
487 case OMAP_DSS_DSI_FMT_RGB888:
488 case OMAP_DSS_DSI_FMT_RGB666:
490 case OMAP_DSS_DSI_FMT_RGB666_PACKED:
492 case OMAP_DSS_DSI_FMT_RGB565:
501 static void dsi_perf_mark_setup(struct platform_device *dsidev)
503 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
504 dsi->perf_setup_time = ktime_get();
507 static void dsi_perf_mark_start(struct platform_device *dsidev)
509 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
510 dsi->perf_start_time = ktime_get();
513 static void dsi_perf_show(struct platform_device *dsidev, const char *name)
515 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
516 ktime_t t, setup_time, trans_time;
518 u32 setup_us, trans_us, total_us;
525 setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time);
526 setup_us = (u32)ktime_to_us(setup_time);
530 trans_time = ktime_sub(t, dsi->perf_start_time);
531 trans_us = (u32)ktime_to_us(trans_time);
535 total_us = setup_us + trans_us;
537 total_bytes = dsi->update_bytes;
539 printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), "
540 "%u bytes, %u kbytes/sec\n",
545 1000*1000 / total_us,
547 total_bytes * 1000 / total_us);
550 static inline void dsi_perf_mark_setup(struct platform_device *dsidev)
554 static inline void dsi_perf_mark_start(struct platform_device *dsidev)
558 static inline void dsi_perf_show(struct platform_device *dsidev,
564 static int verbose_irq;
566 static void print_irq_status(u32 status)
571 if (!verbose_irq && (status & ~DSI_IRQ_CHANNEL_MASK) == 0)
574 #define PIS(x) (status & DSI_IRQ_##x) ? (#x " ") : ""
576 pr_debug("DSI IRQ: 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
578 verbose_irq ? PIS(VC0) : "",
579 verbose_irq ? PIS(VC1) : "",
580 verbose_irq ? PIS(VC2) : "",
581 verbose_irq ? PIS(VC3) : "",
598 static void print_irq_status_vc(int channel, u32 status)
603 if (!verbose_irq && (status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
606 #define PIS(x) (status & DSI_VC_IRQ_##x) ? (#x " ") : ""
608 pr_debug("DSI VC(%d) IRQ 0x%x: %s%s%s%s%s%s%s%s%s\n",
614 verbose_irq ? PIS(PACKET_SENT) : "",
619 PIS(PP_BUSY_CHANGE));
623 static void print_irq_status_cio(u32 status)
628 #define PIS(x) (status & DSI_CIO_IRQ_##x) ? (#x " ") : ""
630 pr_debug("DSI CIO IRQ 0x%x: %s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n",
644 PIS(ERRCONTENTIONLP0_1),
645 PIS(ERRCONTENTIONLP1_1),
646 PIS(ERRCONTENTIONLP0_2),
647 PIS(ERRCONTENTIONLP1_2),
648 PIS(ERRCONTENTIONLP0_3),
649 PIS(ERRCONTENTIONLP1_3),
650 PIS(ULPSACTIVENOT_ALL0),
651 PIS(ULPSACTIVENOT_ALL1));
655 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
656 static void dsi_collect_irq_stats(struct platform_device *dsidev, u32 irqstatus,
657 u32 *vcstatus, u32 ciostatus)
659 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
662 spin_lock(&dsi->irq_stats_lock);
664 dsi->irq_stats.irq_count++;
665 dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs);
667 for (i = 0; i < 4; ++i)
668 dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]);
670 dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs);
672 spin_unlock(&dsi->irq_stats_lock);
675 #define dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus)
678 static int debug_irq;
680 static void dsi_handle_irq_errors(struct platform_device *dsidev, u32 irqstatus,
681 u32 *vcstatus, u32 ciostatus)
683 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
686 if (irqstatus & DSI_IRQ_ERROR_MASK) {
687 DSSERR("DSI error, irqstatus %x\n", irqstatus);
688 print_irq_status(irqstatus);
689 spin_lock(&dsi->errors_lock);
690 dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK;
691 spin_unlock(&dsi->errors_lock);
692 } else if (debug_irq) {
693 print_irq_status(irqstatus);
696 for (i = 0; i < 4; ++i) {
697 if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) {
698 DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
700 print_irq_status_vc(i, vcstatus[i]);
701 } else if (debug_irq) {
702 print_irq_status_vc(i, vcstatus[i]);
706 if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) {
707 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
708 print_irq_status_cio(ciostatus);
709 } else if (debug_irq) {
710 print_irq_status_cio(ciostatus);
714 static void dsi_call_isrs(struct dsi_isr_data *isr_array,
715 unsigned isr_array_size, u32 irqstatus)
717 struct dsi_isr_data *isr_data;
720 for (i = 0; i < isr_array_size; i++) {
721 isr_data = &isr_array[i];
722 if (isr_data->isr && isr_data->mask & irqstatus)
723 isr_data->isr(isr_data->arg, irqstatus);
727 static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables,
728 u32 irqstatus, u32 *vcstatus, u32 ciostatus)
732 dsi_call_isrs(isr_tables->isr_table,
733 ARRAY_SIZE(isr_tables->isr_table),
736 for (i = 0; i < 4; ++i) {
737 if (vcstatus[i] == 0)
739 dsi_call_isrs(isr_tables->isr_table_vc[i],
740 ARRAY_SIZE(isr_tables->isr_table_vc[i]),
745 dsi_call_isrs(isr_tables->isr_table_cio,
746 ARRAY_SIZE(isr_tables->isr_table_cio),
750 static irqreturn_t omap_dsi_irq_handler(int irq, void *arg)
752 struct platform_device *dsidev;
753 struct dsi_data *dsi;
754 u32 irqstatus, vcstatus[4], ciostatus;
757 dsidev = (struct platform_device *) arg;
758 dsi = dsi_get_dsidrv_data(dsidev);
760 spin_lock(&dsi->irq_lock);
762 irqstatus = dsi_read_reg(dsidev, DSI_IRQSTATUS);
764 /* IRQ is not for us */
766 spin_unlock(&dsi->irq_lock);
770 dsi_write_reg(dsidev, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
771 /* flush posted write */
772 dsi_read_reg(dsidev, DSI_IRQSTATUS);
774 for (i = 0; i < 4; ++i) {
775 if ((irqstatus & (1 << i)) == 0) {
780 vcstatus[i] = dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
782 dsi_write_reg(dsidev, DSI_VC_IRQSTATUS(i), vcstatus[i]);
783 /* flush posted write */
784 dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
787 if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
788 ciostatus = dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
790 dsi_write_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
791 /* flush posted write */
792 dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
797 #ifdef DSI_CATCH_MISSING_TE
798 if (irqstatus & DSI_IRQ_TE_TRIGGER)
799 del_timer(&dsi->te_timer);
802 /* make a copy and unlock, so that isrs can unregister
804 memcpy(&dsi->isr_tables_copy, &dsi->isr_tables,
805 sizeof(dsi->isr_tables));
807 spin_unlock(&dsi->irq_lock);
809 dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus);
811 dsi_handle_irq_errors(dsidev, irqstatus, vcstatus, ciostatus);
813 dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus);
818 /* dsi->irq_lock has to be locked by the caller */
819 static void _omap_dsi_configure_irqs(struct platform_device *dsidev,
820 struct dsi_isr_data *isr_array,
821 unsigned isr_array_size, u32 default_mask,
822 const struct dsi_reg enable_reg,
823 const struct dsi_reg status_reg)
825 struct dsi_isr_data *isr_data;
832 for (i = 0; i < isr_array_size; i++) {
833 isr_data = &isr_array[i];
835 if (isr_data->isr == NULL)
838 mask |= isr_data->mask;
841 old_mask = dsi_read_reg(dsidev, enable_reg);
842 /* clear the irqstatus for newly enabled irqs */
843 dsi_write_reg(dsidev, status_reg, (mask ^ old_mask) & mask);
844 dsi_write_reg(dsidev, enable_reg, mask);
846 /* flush posted writes */
847 dsi_read_reg(dsidev, enable_reg);
848 dsi_read_reg(dsidev, status_reg);
851 /* dsi->irq_lock has to be locked by the caller */
852 static void _omap_dsi_set_irqs(struct platform_device *dsidev)
854 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
855 u32 mask = DSI_IRQ_ERROR_MASK;
856 #ifdef DSI_CATCH_MISSING_TE
857 mask |= DSI_IRQ_TE_TRIGGER;
859 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table,
860 ARRAY_SIZE(dsi->isr_tables.isr_table), mask,
861 DSI_IRQENABLE, DSI_IRQSTATUS);
864 /* dsi->irq_lock has to be locked by the caller */
865 static void _omap_dsi_set_irqs_vc(struct platform_device *dsidev, int vc)
867 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
869 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_vc[vc],
870 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]),
871 DSI_VC_IRQ_ERROR_MASK,
872 DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc));
875 /* dsi->irq_lock has to be locked by the caller */
876 static void _omap_dsi_set_irqs_cio(struct platform_device *dsidev)
878 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
880 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_cio,
881 ARRAY_SIZE(dsi->isr_tables.isr_table_cio),
882 DSI_CIO_IRQ_ERROR_MASK,
883 DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS);
886 static void _dsi_initialize_irq(struct platform_device *dsidev)
888 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
892 spin_lock_irqsave(&dsi->irq_lock, flags);
894 memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables));
896 _omap_dsi_set_irqs(dsidev);
897 for (vc = 0; vc < 4; ++vc)
898 _omap_dsi_set_irqs_vc(dsidev, vc);
899 _omap_dsi_set_irqs_cio(dsidev);
901 spin_unlock_irqrestore(&dsi->irq_lock, flags);
904 static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
905 struct dsi_isr_data *isr_array, unsigned isr_array_size)
907 struct dsi_isr_data *isr_data;
913 /* check for duplicate entry and find a free slot */
915 for (i = 0; i < isr_array_size; i++) {
916 isr_data = &isr_array[i];
918 if (isr_data->isr == isr && isr_data->arg == arg &&
919 isr_data->mask == mask) {
923 if (isr_data->isr == NULL && free_idx == -1)
930 isr_data = &isr_array[free_idx];
933 isr_data->mask = mask;
938 static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
939 struct dsi_isr_data *isr_array, unsigned isr_array_size)
941 struct dsi_isr_data *isr_data;
944 for (i = 0; i < isr_array_size; i++) {
945 isr_data = &isr_array[i];
946 if (isr_data->isr != isr || isr_data->arg != arg ||
947 isr_data->mask != mask)
950 isr_data->isr = NULL;
951 isr_data->arg = NULL;
960 static int dsi_register_isr(struct platform_device *dsidev, omap_dsi_isr_t isr,
963 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
967 spin_lock_irqsave(&dsi->irq_lock, flags);
969 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table,
970 ARRAY_SIZE(dsi->isr_tables.isr_table));
973 _omap_dsi_set_irqs(dsidev);
975 spin_unlock_irqrestore(&dsi->irq_lock, flags);
980 static int dsi_unregister_isr(struct platform_device *dsidev,
981 omap_dsi_isr_t isr, void *arg, u32 mask)
983 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
987 spin_lock_irqsave(&dsi->irq_lock, flags);
989 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table,
990 ARRAY_SIZE(dsi->isr_tables.isr_table));
993 _omap_dsi_set_irqs(dsidev);
995 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1000 static int dsi_register_isr_vc(struct platform_device *dsidev, int channel,
1001 omap_dsi_isr_t isr, void *arg, u32 mask)
1003 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1004 unsigned long flags;
1007 spin_lock_irqsave(&dsi->irq_lock, flags);
1009 r = _dsi_register_isr(isr, arg, mask,
1010 dsi->isr_tables.isr_table_vc[channel],
1011 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
1014 _omap_dsi_set_irqs_vc(dsidev, channel);
1016 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1021 static int dsi_unregister_isr_vc(struct platform_device *dsidev, int channel,
1022 omap_dsi_isr_t isr, void *arg, u32 mask)
1024 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1025 unsigned long flags;
1028 spin_lock_irqsave(&dsi->irq_lock, flags);
1030 r = _dsi_unregister_isr(isr, arg, mask,
1031 dsi->isr_tables.isr_table_vc[channel],
1032 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
1035 _omap_dsi_set_irqs_vc(dsidev, channel);
1037 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1042 static int dsi_register_isr_cio(struct platform_device *dsidev,
1043 omap_dsi_isr_t isr, void *arg, u32 mask)
1045 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1046 unsigned long flags;
1049 spin_lock_irqsave(&dsi->irq_lock, flags);
1051 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1052 ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1055 _omap_dsi_set_irqs_cio(dsidev);
1057 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1062 static int dsi_unregister_isr_cio(struct platform_device *dsidev,
1063 omap_dsi_isr_t isr, void *arg, u32 mask)
1065 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1066 unsigned long flags;
1069 spin_lock_irqsave(&dsi->irq_lock, flags);
1071 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1072 ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1075 _omap_dsi_set_irqs_cio(dsidev);
1077 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1082 static u32 dsi_get_errors(struct platform_device *dsidev)
1084 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1085 unsigned long flags;
1087 spin_lock_irqsave(&dsi->errors_lock, flags);
1090 spin_unlock_irqrestore(&dsi->errors_lock, flags);
1094 int dsi_runtime_get(struct platform_device *dsidev)
1097 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1099 DSSDBG("dsi_runtime_get\n");
1101 r = pm_runtime_get_sync(&dsi->pdev->dev);
1103 return r < 0 ? r : 0;
1106 void dsi_runtime_put(struct platform_device *dsidev)
1108 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1111 DSSDBG("dsi_runtime_put\n");
1113 r = pm_runtime_put_sync(&dsi->pdev->dev);
1114 WARN_ON(r < 0 && r != -ENOSYS);
1117 /* source clock for DSI PLL. this could also be PCLKFREE */
1118 static inline void dsi_enable_pll_clock(struct platform_device *dsidev,
1121 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1124 clk_prepare_enable(dsi->sys_clk);
1126 clk_disable_unprepare(dsi->sys_clk);
1128 if (enable && dsi->pll_locked) {
1129 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1)
1130 DSSERR("cannot lock PLL when enabling clocks\n");
1134 static void _dsi_print_reset_status(struct platform_device *dsidev)
1139 /* A dummy read using the SCP interface to any DSIPHY register is
1140 * required after DSIPHY reset to complete the reset of the DSI complex
1142 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
1144 if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) {
1154 #define DSI_FLD_GET(fld, start, end)\
1155 FLD_GET(dsi_read_reg(dsidev, DSI_##fld), start, end)
1157 pr_debug("DSI resets: PLL (%d) CIO (%d) PHY (%x%x%x, %d, %d, %d)\n",
1158 DSI_FLD_GET(PLL_STATUS, 0, 0),
1159 DSI_FLD_GET(COMPLEXIO_CFG1, 29, 29),
1160 DSI_FLD_GET(DSIPHY_CFG5, b0, b0),
1161 DSI_FLD_GET(DSIPHY_CFG5, b1, b1),
1162 DSI_FLD_GET(DSIPHY_CFG5, b2, b2),
1163 DSI_FLD_GET(DSIPHY_CFG5, 29, 29),
1164 DSI_FLD_GET(DSIPHY_CFG5, 30, 30),
1165 DSI_FLD_GET(DSIPHY_CFG5, 31, 31));
1170 static inline int dsi_if_enable(struct platform_device *dsidev, bool enable)
1172 DSSDBG("dsi_if_enable(%d)\n", enable);
1174 enable = enable ? 1 : 0;
1175 REG_FLD_MOD(dsidev, DSI_CTRL, enable, 0, 0); /* IF_EN */
1177 if (wait_for_bit_change(dsidev, DSI_CTRL, 0, enable) != enable) {
1178 DSSERR("Failed to set dsi_if_enable to %d\n", enable);
1185 unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev)
1187 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1189 return dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk;
1192 static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct platform_device *dsidev)
1194 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1196 return dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk;
1199 static unsigned long dsi_get_txbyteclkhs(struct platform_device *dsidev)
1201 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1203 return dsi->current_cinfo.clkin4ddr / 16;
1206 static unsigned long dsi_fclk_rate(struct platform_device *dsidev)
1209 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1211 if (dss_get_dsi_clk_source(dsi->module_id) == OMAP_DSS_CLK_SRC_FCK) {
1212 /* DSI FCLK source is DSS_CLK_FCK */
1213 r = clk_get_rate(dsi->dss_clk);
1215 /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */
1216 r = dsi_get_pll_hsdiv_dsi_rate(dsidev);
1222 static int dsi_lp_clock_calc(struct dsi_clock_info *cinfo,
1223 unsigned long lp_clk_min, unsigned long lp_clk_max)
1225 unsigned long dsi_fclk = cinfo->dsi_pll_hsdiv_dsi_clk;
1226 unsigned lp_clk_div;
1227 unsigned long lp_clk;
1229 lp_clk_div = DIV_ROUND_UP(dsi_fclk, lp_clk_max * 2);
1230 lp_clk = dsi_fclk / 2 / lp_clk_div;
1232 if (lp_clk < lp_clk_min || lp_clk > lp_clk_max)
1235 cinfo->lp_clk_div = lp_clk_div;
1236 cinfo->lp_clk = lp_clk;
1241 static int dsi_set_lp_clk_divisor(struct platform_device *dsidev)
1243 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1244 unsigned long dsi_fclk;
1245 unsigned lp_clk_div;
1246 unsigned long lp_clk;
1248 lp_clk_div = dsi->user_dsi_cinfo.lp_clk_div;
1250 if (lp_clk_div == 0 || lp_clk_div > dsi->lpdiv_max)
1253 dsi_fclk = dsi_fclk_rate(dsidev);
1255 lp_clk = dsi_fclk / 2 / lp_clk_div;
1257 DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk);
1258 dsi->current_cinfo.lp_clk = lp_clk;
1259 dsi->current_cinfo.lp_clk_div = lp_clk_div;
1261 /* LP_CLK_DIVISOR */
1262 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, lp_clk_div, 12, 0);
1264 /* LP_RX_SYNCHRO_ENABLE */
1265 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21);
1270 static void dsi_enable_scp_clk(struct platform_device *dsidev)
1272 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1274 if (dsi->scp_clk_refcount++ == 0)
1275 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */
1278 static void dsi_disable_scp_clk(struct platform_device *dsidev)
1280 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1282 WARN_ON(dsi->scp_clk_refcount == 0);
1283 if (--dsi->scp_clk_refcount == 0)
1284 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */
1287 enum dsi_pll_power_state {
1288 DSI_PLL_POWER_OFF = 0x0,
1289 DSI_PLL_POWER_ON_HSCLK = 0x1,
1290 DSI_PLL_POWER_ON_ALL = 0x2,
1291 DSI_PLL_POWER_ON_DIV = 0x3,
1294 static int dsi_pll_power(struct platform_device *dsidev,
1295 enum dsi_pll_power_state state)
1299 /* DSI-PLL power command 0x3 is not working */
1300 if (dss_has_feature(FEAT_DSI_PLL_PWR_BUG) &&
1301 state == DSI_PLL_POWER_ON_DIV)
1302 state = DSI_PLL_POWER_ON_ALL;
1305 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, state, 31, 30);
1307 /* PLL_PWR_STATUS */
1308 while (FLD_GET(dsi_read_reg(dsidev, DSI_CLK_CTRL), 29, 28) != state) {
1310 DSSERR("Failed to set DSI PLL power mode to %d\n",
1320 unsigned long dsi_get_pll_clkin(struct platform_device *dsidev)
1322 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1323 return clk_get_rate(dsi->sys_clk);
1326 bool dsi_hsdiv_calc(struct platform_device *dsidev, unsigned long pll,
1327 unsigned long out_min, dsi_hsdiv_calc_func func, void *data)
1329 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1330 int regm, regm_start, regm_stop;
1331 unsigned long out_max;
1334 out_min = out_min ? out_min : 1;
1335 out_max = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
1337 regm_start = max(DIV_ROUND_UP(pll, out_max), 1ul);
1338 regm_stop = min(pll / out_min, dsi->regm_dispc_max);
1340 for (regm = regm_start; regm <= regm_stop; ++regm) {
1343 if (func(regm, out, data))
1350 bool dsi_pll_calc(struct platform_device *dsidev, unsigned long clkin,
1351 unsigned long pll_min, unsigned long pll_max,
1352 dsi_pll_calc_func func, void *data)
1354 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1355 int regn, regn_start, regn_stop;
1356 int regm, regm_start, regm_stop;
1357 unsigned long fint, pll;
1358 const unsigned long pll_hw_max = 1800000000;
1359 unsigned long fint_hw_min, fint_hw_max;
1361 fint_hw_min = dsi->fint_min;
1362 fint_hw_max = dsi->fint_max;
1364 regn_start = max(DIV_ROUND_UP(clkin, fint_hw_max), 1ul);
1365 regn_stop = min(clkin / fint_hw_min, dsi->regn_max);
1367 pll_max = pll_max ? pll_max : ULONG_MAX;
1369 for (regn = regn_start; regn <= regn_stop; ++regn) {
1370 fint = clkin / regn;
1372 regm_start = max(DIV_ROUND_UP(DIV_ROUND_UP(pll_min, fint), 2),
1374 regm_stop = min3(pll_max / fint / 2,
1375 pll_hw_max / fint / 2,
1378 for (regm = regm_start; regm <= regm_stop; ++regm) {
1379 pll = 2 * regm * fint;
1381 if (func(regn, regm, fint, pll, data))
1389 /* calculate clock rates using dividers in cinfo */
1390 static int dsi_calc_clock_rates(struct platform_device *dsidev,
1391 struct dsi_clock_info *cinfo)
1393 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1395 if (cinfo->regn == 0 || cinfo->regn > dsi->regn_max)
1398 if (cinfo->regm == 0 || cinfo->regm > dsi->regm_max)
1401 if (cinfo->regm_dispc > dsi->regm_dispc_max)
1404 if (cinfo->regm_dsi > dsi->regm_dsi_max)
1407 cinfo->clkin = clk_get_rate(dsi->sys_clk);
1408 cinfo->fint = cinfo->clkin / cinfo->regn;
1410 if (cinfo->fint > dsi->fint_max || cinfo->fint < dsi->fint_min)
1413 cinfo->clkin4ddr = 2 * cinfo->regm * cinfo->fint;
1415 if (cinfo->clkin4ddr > 1800 * 1000 * 1000)
1418 if (cinfo->regm_dispc > 0)
1419 cinfo->dsi_pll_hsdiv_dispc_clk =
1420 cinfo->clkin4ddr / cinfo->regm_dispc;
1422 cinfo->dsi_pll_hsdiv_dispc_clk = 0;
1424 if (cinfo->regm_dsi > 0)
1425 cinfo->dsi_pll_hsdiv_dsi_clk =
1426 cinfo->clkin4ddr / cinfo->regm_dsi;
1428 cinfo->dsi_pll_hsdiv_dsi_clk = 0;
1433 static void dsi_pll_calc_dsi_fck(struct dsi_clock_info *cinfo)
1435 unsigned long max_dsi_fck;
1437 max_dsi_fck = dss_feat_get_param_max(FEAT_PARAM_DSI_FCK);
1439 cinfo->regm_dsi = DIV_ROUND_UP(cinfo->clkin4ddr, max_dsi_fck);
1440 cinfo->dsi_pll_hsdiv_dsi_clk = cinfo->clkin4ddr / cinfo->regm_dsi;
1443 int dsi_pll_set_clock_div(struct platform_device *dsidev,
1444 struct dsi_clock_info *cinfo)
1446 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1450 u8 regn_start, regn_end, regm_start, regm_end;
1451 u8 regm_dispc_start, regm_dispc_end, regm_dsi_start, regm_dsi_end;
1453 DSSDBG("DSI PLL clock config starts");
1455 dsi->current_cinfo.clkin = cinfo->clkin;
1456 dsi->current_cinfo.fint = cinfo->fint;
1457 dsi->current_cinfo.clkin4ddr = cinfo->clkin4ddr;
1458 dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk =
1459 cinfo->dsi_pll_hsdiv_dispc_clk;
1460 dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk =
1461 cinfo->dsi_pll_hsdiv_dsi_clk;
1463 dsi->current_cinfo.regn = cinfo->regn;
1464 dsi->current_cinfo.regm = cinfo->regm;
1465 dsi->current_cinfo.regm_dispc = cinfo->regm_dispc;
1466 dsi->current_cinfo.regm_dsi = cinfo->regm_dsi;
1468 DSSDBG("DSI Fint %ld\n", cinfo->fint);
1470 DSSDBG("clkin rate %ld\n", cinfo->clkin);
1472 /* DSIPHY == CLKIN4DDR */
1473 DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu = %lu\n",
1479 DSSDBG("Data rate on 1 DSI lane %ld Mbps\n",
1480 cinfo->clkin4ddr / 1000 / 1000 / 2);
1482 DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4);
1484 DSSDBG("regm_dispc = %d, %s (%s) = %lu\n", cinfo->regm_dispc,
1485 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
1486 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
1487 cinfo->dsi_pll_hsdiv_dispc_clk);
1488 DSSDBG("regm_dsi = %d, %s (%s) = %lu\n", cinfo->regm_dsi,
1489 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
1490 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
1491 cinfo->dsi_pll_hsdiv_dsi_clk);
1493 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGN, ®n_start, ®n_end);
1494 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM, ®m_start, ®m_end);
1495 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DISPC, ®m_dispc_start,
1497 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DSI, ®m_dsi_start,
1500 /* DSI_PLL_AUTOMODE = manual */
1501 REG_FLD_MOD(dsidev, DSI_PLL_CONTROL, 0, 0, 0);
1503 l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION1);
1504 l = FLD_MOD(l, 1, 0, 0); /* DSI_PLL_STOPMODE */
1506 l = FLD_MOD(l, cinfo->regn - 1, regn_start, regn_end);
1508 l = FLD_MOD(l, cinfo->regm, regm_start, regm_end);
1510 l = FLD_MOD(l, cinfo->regm_dispc > 0 ? cinfo->regm_dispc - 1 : 0,
1511 regm_dispc_start, regm_dispc_end);
1512 /* DSIPROTO_CLOCK_DIV */
1513 l = FLD_MOD(l, cinfo->regm_dsi > 0 ? cinfo->regm_dsi - 1 : 0,
1514 regm_dsi_start, regm_dsi_end);
1515 dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION1, l);
1517 BUG_ON(cinfo->fint < dsi->fint_min || cinfo->fint > dsi->fint_max);
1519 l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2);
1521 if (dss_has_feature(FEAT_DSI_PLL_FREQSEL)) {
1522 f = cinfo->fint < 1000000 ? 0x3 :
1523 cinfo->fint < 1250000 ? 0x4 :
1524 cinfo->fint < 1500000 ? 0x5 :
1525 cinfo->fint < 1750000 ? 0x6 :
1528 l = FLD_MOD(l, f, 4, 1); /* DSI_PLL_FREQSEL */
1529 } else if (dss_has_feature(FEAT_DSI_PLL_SELFREQDCO)) {
1530 f = cinfo->clkin4ddr < 1000000000 ? 0x2 : 0x4;
1532 l = FLD_MOD(l, f, 4, 1); /* PLL_SELFREQDCO */
1535 l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
1536 l = FLD_MOD(l, 0, 14, 14); /* DSIPHY_CLKINEN */
1537 l = FLD_MOD(l, 1, 20, 20); /* DSI_HSDIVBYPASS */
1538 if (dss_has_feature(FEAT_DSI_PLL_REFSEL))
1539 l = FLD_MOD(l, 3, 22, 21); /* REF_SYSCLK = sysclk */
1540 dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l);
1542 REG_FLD_MOD(dsidev, DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */
1544 if (wait_for_bit_change(dsidev, DSI_PLL_GO, 0, 0) != 0) {
1545 DSSERR("dsi pll go bit not going down.\n");
1550 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1) {
1551 DSSERR("cannot lock PLL\n");
1556 dsi->pll_locked = 1;
1558 l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2);
1559 l = FLD_MOD(l, 0, 0, 0); /* DSI_PLL_IDLE */
1560 l = FLD_MOD(l, 0, 5, 5); /* DSI_PLL_PLLLPMODE */
1561 l = FLD_MOD(l, 0, 6, 6); /* DSI_PLL_LOWCURRSTBY */
1562 l = FLD_MOD(l, 0, 7, 7); /* DSI_PLL_TIGHTPHASELOCK */
1563 l = FLD_MOD(l, 0, 8, 8); /* DSI_PLL_DRIFTGUARDEN */
1564 l = FLD_MOD(l, 0, 10, 9); /* DSI_PLL_LOCKSEL */
1565 l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
1566 l = FLD_MOD(l, 1, 14, 14); /* DSIPHY_CLKINEN */
1567 l = FLD_MOD(l, 0, 15, 15); /* DSI_BYPASSEN */
1568 l = FLD_MOD(l, 1, 16, 16); /* DSS_CLOCK_EN */
1569 l = FLD_MOD(l, 0, 17, 17); /* DSS_CLOCK_PWDN */
1570 l = FLD_MOD(l, 1, 18, 18); /* DSI_PROTO_CLOCK_EN */
1571 l = FLD_MOD(l, 0, 19, 19); /* DSI_PROTO_CLOCK_PWDN */
1572 l = FLD_MOD(l, 0, 20, 20); /* DSI_HSDIVBYPASS */
1573 dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l);
1575 DSSDBG("PLL config done\n");
1580 int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk,
1583 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1585 enum dsi_pll_power_state pwstate;
1587 DSSDBG("PLL init\n");
1590 * It seems that on many OMAPs we need to enable both to have a
1591 * functional HSDivider.
1593 enable_hsclk = enable_hsdiv = true;
1595 if (dsi->vdds_dsi_reg == NULL) {
1596 struct regulator *vdds_dsi;
1598 vdds_dsi = regulator_get(&dsi->pdev->dev, "vdds_dsi");
1600 /* DT HACK: try VCXIO to make omapdss work for o4 sdp/panda */
1601 if (IS_ERR(vdds_dsi))
1602 vdds_dsi = regulator_get(&dsi->pdev->dev, "VCXIO");
1604 if (IS_ERR(vdds_dsi)) {
1605 DSSERR("can't get VDDS_DSI regulator\n");
1606 return PTR_ERR(vdds_dsi);
1609 dsi->vdds_dsi_reg = vdds_dsi;
1612 dsi_enable_pll_clock(dsidev, 1);
1614 * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4.
1616 dsi_enable_scp_clk(dsidev);
1618 if (!dsi->vdds_dsi_enabled) {
1619 r = regulator_enable(dsi->vdds_dsi_reg);
1622 dsi->vdds_dsi_enabled = true;
1625 /* XXX PLL does not come out of reset without this... */
1626 dispc_pck_free_enable(1);
1628 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 0, 1) != 1) {
1629 DSSERR("PLL not coming out of reset.\n");
1631 dispc_pck_free_enable(0);
1635 /* XXX ... but if left on, we get problems when planes do not
1636 * fill the whole display. No idea about this */
1637 dispc_pck_free_enable(0);
1639 if (enable_hsclk && enable_hsdiv)
1640 pwstate = DSI_PLL_POWER_ON_ALL;
1641 else if (enable_hsclk)
1642 pwstate = DSI_PLL_POWER_ON_HSCLK;
1643 else if (enable_hsdiv)
1644 pwstate = DSI_PLL_POWER_ON_DIV;
1646 pwstate = DSI_PLL_POWER_OFF;
1648 r = dsi_pll_power(dsidev, pwstate);
1653 DSSDBG("PLL init done\n");
1657 if (dsi->vdds_dsi_enabled) {
1658 regulator_disable(dsi->vdds_dsi_reg);
1659 dsi->vdds_dsi_enabled = false;
1662 dsi_disable_scp_clk(dsidev);
1663 dsi_enable_pll_clock(dsidev, 0);
1667 void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes)
1669 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1671 dsi->pll_locked = 0;
1672 dsi_pll_power(dsidev, DSI_PLL_POWER_OFF);
1673 if (disconnect_lanes) {
1674 WARN_ON(!dsi->vdds_dsi_enabled);
1675 regulator_disable(dsi->vdds_dsi_reg);
1676 dsi->vdds_dsi_enabled = false;
1679 dsi_disable_scp_clk(dsidev);
1680 dsi_enable_pll_clock(dsidev, 0);
1682 DSSDBG("PLL uninit done\n");
1685 static void dsi_dump_dsidev_clocks(struct platform_device *dsidev,
1688 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1689 struct dsi_clock_info *cinfo = &dsi->current_cinfo;
1690 enum omap_dss_clk_source dispc_clk_src, dsi_clk_src;
1691 int dsi_module = dsi->module_id;
1693 dispc_clk_src = dss_get_dispc_clk_source();
1694 dsi_clk_src = dss_get_dsi_clk_source(dsi_module);
1696 if (dsi_runtime_get(dsidev))
1699 seq_printf(s, "- DSI%d PLL -\n", dsi_module + 1);
1701 seq_printf(s, "dsi pll clkin\t%lu\n", cinfo->clkin);
1703 seq_printf(s, "Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn);
1705 seq_printf(s, "CLKIN4DDR\t%-16luregm %u\n",
1706 cinfo->clkin4ddr, cinfo->regm);
1708 seq_printf(s, "DSI_PLL_HSDIV_DISPC (%s)\t%-16luregm_dispc %u\t(%s)\n",
1709 dss_feat_get_clk_source_name(dsi_module == 0 ?
1710 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC :
1711 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC),
1712 cinfo->dsi_pll_hsdiv_dispc_clk,
1714 dispc_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1717 seq_printf(s, "DSI_PLL_HSDIV_DSI (%s)\t%-16luregm_dsi %u\t(%s)\n",
1718 dss_feat_get_clk_source_name(dsi_module == 0 ?
1719 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI :
1720 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI),
1721 cinfo->dsi_pll_hsdiv_dsi_clk,
1723 dsi_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1726 seq_printf(s, "- DSI%d -\n", dsi_module + 1);
1728 seq_printf(s, "dsi fclk source = %s (%s)\n",
1729 dss_get_generic_clk_source_name(dsi_clk_src),
1730 dss_feat_get_clk_source_name(dsi_clk_src));
1732 seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsidev));
1734 seq_printf(s, "DDR_CLK\t\t%lu\n",
1735 cinfo->clkin4ddr / 4);
1737 seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsidev));
1739 seq_printf(s, "LP_CLK\t\t%lu\n", cinfo->lp_clk);
1741 dsi_runtime_put(dsidev);
1744 void dsi_dump_clocks(struct seq_file *s)
1746 struct platform_device *dsidev;
1749 for (i = 0; i < MAX_NUM_DSI; i++) {
1750 dsidev = dsi_get_dsidev_from_id(i);
1752 dsi_dump_dsidev_clocks(dsidev, s);
1756 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
1757 static void dsi_dump_dsidev_irqs(struct platform_device *dsidev,
1760 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1761 unsigned long flags;
1762 struct dsi_irq_stats stats;
1764 spin_lock_irqsave(&dsi->irq_stats_lock, flags);
1766 stats = dsi->irq_stats;
1767 memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats));
1768 dsi->irq_stats.last_reset = jiffies;
1770 spin_unlock_irqrestore(&dsi->irq_stats_lock, flags);
1772 seq_printf(s, "period %u ms\n",
1773 jiffies_to_msecs(jiffies - stats.last_reset));
1775 seq_printf(s, "irqs %d\n", stats.irq_count);
1777 seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]);
1779 seq_printf(s, "-- DSI%d interrupts --\n", dsi->module_id + 1);
1795 PIS(LDO_POWER_GOOD);
1800 seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
1801 stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
1802 stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
1803 stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
1804 stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);
1806 seq_printf(s, "-- VC interrupts --\n");
1815 PIS(PP_BUSY_CHANGE);
1819 seq_printf(s, "%-20s %10d\n", #x, \
1820 stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);
1822 seq_printf(s, "-- CIO interrupts --\n");
1835 PIS(ERRCONTENTIONLP0_1);
1836 PIS(ERRCONTENTIONLP1_1);
1837 PIS(ERRCONTENTIONLP0_2);
1838 PIS(ERRCONTENTIONLP1_2);
1839 PIS(ERRCONTENTIONLP0_3);
1840 PIS(ERRCONTENTIONLP1_3);
1841 PIS(ULPSACTIVENOT_ALL0);
1842 PIS(ULPSACTIVENOT_ALL1);
1846 static void dsi1_dump_irqs(struct seq_file *s)
1848 struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
1850 dsi_dump_dsidev_irqs(dsidev, s);
1853 static void dsi2_dump_irqs(struct seq_file *s)
1855 struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
1857 dsi_dump_dsidev_irqs(dsidev, s);
1861 static void dsi_dump_dsidev_regs(struct platform_device *dsidev,
1864 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsidev, r))
1866 if (dsi_runtime_get(dsidev))
1868 dsi_enable_scp_clk(dsidev);
1870 DUMPREG(DSI_REVISION);
1871 DUMPREG(DSI_SYSCONFIG);
1872 DUMPREG(DSI_SYSSTATUS);
1873 DUMPREG(DSI_IRQSTATUS);
1874 DUMPREG(DSI_IRQENABLE);
1876 DUMPREG(DSI_COMPLEXIO_CFG1);
1877 DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
1878 DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
1879 DUMPREG(DSI_CLK_CTRL);
1880 DUMPREG(DSI_TIMING1);
1881 DUMPREG(DSI_TIMING2);
1882 DUMPREG(DSI_VM_TIMING1);
1883 DUMPREG(DSI_VM_TIMING2);
1884 DUMPREG(DSI_VM_TIMING3);
1885 DUMPREG(DSI_CLK_TIMING);
1886 DUMPREG(DSI_TX_FIFO_VC_SIZE);
1887 DUMPREG(DSI_RX_FIFO_VC_SIZE);
1888 DUMPREG(DSI_COMPLEXIO_CFG2);
1889 DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
1890 DUMPREG(DSI_VM_TIMING4);
1891 DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
1892 DUMPREG(DSI_VM_TIMING5);
1893 DUMPREG(DSI_VM_TIMING6);
1894 DUMPREG(DSI_VM_TIMING7);
1895 DUMPREG(DSI_STOPCLK_TIMING);
1897 DUMPREG(DSI_VC_CTRL(0));
1898 DUMPREG(DSI_VC_TE(0));
1899 DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
1900 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
1901 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
1902 DUMPREG(DSI_VC_IRQSTATUS(0));
1903 DUMPREG(DSI_VC_IRQENABLE(0));
1905 DUMPREG(DSI_VC_CTRL(1));
1906 DUMPREG(DSI_VC_TE(1));
1907 DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
1908 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
1909 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
1910 DUMPREG(DSI_VC_IRQSTATUS(1));
1911 DUMPREG(DSI_VC_IRQENABLE(1));
1913 DUMPREG(DSI_VC_CTRL(2));
1914 DUMPREG(DSI_VC_TE(2));
1915 DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
1916 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
1917 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
1918 DUMPREG(DSI_VC_IRQSTATUS(2));
1919 DUMPREG(DSI_VC_IRQENABLE(2));
1921 DUMPREG(DSI_VC_CTRL(3));
1922 DUMPREG(DSI_VC_TE(3));
1923 DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
1924 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
1925 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
1926 DUMPREG(DSI_VC_IRQSTATUS(3));
1927 DUMPREG(DSI_VC_IRQENABLE(3));
1929 DUMPREG(DSI_DSIPHY_CFG0);
1930 DUMPREG(DSI_DSIPHY_CFG1);
1931 DUMPREG(DSI_DSIPHY_CFG2);
1932 DUMPREG(DSI_DSIPHY_CFG5);
1934 DUMPREG(DSI_PLL_CONTROL);
1935 DUMPREG(DSI_PLL_STATUS);
1936 DUMPREG(DSI_PLL_GO);
1937 DUMPREG(DSI_PLL_CONFIGURATION1);
1938 DUMPREG(DSI_PLL_CONFIGURATION2);
1940 dsi_disable_scp_clk(dsidev);
1941 dsi_runtime_put(dsidev);
1945 static void dsi1_dump_regs(struct seq_file *s)
1947 struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
1949 dsi_dump_dsidev_regs(dsidev, s);
1952 static void dsi2_dump_regs(struct seq_file *s)
1954 struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
1956 dsi_dump_dsidev_regs(dsidev, s);
1959 enum dsi_cio_power_state {
1960 DSI_COMPLEXIO_POWER_OFF = 0x0,
1961 DSI_COMPLEXIO_POWER_ON = 0x1,
1962 DSI_COMPLEXIO_POWER_ULPS = 0x2,
1965 static int dsi_cio_power(struct platform_device *dsidev,
1966 enum dsi_cio_power_state state)
1971 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG1, state, 28, 27);
1974 while (FLD_GET(dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1),
1977 DSSERR("failed to set complexio power state to "
1987 static unsigned dsi_get_line_buf_size(struct platform_device *dsidev)
1991 /* line buffer on OMAP3 is 1024 x 24bits */
1992 /* XXX: for some reason using full buffer size causes
1993 * considerable TX slowdown with update sizes that fill the
1995 if (!dss_has_feature(FEAT_DSI_GNQ))
1998 val = REG_GET(dsidev, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */
2002 return 512 * 3; /* 512x24 bits */
2004 return 682 * 3; /* 682x24 bits */
2006 return 853 * 3; /* 853x24 bits */
2008 return 1024 * 3; /* 1024x24 bits */
2010 return 1194 * 3; /* 1194x24 bits */
2012 return 1365 * 3; /* 1365x24 bits */
2014 return 1920 * 3; /* 1920x24 bits */
2021 static int dsi_set_lane_config(struct platform_device *dsidev)
2023 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2024 static const u8 offsets[] = { 0, 4, 8, 12, 16 };
2025 static const enum dsi_lane_function functions[] = {
2035 r = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1);
2037 for (i = 0; i < dsi->num_lanes_used; ++i) {
2038 unsigned offset = offsets[i];
2039 unsigned polarity, lane_number;
2042 for (t = 0; t < dsi->num_lanes_supported; ++t)
2043 if (dsi->lanes[t].function == functions[i])
2046 if (t == dsi->num_lanes_supported)
2050 polarity = dsi->lanes[t].polarity;
2052 r = FLD_MOD(r, lane_number + 1, offset + 2, offset);
2053 r = FLD_MOD(r, polarity, offset + 3, offset + 3);
2056 /* clear the unused lanes */
2057 for (; i < dsi->num_lanes_supported; ++i) {
2058 unsigned offset = offsets[i];
2060 r = FLD_MOD(r, 0, offset + 2, offset);
2061 r = FLD_MOD(r, 0, offset + 3, offset + 3);
2064 dsi_write_reg(dsidev, DSI_COMPLEXIO_CFG1, r);
2069 static inline unsigned ns2ddr(struct platform_device *dsidev, unsigned ns)
2071 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2073 /* convert time in ns to ddr ticks, rounding up */
2074 unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4;
2075 return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000;
2078 static inline unsigned ddr2ns(struct platform_device *dsidev, unsigned ddr)
2080 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2082 unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4;
2083 return ddr * 1000 * 1000 / (ddr_clk / 1000);
2086 static void dsi_cio_timings(struct platform_device *dsidev)
2089 u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
2090 u32 tlpx_half, tclk_trail, tclk_zero;
2093 /* calculate timings */
2095 /* 1 * DDR_CLK = 2 * UI */
2097 /* min 40ns + 4*UI max 85ns + 6*UI */
2098 ths_prepare = ns2ddr(dsidev, 70) + 2;
2100 /* min 145ns + 10*UI */
2101 ths_prepare_ths_zero = ns2ddr(dsidev, 175) + 2;
2103 /* min max(8*UI, 60ns+4*UI) */
2104 ths_trail = ns2ddr(dsidev, 60) + 5;
2107 ths_exit = ns2ddr(dsidev, 145);
2110 tlpx_half = ns2ddr(dsidev, 25);
2113 tclk_trail = ns2ddr(dsidev, 60) + 2;
2115 /* min 38ns, max 95ns */
2116 tclk_prepare = ns2ddr(dsidev, 65);
2118 /* min tclk-prepare + tclk-zero = 300ns */
2119 tclk_zero = ns2ddr(dsidev, 260);
2121 DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
2122 ths_prepare, ddr2ns(dsidev, ths_prepare),
2123 ths_prepare_ths_zero, ddr2ns(dsidev, ths_prepare_ths_zero));
2124 DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
2125 ths_trail, ddr2ns(dsidev, ths_trail),
2126 ths_exit, ddr2ns(dsidev, ths_exit));
2128 DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
2129 "tclk_zero %u (%uns)\n",
2130 tlpx_half, ddr2ns(dsidev, tlpx_half),
2131 tclk_trail, ddr2ns(dsidev, tclk_trail),
2132 tclk_zero, ddr2ns(dsidev, tclk_zero));
2133 DSSDBG("tclk_prepare %u (%uns)\n",
2134 tclk_prepare, ddr2ns(dsidev, tclk_prepare));
2136 /* program timings */
2138 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
2139 r = FLD_MOD(r, ths_prepare, 31, 24);
2140 r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
2141 r = FLD_MOD(r, ths_trail, 15, 8);
2142 r = FLD_MOD(r, ths_exit, 7, 0);
2143 dsi_write_reg(dsidev, DSI_DSIPHY_CFG0, r);
2145 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
2146 r = FLD_MOD(r, tlpx_half, 20, 16);
2147 r = FLD_MOD(r, tclk_trail, 15, 8);
2148 r = FLD_MOD(r, tclk_zero, 7, 0);
2150 if (dss_has_feature(FEAT_DSI_PHY_DCC)) {
2151 r = FLD_MOD(r, 0, 21, 21); /* DCCEN = disable */
2152 r = FLD_MOD(r, 1, 22, 22); /* CLKINP_DIVBY2EN = enable */
2153 r = FLD_MOD(r, 1, 23, 23); /* CLKINP_SEL = enable */
2156 dsi_write_reg(dsidev, DSI_DSIPHY_CFG1, r);
2158 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
2159 r = FLD_MOD(r, tclk_prepare, 7, 0);
2160 dsi_write_reg(dsidev, DSI_DSIPHY_CFG2, r);
2163 /* lane masks have lane 0 at lsb. mask_p for positive lines, n for negative */
2164 static void dsi_cio_enable_lane_override(struct platform_device *dsidev,
2165 unsigned mask_p, unsigned mask_n)
2167 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2170 u8 lptxscp_start = dsi->num_lanes_supported == 3 ? 22 : 26;
2174 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2175 unsigned p = dsi->lanes[i].polarity;
2177 if (mask_p & (1 << i))
2178 l |= 1 << (i * 2 + (p ? 0 : 1));
2180 if (mask_n & (1 << i))
2181 l |= 1 << (i * 2 + (p ? 1 : 0));
2185 * Bits in REGLPTXSCPDAT4TO0DXDY:
2193 /* Set the lane override configuration */
2195 /* REGLPTXSCPDAT4TO0DXDY */
2196 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, l, lptxscp_start, 17);
2198 /* Enable lane override */
2201 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 1, 27, 27);
2204 static void dsi_cio_disable_lane_override(struct platform_device *dsidev)
2206 /* Disable lane override */
2207 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */
2208 /* Reset the lane override configuration */
2209 /* REGLPTXSCPDAT4TO0DXDY */
2210 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 22, 17);
2213 static int dsi_cio_wait_tx_clk_esc_reset(struct platform_device *dsidev)
2215 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2217 bool in_use[DSI_MAX_NR_LANES];
2218 static const u8 offsets_old[] = { 28, 27, 26 };
2219 static const u8 offsets_new[] = { 24, 25, 26, 27, 28 };
2222 if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC))
2223 offsets = offsets_old;
2225 offsets = offsets_new;
2227 for (i = 0; i < dsi->num_lanes_supported; ++i)
2228 in_use[i] = dsi->lanes[i].function != DSI_LANE_UNUSED;
2235 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2238 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2239 if (!in_use[i] || (l & (1 << offsets[i])))
2243 if (ok == dsi->num_lanes_supported)
2247 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2248 if (!in_use[i] || (l & (1 << offsets[i])))
2251 DSSERR("CIO TXCLKESC%d domain not coming " \
2252 "out of reset\n", i);
2261 /* return bitmask of enabled lanes, lane0 being the lsb */
2262 static unsigned dsi_get_lane_mask(struct platform_device *dsidev)
2264 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2268 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2269 if (dsi->lanes[i].function != DSI_LANE_UNUSED)
2276 static int dsi_cio_init(struct platform_device *dsidev)
2278 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2282 DSSDBG("DSI CIO init starts");
2284 r = dss_dsi_enable_pads(dsi->module_id, dsi_get_lane_mask(dsidev));
2288 dsi_enable_scp_clk(dsidev);
2290 /* A dummy read using the SCP interface to any DSIPHY register is
2291 * required after DSIPHY reset to complete the reset of the DSI complex
2293 dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2295 if (wait_for_bit_change(dsidev, DSI_DSIPHY_CFG5, 30, 1) != 1) {
2296 DSSERR("CIO SCP Clock domain not coming out of reset.\n");
2298 goto err_scp_clk_dom;
2301 r = dsi_set_lane_config(dsidev);
2303 goto err_scp_clk_dom;
2305 /* set TX STOP MODE timer to maximum for this operation */
2306 l = dsi_read_reg(dsidev, DSI_TIMING1);
2307 l = FLD_MOD(l, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2308 l = FLD_MOD(l, 1, 14, 14); /* STOP_STATE_X16_IO */
2309 l = FLD_MOD(l, 1, 13, 13); /* STOP_STATE_X4_IO */
2310 l = FLD_MOD(l, 0x1fff, 12, 0); /* STOP_STATE_COUNTER_IO */
2311 dsi_write_reg(dsidev, DSI_TIMING1, l);
2313 if (dsi->ulps_enabled) {
2317 DSSDBG("manual ulps exit\n");
2319 /* ULPS is exited by Mark-1 state for 1ms, followed by
2320 * stop state. DSS HW cannot do this via the normal
2321 * ULPS exit sequence, as after reset the DSS HW thinks
2322 * that we are not in ULPS mode, and refuses to send the
2323 * sequence. So we need to send the ULPS exit sequence
2324 * manually by setting positive lines high and negative lines
2330 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2331 if (dsi->lanes[i].function == DSI_LANE_UNUSED)
2336 dsi_cio_enable_lane_override(dsidev, mask_p, 0);
2339 r = dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ON);
2343 if (wait_for_bit_change(dsidev, DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
2344 DSSERR("CIO PWR clock domain not coming out of reset.\n");
2346 goto err_cio_pwr_dom;
2349 dsi_if_enable(dsidev, true);
2350 dsi_if_enable(dsidev, false);
2351 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
2353 r = dsi_cio_wait_tx_clk_esc_reset(dsidev);
2355 goto err_tx_clk_esc_rst;
2357 if (dsi->ulps_enabled) {
2358 /* Keep Mark-1 state for 1ms (as per DSI spec) */
2359 ktime_t wait = ns_to_ktime(1000 * 1000);
2360 set_current_state(TASK_UNINTERRUPTIBLE);
2361 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
2363 /* Disable the override. The lanes should be set to Mark-11
2364 * state by the HW */
2365 dsi_cio_disable_lane_override(dsidev);
2368 /* FORCE_TX_STOP_MODE_IO */
2369 REG_FLD_MOD(dsidev, DSI_TIMING1, 0, 15, 15);
2371 dsi_cio_timings(dsidev);
2373 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
2374 /* DDR_CLK_ALWAYS_ON */
2375 REG_FLD_MOD(dsidev, DSI_CLK_CTRL,
2376 dsi->vm_timings.ddr_clk_always_on, 13, 13);
2379 dsi->ulps_enabled = false;
2381 DSSDBG("CIO init done\n");
2386 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */
2388 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2390 if (dsi->ulps_enabled)
2391 dsi_cio_disable_lane_override(dsidev);
2393 dsi_disable_scp_clk(dsidev);
2394 dss_dsi_disable_pads(dsi->module_id, dsi_get_lane_mask(dsidev));
2398 static void dsi_cio_uninit(struct platform_device *dsidev)
2400 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2402 /* DDR_CLK_ALWAYS_ON */
2403 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13);
2405 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2406 dsi_disable_scp_clk(dsidev);
2407 dss_dsi_disable_pads(dsi->module_id, dsi_get_lane_mask(dsidev));
2410 static void dsi_config_tx_fifo(struct platform_device *dsidev,
2411 enum fifo_size size1, enum fifo_size size2,
2412 enum fifo_size size3, enum fifo_size size4)
2414 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2419 dsi->vc[0].fifo_size = size1;
2420 dsi->vc[1].fifo_size = size2;
2421 dsi->vc[2].fifo_size = size3;
2422 dsi->vc[3].fifo_size = size4;
2424 for (i = 0; i < 4; i++) {
2426 int size = dsi->vc[i].fifo_size;
2428 if (add + size > 4) {
2429 DSSERR("Illegal FIFO configuration\n");
2434 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2436 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
2440 dsi_write_reg(dsidev, DSI_TX_FIFO_VC_SIZE, r);
2443 static void dsi_config_rx_fifo(struct platform_device *dsidev,
2444 enum fifo_size size1, enum fifo_size size2,
2445 enum fifo_size size3, enum fifo_size size4)
2447 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2452 dsi->vc[0].fifo_size = size1;
2453 dsi->vc[1].fifo_size = size2;
2454 dsi->vc[2].fifo_size = size3;
2455 dsi->vc[3].fifo_size = size4;
2457 for (i = 0; i < 4; i++) {
2459 int size = dsi->vc[i].fifo_size;
2461 if (add + size > 4) {
2462 DSSERR("Illegal FIFO configuration\n");
2467 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2469 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
2473 dsi_write_reg(dsidev, DSI_RX_FIFO_VC_SIZE, r);
2476 static int dsi_force_tx_stop_mode_io(struct platform_device *dsidev)
2480 r = dsi_read_reg(dsidev, DSI_TIMING1);
2481 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2482 dsi_write_reg(dsidev, DSI_TIMING1, r);
2484 if (wait_for_bit_change(dsidev, DSI_TIMING1, 15, 0) != 0) {
2485 DSSERR("TX_STOP bit not going down\n");
2492 static bool dsi_vc_is_enabled(struct platform_device *dsidev, int channel)
2494 return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0);
2497 static void dsi_packet_sent_handler_vp(void *data, u32 mask)
2499 struct dsi_packet_sent_handler_data *vp_data =
2500 (struct dsi_packet_sent_handler_data *) data;
2501 struct dsi_data *dsi = dsi_get_dsidrv_data(vp_data->dsidev);
2502 const int channel = dsi->update_channel;
2503 u8 bit = dsi->te_enabled ? 30 : 31;
2505 if (REG_GET(vp_data->dsidev, DSI_VC_TE(channel), bit, bit) == 0)
2506 complete(vp_data->completion);
2509 static int dsi_sync_vc_vp(struct platform_device *dsidev, int channel)
2511 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2512 DECLARE_COMPLETION_ONSTACK(completion);
2513 struct dsi_packet_sent_handler_data vp_data = { dsidev, &completion };
2517 bit = dsi->te_enabled ? 30 : 31;
2519 r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2520 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2524 /* Wait for completion only if TE_EN/TE_START is still set */
2525 if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit)) {
2526 if (wait_for_completion_timeout(&completion,
2527 msecs_to_jiffies(10)) == 0) {
2528 DSSERR("Failed to complete previous frame transfer\n");
2534 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2535 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2539 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2540 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2545 static void dsi_packet_sent_handler_l4(void *data, u32 mask)
2547 struct dsi_packet_sent_handler_data *l4_data =
2548 (struct dsi_packet_sent_handler_data *) data;
2549 struct dsi_data *dsi = dsi_get_dsidrv_data(l4_data->dsidev);
2550 const int channel = dsi->update_channel;
2552 if (REG_GET(l4_data->dsidev, DSI_VC_CTRL(channel), 5, 5) == 0)
2553 complete(l4_data->completion);
2556 static int dsi_sync_vc_l4(struct platform_device *dsidev, int channel)
2558 DECLARE_COMPLETION_ONSTACK(completion);
2559 struct dsi_packet_sent_handler_data l4_data = { dsidev, &completion };
2562 r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2563 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2567 /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */
2568 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) {
2569 if (wait_for_completion_timeout(&completion,
2570 msecs_to_jiffies(10)) == 0) {
2571 DSSERR("Failed to complete previous l4 transfer\n");
2577 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2578 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2582 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2583 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2588 static int dsi_sync_vc(struct platform_device *dsidev, int channel)
2590 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2592 WARN_ON(!dsi_bus_is_locked(dsidev));
2594 WARN_ON(in_interrupt());
2596 if (!dsi_vc_is_enabled(dsidev, channel))
2599 switch (dsi->vc[channel].source) {
2600 case DSI_VC_SOURCE_VP:
2601 return dsi_sync_vc_vp(dsidev, channel);
2602 case DSI_VC_SOURCE_L4:
2603 return dsi_sync_vc_l4(dsidev, channel);
2610 static int dsi_vc_enable(struct platform_device *dsidev, int channel,
2613 DSSDBG("dsi_vc_enable channel %d, enable %d\n",
2616 enable = enable ? 1 : 0;
2618 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 0, 0);
2620 if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel),
2621 0, enable) != enable) {
2622 DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
2629 static void dsi_vc_initial_config(struct platform_device *dsidev, int channel)
2631 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2634 DSSDBG("Initial config of virtual channel %d", channel);
2636 r = dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
2638 if (FLD_GET(r, 15, 15)) /* VC_BUSY */
2639 DSSERR("VC(%d) busy when trying to configure it!\n",
2642 r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
2643 r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */
2644 r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
2645 r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
2646 r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
2647 r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
2648 r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
2649 if (dss_has_feature(FEAT_DSI_VC_OCP_WIDTH))
2650 r = FLD_MOD(r, 3, 11, 10); /* OCP_WIDTH = 32 bit */
2652 r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
2653 r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
2655 dsi_write_reg(dsidev, DSI_VC_CTRL(channel), r);
2657 dsi->vc[channel].source = DSI_VC_SOURCE_L4;
2660 static int dsi_vc_config_source(struct platform_device *dsidev, int channel,
2661 enum dsi_vc_source source)
2663 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2665 if (dsi->vc[channel].source == source)
2668 DSSDBG("Source config of virtual channel %d", channel);
2670 dsi_sync_vc(dsidev, channel);
2672 dsi_vc_enable(dsidev, channel, 0);
2675 if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 15, 0) != 0) {
2676 DSSERR("vc(%d) busy when trying to config for VP\n", channel);
2680 /* SOURCE, 0 = L4, 1 = video port */
2681 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), source, 1, 1);
2683 /* DCS_CMD_ENABLE */
2684 if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
2685 bool enable = source == DSI_VC_SOURCE_VP;
2686 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 30, 30);
2689 dsi_vc_enable(dsidev, channel, 1);
2691 dsi->vc[channel].source = source;
2696 void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
2699 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2700 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2702 DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
2704 WARN_ON(!dsi_bus_is_locked(dsidev));
2706 dsi_vc_enable(dsidev, channel, 0);
2707 dsi_if_enable(dsidev, 0);
2709 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 9, 9);
2711 dsi_vc_enable(dsidev, channel, 1);
2712 dsi_if_enable(dsidev, 1);
2714 dsi_force_tx_stop_mode_io(dsidev);
2716 /* start the DDR clock by sending a NULL packet */
2717 if (dsi->vm_timings.ddr_clk_always_on && enable)
2718 dsi_vc_send_null(dssdev, channel);
2720 EXPORT_SYMBOL(omapdss_dsi_vc_enable_hs);
2722 static void dsi_vc_flush_long_data(struct platform_device *dsidev, int channel)
2724 while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2726 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2727 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
2731 (val >> 24) & 0xff);
2735 static void dsi_show_rx_ack_with_err(u16 err)
2737 DSSERR("\tACK with ERROR (%#x):\n", err);
2739 DSSERR("\t\tSoT Error\n");
2741 DSSERR("\t\tSoT Sync Error\n");
2743 DSSERR("\t\tEoT Sync Error\n");
2745 DSSERR("\t\tEscape Mode Entry Command Error\n");
2747 DSSERR("\t\tLP Transmit Sync Error\n");
2749 DSSERR("\t\tHS Receive Timeout Error\n");
2751 DSSERR("\t\tFalse Control Error\n");
2753 DSSERR("\t\t(reserved7)\n");
2755 DSSERR("\t\tECC Error, single-bit (corrected)\n");
2757 DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
2758 if (err & (1 << 10))
2759 DSSERR("\t\tChecksum Error\n");
2760 if (err & (1 << 11))
2761 DSSERR("\t\tData type not recognized\n");
2762 if (err & (1 << 12))
2763 DSSERR("\t\tInvalid VC ID\n");
2764 if (err & (1 << 13))
2765 DSSERR("\t\tInvalid Transmission Length\n");
2766 if (err & (1 << 14))
2767 DSSERR("\t\t(reserved14)\n");
2768 if (err & (1 << 15))
2769 DSSERR("\t\tDSI Protocol Violation\n");
2772 static u16 dsi_vc_flush_receive_data(struct platform_device *dsidev,
2775 /* RX_FIFO_NOT_EMPTY */
2776 while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2779 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2780 DSSERR("\trawval %#08x\n", val);
2781 dt = FLD_GET(val, 5, 0);
2782 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
2783 u16 err = FLD_GET(val, 23, 8);
2784 dsi_show_rx_ack_with_err(err);
2785 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE) {
2786 DSSERR("\tDCS short response, 1 byte: %#x\n",
2787 FLD_GET(val, 23, 8));
2788 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE) {
2789 DSSERR("\tDCS short response, 2 byte: %#x\n",
2790 FLD_GET(val, 23, 8));
2791 } else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) {
2792 DSSERR("\tDCS long response, len %d\n",
2793 FLD_GET(val, 23, 8));
2794 dsi_vc_flush_long_data(dsidev, channel);
2796 DSSERR("\tunknown datatype 0x%02x\n", dt);
2802 static int dsi_vc_send_bta(struct platform_device *dsidev, int channel)
2804 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2806 if (dsi->debug_write || dsi->debug_read)
2807 DSSDBG("dsi_vc_send_bta %d\n", channel);
2809 WARN_ON(!dsi_bus_is_locked(dsidev));
2811 /* RX_FIFO_NOT_EMPTY */
2812 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2813 DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
2814 dsi_vc_flush_receive_data(dsidev, channel);
2817 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
2819 /* flush posted write */
2820 dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
2825 int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel)
2827 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2828 DECLARE_COMPLETION_ONSTACK(completion);
2832 r = dsi_register_isr_vc(dsidev, channel, dsi_completion_handler,
2833 &completion, DSI_VC_IRQ_BTA);
2837 r = dsi_register_isr(dsidev, dsi_completion_handler, &completion,
2838 DSI_IRQ_ERROR_MASK);
2842 r = dsi_vc_send_bta(dsidev, channel);
2846 if (wait_for_completion_timeout(&completion,
2847 msecs_to_jiffies(500)) == 0) {
2848 DSSERR("Failed to receive BTA\n");
2853 err = dsi_get_errors(dsidev);
2855 DSSERR("Error while sending BTA: %x\n", err);
2860 dsi_unregister_isr(dsidev, dsi_completion_handler, &completion,
2861 DSI_IRQ_ERROR_MASK);
2863 dsi_unregister_isr_vc(dsidev, channel, dsi_completion_handler,
2864 &completion, DSI_VC_IRQ_BTA);
2868 EXPORT_SYMBOL(dsi_vc_send_bta_sync);
2870 static inline void dsi_vc_write_long_header(struct platform_device *dsidev,
2871 int channel, u8 data_type, u16 len, u8 ecc)
2873 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2877 WARN_ON(!dsi_bus_is_locked(dsidev));
2879 data_id = data_type | dsi->vc[channel].vc_id << 6;
2881 val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
2882 FLD_VAL(ecc, 31, 24);
2884 dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_HEADER(channel), val);
2887 static inline void dsi_vc_write_long_payload(struct platform_device *dsidev,
2888 int channel, u8 b1, u8 b2, u8 b3, u8 b4)
2892 val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0;
2894 /* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
2895 b1, b2, b3, b4, val); */
2897 dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
2900 static int dsi_vc_send_long(struct platform_device *dsidev, int channel,
2901 u8 data_type, u8 *data, u16 len, u8 ecc)
2904 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2910 if (dsi->debug_write)
2911 DSSDBG("dsi_vc_send_long, %d bytes\n", len);
2914 if (dsi->vc[channel].fifo_size * 32 * 4 < len + 4) {
2915 DSSERR("unable to send long packet: packet too long.\n");
2919 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
2921 dsi_vc_write_long_header(dsidev, channel, data_type, len, ecc);
2924 for (i = 0; i < len >> 2; i++) {
2925 if (dsi->debug_write)
2926 DSSDBG("\tsending full packet %d\n", i);
2933 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, b4);
2938 b1 = 0; b2 = 0; b3 = 0;
2940 if (dsi->debug_write)
2941 DSSDBG("\tsending remainder bytes %d\n", i);
2958 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, 0);
2964 static int dsi_vc_send_short(struct platform_device *dsidev, int channel,
2965 u8 data_type, u16 data, u8 ecc)
2967 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2971 WARN_ON(!dsi_bus_is_locked(dsidev));
2973 if (dsi->debug_write)
2974 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
2976 data_type, data & 0xff, (data >> 8) & 0xff);
2978 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
2980 if (FLD_GET(dsi_read_reg(dsidev, DSI_VC_CTRL(channel)), 16, 16)) {
2981 DSSERR("ERROR FIFO FULL, aborting transfer\n");
2985 data_id = data_type | dsi->vc[channel].vc_id << 6;
2987 r = (data_id << 0) | (data << 8) | (ecc << 24);
2989 dsi_write_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel), r);
2994 int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel)
2996 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2998 return dsi_vc_send_long(dsidev, channel, MIPI_DSI_NULL_PACKET, NULL,
3001 EXPORT_SYMBOL(dsi_vc_send_null);
3003 static int dsi_vc_write_nosync_common(struct platform_device *dsidev,
3004 int channel, u8 *data, int len, enum dss_dsi_content_type type)
3009 BUG_ON(type == DSS_DSI_CONTENT_DCS);
3010 r = dsi_vc_send_short(dsidev, channel,
3011 MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM, 0, 0);
3012 } else if (len == 1) {
3013 r = dsi_vc_send_short(dsidev, channel,
3014 type == DSS_DSI_CONTENT_GENERIC ?
3015 MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM :
3016 MIPI_DSI_DCS_SHORT_WRITE, data[0], 0);
3017 } else if (len == 2) {
3018 r = dsi_vc_send_short(dsidev, channel,
3019 type == DSS_DSI_CONTENT_GENERIC ?
3020 MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM :
3021 MIPI_DSI_DCS_SHORT_WRITE_PARAM,
3022 data[0] | (data[1] << 8), 0);
3024 r = dsi_vc_send_long(dsidev, channel,
3025 type == DSS_DSI_CONTENT_GENERIC ?
3026 MIPI_DSI_GENERIC_LONG_WRITE :
3027 MIPI_DSI_DCS_LONG_WRITE, data, len, 0);
3033 int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
3036 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3038 return dsi_vc_write_nosync_common(dsidev, channel, data, len,
3039 DSS_DSI_CONTENT_DCS);
3041 EXPORT_SYMBOL(dsi_vc_dcs_write_nosync);
3043 int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel,
3046 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3048 return dsi_vc_write_nosync_common(dsidev, channel, data, len,
3049 DSS_DSI_CONTENT_GENERIC);
3051 EXPORT_SYMBOL(dsi_vc_generic_write_nosync);
3053 static int dsi_vc_write_common(struct omap_dss_device *dssdev, int channel,
3054 u8 *data, int len, enum dss_dsi_content_type type)
3056 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3059 r = dsi_vc_write_nosync_common(dsidev, channel, data, len, type);
3063 r = dsi_vc_send_bta_sync(dssdev, channel);
3067 /* RX_FIFO_NOT_EMPTY */
3068 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
3069 DSSERR("rx fifo not empty after write, dumping data:\n");
3070 dsi_vc_flush_receive_data(dsidev, channel);
3077 DSSERR("dsi_vc_write_common(ch %d, cmd 0x%02x, len %d) failed\n",
3078 channel, data[0], len);
3082 int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
3085 return dsi_vc_write_common(dssdev, channel, data, len,
3086 DSS_DSI_CONTENT_DCS);
3088 EXPORT_SYMBOL(dsi_vc_dcs_write);
3090 int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data,
3093 return dsi_vc_write_common(dssdev, channel, data, len,
3094 DSS_DSI_CONTENT_GENERIC);
3096 EXPORT_SYMBOL(dsi_vc_generic_write);
3098 int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd)
3100 return dsi_vc_dcs_write(dssdev, channel, &dcs_cmd, 1);
3102 EXPORT_SYMBOL(dsi_vc_dcs_write_0);
3104 int dsi_vc_generic_write_0(struct omap_dss_device *dssdev, int channel)
3106 return dsi_vc_generic_write(dssdev, channel, NULL, 0);
3108 EXPORT_SYMBOL(dsi_vc_generic_write_0);
3110 int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3116 return dsi_vc_dcs_write(dssdev, channel, buf, 2);
3118 EXPORT_SYMBOL(dsi_vc_dcs_write_1);
3120 int dsi_vc_generic_write_1(struct omap_dss_device *dssdev, int channel,
3123 return dsi_vc_generic_write(dssdev, channel, ¶m, 1);
3125 EXPORT_SYMBOL(dsi_vc_generic_write_1);
3127 int dsi_vc_generic_write_2(struct omap_dss_device *dssdev, int channel,
3128 u8 param1, u8 param2)
3133 return dsi_vc_generic_write(dssdev, channel, buf, 2);
3135 EXPORT_SYMBOL(dsi_vc_generic_write_2);
3137 static int dsi_vc_dcs_send_read_request(struct platform_device *dsidev,
3138 int channel, u8 dcs_cmd)
3140 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3143 if (dsi->debug_read)
3144 DSSDBG("dsi_vc_dcs_send_read_request(ch%d, dcs_cmd %x)\n",
3147 r = dsi_vc_send_short(dsidev, channel, MIPI_DSI_DCS_READ, dcs_cmd, 0);
3149 DSSERR("dsi_vc_dcs_send_read_request(ch %d, cmd 0x%02x)"
3150 " failed\n", channel, dcs_cmd);
3157 static int dsi_vc_generic_send_read_request(struct platform_device *dsidev,
3158 int channel, u8 *reqdata, int reqlen)
3160 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3165 if (dsi->debug_read)
3166 DSSDBG("dsi_vc_generic_send_read_request(ch %d, reqlen %d)\n",
3170 data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM;
3172 } else if (reqlen == 1) {
3173 data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM;
3175 } else if (reqlen == 2) {
3176 data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM;
3177 data = reqdata[0] | (reqdata[1] << 8);
3183 r = dsi_vc_send_short(dsidev, channel, data_type, data, 0);
3185 DSSERR("dsi_vc_generic_send_read_request(ch %d, reqlen %d)"
3186 " failed\n", channel, reqlen);
3193 static int dsi_vc_read_rx_fifo(struct platform_device *dsidev, int channel,
3194 u8 *buf, int buflen, enum dss_dsi_content_type type)
3196 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3201 /* RX_FIFO_NOT_EMPTY */
3202 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20) == 0) {
3203 DSSERR("RX fifo empty when trying to read.\n");
3208 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
3209 if (dsi->debug_read)
3210 DSSDBG("\theader: %08x\n", val);
3211 dt = FLD_GET(val, 5, 0);
3212 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
3213 u16 err = FLD_GET(val, 23, 8);
3214 dsi_show_rx_ack_with_err(err);
3218 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3219 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE :
3220 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE)) {
3221 u8 data = FLD_GET(val, 15, 8);
3222 if (dsi->debug_read)
3223 DSSDBG("\t%s short response, 1 byte: %02x\n",
3224 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3235 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3236 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE :
3237 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE)) {
3238 u16 data = FLD_GET(val, 23, 8);
3239 if (dsi->debug_read)
3240 DSSDBG("\t%s short response, 2 byte: %04x\n",
3241 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3249 buf[0] = data & 0xff;
3250 buf[1] = (data >> 8) & 0xff;
3253 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3254 MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE :
3255 MIPI_DSI_RX_DCS_LONG_READ_RESPONSE)) {
3257 int len = FLD_GET(val, 23, 8);
3258 if (dsi->debug_read)
3259 DSSDBG("\t%s long response, len %d\n",
3260 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3268 /* two byte checksum ends the packet, not included in len */
3269 for (w = 0; w < len + 2;) {
3271 val = dsi_read_reg(dsidev,
3272 DSI_VC_SHORT_PACKET_HEADER(channel));
3273 if (dsi->debug_read)
3274 DSSDBG("\t\t%02x %02x %02x %02x\n",
3278 (val >> 24) & 0xff);
3280 for (b = 0; b < 4; ++b) {
3282 buf[w] = (val >> (b * 8)) & 0xff;
3283 /* we discard the 2 byte checksum */
3290 DSSERR("\tunknown datatype 0x%02x\n", dt);
3296 DSSERR("dsi_vc_read_rx_fifo(ch %d type %s) failed\n", channel,
3297 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : "DCS");
3302 int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3303 u8 *buf, int buflen)
3305 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3308 r = dsi_vc_dcs_send_read_request(dsidev, channel, dcs_cmd);
3312 r = dsi_vc_send_bta_sync(dssdev, channel);
3316 r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
3317 DSS_DSI_CONTENT_DCS);
3328 DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", channel, dcs_cmd);
3331 EXPORT_SYMBOL(dsi_vc_dcs_read);
3333 static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int channel,
3334 u8 *reqdata, int reqlen, u8 *buf, int buflen)
3336 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3339 r = dsi_vc_generic_send_read_request(dsidev, channel, reqdata, reqlen);
3343 r = dsi_vc_send_bta_sync(dssdev, channel);
3347 r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
3348 DSS_DSI_CONTENT_GENERIC);
3360 int dsi_vc_generic_read_0(struct omap_dss_device *dssdev, int channel, u8 *buf,
3365 r = dsi_vc_generic_read(dssdev, channel, NULL, 0, buf, buflen);
3367 DSSERR("dsi_vc_generic_read_0(ch %d) failed\n", channel);
3373 EXPORT_SYMBOL(dsi_vc_generic_read_0);
3375 int dsi_vc_generic_read_1(struct omap_dss_device *dssdev, int channel, u8 param,
3376 u8 *buf, int buflen)
3380 r = dsi_vc_generic_read(dssdev, channel, ¶m, 1, buf, buflen);
3382 DSSERR("dsi_vc_generic_read_1(ch %d) failed\n", channel);
3388 EXPORT_SYMBOL(dsi_vc_generic_read_1);
3390 int dsi_vc_generic_read_2(struct omap_dss_device *dssdev, int channel,
3391 u8 param1, u8 param2, u8 *buf, int buflen)
3396 reqdata[0] = param1;
3397 reqdata[1] = param2;
3399 r = dsi_vc_generic_read(dssdev, channel, reqdata, 2, buf, buflen);
3401 DSSERR("dsi_vc_generic_read_2(ch %d) failed\n", channel);
3407 EXPORT_SYMBOL(dsi_vc_generic_read_2);
3409 int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
3412 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3414 return dsi_vc_send_short(dsidev, channel,
3415 MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0);
3417 EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size);
3419 static int dsi_enter_ulps(struct platform_device *dsidev)
3421 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3422 DECLARE_COMPLETION_ONSTACK(completion);
3426 DSSDBG("Entering ULPS");
3428 WARN_ON(!dsi_bus_is_locked(dsidev));
3430 WARN_ON(dsi->ulps_enabled);
3432 if (dsi->ulps_enabled)
3435 /* DDR_CLK_ALWAYS_ON */
3436 if (REG_GET(dsidev, DSI_CLK_CTRL, 13, 13)) {
3437 dsi_if_enable(dsidev, 0);
3438 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13);
3439 dsi_if_enable(dsidev, 1);
3442 dsi_sync_vc(dsidev, 0);
3443 dsi_sync_vc(dsidev, 1);
3444 dsi_sync_vc(dsidev, 2);
3445 dsi_sync_vc(dsidev, 3);
3447 dsi_force_tx_stop_mode_io(dsidev);
3449 dsi_vc_enable(dsidev, 0, false);
3450 dsi_vc_enable(dsidev, 1, false);
3451 dsi_vc_enable(dsidev, 2, false);
3452 dsi_vc_enable(dsidev, 3, false);
3454 if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 16, 16)) { /* HS_BUSY */
3455 DSSERR("HS busy when enabling ULPS\n");
3459 if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 17, 17)) { /* LP_BUSY */
3460 DSSERR("LP busy when enabling ULPS\n");
3464 r = dsi_register_isr_cio(dsidev, dsi_completion_handler, &completion,
3465 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3471 for (i = 0; i < dsi->num_lanes_supported; ++i) {
3472 if (dsi->lanes[i].function == DSI_LANE_UNUSED)
3476 /* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */
3477 /* LANEx_ULPS_SIG2 */
3478 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, mask, 9, 5);
3480 /* flush posted write and wait for SCP interface to finish the write */
3481 dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
3483 if (wait_for_completion_timeout(&completion,
3484 msecs_to_jiffies(1000)) == 0) {
3485 DSSERR("ULPS enable timeout\n");
3490 dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3491 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3493 /* Reset LANEx_ULPS_SIG2 */
3494 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, 0, 9, 5);
3496 /* flush posted write and wait for SCP interface to finish the write */
3497 dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
3499 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ULPS);
3501 dsi_if_enable(dsidev, false);
3503 dsi->ulps_enabled = true;
3508 dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3509 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3513 static void dsi_set_lp_rx_timeout(struct platform_device *dsidev,
3514 unsigned ticks, bool x4, bool x16)
3517 unsigned long total_ticks;
3520 BUG_ON(ticks > 0x1fff);
3522 /* ticks in DSI_FCK */
3523 fck = dsi_fclk_rate(dsidev);
3525 r = dsi_read_reg(dsidev, DSI_TIMING2);
3526 r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */
3527 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */
3528 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */
3529 r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */
3530 dsi_write_reg(dsidev, DSI_TIMING2, r);
3532 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3534 DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3536 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3537 (total_ticks * 1000) / (fck / 1000 / 1000));
3540 static void dsi_set_ta_timeout(struct platform_device *dsidev, unsigned ticks,
3544 unsigned long total_ticks;
3547 BUG_ON(ticks > 0x1fff);
3549 /* ticks in DSI_FCK */
3550 fck = dsi_fclk_rate(dsidev);
3552 r = dsi_read_reg(dsidev, DSI_TIMING1);
3553 r = FLD_MOD(r, 1, 31, 31); /* TA_TO */
3554 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */
3555 r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */
3556 r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */
3557 dsi_write_reg(dsidev, DSI_TIMING1, r);
3559 total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1);
3561 DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n",
3563 ticks, x8 ? " x8" : "", x16 ? " x16" : "",
3564 (total_ticks * 1000) / (fck / 1000 / 1000));
3567 static void dsi_set_stop_state_counter(struct platform_device *dsidev,
3568 unsigned ticks, bool x4, bool x16)
3571 unsigned long total_ticks;
3574 BUG_ON(ticks > 0x1fff);
3576 /* ticks in DSI_FCK */
3577 fck = dsi_fclk_rate(dsidev);
3579 r = dsi_read_reg(dsidev, DSI_TIMING1);
3580 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
3581 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */
3582 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */
3583 r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */
3584 dsi_write_reg(dsidev, DSI_TIMING1, r);
3586 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3588 DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n",
3590 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3591 (total_ticks * 1000) / (fck / 1000 / 1000));
3594 static void dsi_set_hs_tx_timeout(struct platform_device *dsidev,
3595 unsigned ticks, bool x4, bool x16)
3598 unsigned long total_ticks;
3601 BUG_ON(ticks > 0x1fff);
3603 /* ticks in TxByteClkHS */
3604 fck = dsi_get_txbyteclkhs(dsidev);
3606 r = dsi_read_reg(dsidev, DSI_TIMING2);
3607 r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */
3608 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */
3609 r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */
3610 r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */
3611 dsi_write_reg(dsidev, DSI_TIMING2, r);
3613 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3615 DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3617 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3618 (total_ticks * 1000) / (fck / 1000 / 1000));
3621 static void dsi_config_vp_num_line_buffers(struct platform_device *dsidev)
3623 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3624 int num_line_buffers;
3626 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3627 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3628 struct omap_video_timings *timings = &dsi->timings;
3630 * Don't use line buffers if width is greater than the video
3631 * port's line buffer size
3633 if (dsi->line_buffer_size <= timings->x_res * bpp / 8)
3634 num_line_buffers = 0;
3636 num_line_buffers = 2;
3638 /* Use maximum number of line buffers in command mode */
3639 num_line_buffers = 2;
3643 REG_FLD_MOD(dsidev, DSI_CTRL, num_line_buffers, 13, 12);
3646 static void dsi_config_vp_sync_events(struct platform_device *dsidev)
3648 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3652 if (dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE)
3657 r = dsi_read_reg(dsidev, DSI_CTRL);
3658 r = FLD_MOD(r, 1, 9, 9); /* VP_DE_POL */
3659 r = FLD_MOD(r, 1, 10, 10); /* VP_HSYNC_POL */
3660 r = FLD_MOD(r, 1, 11, 11); /* VP_VSYNC_POL */
3661 r = FLD_MOD(r, 1, 15, 15); /* VP_VSYNC_START */
3662 r = FLD_MOD(r, sync_end, 16, 16); /* VP_VSYNC_END */
3663 r = FLD_MOD(r, 1, 17, 17); /* VP_HSYNC_START */
3664 r = FLD_MOD(r, sync_end, 18, 18); /* VP_HSYNC_END */
3665 dsi_write_reg(dsidev, DSI_CTRL, r);
3668 static void dsi_config_blanking_modes(struct platform_device *dsidev)
3670 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3671 int blanking_mode = dsi->vm_timings.blanking_mode;
3672 int hfp_blanking_mode = dsi->vm_timings.hfp_blanking_mode;
3673 int hbp_blanking_mode = dsi->vm_timings.hbp_blanking_mode;
3674 int hsa_blanking_mode = dsi->vm_timings.hsa_blanking_mode;
3678 * 0 = TX FIFO packets sent or LPS in corresponding blanking periods
3679 * 1 = Long blanking packets are sent in corresponding blanking periods
3681 r = dsi_read_reg(dsidev, DSI_CTRL);
3682 r = FLD_MOD(r, blanking_mode, 20, 20); /* BLANKING_MODE */
3683 r = FLD_MOD(r, hfp_blanking_mode, 21, 21); /* HFP_BLANKING */
3684 r = FLD_MOD(r, hbp_blanking_mode, 22, 22); /* HBP_BLANKING */
3685 r = FLD_MOD(r, hsa_blanking_mode, 23, 23); /* HSA_BLANKING */
3686 dsi_write_reg(dsidev, DSI_CTRL, r);
3690 * According to section 'HS Command Mode Interleaving' in OMAP TRM, Scenario 3
3691 * results in maximum transition time for data and clock lanes to enter and
3692 * exit HS mode. Hence, this is the scenario where the least amount of command
3693 * mode data can be interleaved. We program the minimum amount of TXBYTECLKHS
3694 * clock cycles that can be used to interleave command mode data in HS so that
3695 * all scenarios are satisfied.
3697 static int dsi_compute_interleave_hs(int blank, bool ddr_alwon, int enter_hs,
3698 int exit_hs, int exiths_clk, int ddr_pre, int ddr_post)
3703 * If DDR_CLK_ALWAYS_ON is set, we need to consider HS mode transition
3704 * time of data lanes only, if it isn't set, we need to consider HS
3705 * transition time of both data and clock lanes. HS transition time
3706 * of Scenario 3 is considered.
3709 transition = enter_hs + exit_hs + max(enter_hs, 2) + 1;
3712 trans1 = ddr_pre + enter_hs + exit_hs + max(enter_hs, 2) + 1;
3713 trans2 = ddr_pre + enter_hs + exiths_clk + ddr_post + ddr_pre +
3715 transition = max(trans1, trans2);
3718 return blank > transition ? blank - transition : 0;
3722 * According to section 'LP Command Mode Interleaving' in OMAP TRM, Scenario 1
3723 * results in maximum transition time for data lanes to enter and exit LP mode.
3724 * Hence, this is the scenario where the least amount of command mode data can
3725 * be interleaved. We program the minimum amount of bytes that can be
3726 * interleaved in LP so that all scenarios are satisfied.
3728 static int dsi_compute_interleave_lp(int blank, int enter_hs, int exit_hs,
3729 int lp_clk_div, int tdsi_fclk)
3731 int trans_lp; /* time required for a LP transition, in TXBYTECLKHS */
3732 int tlp_avail; /* time left for interleaving commands, in CLKIN4DDR */
3733 int ttxclkesc; /* period of LP transmit escape clock, in CLKIN4DDR */
3734 int thsbyte_clk = 16; /* Period of TXBYTECLKHS clock, in CLKIN4DDR */
3735 int lp_inter; /* cmd mode data that can be interleaved, in bytes */
3737 /* maximum LP transition time according to Scenario 1 */
3738 trans_lp = exit_hs + max(enter_hs, 2) + 1;
3740 /* CLKIN4DDR = 16 * TXBYTECLKHS */
3741 tlp_avail = thsbyte_clk * (blank - trans_lp);
3743 ttxclkesc = tdsi_fclk * lp_clk_div;
3745 lp_inter = ((tlp_avail - 8 * thsbyte_clk - 5 * tdsi_fclk) / ttxclkesc -
3748 return max(lp_inter, 0);
3751 static void dsi_config_cmd_mode_interleaving(struct platform_device *dsidev)
3753 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3755 int hfp_blanking_mode, hbp_blanking_mode, hsa_blanking_mode;
3756 int hsa, hfp, hbp, width_bytes, bllp, lp_clk_div;
3757 int ddr_clk_pre, ddr_clk_post, enter_hs_mode_lat, exit_hs_mode_lat;
3758 int tclk_trail, ths_exit, exiths_clk;
3760 struct omap_video_timings *timings = &dsi->timings;
3761 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
3762 int ndl = dsi->num_lanes_used - 1;
3763 int dsi_fclk_hsdiv = dsi->user_dsi_cinfo.regm_dsi + 1;
3764 int hsa_interleave_hs = 0, hsa_interleave_lp = 0;
3765 int hfp_interleave_hs = 0, hfp_interleave_lp = 0;
3766 int hbp_interleave_hs = 0, hbp_interleave_lp = 0;
3767 int bl_interleave_hs = 0, bl_interleave_lp = 0;
3770 r = dsi_read_reg(dsidev, DSI_CTRL);
3771 blanking_mode = FLD_GET(r, 20, 20);
3772 hfp_blanking_mode = FLD_GET(r, 21, 21);
3773 hbp_blanking_mode = FLD_GET(r, 22, 22);
3774 hsa_blanking_mode = FLD_GET(r, 23, 23);
3776 r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
3777 hbp = FLD_GET(r, 11, 0);
3778 hfp = FLD_GET(r, 23, 12);
3779 hsa = FLD_GET(r, 31, 24);
3781 r = dsi_read_reg(dsidev, DSI_CLK_TIMING);
3782 ddr_clk_post = FLD_GET(r, 7, 0);
3783 ddr_clk_pre = FLD_GET(r, 15, 8);
3785 r = dsi_read_reg(dsidev, DSI_VM_TIMING7);
3786 exit_hs_mode_lat = FLD_GET(r, 15, 0);
3787 enter_hs_mode_lat = FLD_GET(r, 31, 16);
3789 r = dsi_read_reg(dsidev, DSI_CLK_CTRL);
3790 lp_clk_div = FLD_GET(r, 12, 0);
3791 ddr_alwon = FLD_GET(r, 13, 13);
3793 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
3794 ths_exit = FLD_GET(r, 7, 0);
3796 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
3797 tclk_trail = FLD_GET(r, 15, 8);
3799 exiths_clk = ths_exit + tclk_trail;
3801 width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8);
3802 bllp = hbp + hfp + hsa + DIV_ROUND_UP(width_bytes + 6, ndl);
3804 if (!hsa_blanking_mode) {
3805 hsa_interleave_hs = dsi_compute_interleave_hs(hsa, ddr_alwon,
3806 enter_hs_mode_lat, exit_hs_mode_lat,
3807 exiths_clk, ddr_clk_pre, ddr_clk_post);
3808 hsa_interleave_lp = dsi_compute_interleave_lp(hsa,
3809 enter_hs_mode_lat, exit_hs_mode_lat,
3810 lp_clk_div, dsi_fclk_hsdiv);
3813 if (!hfp_blanking_mode) {
3814 hfp_interleave_hs = dsi_compute_interleave_hs(hfp, ddr_alwon,
3815 enter_hs_mode_lat, exit_hs_mode_lat,
3816 exiths_clk, ddr_clk_pre, ddr_clk_post);
3817 hfp_interleave_lp = dsi_compute_interleave_lp(hfp,
3818 enter_hs_mode_lat, exit_hs_mode_lat,
3819 lp_clk_div, dsi_fclk_hsdiv);
3822 if (!hbp_blanking_mode) {
3823 hbp_interleave_hs = dsi_compute_interleave_hs(hbp, ddr_alwon,
3824 enter_hs_mode_lat, exit_hs_mode_lat,
3825 exiths_clk, ddr_clk_pre, ddr_clk_post);
3827 hbp_interleave_lp = dsi_compute_interleave_lp(hbp,
3828 enter_hs_mode_lat, exit_hs_mode_lat,
3829 lp_clk_div, dsi_fclk_hsdiv);
3832 if (!blanking_mode) {
3833 bl_interleave_hs = dsi_compute_interleave_hs(bllp, ddr_alwon,
3834 enter_hs_mode_lat, exit_hs_mode_lat,
3835 exiths_clk, ddr_clk_pre, ddr_clk_post);
3837 bl_interleave_lp = dsi_compute_interleave_lp(bllp,
3838 enter_hs_mode_lat, exit_hs_mode_lat,
3839 lp_clk_div, dsi_fclk_hsdiv);
3842 DSSDBG("DSI HS interleaving(TXBYTECLKHS) HSA %d, HFP %d, HBP %d, BLLP %d\n",
3843 hsa_interleave_hs, hfp_interleave_hs, hbp_interleave_hs,
3846 DSSDBG("DSI LP interleaving(bytes) HSA %d, HFP %d, HBP %d, BLLP %d\n",
3847 hsa_interleave_lp, hfp_interleave_lp, hbp_interleave_lp,
3850 r = dsi_read_reg(dsidev, DSI_VM_TIMING4);
3851 r = FLD_MOD(r, hsa_interleave_hs, 23, 16);
3852 r = FLD_MOD(r, hfp_interleave_hs, 15, 8);
3853 r = FLD_MOD(r, hbp_interleave_hs, 7, 0);
3854 dsi_write_reg(dsidev, DSI_VM_TIMING4, r);
3856 r = dsi_read_reg(dsidev, DSI_VM_TIMING5);
3857 r = FLD_MOD(r, hsa_interleave_lp, 23, 16);
3858 r = FLD_MOD(r, hfp_interleave_lp, 15, 8);
3859 r = FLD_MOD(r, hbp_interleave_lp, 7, 0);
3860 dsi_write_reg(dsidev, DSI_VM_TIMING5, r);
3862 r = dsi_read_reg(dsidev, DSI_VM_TIMING6);
3863 r = FLD_MOD(r, bl_interleave_hs, 31, 15);
3864 r = FLD_MOD(r, bl_interleave_lp, 16, 0);
3865 dsi_write_reg(dsidev, DSI_VM_TIMING6, r);
3868 static int dsi_proto_config(struct platform_device *dsidev)
3870 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3874 dsi_config_tx_fifo(dsidev, DSI_FIFO_SIZE_32,
3879 dsi_config_rx_fifo(dsidev, DSI_FIFO_SIZE_32,
3884 /* XXX what values for the timeouts? */
3885 dsi_set_stop_state_counter(dsidev, 0x1000, false, false);
3886 dsi_set_ta_timeout(dsidev, 0x1fff, true, true);
3887 dsi_set_lp_rx_timeout(dsidev, 0x1fff, true, true);
3888 dsi_set_hs_tx_timeout(dsidev, 0x1fff, true, true);
3890 switch (dsi_get_pixel_size(dsi->pix_fmt)) {
3905 r = dsi_read_reg(dsidev, DSI_CTRL);
3906 r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */
3907 r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */
3908 r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */
3909 r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/
3910 r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
3911 r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */
3912 r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */
3913 r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */
3914 if (!dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
3915 r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */
3916 /* DCS_CMD_CODE, 1=start, 0=continue */
3917 r = FLD_MOD(r, 0, 25, 25);
3920 dsi_write_reg(dsidev, DSI_CTRL, r);
3922 dsi_config_vp_num_line_buffers(dsidev);
3924 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
3925 dsi_config_vp_sync_events(dsidev);
3926 dsi_config_blanking_modes(dsidev);
3927 dsi_config_cmd_mode_interleaving(dsidev);
3930 dsi_vc_initial_config(dsidev, 0);
3931 dsi_vc_initial_config(dsidev, 1);
3932 dsi_vc_initial_config(dsidev, 2);
3933 dsi_vc_initial_config(dsidev, 3);
3938 static void dsi_proto_timings(struct platform_device *dsidev)
3940 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3941 unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail;
3942 unsigned tclk_pre, tclk_post;
3943 unsigned ths_prepare, ths_prepare_ths_zero, ths_zero;
3944 unsigned ths_trail, ths_exit;
3945 unsigned ddr_clk_pre, ddr_clk_post;
3946 unsigned enter_hs_mode_lat, exit_hs_mode_lat;
3948 int ndl = dsi->num_lanes_used - 1;
3951 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
3952 ths_prepare = FLD_GET(r, 31, 24);
3953 ths_prepare_ths_zero = FLD_GET(r, 23, 16);
3954 ths_zero = ths_prepare_ths_zero - ths_prepare;
3955 ths_trail = FLD_GET(r, 15, 8);
3956 ths_exit = FLD_GET(r, 7, 0);
3958 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
3959 tlpx = FLD_GET(r, 20, 16) * 2;
3960 tclk_trail = FLD_GET(r, 15, 8);
3961 tclk_zero = FLD_GET(r, 7, 0);
3963 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
3964 tclk_prepare = FLD_GET(r, 7, 0);
3968 /* min 60ns + 52*UI */
3969 tclk_post = ns2ddr(dsidev, 60) + 26;
3971 ths_eot = DIV_ROUND_UP(4, ndl);
3973 ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
3975 ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot;
3977 BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
3978 BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);
3980 r = dsi_read_reg(dsidev, DSI_CLK_TIMING);
3981 r = FLD_MOD(r, ddr_clk_pre, 15, 8);
3982 r = FLD_MOD(r, ddr_clk_post, 7, 0);
3983 dsi_write_reg(dsidev, DSI_CLK_TIMING, r);
3985 DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
3989 enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) +
3990 DIV_ROUND_UP(ths_prepare, 4) +
3991 DIV_ROUND_UP(ths_zero + 3, 4);
3993 exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;
3995 r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
3996 FLD_VAL(exit_hs_mode_lat, 15, 0);
3997 dsi_write_reg(dsidev, DSI_VM_TIMING7, r);
3999 DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
4000 enter_hs_mode_lat, exit_hs_mode_lat);
4002 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
4003 /* TODO: Implement a video mode check_timings function */
4004 int hsa = dsi->vm_timings.hsa;
4005 int hfp = dsi->vm_timings.hfp;
4006 int hbp = dsi->vm_timings.hbp;
4007 int vsa = dsi->vm_timings.vsa;
4008 int vfp = dsi->vm_timings.vfp;
4009 int vbp = dsi->vm_timings.vbp;
4010 int window_sync = dsi->vm_timings.window_sync;
4012 struct omap_video_timings *timings = &dsi->timings;
4013 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
4014 int tl, t_he, width_bytes;
4016 hsync_end = dsi->vm_timings.trans_mode == OMAP_DSS_DSI_PULSE_MODE;
4018 ((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0;
4020 width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8);
4022 /* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */
4023 tl = DIV_ROUND_UP(4, ndl) + (hsync_end ? hsa : 0) + t_he + hfp +
4024 DIV_ROUND_UP(width_bytes + 6, ndl) + hbp;
4026 DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp,
4027 hfp, hsync_end ? hsa : 0, tl);
4028 DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp, vfp,
4029 vsa, timings->y_res);
4031 r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
4032 r = FLD_MOD(r, hbp, 11, 0); /* HBP */
4033 r = FLD_MOD(r, hfp, 23, 12); /* HFP */
4034 r = FLD_MOD(r, hsync_end ? hsa : 0, 31, 24); /* HSA */
4035 dsi_write_reg(dsidev, DSI_VM_TIMING1, r);
4037 r = dsi_read_reg(dsidev, DSI_VM_TIMING2);
4038 r = FLD_MOD(r, vbp, 7, 0); /* VBP */
4039 r = FLD_MOD(r, vfp, 15, 8); /* VFP */
4040 r = FLD_MOD(r, vsa, 23, 16); /* VSA */
4041 r = FLD_MOD(r, window_sync, 27, 24); /* WINDOW_SYNC */
4042 dsi_write_reg(dsidev, DSI_VM_TIMING2, r);
4044 r = dsi_read_reg(dsidev, DSI_VM_TIMING3);
4045 r = FLD_MOD(r, timings->y_res, 14, 0); /* VACT */
4046 r = FLD_MOD(r, tl, 31, 16); /* TL */
4047 dsi_write_reg(dsidev, DSI_VM_TIMING3, r);
4051 int omapdss_dsi_configure_pins(struct omap_dss_device *dssdev,
4052 const struct omap_dsi_pin_config *pin_cfg)
4054 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4055 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4058 struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
4062 static const enum dsi_lane_function functions[] = {
4070 num_pins = pin_cfg->num_pins;
4071 pins = pin_cfg->pins;
4073 if (num_pins < 4 || num_pins > dsi->num_lanes_supported * 2
4074 || num_pins % 2 != 0)
4077 for (i = 0; i < DSI_MAX_NR_LANES; ++i)
4078 lanes[i].function = DSI_LANE_UNUSED;
4082 for (i = 0; i < num_pins; i += 2) {
4089 if (dx < 0 || dx >= dsi->num_lanes_supported * 2)
4092 if (dy < 0 || dy >= dsi->num_lanes_supported * 2)
4107 lanes[lane].function = functions[i / 2];
4108 lanes[lane].polarity = pol;
4112 memcpy(dsi->lanes, lanes, sizeof(dsi->lanes));
4113 dsi->num_lanes_used = num_lanes;
4117 EXPORT_SYMBOL(omapdss_dsi_configure_pins);
4119 int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel)
4121 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4122 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4123 struct omap_overlay_manager *mgr = dsi->output.manager;
4124 int bpp = dsi_get_pixel_size(dsi->pix_fmt);
4125 struct omap_dss_output *out = &dsi->output;
4130 if (out == NULL || out->manager == NULL) {
4131 DSSERR("failed to enable display: no output/manager\n");
4135 r = dsi_display_init_dispc(dsidev, mgr);
4137 goto err_init_dispc;
4139 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
4140 switch (dsi->pix_fmt) {
4141 case OMAP_DSS_DSI_FMT_RGB888:
4142 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24;
4144 case OMAP_DSS_DSI_FMT_RGB666:
4145 data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
4147 case OMAP_DSS_DSI_FMT_RGB666_PACKED:
4148 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18;
4150 case OMAP_DSS_DSI_FMT_RGB565:
4151 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16;
4158 dsi_if_enable(dsidev, false);
4159 dsi_vc_enable(dsidev, channel, false);
4161 /* MODE, 1 = video mode */
4162 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 4, 4);
4164 word_count = DIV_ROUND_UP(dsi->timings.x_res * bpp, 8);
4166 dsi_vc_write_long_header(dsidev, channel, data_type,
4169 dsi_vc_enable(dsidev, channel, true);
4170 dsi_if_enable(dsidev, true);
4173 r = dss_mgr_enable(mgr);
4175 goto err_mgr_enable;
4180 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
4181 dsi_if_enable(dsidev, false);
4182 dsi_vc_enable(dsidev, channel, false);
4185 dsi_display_uninit_dispc(dsidev, mgr);
4189 EXPORT_SYMBOL(dsi_enable_video_output);
4191 void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel)
4193 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4194 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4195 struct omap_overlay_manager *mgr = dsi->output.manager;
4197 if (dsi->mode == OMAP_DSS_DSI_VIDEO_MODE) {
4198 dsi_if_enable(dsidev, false);
4199 dsi_vc_enable(dsidev, channel, false);
4201 /* MODE, 0 = command mode */
4202 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 0, 4, 4);
4204 dsi_vc_enable(dsidev, channel, true);
4205 dsi_if_enable(dsidev, true);
4208 dss_mgr_disable(mgr);
4210 dsi_display_uninit_dispc(dsidev, mgr);
4212 EXPORT_SYMBOL(dsi_disable_video_output);
4214 static void dsi_update_screen_dispc(struct platform_device *dsidev)
4216 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4217 struct omap_overlay_manager *mgr = dsi->output.manager;
4222 unsigned packet_payload;
4223 unsigned packet_len;
4226 const unsigned channel = dsi->update_channel;
4227 const unsigned line_buf_size = dsi->line_buffer_size;
4228 u16 w = dsi->timings.x_res;
4229 u16 h = dsi->timings.y_res;
4231 DSSDBG("dsi_update_screen_dispc(%dx%d)\n", w, h);
4233 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_VP);
4235 bytespp = dsi_get_pixel_size(dsi->pix_fmt) / 8;
4236 bytespl = w * bytespp;
4237 bytespf = bytespl * h;
4239 /* NOTE: packet_payload has to be equal to N * bytespl, where N is
4240 * number of lines in a packet. See errata about VP_CLK_RATIO */
4242 if (bytespf < line_buf_size)
4243 packet_payload = bytespf;
4245 packet_payload = (line_buf_size) / bytespl * bytespl;
4247 packet_len = packet_payload + 1; /* 1 byte for DCS cmd */
4248 total_len = (bytespf / packet_payload) * packet_len;
4250 if (bytespf % packet_payload)
4251 total_len += (bytespf % packet_payload) + 1;
4253 l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
4254 dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
4256 dsi_vc_write_long_header(dsidev, channel, MIPI_DSI_DCS_LONG_WRITE,
4259 if (dsi->te_enabled)
4260 l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
4262 l = FLD_MOD(l, 1, 31, 31); /* TE_START */
4263 dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
4265 /* We put SIDLEMODE to no-idle for the duration of the transfer,
4266 * because DSS interrupts are not capable of waking up the CPU and the
4267 * framedone interrupt could be delayed for quite a long time. I think
4268 * the same goes for any DSS interrupts, but for some reason I have not
4269 * seen the problem anywhere else than here.
4271 dispc_disable_sidle();
4273 dsi_perf_mark_start(dsidev);
4275 r = schedule_delayed_work(&dsi->framedone_timeout_work,
4276 msecs_to_jiffies(250));
4279 dss_mgr_set_timings(mgr, &dsi->timings);
4281 dss_mgr_start_update(mgr);
4283 if (dsi->te_enabled) {
4284 /* disable LP_RX_TO, so that we can receive TE. Time to wait
4285 * for TE is longer than the timer allows */
4286 REG_FLD_MOD(dsidev, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
4288 dsi_vc_send_bta(dsidev, channel);
4290 #ifdef DSI_CATCH_MISSING_TE
4291 mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250));
4296 #ifdef DSI_CATCH_MISSING_TE
4297 static void dsi_te_timeout(unsigned long arg)
4299 DSSERR("TE not received for 250ms!\n");
4303 static void dsi_handle_framedone(struct platform_device *dsidev, int error)
4305 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4307 /* SIDLEMODE back to smart-idle */
4308 dispc_enable_sidle();
4310 if (dsi->te_enabled) {
4311 /* enable LP_RX_TO again after the TE */
4312 REG_FLD_MOD(dsidev, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
4315 dsi->framedone_callback(error, dsi->framedone_data);
4318 dsi_perf_show(dsidev, "DISPC");
4321 static void dsi_framedone_timeout_work_callback(struct work_struct *work)
4323 struct dsi_data *dsi = container_of(work, struct dsi_data,
4324 framedone_timeout_work.work);
4325 /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after
4326 * 250ms which would conflict with this timeout work. What should be
4327 * done is first cancel the transfer on the HW, and then cancel the
4328 * possibly scheduled framedone work. However, cancelling the transfer
4329 * on the HW is buggy, and would probably require resetting the whole
4332 DSSERR("Framedone not received for 250ms!\n");
4334 dsi_handle_framedone(dsi->pdev, -ETIMEDOUT);
4337 static void dsi_framedone_irq_callback(void *data)
4339 struct platform_device *dsidev = (struct platform_device *) data;
4340 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4342 /* Note: We get FRAMEDONE when DISPC has finished sending pixels and
4343 * turns itself off. However, DSI still has the pixels in its buffers,
4344 * and is sending the data.
4347 cancel_delayed_work(&dsi->framedone_timeout_work);
4349 dsi_handle_framedone(dsidev, 0);
4352 int omap_dsi_update(struct omap_dss_device *dssdev, int channel,
4353 void (*callback)(int, void *), void *data)
4355 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4356 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4359 dsi_perf_mark_setup(dsidev);
4361 dsi->update_channel = channel;
4363 dsi->framedone_callback = callback;
4364 dsi->framedone_data = data;
4366 dw = dsi->timings.x_res;
4367 dh = dsi->timings.y_res;
4370 dsi->update_bytes = dw * dh *
4371 dsi_get_pixel_size(dsi->pix_fmt) / 8;
4373 dsi_update_screen_dispc(dsidev);
4377 EXPORT_SYMBOL(omap_dsi_update);
4381 static int dsi_configure_dispc_clocks(struct platform_device *dsidev)
4383 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4384 struct dispc_clock_info dispc_cinfo;
4388 fck = dsi_get_pll_hsdiv_dispc_rate(dsidev);
4390 dispc_cinfo.lck_div = dsi->user_dispc_cinfo.lck_div;
4391 dispc_cinfo.pck_div = dsi->user_dispc_cinfo.pck_div;
4393 r = dispc_calc_clock_rates(fck, &dispc_cinfo);
4395 DSSERR("Failed to calc dispc clocks\n");
4399 dsi->mgr_config.clock_info = dispc_cinfo;
4404 static int dsi_display_init_dispc(struct platform_device *dsidev,
4405 struct omap_overlay_manager *mgr)
4407 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4410 dss_select_lcd_clk_source(mgr->id, dsi->module_id == 0 ?
4411 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC :
4412 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC);
4414 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE) {
4415 r = dss_mgr_register_framedone_handler(mgr,
4416 dsi_framedone_irq_callback, dsidev);
4418 DSSERR("can't register FRAMEDONE handler\n");
4422 dsi->mgr_config.stallmode = true;
4423 dsi->mgr_config.fifohandcheck = true;
4425 dsi->mgr_config.stallmode = false;
4426 dsi->mgr_config.fifohandcheck = false;
4430 * override interlace, logic level and edge related parameters in
4431 * omap_video_timings with default values
4433 dsi->timings.interlace = false;
4434 dsi->timings.hsync_level = OMAPDSS_SIG_ACTIVE_HIGH;
4435 dsi->timings.vsync_level = OMAPDSS_SIG_ACTIVE_HIGH;
4436 dsi->timings.data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
4437 dsi->timings.de_level = OMAPDSS_SIG_ACTIVE_HIGH;
4438 dsi->timings.sync_pclk_edge = OMAPDSS_DRIVE_SIG_OPPOSITE_EDGES;
4440 dss_mgr_set_timings(mgr, &dsi->timings);
4442 r = dsi_configure_dispc_clocks(dsidev);
4446 dsi->mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
4447 dsi->mgr_config.video_port_width =
4448 dsi_get_pixel_size(dsi->pix_fmt);
4449 dsi->mgr_config.lcden_sig_polarity = 0;
4451 dss_mgr_set_lcd_config(mgr, &dsi->mgr_config);
4455 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE)
4456 dss_mgr_unregister_framedone_handler(mgr,
4457 dsi_framedone_irq_callback, dsidev);
4459 dss_select_lcd_clk_source(mgr->id, OMAP_DSS_CLK_SRC_FCK);
4463 static void dsi_display_uninit_dispc(struct platform_device *dsidev,
4464 struct omap_overlay_manager *mgr)
4466 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4468 if (dsi->mode == OMAP_DSS_DSI_CMD_MODE)
4469 dss_mgr_unregister_framedone_handler(mgr,
4470 dsi_framedone_irq_callback, dsidev);
4472 dss_select_lcd_clk_source(mgr->id, OMAP_DSS_CLK_SRC_FCK);
4475 static int dsi_configure_dsi_clocks(struct platform_device *dsidev)
4477 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4478 struct dsi_clock_info cinfo;
4481 cinfo = dsi->user_dsi_cinfo;
4483 r = dsi_calc_clock_rates(dsidev, &cinfo);
4485 DSSERR("Failed to calc dsi clocks\n");
4489 r = dsi_pll_set_clock_div(dsidev, &cinfo);
4491 DSSERR("Failed to set dsi clocks\n");
4498 static int dsi_display_init_dsi(struct platform_device *dsidev)
4500 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4503 r = dsi_pll_init(dsidev, true, true);
4507 r = dsi_configure_dsi_clocks(dsidev);
4511 dss_select_dsi_clk_source(dsi->module_id, dsi->module_id == 0 ?
4512 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI :
4513 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI);
4517 r = dsi_cio_init(dsidev);
4521 _dsi_print_reset_status(dsidev);
4523 dsi_proto_timings(dsidev);
4524 dsi_set_lp_clk_divisor(dsidev);
4527 _dsi_print_reset_status(dsidev);
4529 r = dsi_proto_config(dsidev);
4533 /* enable interface */
4534 dsi_vc_enable(dsidev, 0, 1);
4535 dsi_vc_enable(dsidev, 1, 1);
4536 dsi_vc_enable(dsidev, 2, 1);
4537 dsi_vc_enable(dsidev, 3, 1);
4538 dsi_if_enable(dsidev, 1);
4539 dsi_force_tx_stop_mode_io(dsidev);
4543 dsi_cio_uninit(dsidev);
4545 dss_select_dsi_clk_source(dsi->module_id, OMAP_DSS_CLK_SRC_FCK);
4547 dsi_pll_uninit(dsidev, true);
4552 static void dsi_display_uninit_dsi(struct platform_device *dsidev,
4553 bool disconnect_lanes, bool enter_ulps)
4555 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4557 if (enter_ulps && !dsi->ulps_enabled)
4558 dsi_enter_ulps(dsidev);
4560 /* disable interface */
4561 dsi_if_enable(dsidev, 0);
4562 dsi_vc_enable(dsidev, 0, 0);
4563 dsi_vc_enable(dsidev, 1, 0);
4564 dsi_vc_enable(dsidev, 2, 0);
4565 dsi_vc_enable(dsidev, 3, 0);
4567 dss_select_dsi_clk_source(dsi->module_id, OMAP_DSS_CLK_SRC_FCK);
4568 dsi_cio_uninit(dsidev);
4569 dsi_pll_uninit(dsidev, disconnect_lanes);
4572 int omapdss_dsi_display_enable(struct omap_dss_device *dssdev)
4574 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4575 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4578 DSSDBG("dsi_display_enable\n");
4580 WARN_ON(!dsi_bus_is_locked(dsidev));
4582 mutex_lock(&dsi->lock);
4584 r = omap_dss_start_device(dssdev);
4586 DSSERR("failed to start device\n");
4590 r = dsi_runtime_get(dsidev);
4594 dsi_enable_pll_clock(dsidev, 1);
4596 _dsi_initialize_irq(dsidev);
4598 r = dsi_display_init_dsi(dsidev);
4602 mutex_unlock(&dsi->lock);
4607 dsi_enable_pll_clock(dsidev, 0);
4608 dsi_runtime_put(dsidev);
4610 omap_dss_stop_device(dssdev);
4612 mutex_unlock(&dsi->lock);
4613 DSSDBG("dsi_display_enable FAILED\n");
4616 EXPORT_SYMBOL(omapdss_dsi_display_enable);
4618 void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
4619 bool disconnect_lanes, bool enter_ulps)
4621 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4622 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4624 DSSDBG("dsi_display_disable\n");
4626 WARN_ON(!dsi_bus_is_locked(dsidev));
4628 mutex_lock(&dsi->lock);
4630 dsi_sync_vc(dsidev, 0);
4631 dsi_sync_vc(dsidev, 1);
4632 dsi_sync_vc(dsidev, 2);
4633 dsi_sync_vc(dsidev, 3);
4635 dsi_display_uninit_dsi(dsidev, disconnect_lanes, enter_ulps);
4637 dsi_runtime_put(dsidev);
4638 dsi_enable_pll_clock(dsidev, 0);
4640 omap_dss_stop_device(dssdev);
4642 mutex_unlock(&dsi->lock);
4644 EXPORT_SYMBOL(omapdss_dsi_display_disable);
4646 int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable)
4648 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4649 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4651 dsi->te_enabled = enable;
4654 EXPORT_SYMBOL(omapdss_dsi_enable_te);
4656 #ifdef PRINT_VERBOSE_VM_TIMINGS
4657 static void print_dsi_vm(const char *str,
4658 const struct omap_dss_dsi_videomode_timings *t)
4660 unsigned long byteclk = t->hsclk / 4;
4661 int bl, wc, pps, tot;
4663 wc = DIV_ROUND_UP(t->hact * t->bitspp, 8);
4664 pps = DIV_ROUND_UP(wc + 6, t->ndl); /* pixel packet size */
4665 bl = t->hss + t->hsa + t->hse + t->hbp + t->hfp;
4668 #define TO_DSI_T(x) ((u32)div64_u64((u64)x * 1000000000llu, byteclk))
4670 pr_debug("%s bck %lu, %u/%u/%u/%u/%u/%u = %u+%u = %u, "
4671 "%u/%u/%u/%u/%u/%u = %u + %u = %u\n",
4674 t->hss, t->hsa, t->hse, t->hbp, pps, t->hfp,
4690 static void print_dispc_vm(const char *str, const struct omap_video_timings *t)
4692 unsigned long pck = t->pixel_clock * 1000;
4696 bl = t->hsw + t->hbp + t->hfp;
4699 #define TO_DISPC_T(x) ((u32)div64_u64((u64)x * 1000000000llu, pck))
4701 pr_debug("%s pck %lu, %u/%u/%u/%u = %u+%u = %u, "
4702 "%u/%u/%u/%u = %u + %u = %u\n",
4705 t->hsw, t->hbp, hact, t->hfp,
4717 /* note: this is not quite accurate */
4718 static void print_dsi_dispc_vm(const char *str,
4719 const struct omap_dss_dsi_videomode_timings *t)
4721 struct omap_video_timings vm = { 0 };
4722 unsigned long byteclk = t->hsclk / 4;
4725 int dsi_hact, dsi_htot;
4727 dsi_tput = (u64)byteclk * t->ndl * 8;
4728 pck = (u32)div64_u64(dsi_tput, t->bitspp);
4729 dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(t->hact * t->bitspp, 8) + 6, t->ndl);
4730 dsi_htot = t->hss + t->hsa + t->hse + t->hbp + dsi_hact + t->hfp;
4732 vm.pixel_clock = pck / 1000;
4733 vm.hsw = div64_u64((u64)(t->hsa + t->hse) * pck, byteclk);
4734 vm.hbp = div64_u64((u64)t->hbp * pck, byteclk);
4735 vm.hfp = div64_u64((u64)t->hfp * pck, byteclk);
4738 print_dispc_vm(str, &vm);
4740 #endif /* PRINT_VERBOSE_VM_TIMINGS */
4742 static bool dsi_cm_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
4743 unsigned long pck, void *data)
4745 struct dsi_clk_calc_ctx *ctx = data;
4746 struct omap_video_timings *t = &ctx->dispc_vm;
4748 ctx->dispc_cinfo.lck_div = lckd;
4749 ctx->dispc_cinfo.pck_div = pckd;
4750 ctx->dispc_cinfo.lck = lck;
4751 ctx->dispc_cinfo.pck = pck;
4753 *t = *ctx->config->timings;
4754 t->pixel_clock = pck / 1000;
4755 t->x_res = ctx->config->timings->x_res;
4756 t->y_res = ctx->config->timings->y_res;
4757 t->hsw = t->hfp = t->hbp = t->vsw = 1;
4758 t->vfp = t->vbp = 0;
4763 static bool dsi_cm_calc_hsdiv_cb(int regm_dispc, unsigned long dispc,
4766 struct dsi_clk_calc_ctx *ctx = data;
4768 ctx->dsi_cinfo.regm_dispc = regm_dispc;
4769 ctx->dsi_cinfo.dsi_pll_hsdiv_dispc_clk = dispc;
4771 return dispc_div_calc(dispc, ctx->req_pck_min, ctx->req_pck_max,
4772 dsi_cm_calc_dispc_cb, ctx);
4775 static bool dsi_cm_calc_pll_cb(int regn, int regm, unsigned long fint,
4776 unsigned long pll, void *data)
4778 struct dsi_clk_calc_ctx *ctx = data;
4780 ctx->dsi_cinfo.regn = regn;
4781 ctx->dsi_cinfo.regm = regm;
4782 ctx->dsi_cinfo.fint = fint;
4783 ctx->dsi_cinfo.clkin4ddr = pll;
4785 return dsi_hsdiv_calc(ctx->dsidev, pll, ctx->req_pck_min,
4786 dsi_cm_calc_hsdiv_cb, ctx);
4789 static bool dsi_cm_calc(struct dsi_data *dsi,
4790 const struct omap_dss_dsi_config *cfg,
4791 struct dsi_clk_calc_ctx *ctx)
4793 unsigned long clkin;
4795 unsigned long pll_min, pll_max;
4796 unsigned long pck, txbyteclk;
4798 clkin = clk_get_rate(dsi->sys_clk);
4799 bitspp = dsi_get_pixel_size(cfg->pixel_format);
4800 ndl = dsi->num_lanes_used - 1;
4803 * Here we should calculate minimum txbyteclk to be able to send the
4804 * frame in time, and also to handle TE. That's not very simple, though,
4805 * especially as we go to LP between each pixel packet due to HW
4806 * "feature". So let's just estimate very roughly and multiply by 1.5.
4808 pck = cfg->timings->pixel_clock * 1000;
4810 txbyteclk = pck * bitspp / 8 / ndl;
4812 memset(ctx, 0, sizeof(*ctx));
4813 ctx->dsidev = dsi->pdev;
4815 ctx->req_pck_min = pck;
4816 ctx->req_pck_nom = pck;
4817 ctx->req_pck_max = pck * 3 / 2;
4818 ctx->dsi_cinfo.clkin = clkin;
4820 pll_min = max(cfg->hs_clk_min * 4, txbyteclk * 4 * 4);
4821 pll_max = cfg->hs_clk_max * 4;
4823 return dsi_pll_calc(dsi->pdev, clkin,
4825 dsi_cm_calc_pll_cb, ctx);
4828 static bool dsi_vm_calc_blanking(struct dsi_clk_calc_ctx *ctx)
4830 struct dsi_data *dsi = dsi_get_dsidrv_data(ctx->dsidev);
4831 const struct omap_dss_dsi_config *cfg = ctx->config;
4832 int bitspp = dsi_get_pixel_size(cfg->pixel_format);
4833 int ndl = dsi->num_lanes_used - 1;
4834 unsigned long hsclk = ctx->dsi_cinfo.clkin4ddr / 4;
4835 unsigned long byteclk = hsclk / 4;
4837 unsigned long dispc_pck, req_pck_min, req_pck_nom, req_pck_max;
4839 int panel_htot, panel_hbl; /* pixels */
4840 int dispc_htot, dispc_hbl; /* pixels */
4841 int dsi_htot, dsi_hact, dsi_hbl, hss, hse; /* byteclks */
4843 const struct omap_video_timings *req_vm;
4844 struct omap_video_timings *dispc_vm;
4845 struct omap_dss_dsi_videomode_timings *dsi_vm;
4846 u64 dsi_tput, dispc_tput;
4848 dsi_tput = (u64)byteclk * ndl * 8;
4850 req_vm = cfg->timings;
4851 req_pck_min = ctx->req_pck_min;
4852 req_pck_max = ctx->req_pck_max;
4853 req_pck_nom = ctx->req_pck_nom;
4855 dispc_pck = ctx->dispc_cinfo.pck;
4856 dispc_tput = (u64)dispc_pck * bitspp;
4858 xres = req_vm->x_res;
4860 panel_hbl = req_vm->hfp + req_vm->hbp + req_vm->hsw;
4861 panel_htot = xres + panel_hbl;
4863 dsi_hact = DIV_ROUND_UP(DIV_ROUND_UP(xres * bitspp, 8) + 6, ndl);
4866 * When there are no line buffers, DISPC and DSI must have the
4867 * same tput. Otherwise DISPC tput needs to be higher than DSI's.
4869 if (dsi->line_buffer_size < xres * bitspp / 8) {
4870 if (dispc_tput != dsi_tput)
4873 if (dispc_tput < dsi_tput)
4877 /* DSI tput must be over the min requirement */
4878 if (dsi_tput < (u64)bitspp * req_pck_min)
4881 /* When non-burst mode, DSI tput must be below max requirement. */
4882 if (cfg->trans_mode != OMAP_DSS_DSI_BURST_MODE) {
4883 if (dsi_tput > (u64)bitspp * req_pck_max)
4887 hss = DIV_ROUND_UP(4, ndl);
4889 if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) {
4890 if (ndl == 3 && req_vm->hsw == 0)
4893 hse = DIV_ROUND_UP(4, ndl);
4898 /* DSI htot to match the panel's nominal pck */
4899 dsi_htot = div64_u64((u64)panel_htot * byteclk, req_pck_nom);
4901 /* fail if there would be no time for blanking */
4902 if (dsi_htot < hss + hse + dsi_hact)
4905 /* total DSI blanking needed to achieve panel's TL */
4906 dsi_hbl = dsi_htot - dsi_hact;
4908 /* DISPC htot to match the DSI TL */
4909 dispc_htot = div64_u64((u64)dsi_htot * dispc_pck, byteclk);
4911 /* verify that the DSI and DISPC TLs are the same */
4912 if ((u64)dsi_htot * dispc_pck != (u64)dispc_htot * byteclk)
4915 dispc_hbl = dispc_htot - xres;
4917 /* setup DSI videomode */
4919 dsi_vm = &ctx->dsi_vm;
4920 memset(dsi_vm, 0, sizeof(*dsi_vm));
4922 dsi_vm->hsclk = hsclk;
4925 dsi_vm->bitspp = bitspp;
4927 if (cfg->trans_mode != OMAP_DSS_DSI_PULSE_MODE) {
4929 } else if (ndl == 3 && req_vm->hsw == 0) {
4932 hsa = div64_u64((u64)req_vm->hsw * byteclk, req_pck_nom);
4933 hsa = max(hsa - hse, 1);
4936 hbp = div64_u64((u64)req_vm->hbp * byteclk, req_pck_nom);
4939 hfp = dsi_hbl - (hss + hsa + hse + hbp);
4942 /* we need to take cycles from hbp */
4945 hbp = max(hbp - t, 1);
4946 hfp = dsi_hbl - (hss + hsa + hse + hbp);
4948 if (hfp < 1 && hsa > 0) {
4949 /* we need to take cycles from hsa */
4951 hsa = max(hsa - t, 1);
4952 hfp = dsi_hbl - (hss + hsa + hse + hbp);
4963 dsi_vm->hact = xres;
4966 dsi_vm->vsa = req_vm->vsw;
4967 dsi_vm->vbp = req_vm->vbp;
4968 dsi_vm->vact = req_vm->y_res;
4969 dsi_vm->vfp = req_vm->vfp;
4971 dsi_vm->trans_mode = cfg->trans_mode;
4973 dsi_vm->blanking_mode = 0;
4974 dsi_vm->hsa_blanking_mode = 1;
4975 dsi_vm->hfp_blanking_mode = 1;
4976 dsi_vm->hbp_blanking_mode = 1;
4978 dsi_vm->ddr_clk_always_on = cfg->ddr_clk_always_on;
4979 dsi_vm->window_sync = 4;
4981 /* setup DISPC videomode */
4983 dispc_vm = &ctx->dispc_vm;
4984 *dispc_vm = *req_vm;
4985 dispc_vm->pixel_clock = dispc_pck / 1000;
4987 if (cfg->trans_mode == OMAP_DSS_DSI_PULSE_MODE) {
4988 hsa = div64_u64((u64)req_vm->hsw * dispc_pck,
4995 hbp = div64_u64((u64)req_vm->hbp * dispc_pck, req_pck_nom);
4998 hfp = dispc_hbl - hsa - hbp;
5001 /* we need to take cycles from hbp */
5004 hbp = max(hbp - t, 1);
5005 hfp = dispc_hbl - hsa - hbp;
5008 /* we need to take cycles from hsa */
5010 hsa = max(hsa - t, 1);
5011 hfp = dispc_hbl - hsa - hbp;
5018 dispc_vm->hfp = hfp;
5019 dispc_vm->hsw = hsa;
5020 dispc_vm->hbp = hbp;
5026 static bool dsi_vm_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
5027 unsigned long pck, void *data)
5029 struct dsi_clk_calc_ctx *ctx = data;
5031 ctx->dispc_cinfo.lck_div = lckd;
5032 ctx->dispc_cinfo.pck_div = pckd;
5033 ctx->dispc_cinfo.lck = lck;
5034 ctx->dispc_cinfo.pck = pck;
5036 if (dsi_vm_calc_blanking(ctx) == false)
5039 #ifdef PRINT_VERBOSE_VM_TIMINGS
5040 print_dispc_vm("dispc", &ctx->dispc_vm);
5041 print_dsi_vm("dsi ", &ctx->dsi_vm);
5042 print_dispc_vm("req ", ctx->config->timings);
5043 print_dsi_dispc_vm("act ", &ctx->dsi_vm);
5049 static bool dsi_vm_calc_hsdiv_cb(int regm_dispc, unsigned long dispc,
5052 struct dsi_clk_calc_ctx *ctx = data;
5053 unsigned long pck_max;
5055 ctx->dsi_cinfo.regm_dispc = regm_dispc;
5056 ctx->dsi_cinfo.dsi_pll_hsdiv_dispc_clk = dispc;
5059 * In burst mode we can let the dispc pck be arbitrarily high, but it
5060 * limits our scaling abilities. So for now, don't aim too high.
5063 if (ctx->config->trans_mode == OMAP_DSS_DSI_BURST_MODE)
5064 pck_max = ctx->req_pck_max + 10000000;
5066 pck_max = ctx->req_pck_max;
5068 return dispc_div_calc(dispc, ctx->req_pck_min, pck_max,
5069 dsi_vm_calc_dispc_cb, ctx);
5072 static bool dsi_vm_calc_pll_cb(int regn, int regm, unsigned long fint,
5073 unsigned long pll, void *data)
5075 struct dsi_clk_calc_ctx *ctx = data;
5077 ctx->dsi_cinfo.regn = regn;
5078 ctx->dsi_cinfo.regm = regm;
5079 ctx->dsi_cinfo.fint = fint;
5080 ctx->dsi_cinfo.clkin4ddr = pll;
5082 return dsi_hsdiv_calc(ctx->dsidev, pll, ctx->req_pck_min,
5083 dsi_vm_calc_hsdiv_cb, ctx);
5086 static bool dsi_vm_calc(struct dsi_data *dsi,
5087 const struct omap_dss_dsi_config *cfg,
5088 struct dsi_clk_calc_ctx *ctx)
5090 const struct omap_video_timings *t = cfg->timings;
5091 unsigned long clkin;
5092 unsigned long pll_min;
5093 unsigned long pll_max;
5094 int ndl = dsi->num_lanes_used - 1;
5095 int bitspp = dsi_get_pixel_size(cfg->pixel_format);
5096 unsigned long byteclk_min;
5098 clkin = clk_get_rate(dsi->sys_clk);
5100 memset(ctx, 0, sizeof(*ctx));
5101 ctx->dsidev = dsi->pdev;
5104 ctx->dsi_cinfo.clkin = clkin;
5106 /* these limits should come from the panel driver */
5107 ctx->req_pck_min = t->pixel_clock * 1000 - 1000;
5108 ctx->req_pck_nom = t->pixel_clock * 1000;
5109 ctx->req_pck_max = t->pixel_clock * 1000 + 1000;
5111 byteclk_min = div64_u64((u64)ctx->req_pck_min * bitspp, ndl * 8);
5112 pll_min = max(cfg->hs_clk_min * 4, byteclk_min * 4 * 4);
5114 if (cfg->trans_mode == OMAP_DSS_DSI_BURST_MODE) {
5115 pll_max = cfg->hs_clk_max * 4;
5117 unsigned long byteclk_max;
5118 byteclk_max = div64_u64((u64)ctx->req_pck_max * bitspp,
5121 pll_max = byteclk_max * 4 * 4;
5124 return dsi_pll_calc(dsi->pdev, clkin,
5126 dsi_vm_calc_pll_cb, ctx);
5129 int omapdss_dsi_set_config(struct omap_dss_device *dssdev,
5130 const struct omap_dss_dsi_config *config)
5132 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
5133 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5134 struct dsi_clk_calc_ctx ctx;
5138 mutex_lock(&dsi->lock);
5140 dsi->pix_fmt = config->pixel_format;
5141 dsi->mode = config->mode;
5143 if (config->mode == OMAP_DSS_DSI_VIDEO_MODE)
5144 ok = dsi_vm_calc(dsi, config, &ctx);
5146 ok = dsi_cm_calc(dsi, config, &ctx);
5149 DSSERR("failed to find suitable DSI clock settings\n");
5154 dsi_pll_calc_dsi_fck(&ctx.dsi_cinfo);
5156 r = dsi_lp_clock_calc(&ctx.dsi_cinfo, config->lp_clk_min,
5157 config->lp_clk_max);
5159 DSSERR("failed to find suitable DSI LP clock settings\n");
5163 dsi->user_dsi_cinfo = ctx.dsi_cinfo;
5164 dsi->user_dispc_cinfo = ctx.dispc_cinfo;
5166 dsi->timings = ctx.dispc_vm;
5167 dsi->vm_timings = ctx.dsi_vm;
5169 mutex_unlock(&dsi->lock);
5173 mutex_unlock(&dsi->lock);
5177 EXPORT_SYMBOL(omapdss_dsi_set_config);
5180 * Return a hardcoded channel for the DSI output. This should work for
5181 * current use cases, but this can be later expanded to either resolve
5182 * the channel in some more dynamic manner, or get the channel as a user
5185 static enum omap_channel dsi_get_channel(int module_id)
5187 switch (omapdss_get_version()) {
5188 case OMAPDSS_VER_OMAP24xx:
5189 DSSWARN("DSI not supported\n");
5190 return OMAP_DSS_CHANNEL_LCD;
5192 case OMAPDSS_VER_OMAP34xx_ES1:
5193 case OMAPDSS_VER_OMAP34xx_ES3:
5194 case OMAPDSS_VER_OMAP3630:
5195 case OMAPDSS_VER_AM35xx:
5196 return OMAP_DSS_CHANNEL_LCD;
5198 case OMAPDSS_VER_OMAP4430_ES1:
5199 case OMAPDSS_VER_OMAP4430_ES2:
5200 case OMAPDSS_VER_OMAP4:
5201 switch (module_id) {
5203 return OMAP_DSS_CHANNEL_LCD;
5205 return OMAP_DSS_CHANNEL_LCD2;
5207 DSSWARN("unsupported module id\n");
5208 return OMAP_DSS_CHANNEL_LCD;
5211 case OMAPDSS_VER_OMAP5:
5212 switch (module_id) {
5214 return OMAP_DSS_CHANNEL_LCD;
5216 return OMAP_DSS_CHANNEL_LCD3;
5218 DSSWARN("unsupported module id\n");
5219 return OMAP_DSS_CHANNEL_LCD;
5223 DSSWARN("unsupported DSS version\n");
5224 return OMAP_DSS_CHANNEL_LCD;
5228 static int dsi_init_display(struct omap_dss_device *dssdev)
5230 struct platform_device *dsidev =
5231 dsi_get_dsidev_from_id(dssdev->phy.dsi.module);
5232 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5234 DSSDBG("DSI init\n");
5236 if (dsi->vdds_dsi_reg == NULL) {
5237 struct regulator *vdds_dsi;
5239 vdds_dsi = regulator_get(&dsi->pdev->dev, "vdds_dsi");
5241 /* DT HACK: try VCXIO to make omapdss work for o4 sdp/panda */
5242 if (IS_ERR(vdds_dsi))
5243 vdds_dsi = regulator_get(&dsi->pdev->dev, "VCXIO");
5245 if (IS_ERR(vdds_dsi)) {
5246 DSSERR("can't get VDDS_DSI regulator\n");
5247 return PTR_ERR(vdds_dsi);
5250 dsi->vdds_dsi_reg = vdds_dsi;
5256 int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel)
5258 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
5259 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5262 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
5263 if (!dsi->vc[i].dssdev) {
5264 dsi->vc[i].dssdev = dssdev;
5270 DSSERR("cannot get VC for display %s", dssdev->name);
5273 EXPORT_SYMBOL(omap_dsi_request_vc);
5275 int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id)
5277 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
5278 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5280 if (vc_id < 0 || vc_id > 3) {
5281 DSSERR("VC ID out of range\n");
5285 if (channel < 0 || channel > 3) {
5286 DSSERR("Virtual Channel out of range\n");
5290 if (dsi->vc[channel].dssdev != dssdev) {
5291 DSSERR("Virtual Channel not allocated to display %s\n",
5296 dsi->vc[channel].vc_id = vc_id;
5300 EXPORT_SYMBOL(omap_dsi_set_vc_id);
5302 void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel)
5304 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
5305 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5307 if ((channel >= 0 && channel <= 3) &&
5308 dsi->vc[channel].dssdev == dssdev) {
5309 dsi->vc[channel].dssdev = NULL;
5310 dsi->vc[channel].vc_id = 0;
5313 EXPORT_SYMBOL(omap_dsi_release_vc);
5315 void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev)
5317 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 7, 1) != 1)
5318 DSSERR("%s (%s) not active\n",
5319 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
5320 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC));
5323 void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev)
5325 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 8, 1) != 1)
5326 DSSERR("%s (%s) not active\n",
5327 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
5328 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI));
5331 static void dsi_calc_clock_param_ranges(struct platform_device *dsidev)
5333 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5335 dsi->regn_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGN);
5336 dsi->regm_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM);
5337 dsi->regm_dispc_max =
5338 dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DISPC);
5339 dsi->regm_dsi_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DSI);
5340 dsi->fint_min = dss_feat_get_param_min(FEAT_PARAM_DSIPLL_FINT);
5341 dsi->fint_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_FINT);
5342 dsi->lpdiv_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV);
5345 static int dsi_get_clocks(struct platform_device *dsidev)
5347 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5350 clk = devm_clk_get(&dsidev->dev, "fck");
5352 DSSERR("can't get fck\n");
5353 return PTR_ERR(clk);
5358 clk = devm_clk_get(&dsidev->dev, "sys_clk");
5360 DSSERR("can't get sys_clk\n");
5361 return PTR_ERR(clk);
5369 static struct omap_dss_device *dsi_find_dssdev(struct platform_device *pdev)
5371 struct omap_dss_board_info *pdata = pdev->dev.platform_data;
5372 struct dsi_data *dsi = dsi_get_dsidrv_data(pdev);
5373 const char *def_disp_name = omapdss_get_default_display_name();
5374 struct omap_dss_device *def_dssdev;
5379 for (i = 0; i < pdata->num_devices; ++i) {
5380 struct omap_dss_device *dssdev = pdata->devices[i];
5382 if (dssdev->type != OMAP_DISPLAY_TYPE_DSI)
5385 if (dssdev->phy.dsi.module != dsi->module_id)
5388 if (def_dssdev == NULL)
5389 def_dssdev = dssdev;
5391 if (def_disp_name != NULL &&
5392 strcmp(dssdev->name, def_disp_name) == 0) {
5393 def_dssdev = dssdev;
5401 static void dsi_probe_pdata(struct platform_device *dsidev)
5403 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5404 struct omap_dss_device *plat_dssdev;
5405 struct omap_dss_device *dssdev;
5408 plat_dssdev = dsi_find_dssdev(dsidev);
5413 dssdev = dss_alloc_and_init_device(&dsidev->dev);
5417 dss_copy_device_pdata(dssdev, plat_dssdev);
5419 r = dsi_init_display(dssdev);
5421 DSSERR("device %s init failed: %d\n", dssdev->name, r);
5422 dss_put_device(dssdev);
5426 r = omapdss_output_set_device(&dsi->output, dssdev);
5428 DSSERR("failed to connect output to new device: %s\n",
5430 dss_put_device(dssdev);
5434 r = dss_add_device(dssdev);
5436 DSSERR("device %s register failed: %d\n", dssdev->name, r);
5437 omapdss_output_unset_device(&dsi->output);
5438 dss_put_device(dssdev);
5445 static void dsi_init_output(struct platform_device *dsidev)
5447 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5448 struct omap_dss_output *out = &dsi->output;
5451 out->id = dsi->module_id == 0 ?
5452 OMAP_DSS_OUTPUT_DSI1 : OMAP_DSS_OUTPUT_DSI2;
5454 out->type = OMAP_DISPLAY_TYPE_DSI;
5455 out->name = dsi->module_id == 0 ? "dsi.0" : "dsi.1";
5456 out->dispc_channel = dsi_get_channel(dsi->module_id);
5458 dss_register_output(out);
5461 static void __exit dsi_uninit_output(struct platform_device *dsidev)
5463 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5464 struct omap_dss_output *out = &dsi->output;
5466 dss_unregister_output(out);
5469 /* DSI1 HW IP initialisation */
5470 static int omap_dsihw_probe(struct platform_device *dsidev)
5474 struct resource *dsi_mem;
5475 struct dsi_data *dsi;
5477 dsi = devm_kzalloc(&dsidev->dev, sizeof(*dsi), GFP_KERNEL);
5481 dsi->module_id = dsidev->id;
5483 dev_set_drvdata(&dsidev->dev, dsi);
5485 spin_lock_init(&dsi->irq_lock);
5486 spin_lock_init(&dsi->errors_lock);
5489 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
5490 spin_lock_init(&dsi->irq_stats_lock);
5491 dsi->irq_stats.last_reset = jiffies;
5494 mutex_init(&dsi->lock);
5495 sema_init(&dsi->bus_lock, 1);
5497 INIT_DEFERRABLE_WORK(&dsi->framedone_timeout_work,
5498 dsi_framedone_timeout_work_callback);
5500 #ifdef DSI_CATCH_MISSING_TE
5501 init_timer(&dsi->te_timer);
5502 dsi->te_timer.function = dsi_te_timeout;
5503 dsi->te_timer.data = 0;
5505 dsi_mem = platform_get_resource(dsi->pdev, IORESOURCE_MEM, 0);
5507 DSSERR("can't get IORESOURCE_MEM DSI\n");
5511 dsi->base = devm_ioremap(&dsidev->dev, dsi_mem->start,
5512 resource_size(dsi_mem));
5514 DSSERR("can't ioremap DSI\n");
5518 dsi->irq = platform_get_irq(dsi->pdev, 0);
5520 DSSERR("platform_get_irq failed\n");
5524 r = devm_request_irq(&dsidev->dev, dsi->irq, omap_dsi_irq_handler,
5525 IRQF_SHARED, dev_name(&dsidev->dev), dsi->pdev);
5527 DSSERR("request_irq failed\n");
5531 /* DSI VCs initialization */
5532 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
5533 dsi->vc[i].source = DSI_VC_SOURCE_L4;
5534 dsi->vc[i].dssdev = NULL;
5535 dsi->vc[i].vc_id = 0;
5538 dsi_calc_clock_param_ranges(dsidev);
5540 r = dsi_get_clocks(dsidev);
5544 pm_runtime_enable(&dsidev->dev);
5546 r = dsi_runtime_get(dsidev);
5548 goto err_runtime_get;
5550 rev = dsi_read_reg(dsidev, DSI_REVISION);
5551 dev_dbg(&dsidev->dev, "OMAP DSI rev %d.%d\n",
5552 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
5554 /* DSI on OMAP3 doesn't have register DSI_GNQ, set number
5555 * of data to 3 by default */
5556 if (dss_has_feature(FEAT_DSI_GNQ))
5558 dsi->num_lanes_supported = 1 + REG_GET(dsidev, DSI_GNQ, 11, 9);
5560 dsi->num_lanes_supported = 3;
5562 dsi->line_buffer_size = dsi_get_line_buf_size(dsidev);
5564 dsi_init_output(dsidev);
5566 dsi_probe_pdata(dsidev);
5568 dsi_runtime_put(dsidev);
5570 if (dsi->module_id == 0)
5571 dss_debugfs_create_file("dsi1_regs", dsi1_dump_regs);
5572 else if (dsi->module_id == 1)
5573 dss_debugfs_create_file("dsi2_regs", dsi2_dump_regs);
5575 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
5576 if (dsi->module_id == 0)
5577 dss_debugfs_create_file("dsi1_irqs", dsi1_dump_irqs);
5578 else if (dsi->module_id == 1)
5579 dss_debugfs_create_file("dsi2_irqs", dsi2_dump_irqs);
5584 pm_runtime_disable(&dsidev->dev);
5588 static int __exit omap_dsihw_remove(struct platform_device *dsidev)
5590 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
5592 WARN_ON(dsi->scp_clk_refcount > 0);
5594 dss_unregister_child_devices(&dsidev->dev);
5596 dsi_uninit_output(dsidev);
5598 pm_runtime_disable(&dsidev->dev);
5600 if (dsi->vdds_dsi_reg != NULL) {
5601 if (dsi->vdds_dsi_enabled) {
5602 regulator_disable(dsi->vdds_dsi_reg);
5603 dsi->vdds_dsi_enabled = false;
5606 regulator_put(dsi->vdds_dsi_reg);
5607 dsi->vdds_dsi_reg = NULL;
5613 static int dsi_runtime_suspend(struct device *dev)
5615 dispc_runtime_put();
5620 static int dsi_runtime_resume(struct device *dev)
5624 r = dispc_runtime_get();
5631 static const struct dev_pm_ops dsi_pm_ops = {
5632 .runtime_suspend = dsi_runtime_suspend,
5633 .runtime_resume = dsi_runtime_resume,
5636 static struct platform_driver omap_dsihw_driver = {
5637 .probe = omap_dsihw_probe,
5638 .remove = __exit_p(omap_dsihw_remove),
5640 .name = "omapdss_dsi",
5641 .owner = THIS_MODULE,
5646 int __init dsi_init_platform_driver(void)
5648 return platform_driver_register(&omap_dsihw_driver);
5651 void __exit dsi_uninit_platform_driver(void)
5653 platform_driver_unregister(&omap_dsihw_driver);