2 * linux/drivers/video/omap2/dss/dsi.c
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #define DSS_SUBSYS_NAME "DSI"
22 #include <linux/kernel.h>
24 #include <linux/clk.h>
25 #include <linux/device.h>
26 #include <linux/err.h>
27 #include <linux/interrupt.h>
28 #include <linux/delay.h>
29 #include <linux/mutex.h>
30 #include <linux/semaphore.h>
31 #include <linux/seq_file.h>
32 #include <linux/platform_device.h>
33 #include <linux/regulator/consumer.h>
34 #include <linux/wait.h>
35 #include <linux/workqueue.h>
36 #include <linux/sched.h>
37 #include <linux/slab.h>
38 #include <linux/debugfs.h>
39 #include <linux/pm_runtime.h>
41 #include <video/omapdss.h>
42 #include <video/mipi_display.h>
43 #include <plat/clock.h>
46 #include "dss_features.h"
48 /*#define VERBOSE_IRQ*/
49 #define DSI_CATCH_MISSING_TE
51 struct dsi_reg { u16 idx; };
53 #define DSI_REG(idx) ((const struct dsi_reg) { idx })
55 #define DSI_SZ_REGS SZ_1K
56 /* DSI Protocol Engine */
58 #define DSI_REVISION DSI_REG(0x0000)
59 #define DSI_SYSCONFIG DSI_REG(0x0010)
60 #define DSI_SYSSTATUS DSI_REG(0x0014)
61 #define DSI_IRQSTATUS DSI_REG(0x0018)
62 #define DSI_IRQENABLE DSI_REG(0x001C)
63 #define DSI_CTRL DSI_REG(0x0040)
64 #define DSI_GNQ DSI_REG(0x0044)
65 #define DSI_COMPLEXIO_CFG1 DSI_REG(0x0048)
66 #define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(0x004C)
67 #define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(0x0050)
68 #define DSI_CLK_CTRL DSI_REG(0x0054)
69 #define DSI_TIMING1 DSI_REG(0x0058)
70 #define DSI_TIMING2 DSI_REG(0x005C)
71 #define DSI_VM_TIMING1 DSI_REG(0x0060)
72 #define DSI_VM_TIMING2 DSI_REG(0x0064)
73 #define DSI_VM_TIMING3 DSI_REG(0x0068)
74 #define DSI_CLK_TIMING DSI_REG(0x006C)
75 #define DSI_TX_FIFO_VC_SIZE DSI_REG(0x0070)
76 #define DSI_RX_FIFO_VC_SIZE DSI_REG(0x0074)
77 #define DSI_COMPLEXIO_CFG2 DSI_REG(0x0078)
78 #define DSI_RX_FIFO_VC_FULLNESS DSI_REG(0x007C)
79 #define DSI_VM_TIMING4 DSI_REG(0x0080)
80 #define DSI_TX_FIFO_VC_EMPTINESS DSI_REG(0x0084)
81 #define DSI_VM_TIMING5 DSI_REG(0x0088)
82 #define DSI_VM_TIMING6 DSI_REG(0x008C)
83 #define DSI_VM_TIMING7 DSI_REG(0x0090)
84 #define DSI_STOPCLK_TIMING DSI_REG(0x0094)
85 #define DSI_VC_CTRL(n) DSI_REG(0x0100 + (n * 0x20))
86 #define DSI_VC_TE(n) DSI_REG(0x0104 + (n * 0x20))
87 #define DSI_VC_LONG_PACKET_HEADER(n) DSI_REG(0x0108 + (n * 0x20))
88 #define DSI_VC_LONG_PACKET_PAYLOAD(n) DSI_REG(0x010C + (n * 0x20))
89 #define DSI_VC_SHORT_PACKET_HEADER(n) DSI_REG(0x0110 + (n * 0x20))
90 #define DSI_VC_IRQSTATUS(n) DSI_REG(0x0118 + (n * 0x20))
91 #define DSI_VC_IRQENABLE(n) DSI_REG(0x011C + (n * 0x20))
95 #define DSI_DSIPHY_CFG0 DSI_REG(0x200 + 0x0000)
96 #define DSI_DSIPHY_CFG1 DSI_REG(0x200 + 0x0004)
97 #define DSI_DSIPHY_CFG2 DSI_REG(0x200 + 0x0008)
98 #define DSI_DSIPHY_CFG5 DSI_REG(0x200 + 0x0014)
99 #define DSI_DSIPHY_CFG10 DSI_REG(0x200 + 0x0028)
101 /* DSI_PLL_CTRL_SCP */
103 #define DSI_PLL_CONTROL DSI_REG(0x300 + 0x0000)
104 #define DSI_PLL_STATUS DSI_REG(0x300 + 0x0004)
105 #define DSI_PLL_GO DSI_REG(0x300 + 0x0008)
106 #define DSI_PLL_CONFIGURATION1 DSI_REG(0x300 + 0x000C)
107 #define DSI_PLL_CONFIGURATION2 DSI_REG(0x300 + 0x0010)
109 #define REG_GET(dsidev, idx, start, end) \
110 FLD_GET(dsi_read_reg(dsidev, idx), start, end)
112 #define REG_FLD_MOD(dsidev, idx, val, start, end) \
113 dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end))
115 /* Global interrupts */
116 #define DSI_IRQ_VC0 (1 << 0)
117 #define DSI_IRQ_VC1 (1 << 1)
118 #define DSI_IRQ_VC2 (1 << 2)
119 #define DSI_IRQ_VC3 (1 << 3)
120 #define DSI_IRQ_WAKEUP (1 << 4)
121 #define DSI_IRQ_RESYNC (1 << 5)
122 #define DSI_IRQ_PLL_LOCK (1 << 7)
123 #define DSI_IRQ_PLL_UNLOCK (1 << 8)
124 #define DSI_IRQ_PLL_RECALL (1 << 9)
125 #define DSI_IRQ_COMPLEXIO_ERR (1 << 10)
126 #define DSI_IRQ_HS_TX_TIMEOUT (1 << 14)
127 #define DSI_IRQ_LP_RX_TIMEOUT (1 << 15)
128 #define DSI_IRQ_TE_TRIGGER (1 << 16)
129 #define DSI_IRQ_ACK_TRIGGER (1 << 17)
130 #define DSI_IRQ_SYNC_LOST (1 << 18)
131 #define DSI_IRQ_LDO_POWER_GOOD (1 << 19)
132 #define DSI_IRQ_TA_TIMEOUT (1 << 20)
133 #define DSI_IRQ_ERROR_MASK \
134 (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
136 #define DSI_IRQ_CHANNEL_MASK 0xf
138 /* Virtual channel interrupts */
139 #define DSI_VC_IRQ_CS (1 << 0)
140 #define DSI_VC_IRQ_ECC_CORR (1 << 1)
141 #define DSI_VC_IRQ_PACKET_SENT (1 << 2)
142 #define DSI_VC_IRQ_FIFO_TX_OVF (1 << 3)
143 #define DSI_VC_IRQ_FIFO_RX_OVF (1 << 4)
144 #define DSI_VC_IRQ_BTA (1 << 5)
145 #define DSI_VC_IRQ_ECC_NO_CORR (1 << 6)
146 #define DSI_VC_IRQ_FIFO_TX_UDF (1 << 7)
147 #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
148 #define DSI_VC_IRQ_ERROR_MASK \
149 (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
150 DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
151 DSI_VC_IRQ_FIFO_TX_UDF)
153 /* ComplexIO interrupts */
154 #define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0)
155 #define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1)
156 #define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2)
157 #define DSI_CIO_IRQ_ERRSYNCESC4 (1 << 3)
158 #define DSI_CIO_IRQ_ERRSYNCESC5 (1 << 4)
159 #define DSI_CIO_IRQ_ERRESC1 (1 << 5)
160 #define DSI_CIO_IRQ_ERRESC2 (1 << 6)
161 #define DSI_CIO_IRQ_ERRESC3 (1 << 7)
162 #define DSI_CIO_IRQ_ERRESC4 (1 << 8)
163 #define DSI_CIO_IRQ_ERRESC5 (1 << 9)
164 #define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10)
165 #define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11)
166 #define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12)
167 #define DSI_CIO_IRQ_ERRCONTROL4 (1 << 13)
168 #define DSI_CIO_IRQ_ERRCONTROL5 (1 << 14)
169 #define DSI_CIO_IRQ_STATEULPS1 (1 << 15)
170 #define DSI_CIO_IRQ_STATEULPS2 (1 << 16)
171 #define DSI_CIO_IRQ_STATEULPS3 (1 << 17)
172 #define DSI_CIO_IRQ_STATEULPS4 (1 << 18)
173 #define DSI_CIO_IRQ_STATEULPS5 (1 << 19)
174 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20)
175 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21)
176 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22)
177 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23)
178 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24)
179 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25)
180 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_4 (1 << 26)
181 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_4 (1 << 27)
182 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_5 (1 << 28)
183 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_5 (1 << 29)
184 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30)
185 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31)
186 #define DSI_CIO_IRQ_ERROR_MASK \
187 (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \
188 DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \
189 DSI_CIO_IRQ_ERRSYNCESC5 | \
190 DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \
191 DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \
192 DSI_CIO_IRQ_ERRESC5 | \
193 DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \
194 DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \
195 DSI_CIO_IRQ_ERRCONTROL5 | \
196 DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \
197 DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \
198 DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \
199 DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \
200 DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5)
202 typedef void (*omap_dsi_isr_t) (void *arg, u32 mask);
204 #define DSI_MAX_NR_ISRS 2
206 struct dsi_isr_data {
214 DSI_FIFO_SIZE_32 = 1,
215 DSI_FIFO_SIZE_64 = 2,
216 DSI_FIFO_SIZE_96 = 3,
217 DSI_FIFO_SIZE_128 = 4,
221 DSI_VC_SOURCE_L4 = 0,
228 DSI_DATA1_P = 1 << 2,
229 DSI_DATA1_N = 1 << 3,
230 DSI_DATA2_P = 1 << 4,
231 DSI_DATA2_N = 1 << 5,
232 DSI_DATA3_P = 1 << 6,
233 DSI_DATA3_N = 1 << 7,
234 DSI_DATA4_P = 1 << 8,
235 DSI_DATA4_N = 1 << 9,
238 struct dsi_update_region {
240 struct omap_dss_device *device;
243 struct dsi_irq_stats {
244 unsigned long last_reset;
246 unsigned dsi_irqs[32];
247 unsigned vc_irqs[4][32];
248 unsigned cio_irqs[32];
251 struct dsi_isr_tables {
252 struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS];
253 struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS];
254 struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS];
258 struct platform_device *pdev;
266 int (*enable_pads)(int dsi_id, unsigned lane_mask);
267 void (*disable_pads)(int dsi_id, unsigned lane_mask);
269 struct dsi_clock_info current_cinfo;
271 bool vdds_dsi_enabled;
272 struct regulator *vdds_dsi_reg;
275 enum dsi_vc_source source;
276 struct omap_dss_device *dssdev;
277 enum fifo_size fifo_size;
282 struct semaphore bus_lock;
287 struct dsi_isr_tables isr_tables;
288 /* space for a copy used by the interrupt handler */
289 struct dsi_isr_tables isr_tables_copy;
292 struct dsi_update_region update_region;
297 void (*framedone_callback)(int, void *);
298 void *framedone_data;
300 struct delayed_work framedone_timeout_work;
302 #ifdef DSI_CATCH_MISSING_TE
303 struct timer_list te_timer;
306 unsigned long cache_req_pck;
307 unsigned long cache_clk_freq;
308 struct dsi_clock_info cache_cinfo;
311 spinlock_t errors_lock;
313 ktime_t perf_setup_time;
314 ktime_t perf_start_time;
319 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
320 spinlock_t irq_stats_lock;
321 struct dsi_irq_stats irq_stats;
323 /* DSI PLL Parameter Ranges */
324 unsigned long regm_max, regn_max;
325 unsigned long regm_dispc_max, regm_dsi_max;
326 unsigned long fint_min, fint_max;
327 unsigned long lpdiv_max;
331 unsigned scp_clk_refcount;
334 struct dsi_packet_sent_handler_data {
335 struct platform_device *dsidev;
336 struct completion *completion;
339 static struct platform_device *dsi_pdev_map[MAX_NUM_DSI];
342 static unsigned int dsi_perf;
343 module_param_named(dsi_perf, dsi_perf, bool, 0644);
346 static inline struct dsi_data *dsi_get_dsidrv_data(struct platform_device *dsidev)
348 return dev_get_drvdata(&dsidev->dev);
351 static inline struct platform_device *dsi_get_dsidev_from_dssdev(struct omap_dss_device *dssdev)
353 return dsi_pdev_map[dssdev->phy.dsi.module];
356 struct platform_device *dsi_get_dsidev_from_id(int module)
358 return dsi_pdev_map[module];
361 static inline int dsi_get_dsidev_id(struct platform_device *dsidev)
366 static inline void dsi_write_reg(struct platform_device *dsidev,
367 const struct dsi_reg idx, u32 val)
369 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
371 __raw_writel(val, dsi->base + idx.idx);
374 static inline u32 dsi_read_reg(struct platform_device *dsidev,
375 const struct dsi_reg idx)
377 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
379 return __raw_readl(dsi->base + idx.idx);
382 void dsi_bus_lock(struct omap_dss_device *dssdev)
384 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
385 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
387 down(&dsi->bus_lock);
389 EXPORT_SYMBOL(dsi_bus_lock);
391 void dsi_bus_unlock(struct omap_dss_device *dssdev)
393 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
394 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
398 EXPORT_SYMBOL(dsi_bus_unlock);
400 static bool dsi_bus_is_locked(struct platform_device *dsidev)
402 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
404 return dsi->bus_lock.count == 0;
407 static void dsi_completion_handler(void *data, u32 mask)
409 complete((struct completion *)data);
412 static inline int wait_for_bit_change(struct platform_device *dsidev,
413 const struct dsi_reg idx, int bitnum, int value)
417 while (REG_GET(dsidev, idx, bitnum, bitnum) != value) {
426 static void dsi_perf_mark_setup(struct platform_device *dsidev)
428 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
429 dsi->perf_setup_time = ktime_get();
432 static void dsi_perf_mark_start(struct platform_device *dsidev)
434 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
435 dsi->perf_start_time = ktime_get();
438 static void dsi_perf_show(struct platform_device *dsidev, const char *name)
440 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
441 ktime_t t, setup_time, trans_time;
443 u32 setup_us, trans_us, total_us;
450 setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time);
451 setup_us = (u32)ktime_to_us(setup_time);
455 trans_time = ktime_sub(t, dsi->perf_start_time);
456 trans_us = (u32)ktime_to_us(trans_time);
460 total_us = setup_us + trans_us;
462 total_bytes = dsi->update_region.w *
463 dsi->update_region.h *
464 dsi->update_region.device->ctrl.pixel_size / 8;
466 printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), "
467 "%u bytes, %u kbytes/sec\n",
472 1000*1000 / total_us,
474 total_bytes * 1000 / total_us);
477 static inline void dsi_perf_mark_setup(struct platform_device *dsidev)
481 static inline void dsi_perf_mark_start(struct platform_device *dsidev)
485 static inline void dsi_perf_show(struct platform_device *dsidev,
491 static void print_irq_status(u32 status)
497 if ((status & ~DSI_IRQ_CHANNEL_MASK) == 0)
500 printk(KERN_DEBUG "DSI IRQ: 0x%x: ", status);
503 if (status & DSI_IRQ_##x) \
529 static void print_irq_status_vc(int channel, u32 status)
535 if ((status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
538 printk(KERN_DEBUG "DSI VC(%d) IRQ 0x%x: ", channel, status);
541 if (status & DSI_VC_IRQ_##x) \
558 static void print_irq_status_cio(u32 status)
563 printk(KERN_DEBUG "DSI CIO IRQ 0x%x: ", status);
566 if (status & DSI_CIO_IRQ_##x) \
580 PIS(ERRCONTENTIONLP0_1);
581 PIS(ERRCONTENTIONLP1_1);
582 PIS(ERRCONTENTIONLP0_2);
583 PIS(ERRCONTENTIONLP1_2);
584 PIS(ERRCONTENTIONLP0_3);
585 PIS(ERRCONTENTIONLP1_3);
586 PIS(ULPSACTIVENOT_ALL0);
587 PIS(ULPSACTIVENOT_ALL1);
593 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
594 static void dsi_collect_irq_stats(struct platform_device *dsidev, u32 irqstatus,
595 u32 *vcstatus, u32 ciostatus)
597 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
600 spin_lock(&dsi->irq_stats_lock);
602 dsi->irq_stats.irq_count++;
603 dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs);
605 for (i = 0; i < 4; ++i)
606 dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]);
608 dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs);
610 spin_unlock(&dsi->irq_stats_lock);
613 #define dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus)
616 static int debug_irq;
618 static void dsi_handle_irq_errors(struct platform_device *dsidev, u32 irqstatus,
619 u32 *vcstatus, u32 ciostatus)
621 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
624 if (irqstatus & DSI_IRQ_ERROR_MASK) {
625 DSSERR("DSI error, irqstatus %x\n", irqstatus);
626 print_irq_status(irqstatus);
627 spin_lock(&dsi->errors_lock);
628 dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK;
629 spin_unlock(&dsi->errors_lock);
630 } else if (debug_irq) {
631 print_irq_status(irqstatus);
634 for (i = 0; i < 4; ++i) {
635 if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) {
636 DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
638 print_irq_status_vc(i, vcstatus[i]);
639 } else if (debug_irq) {
640 print_irq_status_vc(i, vcstatus[i]);
644 if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) {
645 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
646 print_irq_status_cio(ciostatus);
647 } else if (debug_irq) {
648 print_irq_status_cio(ciostatus);
652 static void dsi_call_isrs(struct dsi_isr_data *isr_array,
653 unsigned isr_array_size, u32 irqstatus)
655 struct dsi_isr_data *isr_data;
658 for (i = 0; i < isr_array_size; i++) {
659 isr_data = &isr_array[i];
660 if (isr_data->isr && isr_data->mask & irqstatus)
661 isr_data->isr(isr_data->arg, irqstatus);
665 static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables,
666 u32 irqstatus, u32 *vcstatus, u32 ciostatus)
670 dsi_call_isrs(isr_tables->isr_table,
671 ARRAY_SIZE(isr_tables->isr_table),
674 for (i = 0; i < 4; ++i) {
675 if (vcstatus[i] == 0)
677 dsi_call_isrs(isr_tables->isr_table_vc[i],
678 ARRAY_SIZE(isr_tables->isr_table_vc[i]),
683 dsi_call_isrs(isr_tables->isr_table_cio,
684 ARRAY_SIZE(isr_tables->isr_table_cio),
688 static irqreturn_t omap_dsi_irq_handler(int irq, void *arg)
690 struct platform_device *dsidev;
691 struct dsi_data *dsi;
692 u32 irqstatus, vcstatus[4], ciostatus;
695 dsidev = (struct platform_device *) arg;
696 dsi = dsi_get_dsidrv_data(dsidev);
698 spin_lock(&dsi->irq_lock);
700 irqstatus = dsi_read_reg(dsidev, DSI_IRQSTATUS);
702 /* IRQ is not for us */
704 spin_unlock(&dsi->irq_lock);
708 dsi_write_reg(dsidev, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
709 /* flush posted write */
710 dsi_read_reg(dsidev, DSI_IRQSTATUS);
712 for (i = 0; i < 4; ++i) {
713 if ((irqstatus & (1 << i)) == 0) {
718 vcstatus[i] = dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
720 dsi_write_reg(dsidev, DSI_VC_IRQSTATUS(i), vcstatus[i]);
721 /* flush posted write */
722 dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
725 if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
726 ciostatus = dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
728 dsi_write_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
729 /* flush posted write */
730 dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
735 #ifdef DSI_CATCH_MISSING_TE
736 if (irqstatus & DSI_IRQ_TE_TRIGGER)
737 del_timer(&dsi->te_timer);
740 /* make a copy and unlock, so that isrs can unregister
742 memcpy(&dsi->isr_tables_copy, &dsi->isr_tables,
743 sizeof(dsi->isr_tables));
745 spin_unlock(&dsi->irq_lock);
747 dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus);
749 dsi_handle_irq_errors(dsidev, irqstatus, vcstatus, ciostatus);
751 dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus);
756 /* dsi->irq_lock has to be locked by the caller */
757 static void _omap_dsi_configure_irqs(struct platform_device *dsidev,
758 struct dsi_isr_data *isr_array,
759 unsigned isr_array_size, u32 default_mask,
760 const struct dsi_reg enable_reg,
761 const struct dsi_reg status_reg)
763 struct dsi_isr_data *isr_data;
770 for (i = 0; i < isr_array_size; i++) {
771 isr_data = &isr_array[i];
773 if (isr_data->isr == NULL)
776 mask |= isr_data->mask;
779 old_mask = dsi_read_reg(dsidev, enable_reg);
780 /* clear the irqstatus for newly enabled irqs */
781 dsi_write_reg(dsidev, status_reg, (mask ^ old_mask) & mask);
782 dsi_write_reg(dsidev, enable_reg, mask);
784 /* flush posted writes */
785 dsi_read_reg(dsidev, enable_reg);
786 dsi_read_reg(dsidev, status_reg);
789 /* dsi->irq_lock has to be locked by the caller */
790 static void _omap_dsi_set_irqs(struct platform_device *dsidev)
792 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
793 u32 mask = DSI_IRQ_ERROR_MASK;
794 #ifdef DSI_CATCH_MISSING_TE
795 mask |= DSI_IRQ_TE_TRIGGER;
797 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table,
798 ARRAY_SIZE(dsi->isr_tables.isr_table), mask,
799 DSI_IRQENABLE, DSI_IRQSTATUS);
802 /* dsi->irq_lock has to be locked by the caller */
803 static void _omap_dsi_set_irqs_vc(struct platform_device *dsidev, int vc)
805 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
807 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_vc[vc],
808 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]),
809 DSI_VC_IRQ_ERROR_MASK,
810 DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc));
813 /* dsi->irq_lock has to be locked by the caller */
814 static void _omap_dsi_set_irqs_cio(struct platform_device *dsidev)
816 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
818 _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_cio,
819 ARRAY_SIZE(dsi->isr_tables.isr_table_cio),
820 DSI_CIO_IRQ_ERROR_MASK,
821 DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS);
824 static void _dsi_initialize_irq(struct platform_device *dsidev)
826 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
830 spin_lock_irqsave(&dsi->irq_lock, flags);
832 memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables));
834 _omap_dsi_set_irqs(dsidev);
835 for (vc = 0; vc < 4; ++vc)
836 _omap_dsi_set_irqs_vc(dsidev, vc);
837 _omap_dsi_set_irqs_cio(dsidev);
839 spin_unlock_irqrestore(&dsi->irq_lock, flags);
842 static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
843 struct dsi_isr_data *isr_array, unsigned isr_array_size)
845 struct dsi_isr_data *isr_data;
851 /* check for duplicate entry and find a free slot */
853 for (i = 0; i < isr_array_size; i++) {
854 isr_data = &isr_array[i];
856 if (isr_data->isr == isr && isr_data->arg == arg &&
857 isr_data->mask == mask) {
861 if (isr_data->isr == NULL && free_idx == -1)
868 isr_data = &isr_array[free_idx];
871 isr_data->mask = mask;
876 static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
877 struct dsi_isr_data *isr_array, unsigned isr_array_size)
879 struct dsi_isr_data *isr_data;
882 for (i = 0; i < isr_array_size; i++) {
883 isr_data = &isr_array[i];
884 if (isr_data->isr != isr || isr_data->arg != arg ||
885 isr_data->mask != mask)
888 isr_data->isr = NULL;
889 isr_data->arg = NULL;
898 static int dsi_register_isr(struct platform_device *dsidev, omap_dsi_isr_t isr,
901 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
905 spin_lock_irqsave(&dsi->irq_lock, flags);
907 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table,
908 ARRAY_SIZE(dsi->isr_tables.isr_table));
911 _omap_dsi_set_irqs(dsidev);
913 spin_unlock_irqrestore(&dsi->irq_lock, flags);
918 static int dsi_unregister_isr(struct platform_device *dsidev,
919 omap_dsi_isr_t isr, void *arg, u32 mask)
921 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
925 spin_lock_irqsave(&dsi->irq_lock, flags);
927 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table,
928 ARRAY_SIZE(dsi->isr_tables.isr_table));
931 _omap_dsi_set_irqs(dsidev);
933 spin_unlock_irqrestore(&dsi->irq_lock, flags);
938 static int dsi_register_isr_vc(struct platform_device *dsidev, int channel,
939 omap_dsi_isr_t isr, void *arg, u32 mask)
941 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
945 spin_lock_irqsave(&dsi->irq_lock, flags);
947 r = _dsi_register_isr(isr, arg, mask,
948 dsi->isr_tables.isr_table_vc[channel],
949 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
952 _omap_dsi_set_irqs_vc(dsidev, channel);
954 spin_unlock_irqrestore(&dsi->irq_lock, flags);
959 static int dsi_unregister_isr_vc(struct platform_device *dsidev, int channel,
960 omap_dsi_isr_t isr, void *arg, u32 mask)
962 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
966 spin_lock_irqsave(&dsi->irq_lock, flags);
968 r = _dsi_unregister_isr(isr, arg, mask,
969 dsi->isr_tables.isr_table_vc[channel],
970 ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
973 _omap_dsi_set_irqs_vc(dsidev, channel);
975 spin_unlock_irqrestore(&dsi->irq_lock, flags);
980 static int dsi_register_isr_cio(struct platform_device *dsidev,
981 omap_dsi_isr_t isr, void *arg, u32 mask)
983 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
987 spin_lock_irqsave(&dsi->irq_lock, flags);
989 r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
990 ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
993 _omap_dsi_set_irqs_cio(dsidev);
995 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1000 static int dsi_unregister_isr_cio(struct platform_device *dsidev,
1001 omap_dsi_isr_t isr, void *arg, u32 mask)
1003 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1004 unsigned long flags;
1007 spin_lock_irqsave(&dsi->irq_lock, flags);
1009 r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1010 ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1013 _omap_dsi_set_irqs_cio(dsidev);
1015 spin_unlock_irqrestore(&dsi->irq_lock, flags);
1020 static u32 dsi_get_errors(struct platform_device *dsidev)
1022 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1023 unsigned long flags;
1025 spin_lock_irqsave(&dsi->errors_lock, flags);
1028 spin_unlock_irqrestore(&dsi->errors_lock, flags);
1032 int dsi_runtime_get(struct platform_device *dsidev)
1035 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1037 DSSDBG("dsi_runtime_get\n");
1039 r = pm_runtime_get_sync(&dsi->pdev->dev);
1041 return r < 0 ? r : 0;
1044 void dsi_runtime_put(struct platform_device *dsidev)
1046 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1049 DSSDBG("dsi_runtime_put\n");
1051 r = pm_runtime_put(&dsi->pdev->dev);
1055 /* source clock for DSI PLL. this could also be PCLKFREE */
1056 static inline void dsi_enable_pll_clock(struct platform_device *dsidev,
1059 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1062 clk_enable(dsi->sys_clk);
1064 clk_disable(dsi->sys_clk);
1066 if (enable && dsi->pll_locked) {
1067 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1)
1068 DSSERR("cannot lock PLL when enabling clocks\n");
1073 static void _dsi_print_reset_status(struct platform_device *dsidev)
1081 /* A dummy read using the SCP interface to any DSIPHY register is
1082 * required after DSIPHY reset to complete the reset of the DSI complex
1084 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
1086 printk(KERN_DEBUG "DSI resets: ");
1088 l = dsi_read_reg(dsidev, DSI_PLL_STATUS);
1089 printk("PLL (%d) ", FLD_GET(l, 0, 0));
1091 l = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1);
1092 printk("CIO (%d) ", FLD_GET(l, 29, 29));
1094 if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) {
1104 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
1105 printk("PHY (%x%x%x, %d, %d, %d)\n",
1111 FLD_GET(l, 31, 31));
1114 #define _dsi_print_reset_status(x)
1117 static inline int dsi_if_enable(struct platform_device *dsidev, bool enable)
1119 DSSDBG("dsi_if_enable(%d)\n", enable);
1121 enable = enable ? 1 : 0;
1122 REG_FLD_MOD(dsidev, DSI_CTRL, enable, 0, 0); /* IF_EN */
1124 if (wait_for_bit_change(dsidev, DSI_CTRL, 0, enable) != enable) {
1125 DSSERR("Failed to set dsi_if_enable to %d\n", enable);
1132 unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev)
1134 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1136 return dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk;
1139 static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct platform_device *dsidev)
1141 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1143 return dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk;
1146 static unsigned long dsi_get_txbyteclkhs(struct platform_device *dsidev)
1148 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1150 return dsi->current_cinfo.clkin4ddr / 16;
1153 static unsigned long dsi_fclk_rate(struct platform_device *dsidev)
1156 int dsi_module = dsi_get_dsidev_id(dsidev);
1157 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1159 if (dss_get_dsi_clk_source(dsi_module) == OMAP_DSS_CLK_SRC_FCK) {
1160 /* DSI FCLK source is DSS_CLK_FCK */
1161 r = clk_get_rate(dsi->dss_clk);
1163 /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */
1164 r = dsi_get_pll_hsdiv_dsi_rate(dsidev);
1170 static int dsi_set_lp_clk_divisor(struct omap_dss_device *dssdev)
1172 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
1173 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1174 unsigned long dsi_fclk;
1175 unsigned lp_clk_div;
1176 unsigned long lp_clk;
1178 lp_clk_div = dssdev->clocks.dsi.lp_clk_div;
1180 if (lp_clk_div == 0 || lp_clk_div > dsi->lpdiv_max)
1183 dsi_fclk = dsi_fclk_rate(dsidev);
1185 lp_clk = dsi_fclk / 2 / lp_clk_div;
1187 DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk);
1188 dsi->current_cinfo.lp_clk = lp_clk;
1189 dsi->current_cinfo.lp_clk_div = lp_clk_div;
1191 /* LP_CLK_DIVISOR */
1192 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, lp_clk_div, 12, 0);
1194 /* LP_RX_SYNCHRO_ENABLE */
1195 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21);
1200 static void dsi_enable_scp_clk(struct platform_device *dsidev)
1202 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1204 if (dsi->scp_clk_refcount++ == 0)
1205 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */
1208 static void dsi_disable_scp_clk(struct platform_device *dsidev)
1210 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1212 WARN_ON(dsi->scp_clk_refcount == 0);
1213 if (--dsi->scp_clk_refcount == 0)
1214 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */
1217 enum dsi_pll_power_state {
1218 DSI_PLL_POWER_OFF = 0x0,
1219 DSI_PLL_POWER_ON_HSCLK = 0x1,
1220 DSI_PLL_POWER_ON_ALL = 0x2,
1221 DSI_PLL_POWER_ON_DIV = 0x3,
1224 static int dsi_pll_power(struct platform_device *dsidev,
1225 enum dsi_pll_power_state state)
1229 /* DSI-PLL power command 0x3 is not working */
1230 if (dss_has_feature(FEAT_DSI_PLL_PWR_BUG) &&
1231 state == DSI_PLL_POWER_ON_DIV)
1232 state = DSI_PLL_POWER_ON_ALL;
1235 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, state, 31, 30);
1237 /* PLL_PWR_STATUS */
1238 while (FLD_GET(dsi_read_reg(dsidev, DSI_CLK_CTRL), 29, 28) != state) {
1240 DSSERR("Failed to set DSI PLL power mode to %d\n",
1250 /* calculate clock rates using dividers in cinfo */
1251 static int dsi_calc_clock_rates(struct omap_dss_device *dssdev,
1252 struct dsi_clock_info *cinfo)
1254 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
1255 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1257 if (cinfo->regn == 0 || cinfo->regn > dsi->regn_max)
1260 if (cinfo->regm == 0 || cinfo->regm > dsi->regm_max)
1263 if (cinfo->regm_dispc > dsi->regm_dispc_max)
1266 if (cinfo->regm_dsi > dsi->regm_dsi_max)
1269 if (cinfo->use_sys_clk) {
1270 cinfo->clkin = clk_get_rate(dsi->sys_clk);
1271 /* XXX it is unclear if highfreq should be used
1272 * with DSS_SYS_CLK source also */
1273 cinfo->highfreq = 0;
1275 cinfo->clkin = dispc_mgr_pclk_rate(dssdev->manager->id);
1277 if (cinfo->clkin < 32000000)
1278 cinfo->highfreq = 0;
1280 cinfo->highfreq = 1;
1283 cinfo->fint = cinfo->clkin / (cinfo->regn * (cinfo->highfreq ? 2 : 1));
1285 if (cinfo->fint > dsi->fint_max || cinfo->fint < dsi->fint_min)
1288 cinfo->clkin4ddr = 2 * cinfo->regm * cinfo->fint;
1290 if (cinfo->clkin4ddr > 1800 * 1000 * 1000)
1293 if (cinfo->regm_dispc > 0)
1294 cinfo->dsi_pll_hsdiv_dispc_clk =
1295 cinfo->clkin4ddr / cinfo->regm_dispc;
1297 cinfo->dsi_pll_hsdiv_dispc_clk = 0;
1299 if (cinfo->regm_dsi > 0)
1300 cinfo->dsi_pll_hsdiv_dsi_clk =
1301 cinfo->clkin4ddr / cinfo->regm_dsi;
1303 cinfo->dsi_pll_hsdiv_dsi_clk = 0;
1308 int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev, bool is_tft,
1309 unsigned long req_pck, struct dsi_clock_info *dsi_cinfo,
1310 struct dispc_clock_info *dispc_cinfo)
1312 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1313 struct dsi_clock_info cur, best;
1314 struct dispc_clock_info best_dispc;
1315 int min_fck_per_pck;
1317 unsigned long dss_sys_clk, max_dss_fck;
1319 dss_sys_clk = clk_get_rate(dsi->sys_clk);
1321 max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
1323 if (req_pck == dsi->cache_req_pck &&
1324 dsi->cache_cinfo.clkin == dss_sys_clk) {
1325 DSSDBG("DSI clock info found from cache\n");
1326 *dsi_cinfo = dsi->cache_cinfo;
1327 dispc_find_clk_divs(is_tft, req_pck,
1328 dsi_cinfo->dsi_pll_hsdiv_dispc_clk, dispc_cinfo);
1332 min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
1334 if (min_fck_per_pck &&
1335 req_pck * min_fck_per_pck > max_dss_fck) {
1336 DSSERR("Requested pixel clock not possible with the current "
1337 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
1338 "the constraint off.\n");
1339 min_fck_per_pck = 0;
1342 DSSDBG("dsi_pll_calc\n");
1345 memset(&best, 0, sizeof(best));
1346 memset(&best_dispc, 0, sizeof(best_dispc));
1348 memset(&cur, 0, sizeof(cur));
1349 cur.clkin = dss_sys_clk;
1350 cur.use_sys_clk = 1;
1353 /* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */
1354 /* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */
1355 /* To reduce PLL lock time, keep Fint high (around 2 MHz) */
1356 for (cur.regn = 1; cur.regn < dsi->regn_max; ++cur.regn) {
1357 if (cur.highfreq == 0)
1358 cur.fint = cur.clkin / cur.regn;
1360 cur.fint = cur.clkin / (2 * cur.regn);
1362 if (cur.fint > dsi->fint_max || cur.fint < dsi->fint_min)
1365 /* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */
1366 for (cur.regm = 1; cur.regm < dsi->regm_max; ++cur.regm) {
1369 a = 2 * cur.regm * (cur.clkin/1000);
1370 b = cur.regn * (cur.highfreq + 1);
1371 cur.clkin4ddr = a / b * 1000;
1373 if (cur.clkin4ddr > 1800 * 1000 * 1000)
1376 /* dsi_pll_hsdiv_dispc_clk(MHz) =
1377 * DSIPHY(MHz) / regm_dispc < 173MHz/186Mhz */
1378 for (cur.regm_dispc = 1; cur.regm_dispc <
1379 dsi->regm_dispc_max; ++cur.regm_dispc) {
1380 struct dispc_clock_info cur_dispc;
1381 cur.dsi_pll_hsdiv_dispc_clk =
1382 cur.clkin4ddr / cur.regm_dispc;
1384 /* this will narrow down the search a bit,
1385 * but still give pixclocks below what was
1387 if (cur.dsi_pll_hsdiv_dispc_clk < req_pck)
1390 if (cur.dsi_pll_hsdiv_dispc_clk > max_dss_fck)
1393 if (min_fck_per_pck &&
1394 cur.dsi_pll_hsdiv_dispc_clk <
1395 req_pck * min_fck_per_pck)
1400 dispc_find_clk_divs(is_tft, req_pck,
1401 cur.dsi_pll_hsdiv_dispc_clk,
1404 if (abs(cur_dispc.pck - req_pck) <
1405 abs(best_dispc.pck - req_pck)) {
1407 best_dispc = cur_dispc;
1409 if (cur_dispc.pck == req_pck)
1417 if (min_fck_per_pck) {
1418 DSSERR("Could not find suitable clock settings.\n"
1419 "Turning FCK/PCK constraint off and"
1421 min_fck_per_pck = 0;
1425 DSSERR("Could not find suitable clock settings.\n");
1430 /* dsi_pll_hsdiv_dsi_clk (regm_dsi) is not used */
1432 best.dsi_pll_hsdiv_dsi_clk = 0;
1437 *dispc_cinfo = best_dispc;
1439 dsi->cache_req_pck = req_pck;
1440 dsi->cache_clk_freq = 0;
1441 dsi->cache_cinfo = best;
1446 int dsi_pll_set_clock_div(struct platform_device *dsidev,
1447 struct dsi_clock_info *cinfo)
1449 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1453 u8 regn_start, regn_end, regm_start, regm_end;
1454 u8 regm_dispc_start, regm_dispc_end, regm_dsi_start, regm_dsi_end;
1458 dsi->current_cinfo.use_sys_clk = cinfo->use_sys_clk;
1459 dsi->current_cinfo.highfreq = cinfo->highfreq;
1461 dsi->current_cinfo.fint = cinfo->fint;
1462 dsi->current_cinfo.clkin4ddr = cinfo->clkin4ddr;
1463 dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk =
1464 cinfo->dsi_pll_hsdiv_dispc_clk;
1465 dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk =
1466 cinfo->dsi_pll_hsdiv_dsi_clk;
1468 dsi->current_cinfo.regn = cinfo->regn;
1469 dsi->current_cinfo.regm = cinfo->regm;
1470 dsi->current_cinfo.regm_dispc = cinfo->regm_dispc;
1471 dsi->current_cinfo.regm_dsi = cinfo->regm_dsi;
1473 DSSDBG("DSI Fint %ld\n", cinfo->fint);
1475 DSSDBG("clkin (%s) rate %ld, highfreq %d\n",
1476 cinfo->use_sys_clk ? "dss_sys_clk" : "pclkfree",
1480 /* DSIPHY == CLKIN4DDR */
1481 DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu / %d = %lu\n",
1485 cinfo->highfreq + 1,
1488 DSSDBG("Data rate on 1 DSI lane %ld Mbps\n",
1489 cinfo->clkin4ddr / 1000 / 1000 / 2);
1491 DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4);
1493 DSSDBG("regm_dispc = %d, %s (%s) = %lu\n", cinfo->regm_dispc,
1494 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
1495 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
1496 cinfo->dsi_pll_hsdiv_dispc_clk);
1497 DSSDBG("regm_dsi = %d, %s (%s) = %lu\n", cinfo->regm_dsi,
1498 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
1499 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
1500 cinfo->dsi_pll_hsdiv_dsi_clk);
1502 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGN, ®n_start, ®n_end);
1503 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM, ®m_start, ®m_end);
1504 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DISPC, ®m_dispc_start,
1506 dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DSI, ®m_dsi_start,
1509 /* DSI_PLL_AUTOMODE = manual */
1510 REG_FLD_MOD(dsidev, DSI_PLL_CONTROL, 0, 0, 0);
1512 l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION1);
1513 l = FLD_MOD(l, 1, 0, 0); /* DSI_PLL_STOPMODE */
1515 l = FLD_MOD(l, cinfo->regn - 1, regn_start, regn_end);
1517 l = FLD_MOD(l, cinfo->regm, regm_start, regm_end);
1519 l = FLD_MOD(l, cinfo->regm_dispc > 0 ? cinfo->regm_dispc - 1 : 0,
1520 regm_dispc_start, regm_dispc_end);
1521 /* DSIPROTO_CLOCK_DIV */
1522 l = FLD_MOD(l, cinfo->regm_dsi > 0 ? cinfo->regm_dsi - 1 : 0,
1523 regm_dsi_start, regm_dsi_end);
1524 dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION1, l);
1526 BUG_ON(cinfo->fint < dsi->fint_min || cinfo->fint > dsi->fint_max);
1528 if (dss_has_feature(FEAT_DSI_PLL_FREQSEL)) {
1529 f = cinfo->fint < 1000000 ? 0x3 :
1530 cinfo->fint < 1250000 ? 0x4 :
1531 cinfo->fint < 1500000 ? 0x5 :
1532 cinfo->fint < 1750000 ? 0x6 :
1536 l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2);
1538 if (dss_has_feature(FEAT_DSI_PLL_FREQSEL))
1539 l = FLD_MOD(l, f, 4, 1); /* DSI_PLL_FREQSEL */
1540 l = FLD_MOD(l, cinfo->use_sys_clk ? 0 : 1,
1541 11, 11); /* DSI_PLL_CLKSEL */
1542 l = FLD_MOD(l, cinfo->highfreq,
1543 12, 12); /* DSI_PLL_HIGHFREQ */
1544 l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
1545 l = FLD_MOD(l, 0, 14, 14); /* DSIPHY_CLKINEN */
1546 l = FLD_MOD(l, 1, 20, 20); /* DSI_HSDIVBYPASS */
1547 dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l);
1549 REG_FLD_MOD(dsidev, DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */
1551 if (wait_for_bit_change(dsidev, DSI_PLL_GO, 0, 0) != 0) {
1552 DSSERR("dsi pll go bit not going down.\n");
1557 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1) {
1558 DSSERR("cannot lock PLL\n");
1563 dsi->pll_locked = 1;
1565 l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2);
1566 l = FLD_MOD(l, 0, 0, 0); /* DSI_PLL_IDLE */
1567 l = FLD_MOD(l, 0, 5, 5); /* DSI_PLL_PLLLPMODE */
1568 l = FLD_MOD(l, 0, 6, 6); /* DSI_PLL_LOWCURRSTBY */
1569 l = FLD_MOD(l, 0, 7, 7); /* DSI_PLL_TIGHTPHASELOCK */
1570 l = FLD_MOD(l, 0, 8, 8); /* DSI_PLL_DRIFTGUARDEN */
1571 l = FLD_MOD(l, 0, 10, 9); /* DSI_PLL_LOCKSEL */
1572 l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
1573 l = FLD_MOD(l, 1, 14, 14); /* DSIPHY_CLKINEN */
1574 l = FLD_MOD(l, 0, 15, 15); /* DSI_BYPASSEN */
1575 l = FLD_MOD(l, 1, 16, 16); /* DSS_CLOCK_EN */
1576 l = FLD_MOD(l, 0, 17, 17); /* DSS_CLOCK_PWDN */
1577 l = FLD_MOD(l, 1, 18, 18); /* DSI_PROTO_CLOCK_EN */
1578 l = FLD_MOD(l, 0, 19, 19); /* DSI_PROTO_CLOCK_PWDN */
1579 l = FLD_MOD(l, 0, 20, 20); /* DSI_HSDIVBYPASS */
1580 dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l);
1582 DSSDBG("PLL config done\n");
1587 int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk,
1590 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1592 enum dsi_pll_power_state pwstate;
1594 DSSDBG("PLL init\n");
1596 if (dsi->vdds_dsi_reg == NULL) {
1597 struct regulator *vdds_dsi;
1599 vdds_dsi = regulator_get(&dsi->pdev->dev, "vdds_dsi");
1601 if (IS_ERR(vdds_dsi)) {
1602 DSSERR("can't get VDDS_DSI regulator\n");
1603 return PTR_ERR(vdds_dsi);
1606 dsi->vdds_dsi_reg = vdds_dsi;
1609 dsi_enable_pll_clock(dsidev, 1);
1611 * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4.
1613 dsi_enable_scp_clk(dsidev);
1615 if (!dsi->vdds_dsi_enabled) {
1616 r = regulator_enable(dsi->vdds_dsi_reg);
1619 dsi->vdds_dsi_enabled = true;
1622 /* XXX PLL does not come out of reset without this... */
1623 dispc_pck_free_enable(1);
1625 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 0, 1) != 1) {
1626 DSSERR("PLL not coming out of reset.\n");
1628 dispc_pck_free_enable(0);
1632 /* XXX ... but if left on, we get problems when planes do not
1633 * fill the whole display. No idea about this */
1634 dispc_pck_free_enable(0);
1636 if (enable_hsclk && enable_hsdiv)
1637 pwstate = DSI_PLL_POWER_ON_ALL;
1638 else if (enable_hsclk)
1639 pwstate = DSI_PLL_POWER_ON_HSCLK;
1640 else if (enable_hsdiv)
1641 pwstate = DSI_PLL_POWER_ON_DIV;
1643 pwstate = DSI_PLL_POWER_OFF;
1645 r = dsi_pll_power(dsidev, pwstate);
1650 DSSDBG("PLL init done\n");
1654 if (dsi->vdds_dsi_enabled) {
1655 regulator_disable(dsi->vdds_dsi_reg);
1656 dsi->vdds_dsi_enabled = false;
1659 dsi_disable_scp_clk(dsidev);
1660 dsi_enable_pll_clock(dsidev, 0);
1664 void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes)
1666 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1668 dsi->pll_locked = 0;
1669 dsi_pll_power(dsidev, DSI_PLL_POWER_OFF);
1670 if (disconnect_lanes) {
1671 WARN_ON(!dsi->vdds_dsi_enabled);
1672 regulator_disable(dsi->vdds_dsi_reg);
1673 dsi->vdds_dsi_enabled = false;
1676 dsi_disable_scp_clk(dsidev);
1677 dsi_enable_pll_clock(dsidev, 0);
1679 DSSDBG("PLL uninit done\n");
1682 static void dsi_dump_dsidev_clocks(struct platform_device *dsidev,
1685 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1686 struct dsi_clock_info *cinfo = &dsi->current_cinfo;
1687 enum omap_dss_clk_source dispc_clk_src, dsi_clk_src;
1688 int dsi_module = dsi_get_dsidev_id(dsidev);
1690 dispc_clk_src = dss_get_dispc_clk_source();
1691 dsi_clk_src = dss_get_dsi_clk_source(dsi_module);
1693 if (dsi_runtime_get(dsidev))
1696 seq_printf(s, "- DSI%d PLL -\n", dsi_module + 1);
1698 seq_printf(s, "dsi pll source = %s\n",
1699 cinfo->use_sys_clk ? "dss_sys_clk" : "pclkfree");
1701 seq_printf(s, "Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn);
1703 seq_printf(s, "CLKIN4DDR\t%-16luregm %u\n",
1704 cinfo->clkin4ddr, cinfo->regm);
1706 seq_printf(s, "%s (%s)\t%-16luregm_dispc %u\t(%s)\n",
1707 dss_get_generic_clk_source_name(dispc_clk_src),
1708 dss_feat_get_clk_source_name(dispc_clk_src),
1709 cinfo->dsi_pll_hsdiv_dispc_clk,
1711 dispc_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1714 seq_printf(s, "%s (%s)\t%-16luregm_dsi %u\t(%s)\n",
1715 dss_get_generic_clk_source_name(dsi_clk_src),
1716 dss_feat_get_clk_source_name(dsi_clk_src),
1717 cinfo->dsi_pll_hsdiv_dsi_clk,
1719 dsi_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1722 seq_printf(s, "- DSI%d -\n", dsi_module + 1);
1724 seq_printf(s, "dsi fclk source = %s (%s)\n",
1725 dss_get_generic_clk_source_name(dsi_clk_src),
1726 dss_feat_get_clk_source_name(dsi_clk_src));
1728 seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsidev));
1730 seq_printf(s, "DDR_CLK\t\t%lu\n",
1731 cinfo->clkin4ddr / 4);
1733 seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsidev));
1735 seq_printf(s, "LP_CLK\t\t%lu\n", cinfo->lp_clk);
1737 dsi_runtime_put(dsidev);
1740 void dsi_dump_clocks(struct seq_file *s)
1742 struct platform_device *dsidev;
1745 for (i = 0; i < MAX_NUM_DSI; i++) {
1746 dsidev = dsi_get_dsidev_from_id(i);
1748 dsi_dump_dsidev_clocks(dsidev, s);
1752 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
1753 static void dsi_dump_dsidev_irqs(struct platform_device *dsidev,
1756 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1757 unsigned long flags;
1758 struct dsi_irq_stats stats;
1759 int dsi_module = dsi_get_dsidev_id(dsidev);
1761 spin_lock_irqsave(&dsi->irq_stats_lock, flags);
1763 stats = dsi->irq_stats;
1764 memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats));
1765 dsi->irq_stats.last_reset = jiffies;
1767 spin_unlock_irqrestore(&dsi->irq_stats_lock, flags);
1769 seq_printf(s, "period %u ms\n",
1770 jiffies_to_msecs(jiffies - stats.last_reset));
1772 seq_printf(s, "irqs %d\n", stats.irq_count);
1774 seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]);
1776 seq_printf(s, "-- DSI%d interrupts --\n", dsi_module + 1);
1792 PIS(LDO_POWER_GOOD);
1797 seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
1798 stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
1799 stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
1800 stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
1801 stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);
1803 seq_printf(s, "-- VC interrupts --\n");
1812 PIS(PP_BUSY_CHANGE);
1816 seq_printf(s, "%-20s %10d\n", #x, \
1817 stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);
1819 seq_printf(s, "-- CIO interrupts --\n");
1832 PIS(ERRCONTENTIONLP0_1);
1833 PIS(ERRCONTENTIONLP1_1);
1834 PIS(ERRCONTENTIONLP0_2);
1835 PIS(ERRCONTENTIONLP1_2);
1836 PIS(ERRCONTENTIONLP0_3);
1837 PIS(ERRCONTENTIONLP1_3);
1838 PIS(ULPSACTIVENOT_ALL0);
1839 PIS(ULPSACTIVENOT_ALL1);
1843 static void dsi1_dump_irqs(struct seq_file *s)
1845 struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
1847 dsi_dump_dsidev_irqs(dsidev, s);
1850 static void dsi2_dump_irqs(struct seq_file *s)
1852 struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
1854 dsi_dump_dsidev_irqs(dsidev, s);
1857 void dsi_create_debugfs_files_irq(struct dentry *debugfs_dir,
1858 const struct file_operations *debug_fops)
1860 struct platform_device *dsidev;
1862 dsidev = dsi_get_dsidev_from_id(0);
1864 debugfs_create_file("dsi1_irqs", S_IRUGO, debugfs_dir,
1865 &dsi1_dump_irqs, debug_fops);
1867 dsidev = dsi_get_dsidev_from_id(1);
1869 debugfs_create_file("dsi2_irqs", S_IRUGO, debugfs_dir,
1870 &dsi2_dump_irqs, debug_fops);
1874 static void dsi_dump_dsidev_regs(struct platform_device *dsidev,
1877 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsidev, r))
1879 if (dsi_runtime_get(dsidev))
1881 dsi_enable_scp_clk(dsidev);
1883 DUMPREG(DSI_REVISION);
1884 DUMPREG(DSI_SYSCONFIG);
1885 DUMPREG(DSI_SYSSTATUS);
1886 DUMPREG(DSI_IRQSTATUS);
1887 DUMPREG(DSI_IRQENABLE);
1889 DUMPREG(DSI_COMPLEXIO_CFG1);
1890 DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
1891 DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
1892 DUMPREG(DSI_CLK_CTRL);
1893 DUMPREG(DSI_TIMING1);
1894 DUMPREG(DSI_TIMING2);
1895 DUMPREG(DSI_VM_TIMING1);
1896 DUMPREG(DSI_VM_TIMING2);
1897 DUMPREG(DSI_VM_TIMING3);
1898 DUMPREG(DSI_CLK_TIMING);
1899 DUMPREG(DSI_TX_FIFO_VC_SIZE);
1900 DUMPREG(DSI_RX_FIFO_VC_SIZE);
1901 DUMPREG(DSI_COMPLEXIO_CFG2);
1902 DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
1903 DUMPREG(DSI_VM_TIMING4);
1904 DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
1905 DUMPREG(DSI_VM_TIMING5);
1906 DUMPREG(DSI_VM_TIMING6);
1907 DUMPREG(DSI_VM_TIMING7);
1908 DUMPREG(DSI_STOPCLK_TIMING);
1910 DUMPREG(DSI_VC_CTRL(0));
1911 DUMPREG(DSI_VC_TE(0));
1912 DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
1913 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
1914 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
1915 DUMPREG(DSI_VC_IRQSTATUS(0));
1916 DUMPREG(DSI_VC_IRQENABLE(0));
1918 DUMPREG(DSI_VC_CTRL(1));
1919 DUMPREG(DSI_VC_TE(1));
1920 DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
1921 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
1922 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
1923 DUMPREG(DSI_VC_IRQSTATUS(1));
1924 DUMPREG(DSI_VC_IRQENABLE(1));
1926 DUMPREG(DSI_VC_CTRL(2));
1927 DUMPREG(DSI_VC_TE(2));
1928 DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
1929 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
1930 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
1931 DUMPREG(DSI_VC_IRQSTATUS(2));
1932 DUMPREG(DSI_VC_IRQENABLE(2));
1934 DUMPREG(DSI_VC_CTRL(3));
1935 DUMPREG(DSI_VC_TE(3));
1936 DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
1937 DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
1938 DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
1939 DUMPREG(DSI_VC_IRQSTATUS(3));
1940 DUMPREG(DSI_VC_IRQENABLE(3));
1942 DUMPREG(DSI_DSIPHY_CFG0);
1943 DUMPREG(DSI_DSIPHY_CFG1);
1944 DUMPREG(DSI_DSIPHY_CFG2);
1945 DUMPREG(DSI_DSIPHY_CFG5);
1947 DUMPREG(DSI_PLL_CONTROL);
1948 DUMPREG(DSI_PLL_STATUS);
1949 DUMPREG(DSI_PLL_GO);
1950 DUMPREG(DSI_PLL_CONFIGURATION1);
1951 DUMPREG(DSI_PLL_CONFIGURATION2);
1953 dsi_disable_scp_clk(dsidev);
1954 dsi_runtime_put(dsidev);
1958 static void dsi1_dump_regs(struct seq_file *s)
1960 struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
1962 dsi_dump_dsidev_regs(dsidev, s);
1965 static void dsi2_dump_regs(struct seq_file *s)
1967 struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
1969 dsi_dump_dsidev_regs(dsidev, s);
1972 void dsi_create_debugfs_files_reg(struct dentry *debugfs_dir,
1973 const struct file_operations *debug_fops)
1975 struct platform_device *dsidev;
1977 dsidev = dsi_get_dsidev_from_id(0);
1979 debugfs_create_file("dsi1_regs", S_IRUGO, debugfs_dir,
1980 &dsi1_dump_regs, debug_fops);
1982 dsidev = dsi_get_dsidev_from_id(1);
1984 debugfs_create_file("dsi2_regs", S_IRUGO, debugfs_dir,
1985 &dsi2_dump_regs, debug_fops);
1987 enum dsi_cio_power_state {
1988 DSI_COMPLEXIO_POWER_OFF = 0x0,
1989 DSI_COMPLEXIO_POWER_ON = 0x1,
1990 DSI_COMPLEXIO_POWER_ULPS = 0x2,
1993 static int dsi_cio_power(struct platform_device *dsidev,
1994 enum dsi_cio_power_state state)
1999 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG1, state, 28, 27);
2002 while (FLD_GET(dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1),
2005 DSSERR("failed to set complexio power state to "
2015 /* Number of data lanes present on DSI interface */
2016 static inline int dsi_get_num_data_lanes(struct platform_device *dsidev)
2018 /* DSI on OMAP3 doesn't have register DSI_GNQ, set number
2019 * of data lanes as 2 by default */
2020 if (dss_has_feature(FEAT_DSI_GNQ))
2021 return REG_GET(dsidev, DSI_GNQ, 11, 9); /* NB_DATA_LANES */
2026 /* Number of data lanes used by the dss device */
2027 static inline int dsi_get_num_data_lanes_dssdev(struct omap_dss_device *dssdev)
2029 int num_data_lanes = 0;
2031 if (dssdev->phy.dsi.data1_lane != 0)
2033 if (dssdev->phy.dsi.data2_lane != 0)
2035 if (dssdev->phy.dsi.data3_lane != 0)
2037 if (dssdev->phy.dsi.data4_lane != 0)
2040 return num_data_lanes;
2043 static unsigned dsi_get_line_buf_size(struct platform_device *dsidev)
2047 /* line buffer on OMAP3 is 1024 x 24bits */
2048 /* XXX: for some reason using full buffer size causes
2049 * considerable TX slowdown with update sizes that fill the
2051 if (!dss_has_feature(FEAT_DSI_GNQ))
2054 val = REG_GET(dsidev, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */
2058 return 512 * 3; /* 512x24 bits */
2060 return 682 * 3; /* 682x24 bits */
2062 return 853 * 3; /* 853x24 bits */
2064 return 1024 * 3; /* 1024x24 bits */
2066 return 1194 * 3; /* 1194x24 bits */
2068 return 1365 * 3; /* 1365x24 bits */
2074 static void dsi_set_lane_config(struct omap_dss_device *dssdev)
2076 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2078 int num_data_lanes_dssdev = dsi_get_num_data_lanes_dssdev(dssdev);
2080 int clk_lane = dssdev->phy.dsi.clk_lane;
2081 int data1_lane = dssdev->phy.dsi.data1_lane;
2082 int data2_lane = dssdev->phy.dsi.data2_lane;
2083 int clk_pol = dssdev->phy.dsi.clk_pol;
2084 int data1_pol = dssdev->phy.dsi.data1_pol;
2085 int data2_pol = dssdev->phy.dsi.data2_pol;
2087 r = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1);
2088 r = FLD_MOD(r, clk_lane, 2, 0);
2089 r = FLD_MOD(r, clk_pol, 3, 3);
2090 r = FLD_MOD(r, data1_lane, 6, 4);
2091 r = FLD_MOD(r, data1_pol, 7, 7);
2092 r = FLD_MOD(r, data2_lane, 10, 8);
2093 r = FLD_MOD(r, data2_pol, 11, 11);
2094 if (num_data_lanes_dssdev > 2) {
2095 int data3_lane = dssdev->phy.dsi.data3_lane;
2096 int data3_pol = dssdev->phy.dsi.data3_pol;
2098 r = FLD_MOD(r, data3_lane, 14, 12);
2099 r = FLD_MOD(r, data3_pol, 15, 15);
2101 if (num_data_lanes_dssdev > 3) {
2102 int data4_lane = dssdev->phy.dsi.data4_lane;
2103 int data4_pol = dssdev->phy.dsi.data4_pol;
2105 r = FLD_MOD(r, data4_lane, 18, 16);
2106 r = FLD_MOD(r, data4_pol, 19, 19);
2108 dsi_write_reg(dsidev, DSI_COMPLEXIO_CFG1, r);
2110 /* The configuration of the DSI complex I/O (number of data lanes,
2111 position, differential order) should not be changed while
2112 DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. In order for
2113 the hardware to take into account a new configuration of the complex
2114 I/O (done in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to
2115 follow this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1,
2116 then reset the DSS.DSI_CTRL[0] IF_EN to 0, then set
2117 DSS.DSI_CLK_CTRL[20] LP_CLK_ENABLE to 1 and finally set again the
2118 DSS.DSI_CTRL[0] IF_EN bit to 1. If the sequence is not followed, the
2119 DSI complex I/O configuration is unknown. */
2122 REG_FLD_MOD(dsidev, DSI_CTRL, 1, 0, 0);
2123 REG_FLD_MOD(dsidev, DSI_CTRL, 0, 0, 0);
2124 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20);
2125 REG_FLD_MOD(dsidev, DSI_CTRL, 1, 0, 0);
2129 static inline unsigned ns2ddr(struct platform_device *dsidev, unsigned ns)
2131 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2133 /* convert time in ns to ddr ticks, rounding up */
2134 unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4;
2135 return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000;
2138 static inline unsigned ddr2ns(struct platform_device *dsidev, unsigned ddr)
2140 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2142 unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4;
2143 return ddr * 1000 * 1000 / (ddr_clk / 1000);
2146 static void dsi_cio_timings(struct platform_device *dsidev)
2149 u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
2150 u32 tlpx_half, tclk_trail, tclk_zero;
2153 /* calculate timings */
2155 /* 1 * DDR_CLK = 2 * UI */
2157 /* min 40ns + 4*UI max 85ns + 6*UI */
2158 ths_prepare = ns2ddr(dsidev, 70) + 2;
2160 /* min 145ns + 10*UI */
2161 ths_prepare_ths_zero = ns2ddr(dsidev, 175) + 2;
2163 /* min max(8*UI, 60ns+4*UI) */
2164 ths_trail = ns2ddr(dsidev, 60) + 5;
2167 ths_exit = ns2ddr(dsidev, 145);
2170 tlpx_half = ns2ddr(dsidev, 25);
2173 tclk_trail = ns2ddr(dsidev, 60) + 2;
2175 /* min 38ns, max 95ns */
2176 tclk_prepare = ns2ddr(dsidev, 65);
2178 /* min tclk-prepare + tclk-zero = 300ns */
2179 tclk_zero = ns2ddr(dsidev, 260);
2181 DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
2182 ths_prepare, ddr2ns(dsidev, ths_prepare),
2183 ths_prepare_ths_zero, ddr2ns(dsidev, ths_prepare_ths_zero));
2184 DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
2185 ths_trail, ddr2ns(dsidev, ths_trail),
2186 ths_exit, ddr2ns(dsidev, ths_exit));
2188 DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
2189 "tclk_zero %u (%uns)\n",
2190 tlpx_half, ddr2ns(dsidev, tlpx_half),
2191 tclk_trail, ddr2ns(dsidev, tclk_trail),
2192 tclk_zero, ddr2ns(dsidev, tclk_zero));
2193 DSSDBG("tclk_prepare %u (%uns)\n",
2194 tclk_prepare, ddr2ns(dsidev, tclk_prepare));
2196 /* program timings */
2198 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
2199 r = FLD_MOD(r, ths_prepare, 31, 24);
2200 r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
2201 r = FLD_MOD(r, ths_trail, 15, 8);
2202 r = FLD_MOD(r, ths_exit, 7, 0);
2203 dsi_write_reg(dsidev, DSI_DSIPHY_CFG0, r);
2205 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
2206 r = FLD_MOD(r, tlpx_half, 22, 16);
2207 r = FLD_MOD(r, tclk_trail, 15, 8);
2208 r = FLD_MOD(r, tclk_zero, 7, 0);
2209 dsi_write_reg(dsidev, DSI_DSIPHY_CFG1, r);
2211 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
2212 r = FLD_MOD(r, tclk_prepare, 7, 0);
2213 dsi_write_reg(dsidev, DSI_DSIPHY_CFG2, r);
2216 static void dsi_cio_enable_lane_override(struct omap_dss_device *dssdev,
2217 enum dsi_lane lanes)
2219 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2220 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2221 int clk_lane = dssdev->phy.dsi.clk_lane;
2222 int data1_lane = dssdev->phy.dsi.data1_lane;
2223 int data2_lane = dssdev->phy.dsi.data2_lane;
2224 int data3_lane = dssdev->phy.dsi.data3_lane;
2225 int data4_lane = dssdev->phy.dsi.data4_lane;
2226 int clk_pol = dssdev->phy.dsi.clk_pol;
2227 int data1_pol = dssdev->phy.dsi.data1_pol;
2228 int data2_pol = dssdev->phy.dsi.data2_pol;
2229 int data3_pol = dssdev->phy.dsi.data3_pol;
2230 int data4_pol = dssdev->phy.dsi.data4_pol;
2233 u8 lptxscp_start = dsi->num_data_lanes == 2 ? 22 : 26;
2235 if (lanes & DSI_CLK_P)
2236 l |= 1 << ((clk_lane - 1) * 2 + (clk_pol ? 0 : 1));
2237 if (lanes & DSI_CLK_N)
2238 l |= 1 << ((clk_lane - 1) * 2 + (clk_pol ? 1 : 0));
2240 if (lanes & DSI_DATA1_P)
2241 l |= 1 << ((data1_lane - 1) * 2 + (data1_pol ? 0 : 1));
2242 if (lanes & DSI_DATA1_N)
2243 l |= 1 << ((data1_lane - 1) * 2 + (data1_pol ? 1 : 0));
2245 if (lanes & DSI_DATA2_P)
2246 l |= 1 << ((data2_lane - 1) * 2 + (data2_pol ? 0 : 1));
2247 if (lanes & DSI_DATA2_N)
2248 l |= 1 << ((data2_lane - 1) * 2 + (data2_pol ? 1 : 0));
2250 if (lanes & DSI_DATA3_P)
2251 l |= 1 << ((data3_lane - 1) * 2 + (data3_pol ? 0 : 1));
2252 if (lanes & DSI_DATA3_N)
2253 l |= 1 << ((data3_lane - 1) * 2 + (data3_pol ? 1 : 0));
2255 if (lanes & DSI_DATA4_P)
2256 l |= 1 << ((data4_lane - 1) * 2 + (data4_pol ? 0 : 1));
2257 if (lanes & DSI_DATA4_N)
2258 l |= 1 << ((data4_lane - 1) * 2 + (data4_pol ? 1 : 0));
2260 * Bits in REGLPTXSCPDAT4TO0DXDY:
2268 /* Set the lane override configuration */
2270 /* REGLPTXSCPDAT4TO0DXDY */
2271 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, l, lptxscp_start, 17);
2273 /* Enable lane override */
2276 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 1, 27, 27);
2279 static void dsi_cio_disable_lane_override(struct platform_device *dsidev)
2281 /* Disable lane override */
2282 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */
2283 /* Reset the lane override configuration */
2284 /* REGLPTXSCPDAT4TO0DXDY */
2285 REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 22, 17);
2288 static int dsi_cio_wait_tx_clk_esc_reset(struct omap_dss_device *dssdev)
2290 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2295 if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) {
2309 if (dssdev->phy.dsi.clk_lane != 0)
2310 in_use[dssdev->phy.dsi.clk_lane - 1] = true;
2311 if (dssdev->phy.dsi.data1_lane != 0)
2312 in_use[dssdev->phy.dsi.data1_lane - 1] = true;
2313 if (dssdev->phy.dsi.data2_lane != 0)
2314 in_use[dssdev->phy.dsi.data2_lane - 1] = true;
2322 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2325 for (i = 0; i < 3; ++i) {
2326 if (!in_use[i] || (l & (1 << bits[i])))
2334 for (i = 0; i < 3; ++i) {
2335 if (!in_use[i] || (l & (1 << bits[i])))
2338 DSSERR("CIO TXCLKESC%d domain not coming " \
2339 "out of reset\n", i);
2348 static unsigned dsi_get_lane_mask(struct omap_dss_device *dssdev)
2352 if (dssdev->phy.dsi.clk_lane != 0)
2353 lanes |= 1 << (dssdev->phy.dsi.clk_lane - 1);
2354 if (dssdev->phy.dsi.data1_lane != 0)
2355 lanes |= 1 << (dssdev->phy.dsi.data1_lane - 1);
2356 if (dssdev->phy.dsi.data2_lane != 0)
2357 lanes |= 1 << (dssdev->phy.dsi.data2_lane - 1);
2358 if (dssdev->phy.dsi.data3_lane != 0)
2359 lanes |= 1 << (dssdev->phy.dsi.data3_lane - 1);
2360 if (dssdev->phy.dsi.data4_lane != 0)
2361 lanes |= 1 << (dssdev->phy.dsi.data4_lane - 1);
2366 static int dsi_cio_init(struct omap_dss_device *dssdev)
2368 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2369 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2371 int num_data_lanes_dssdev = dsi_get_num_data_lanes_dssdev(dssdev);
2376 r = dsi->enable_pads(dsidev->id, dsi_get_lane_mask(dssdev));
2380 dsi_enable_scp_clk(dsidev);
2382 /* A dummy read using the SCP interface to any DSIPHY register is
2383 * required after DSIPHY reset to complete the reset of the DSI complex
2385 dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2387 if (wait_for_bit_change(dsidev, DSI_DSIPHY_CFG5, 30, 1) != 1) {
2388 DSSERR("CIO SCP Clock domain not coming out of reset.\n");
2390 goto err_scp_clk_dom;
2393 dsi_set_lane_config(dssdev);
2395 /* set TX STOP MODE timer to maximum for this operation */
2396 l = dsi_read_reg(dsidev, DSI_TIMING1);
2397 l = FLD_MOD(l, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2398 l = FLD_MOD(l, 1, 14, 14); /* STOP_STATE_X16_IO */
2399 l = FLD_MOD(l, 1, 13, 13); /* STOP_STATE_X4_IO */
2400 l = FLD_MOD(l, 0x1fff, 12, 0); /* STOP_STATE_COUNTER_IO */
2401 dsi_write_reg(dsidev, DSI_TIMING1, l);
2403 if (dsi->ulps_enabled) {
2404 u32 lane_mask = DSI_CLK_P | DSI_DATA1_P | DSI_DATA2_P;
2406 DSSDBG("manual ulps exit\n");
2408 /* ULPS is exited by Mark-1 state for 1ms, followed by
2409 * stop state. DSS HW cannot do this via the normal
2410 * ULPS exit sequence, as after reset the DSS HW thinks
2411 * that we are not in ULPS mode, and refuses to send the
2412 * sequence. So we need to send the ULPS exit sequence
2416 if (num_data_lanes_dssdev > 2)
2417 lane_mask |= DSI_DATA3_P;
2419 if (num_data_lanes_dssdev > 3)
2420 lane_mask |= DSI_DATA4_P;
2422 dsi_cio_enable_lane_override(dssdev, lane_mask);
2425 r = dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ON);
2429 if (wait_for_bit_change(dsidev, DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
2430 DSSERR("CIO PWR clock domain not coming out of reset.\n");
2432 goto err_cio_pwr_dom;
2435 dsi_if_enable(dsidev, true);
2436 dsi_if_enable(dsidev, false);
2437 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
2439 r = dsi_cio_wait_tx_clk_esc_reset(dssdev);
2441 goto err_tx_clk_esc_rst;
2443 if (dsi->ulps_enabled) {
2444 /* Keep Mark-1 state for 1ms (as per DSI spec) */
2445 ktime_t wait = ns_to_ktime(1000 * 1000);
2446 set_current_state(TASK_UNINTERRUPTIBLE);
2447 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
2449 /* Disable the override. The lanes should be set to Mark-11
2450 * state by the HW */
2451 dsi_cio_disable_lane_override(dsidev);
2454 /* FORCE_TX_STOP_MODE_IO */
2455 REG_FLD_MOD(dsidev, DSI_TIMING1, 0, 15, 15);
2457 dsi_cio_timings(dsidev);
2459 dsi->ulps_enabled = false;
2461 DSSDBG("CIO init done\n");
2466 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */
2468 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2470 if (dsi->ulps_enabled)
2471 dsi_cio_disable_lane_override(dsidev);
2473 dsi_disable_scp_clk(dsidev);
2474 dsi->disable_pads(dsidev->id, dsi_get_lane_mask(dssdev));
2478 static void dsi_cio_uninit(struct omap_dss_device *dssdev)
2480 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2481 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2483 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2484 dsi_disable_scp_clk(dsidev);
2485 dsi->disable_pads(dsidev->id, dsi_get_lane_mask(dssdev));
2488 static void dsi_config_tx_fifo(struct platform_device *dsidev,
2489 enum fifo_size size1, enum fifo_size size2,
2490 enum fifo_size size3, enum fifo_size size4)
2492 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2497 dsi->vc[0].fifo_size = size1;
2498 dsi->vc[1].fifo_size = size2;
2499 dsi->vc[2].fifo_size = size3;
2500 dsi->vc[3].fifo_size = size4;
2502 for (i = 0; i < 4; i++) {
2504 int size = dsi->vc[i].fifo_size;
2506 if (add + size > 4) {
2507 DSSERR("Illegal FIFO configuration\n");
2511 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2513 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
2517 dsi_write_reg(dsidev, DSI_TX_FIFO_VC_SIZE, r);
2520 static void dsi_config_rx_fifo(struct platform_device *dsidev,
2521 enum fifo_size size1, enum fifo_size size2,
2522 enum fifo_size size3, enum fifo_size size4)
2524 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2529 dsi->vc[0].fifo_size = size1;
2530 dsi->vc[1].fifo_size = size2;
2531 dsi->vc[2].fifo_size = size3;
2532 dsi->vc[3].fifo_size = size4;
2534 for (i = 0; i < 4; i++) {
2536 int size = dsi->vc[i].fifo_size;
2538 if (add + size > 4) {
2539 DSSERR("Illegal FIFO configuration\n");
2543 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2545 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
2549 dsi_write_reg(dsidev, DSI_RX_FIFO_VC_SIZE, r);
2552 static int dsi_force_tx_stop_mode_io(struct platform_device *dsidev)
2556 r = dsi_read_reg(dsidev, DSI_TIMING1);
2557 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
2558 dsi_write_reg(dsidev, DSI_TIMING1, r);
2560 if (wait_for_bit_change(dsidev, DSI_TIMING1, 15, 0) != 0) {
2561 DSSERR("TX_STOP bit not going down\n");
2568 static bool dsi_vc_is_enabled(struct platform_device *dsidev, int channel)
2570 return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0);
2573 static void dsi_packet_sent_handler_vp(void *data, u32 mask)
2575 struct dsi_packet_sent_handler_data *vp_data =
2576 (struct dsi_packet_sent_handler_data *) data;
2577 struct dsi_data *dsi = dsi_get_dsidrv_data(vp_data->dsidev);
2578 const int channel = dsi->update_channel;
2579 u8 bit = dsi->te_enabled ? 30 : 31;
2581 if (REG_GET(vp_data->dsidev, DSI_VC_TE(channel), bit, bit) == 0)
2582 complete(vp_data->completion);
2585 static int dsi_sync_vc_vp(struct platform_device *dsidev, int channel)
2587 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2588 DECLARE_COMPLETION_ONSTACK(completion);
2589 struct dsi_packet_sent_handler_data vp_data = { dsidev, &completion };
2593 bit = dsi->te_enabled ? 30 : 31;
2595 r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2596 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2600 /* Wait for completion only if TE_EN/TE_START is still set */
2601 if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit)) {
2602 if (wait_for_completion_timeout(&completion,
2603 msecs_to_jiffies(10)) == 0) {
2604 DSSERR("Failed to complete previous frame transfer\n");
2610 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2611 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2615 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2616 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2621 static void dsi_packet_sent_handler_l4(void *data, u32 mask)
2623 struct dsi_packet_sent_handler_data *l4_data =
2624 (struct dsi_packet_sent_handler_data *) data;
2625 struct dsi_data *dsi = dsi_get_dsidrv_data(l4_data->dsidev);
2626 const int channel = dsi->update_channel;
2628 if (REG_GET(l4_data->dsidev, DSI_VC_CTRL(channel), 5, 5) == 0)
2629 complete(l4_data->completion);
2632 static int dsi_sync_vc_l4(struct platform_device *dsidev, int channel)
2634 DECLARE_COMPLETION_ONSTACK(completion);
2635 struct dsi_packet_sent_handler_data l4_data = { dsidev, &completion };
2638 r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2639 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2643 /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */
2644 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) {
2645 if (wait_for_completion_timeout(&completion,
2646 msecs_to_jiffies(10)) == 0) {
2647 DSSERR("Failed to complete previous l4 transfer\n");
2653 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2654 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2658 dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2659 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2664 static int dsi_sync_vc(struct platform_device *dsidev, int channel)
2666 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2668 WARN_ON(!dsi_bus_is_locked(dsidev));
2670 WARN_ON(in_interrupt());
2672 if (!dsi_vc_is_enabled(dsidev, channel))
2675 switch (dsi->vc[channel].source) {
2676 case DSI_VC_SOURCE_VP:
2677 return dsi_sync_vc_vp(dsidev, channel);
2678 case DSI_VC_SOURCE_L4:
2679 return dsi_sync_vc_l4(dsidev, channel);
2685 static int dsi_vc_enable(struct platform_device *dsidev, int channel,
2688 DSSDBG("dsi_vc_enable channel %d, enable %d\n",
2691 enable = enable ? 1 : 0;
2693 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 0, 0);
2695 if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel),
2696 0, enable) != enable) {
2697 DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
2704 static void dsi_vc_initial_config(struct platform_device *dsidev, int channel)
2708 DSSDBGF("%d", channel);
2710 r = dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
2712 if (FLD_GET(r, 15, 15)) /* VC_BUSY */
2713 DSSERR("VC(%d) busy when trying to configure it!\n",
2716 r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
2717 r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN */
2718 r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
2719 r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
2720 r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
2721 r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
2722 r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
2723 if (dss_has_feature(FEAT_DSI_VC_OCP_WIDTH))
2724 r = FLD_MOD(r, 3, 11, 10); /* OCP_WIDTH = 32 bit */
2726 r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
2727 r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
2729 dsi_write_reg(dsidev, DSI_VC_CTRL(channel), r);
2732 static int dsi_vc_config_source(struct platform_device *dsidev, int channel,
2733 enum dsi_vc_source source)
2735 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2737 if (dsi->vc[channel].source == source)
2740 DSSDBGF("%d", channel);
2742 dsi_sync_vc(dsidev, channel);
2744 dsi_vc_enable(dsidev, channel, 0);
2747 if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 15, 0) != 0) {
2748 DSSERR("vc(%d) busy when trying to config for VP\n", channel);
2752 /* SOURCE, 0 = L4, 1 = video port */
2753 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), source, 1, 1);
2755 /* DCS_CMD_ENABLE */
2756 if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
2757 bool enable = source == DSI_VC_SOURCE_VP;
2758 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 30, 30);
2761 dsi_vc_enable(dsidev, channel, 1);
2763 dsi->vc[channel].source = source;
2768 void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
2771 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2773 DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
2775 WARN_ON(!dsi_bus_is_locked(dsidev));
2777 dsi_vc_enable(dsidev, channel, 0);
2778 dsi_if_enable(dsidev, 0);
2780 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 9, 9);
2782 dsi_vc_enable(dsidev, channel, 1);
2783 dsi_if_enable(dsidev, 1);
2785 dsi_force_tx_stop_mode_io(dsidev);
2787 EXPORT_SYMBOL(omapdss_dsi_vc_enable_hs);
2789 static void dsi_vc_flush_long_data(struct platform_device *dsidev, int channel)
2791 while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2793 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2794 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
2798 (val >> 24) & 0xff);
2802 static void dsi_show_rx_ack_with_err(u16 err)
2804 DSSERR("\tACK with ERROR (%#x):\n", err);
2806 DSSERR("\t\tSoT Error\n");
2808 DSSERR("\t\tSoT Sync Error\n");
2810 DSSERR("\t\tEoT Sync Error\n");
2812 DSSERR("\t\tEscape Mode Entry Command Error\n");
2814 DSSERR("\t\tLP Transmit Sync Error\n");
2816 DSSERR("\t\tHS Receive Timeout Error\n");
2818 DSSERR("\t\tFalse Control Error\n");
2820 DSSERR("\t\t(reserved7)\n");
2822 DSSERR("\t\tECC Error, single-bit (corrected)\n");
2824 DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
2825 if (err & (1 << 10))
2826 DSSERR("\t\tChecksum Error\n");
2827 if (err & (1 << 11))
2828 DSSERR("\t\tData type not recognized\n");
2829 if (err & (1 << 12))
2830 DSSERR("\t\tInvalid VC ID\n");
2831 if (err & (1 << 13))
2832 DSSERR("\t\tInvalid Transmission Length\n");
2833 if (err & (1 << 14))
2834 DSSERR("\t\t(reserved14)\n");
2835 if (err & (1 << 15))
2836 DSSERR("\t\tDSI Protocol Violation\n");
2839 static u16 dsi_vc_flush_receive_data(struct platform_device *dsidev,
2842 /* RX_FIFO_NOT_EMPTY */
2843 while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2846 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2847 DSSERR("\trawval %#08x\n", val);
2848 dt = FLD_GET(val, 5, 0);
2849 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
2850 u16 err = FLD_GET(val, 23, 8);
2851 dsi_show_rx_ack_with_err(err);
2852 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE) {
2853 DSSERR("\tDCS short response, 1 byte: %#x\n",
2854 FLD_GET(val, 23, 8));
2855 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE) {
2856 DSSERR("\tDCS short response, 2 byte: %#x\n",
2857 FLD_GET(val, 23, 8));
2858 } else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) {
2859 DSSERR("\tDCS long response, len %d\n",
2860 FLD_GET(val, 23, 8));
2861 dsi_vc_flush_long_data(dsidev, channel);
2863 DSSERR("\tunknown datatype 0x%02x\n", dt);
2869 static int dsi_vc_send_bta(struct platform_device *dsidev, int channel)
2871 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2873 if (dsi->debug_write || dsi->debug_read)
2874 DSSDBG("dsi_vc_send_bta %d\n", channel);
2876 WARN_ON(!dsi_bus_is_locked(dsidev));
2878 /* RX_FIFO_NOT_EMPTY */
2879 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2880 DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
2881 dsi_vc_flush_receive_data(dsidev, channel);
2884 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
2889 int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel)
2891 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2892 DECLARE_COMPLETION_ONSTACK(completion);
2896 r = dsi_register_isr_vc(dsidev, channel, dsi_completion_handler,
2897 &completion, DSI_VC_IRQ_BTA);
2901 r = dsi_register_isr(dsidev, dsi_completion_handler, &completion,
2902 DSI_IRQ_ERROR_MASK);
2906 r = dsi_vc_send_bta(dsidev, channel);
2910 if (wait_for_completion_timeout(&completion,
2911 msecs_to_jiffies(500)) == 0) {
2912 DSSERR("Failed to receive BTA\n");
2917 err = dsi_get_errors(dsidev);
2919 DSSERR("Error while sending BTA: %x\n", err);
2924 dsi_unregister_isr(dsidev, dsi_completion_handler, &completion,
2925 DSI_IRQ_ERROR_MASK);
2927 dsi_unregister_isr_vc(dsidev, channel, dsi_completion_handler,
2928 &completion, DSI_VC_IRQ_BTA);
2932 EXPORT_SYMBOL(dsi_vc_send_bta_sync);
2934 static inline void dsi_vc_write_long_header(struct platform_device *dsidev,
2935 int channel, u8 data_type, u16 len, u8 ecc)
2937 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2941 WARN_ON(!dsi_bus_is_locked(dsidev));
2943 data_id = data_type | dsi->vc[channel].vc_id << 6;
2945 val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
2946 FLD_VAL(ecc, 31, 24);
2948 dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_HEADER(channel), val);
2951 static inline void dsi_vc_write_long_payload(struct platform_device *dsidev,
2952 int channel, u8 b1, u8 b2, u8 b3, u8 b4)
2956 val = b4 << 24 | b3 << 16 | b2 << 8 | b1 << 0;
2958 /* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
2959 b1, b2, b3, b4, val); */
2961 dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
2964 static int dsi_vc_send_long(struct platform_device *dsidev, int channel,
2965 u8 data_type, u8 *data, u16 len, u8 ecc)
2968 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2974 if (dsi->debug_write)
2975 DSSDBG("dsi_vc_send_long, %d bytes\n", len);
2978 if (dsi->vc[channel].fifo_size * 32 * 4 < len + 4) {
2979 DSSERR("unable to send long packet: packet too long.\n");
2983 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
2985 dsi_vc_write_long_header(dsidev, channel, data_type, len, ecc);
2988 for (i = 0; i < len >> 2; i++) {
2989 if (dsi->debug_write)
2990 DSSDBG("\tsending full packet %d\n", i);
2997 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, b4);
3002 b1 = 0; b2 = 0; b3 = 0;
3004 if (dsi->debug_write)
3005 DSSDBG("\tsending remainder bytes %d\n", i);
3022 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, 0);
3028 static int dsi_vc_send_short(struct platform_device *dsidev, int channel,
3029 u8 data_type, u16 data, u8 ecc)
3031 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3035 WARN_ON(!dsi_bus_is_locked(dsidev));
3037 if (dsi->debug_write)
3038 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
3040 data_type, data & 0xff, (data >> 8) & 0xff);
3042 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
3044 if (FLD_GET(dsi_read_reg(dsidev, DSI_VC_CTRL(channel)), 16, 16)) {
3045 DSSERR("ERROR FIFO FULL, aborting transfer\n");
3049 data_id = data_type | dsi->vc[channel].vc_id << 6;
3051 r = (data_id << 0) | (data << 8) | (ecc << 24);
3053 dsi_write_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel), r);
3058 int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel)
3060 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3061 u8 nullpkg[] = {0, 0, 0, 0};
3063 return dsi_vc_send_long(dsidev, channel, MIPI_DSI_NULL_PACKET, nullpkg,
3066 EXPORT_SYMBOL(dsi_vc_send_null);
3068 static int dsi_vc_write_nosync_common(struct omap_dss_device *dssdev,
3069 int channel, u8 *data, int len, enum dss_dsi_content_type type)
3071 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3075 BUG_ON(type == DSS_DSI_CONTENT_DCS);
3076 r = dsi_vc_send_short(dsidev, channel,
3077 MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM, 0, 0);
3078 } else if (len == 1) {
3079 r = dsi_vc_send_short(dsidev, channel,
3080 type == DSS_DSI_CONTENT_GENERIC ?
3081 MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM :
3082 MIPI_DSI_DCS_SHORT_WRITE, data[0], 0);
3083 } else if (len == 2) {
3084 r = dsi_vc_send_short(dsidev, channel,
3085 type == DSS_DSI_CONTENT_GENERIC ?
3086 MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM :
3087 MIPI_DSI_DCS_SHORT_WRITE_PARAM,
3088 data[0] | (data[1] << 8), 0);
3090 r = dsi_vc_send_long(dsidev, channel,
3091 type == DSS_DSI_CONTENT_GENERIC ?
3092 MIPI_DSI_GENERIC_LONG_WRITE :
3093 MIPI_DSI_DCS_LONG_WRITE, data, len, 0);
3099 int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
3102 return dsi_vc_write_nosync_common(dssdev, channel, data, len,
3103 DSS_DSI_CONTENT_DCS);
3105 EXPORT_SYMBOL(dsi_vc_dcs_write_nosync);
3107 int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel,
3110 return dsi_vc_write_nosync_common(dssdev, channel, data, len,
3111 DSS_DSI_CONTENT_GENERIC);
3113 EXPORT_SYMBOL(dsi_vc_generic_write_nosync);
3115 static int dsi_vc_write_common(struct omap_dss_device *dssdev, int channel,
3116 u8 *data, int len, enum dss_dsi_content_type type)
3118 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3121 r = dsi_vc_write_nosync_common(dssdev, channel, data, len, type);
3125 r = dsi_vc_send_bta_sync(dssdev, channel);
3129 /* RX_FIFO_NOT_EMPTY */
3130 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
3131 DSSERR("rx fifo not empty after write, dumping data:\n");
3132 dsi_vc_flush_receive_data(dsidev, channel);
3139 DSSERR("dsi_vc_write_common(ch %d, cmd 0x%02x, len %d) failed\n",
3140 channel, data[0], len);
3144 int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
3147 return dsi_vc_write_common(dssdev, channel, data, len,
3148 DSS_DSI_CONTENT_DCS);
3150 EXPORT_SYMBOL(dsi_vc_dcs_write);
3152 int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data,
3155 return dsi_vc_write_common(dssdev, channel, data, len,
3156 DSS_DSI_CONTENT_GENERIC);
3158 EXPORT_SYMBOL(dsi_vc_generic_write);
3160 int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd)
3162 return dsi_vc_dcs_write(dssdev, channel, &dcs_cmd, 1);
3164 EXPORT_SYMBOL(dsi_vc_dcs_write_0);
3166 int dsi_vc_generic_write_0(struct omap_dss_device *dssdev, int channel)
3168 return dsi_vc_generic_write(dssdev, channel, NULL, 0);
3170 EXPORT_SYMBOL(dsi_vc_generic_write_0);
3172 int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3178 return dsi_vc_dcs_write(dssdev, channel, buf, 2);
3180 EXPORT_SYMBOL(dsi_vc_dcs_write_1);
3182 int dsi_vc_generic_write_1(struct omap_dss_device *dssdev, int channel,
3185 return dsi_vc_generic_write(dssdev, channel, ¶m, 1);
3187 EXPORT_SYMBOL(dsi_vc_generic_write_1);
3189 int dsi_vc_generic_write_2(struct omap_dss_device *dssdev, int channel,
3190 u8 param1, u8 param2)
3195 return dsi_vc_generic_write(dssdev, channel, buf, 2);
3197 EXPORT_SYMBOL(dsi_vc_generic_write_2);
3199 static int dsi_vc_dcs_send_read_request(struct omap_dss_device *dssdev,
3200 int channel, u8 dcs_cmd)
3202 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3203 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3206 if (dsi->debug_read)
3207 DSSDBG("dsi_vc_dcs_send_read_request(ch%d, dcs_cmd %x)\n",
3210 r = dsi_vc_send_short(dsidev, channel, MIPI_DSI_DCS_READ, dcs_cmd, 0);
3212 DSSERR("dsi_vc_dcs_send_read_request(ch %d, cmd 0x%02x)"
3213 " failed\n", channel, dcs_cmd);
3220 static int dsi_vc_generic_send_read_request(struct omap_dss_device *dssdev,
3221 int channel, u8 *reqdata, int reqlen)
3223 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3224 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3229 if (dsi->debug_read)
3230 DSSDBG("dsi_vc_generic_send_read_request(ch %d, reqlen %d)\n",
3234 data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM;
3236 } else if (reqlen == 1) {
3237 data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM;
3239 } else if (reqlen == 2) {
3240 data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM;
3241 data = reqdata[0] | (reqdata[1] << 8);
3246 r = dsi_vc_send_short(dsidev, channel, data_type, data, 0);
3248 DSSERR("dsi_vc_generic_send_read_request(ch %d, reqlen %d)"
3249 " failed\n", channel, reqlen);
3256 static int dsi_vc_read_rx_fifo(struct platform_device *dsidev, int channel,
3257 u8 *buf, int buflen, enum dss_dsi_content_type type)
3259 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3264 /* RX_FIFO_NOT_EMPTY */
3265 if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20) == 0) {
3266 DSSERR("RX fifo empty when trying to read.\n");
3271 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
3272 if (dsi->debug_read)
3273 DSSDBG("\theader: %08x\n", val);
3274 dt = FLD_GET(val, 5, 0);
3275 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
3276 u16 err = FLD_GET(val, 23, 8);
3277 dsi_show_rx_ack_with_err(err);
3281 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3282 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE :
3283 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE)) {
3284 u8 data = FLD_GET(val, 15, 8);
3285 if (dsi->debug_read)
3286 DSSDBG("\t%s short response, 1 byte: %02x\n",
3287 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3298 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3299 MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE :
3300 MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE)) {
3301 u16 data = FLD_GET(val, 23, 8);
3302 if (dsi->debug_read)
3303 DSSDBG("\t%s short response, 2 byte: %04x\n",
3304 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3312 buf[0] = data & 0xff;
3313 buf[1] = (data >> 8) & 0xff;
3316 } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3317 MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE :
3318 MIPI_DSI_RX_DCS_LONG_READ_RESPONSE)) {
3320 int len = FLD_GET(val, 23, 8);
3321 if (dsi->debug_read)
3322 DSSDBG("\t%s long response, len %d\n",
3323 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3331 /* two byte checksum ends the packet, not included in len */
3332 for (w = 0; w < len + 2;) {
3334 val = dsi_read_reg(dsidev,
3335 DSI_VC_SHORT_PACKET_HEADER(channel));
3336 if (dsi->debug_read)
3337 DSSDBG("\t\t%02x %02x %02x %02x\n",
3341 (val >> 24) & 0xff);
3343 for (b = 0; b < 4; ++b) {
3345 buf[w] = (val >> (b * 8)) & 0xff;
3346 /* we discard the 2 byte checksum */
3353 DSSERR("\tunknown datatype 0x%02x\n", dt);
3360 DSSERR("dsi_vc_read_rx_fifo(ch %d type %s) failed\n", channel,
3361 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : "DCS");
3366 int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3367 u8 *buf, int buflen)
3369 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3372 r = dsi_vc_dcs_send_read_request(dssdev, channel, dcs_cmd);
3376 r = dsi_vc_send_bta_sync(dssdev, channel);
3380 r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
3381 DSS_DSI_CONTENT_DCS);
3392 DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", channel, dcs_cmd);
3395 EXPORT_SYMBOL(dsi_vc_dcs_read);
3397 static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int channel,
3398 u8 *reqdata, int reqlen, u8 *buf, int buflen)
3400 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3403 r = dsi_vc_generic_send_read_request(dssdev, channel, reqdata, reqlen);
3407 r = dsi_vc_send_bta_sync(dssdev, channel);
3411 r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
3412 DSS_DSI_CONTENT_GENERIC);
3424 int dsi_vc_generic_read_0(struct omap_dss_device *dssdev, int channel, u8 *buf,
3429 r = dsi_vc_generic_read(dssdev, channel, NULL, 0, buf, buflen);
3431 DSSERR("dsi_vc_generic_read_0(ch %d) failed\n", channel);
3437 EXPORT_SYMBOL(dsi_vc_generic_read_0);
3439 int dsi_vc_generic_read_1(struct omap_dss_device *dssdev, int channel, u8 param,
3440 u8 *buf, int buflen)
3444 r = dsi_vc_generic_read(dssdev, channel, ¶m, 1, buf, buflen);
3446 DSSERR("dsi_vc_generic_read_1(ch %d) failed\n", channel);
3452 EXPORT_SYMBOL(dsi_vc_generic_read_1);
3454 int dsi_vc_generic_read_2(struct omap_dss_device *dssdev, int channel,
3455 u8 param1, u8 param2, u8 *buf, int buflen)
3460 reqdata[0] = param1;
3461 reqdata[1] = param2;
3463 r = dsi_vc_generic_read(dssdev, channel, reqdata, 2, buf, buflen);
3465 DSSERR("dsi_vc_generic_read_2(ch %d) failed\n", channel);
3471 EXPORT_SYMBOL(dsi_vc_generic_read_2);
3473 int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
3476 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3478 return dsi_vc_send_short(dsidev, channel,
3479 MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0);
3481 EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size);
3483 static int dsi_enter_ulps(struct platform_device *dsidev)
3485 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3486 DECLARE_COMPLETION_ONSTACK(completion);
3491 WARN_ON(!dsi_bus_is_locked(dsidev));
3493 WARN_ON(dsi->ulps_enabled);
3495 if (dsi->ulps_enabled)
3498 if (REG_GET(dsidev, DSI_CLK_CTRL, 13, 13)) {
3499 DSSERR("DDR_CLK_ALWAYS_ON enabled when entering ULPS\n");
3503 dsi_sync_vc(dsidev, 0);
3504 dsi_sync_vc(dsidev, 1);
3505 dsi_sync_vc(dsidev, 2);
3506 dsi_sync_vc(dsidev, 3);
3508 dsi_force_tx_stop_mode_io(dsidev);
3510 dsi_vc_enable(dsidev, 0, false);
3511 dsi_vc_enable(dsidev, 1, false);
3512 dsi_vc_enable(dsidev, 2, false);
3513 dsi_vc_enable(dsidev, 3, false);
3515 if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 16, 16)) { /* HS_BUSY */
3516 DSSERR("HS busy when enabling ULPS\n");
3520 if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 17, 17)) { /* LP_BUSY */
3521 DSSERR("LP busy when enabling ULPS\n");
3525 r = dsi_register_isr_cio(dsidev, dsi_completion_handler, &completion,
3526 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3530 /* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */
3531 /* LANEx_ULPS_SIG2 */
3532 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, (1 << 0) | (1 << 1) | (1 << 2),
3535 if (wait_for_completion_timeout(&completion,
3536 msecs_to_jiffies(1000)) == 0) {
3537 DSSERR("ULPS enable timeout\n");
3542 dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3543 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3545 /* Reset LANEx_ULPS_SIG2 */
3546 REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, (0 << 0) | (0 << 1) | (0 << 2),
3549 dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ULPS);
3551 dsi_if_enable(dsidev, false);
3553 dsi->ulps_enabled = true;
3558 dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3559 DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3563 static void dsi_set_lp_rx_timeout(struct platform_device *dsidev,
3564 unsigned ticks, bool x4, bool x16)
3567 unsigned long total_ticks;
3570 BUG_ON(ticks > 0x1fff);
3572 /* ticks in DSI_FCK */
3573 fck = dsi_fclk_rate(dsidev);
3575 r = dsi_read_reg(dsidev, DSI_TIMING2);
3576 r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */
3577 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */
3578 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */
3579 r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */
3580 dsi_write_reg(dsidev, DSI_TIMING2, r);
3582 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3584 DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3586 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3587 (total_ticks * 1000) / (fck / 1000 / 1000));
3590 static void dsi_set_ta_timeout(struct platform_device *dsidev, unsigned ticks,
3594 unsigned long total_ticks;
3597 BUG_ON(ticks > 0x1fff);
3599 /* ticks in DSI_FCK */
3600 fck = dsi_fclk_rate(dsidev);
3602 r = dsi_read_reg(dsidev, DSI_TIMING1);
3603 r = FLD_MOD(r, 1, 31, 31); /* TA_TO */
3604 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */
3605 r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */
3606 r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */
3607 dsi_write_reg(dsidev, DSI_TIMING1, r);
3609 total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1);
3611 DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n",
3613 ticks, x8 ? " x8" : "", x16 ? " x16" : "",
3614 (total_ticks * 1000) / (fck / 1000 / 1000));
3617 static void dsi_set_stop_state_counter(struct platform_device *dsidev,
3618 unsigned ticks, bool x4, bool x16)
3621 unsigned long total_ticks;
3624 BUG_ON(ticks > 0x1fff);
3626 /* ticks in DSI_FCK */
3627 fck = dsi_fclk_rate(dsidev);
3629 r = dsi_read_reg(dsidev, DSI_TIMING1);
3630 r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
3631 r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */
3632 r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */
3633 r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */
3634 dsi_write_reg(dsidev, DSI_TIMING1, r);
3636 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3638 DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n",
3640 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3641 (total_ticks * 1000) / (fck / 1000 / 1000));
3644 static void dsi_set_hs_tx_timeout(struct platform_device *dsidev,
3645 unsigned ticks, bool x4, bool x16)
3648 unsigned long total_ticks;
3651 BUG_ON(ticks > 0x1fff);
3653 /* ticks in TxByteClkHS */
3654 fck = dsi_get_txbyteclkhs(dsidev);
3656 r = dsi_read_reg(dsidev, DSI_TIMING2);
3657 r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */
3658 r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */
3659 r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */
3660 r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */
3661 dsi_write_reg(dsidev, DSI_TIMING2, r);
3663 total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3665 DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3667 ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3668 (total_ticks * 1000) / (fck / 1000 / 1000));
3670 static int dsi_proto_config(struct omap_dss_device *dssdev)
3672 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3676 dsi_config_tx_fifo(dsidev, DSI_FIFO_SIZE_32,
3681 dsi_config_rx_fifo(dsidev, DSI_FIFO_SIZE_32,
3686 /* XXX what values for the timeouts? */
3687 dsi_set_stop_state_counter(dsidev, 0x1000, false, false);
3688 dsi_set_ta_timeout(dsidev, 0x1fff, true, true);
3689 dsi_set_lp_rx_timeout(dsidev, 0x1fff, true, true);
3690 dsi_set_hs_tx_timeout(dsidev, 0x1fff, true, true);
3692 switch (dssdev->ctrl.pixel_size) {
3706 r = dsi_read_reg(dsidev, DSI_CTRL);
3707 r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */
3708 r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */
3709 r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */
3710 r = FLD_MOD(r, 1, 4, 4); /* VP_CLK_RATIO, always 1, see errata*/
3711 r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
3712 r = FLD_MOD(r, 0, 8, 8); /* VP_CLK_POL */
3713 r = FLD_MOD(r, 2, 13, 12); /* LINE_BUFFER, 2 lines */
3714 r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */
3715 r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */
3716 if (!dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
3717 r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */
3718 /* DCS_CMD_CODE, 1=start, 0=continue */
3719 r = FLD_MOD(r, 0, 25, 25);
3722 dsi_write_reg(dsidev, DSI_CTRL, r);
3724 dsi_vc_initial_config(dsidev, 0);
3725 dsi_vc_initial_config(dsidev, 1);
3726 dsi_vc_initial_config(dsidev, 2);
3727 dsi_vc_initial_config(dsidev, 3);
3732 static void dsi_proto_timings(struct omap_dss_device *dssdev)
3734 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3735 unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail;
3736 unsigned tclk_pre, tclk_post;
3737 unsigned ths_prepare, ths_prepare_ths_zero, ths_zero;
3738 unsigned ths_trail, ths_exit;
3739 unsigned ddr_clk_pre, ddr_clk_post;
3740 unsigned enter_hs_mode_lat, exit_hs_mode_lat;
3744 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
3745 ths_prepare = FLD_GET(r, 31, 24);
3746 ths_prepare_ths_zero = FLD_GET(r, 23, 16);
3747 ths_zero = ths_prepare_ths_zero - ths_prepare;
3748 ths_trail = FLD_GET(r, 15, 8);
3749 ths_exit = FLD_GET(r, 7, 0);
3751 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
3752 tlpx = FLD_GET(r, 22, 16) * 2;
3753 tclk_trail = FLD_GET(r, 15, 8);
3754 tclk_zero = FLD_GET(r, 7, 0);
3756 r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
3757 tclk_prepare = FLD_GET(r, 7, 0);
3761 /* min 60ns + 52*UI */
3762 tclk_post = ns2ddr(dsidev, 60) + 26;
3764 ths_eot = DIV_ROUND_UP(4, dsi_get_num_data_lanes_dssdev(dssdev));
3766 ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
3768 ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot;
3770 BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
3771 BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);
3773 r = dsi_read_reg(dsidev, DSI_CLK_TIMING);
3774 r = FLD_MOD(r, ddr_clk_pre, 15, 8);
3775 r = FLD_MOD(r, ddr_clk_post, 7, 0);
3776 dsi_write_reg(dsidev, DSI_CLK_TIMING, r);
3778 DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
3782 enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) +
3783 DIV_ROUND_UP(ths_prepare, 4) +
3784 DIV_ROUND_UP(ths_zero + 3, 4);
3786 exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;
3788 r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
3789 FLD_VAL(exit_hs_mode_lat, 15, 0);
3790 dsi_write_reg(dsidev, DSI_VM_TIMING7, r);
3792 DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
3793 enter_hs_mode_lat, exit_hs_mode_lat);
3796 static void dsi_update_screen_dispc(struct omap_dss_device *dssdev,
3797 u16 x, u16 y, u16 w, u16 h)
3799 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3800 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3805 unsigned packet_payload;
3806 unsigned packet_len;
3809 const unsigned channel = dsi->update_channel;
3810 const unsigned line_buf_size = dsi_get_line_buf_size(dsidev);
3812 DSSDBG("dsi_update_screen_dispc(%d,%d %dx%d)\n",
3815 dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_VP);
3817 bytespp = dssdev->ctrl.pixel_size / 8;
3818 bytespl = w * bytespp;
3819 bytespf = bytespl * h;
3821 /* NOTE: packet_payload has to be equal to N * bytespl, where N is
3822 * number of lines in a packet. See errata about VP_CLK_RATIO */
3824 if (bytespf < line_buf_size)
3825 packet_payload = bytespf;
3827 packet_payload = (line_buf_size) / bytespl * bytespl;
3829 packet_len = packet_payload + 1; /* 1 byte for DCS cmd */
3830 total_len = (bytespf / packet_payload) * packet_len;
3832 if (bytespf % packet_payload)
3833 total_len += (bytespf % packet_payload) + 1;
3835 l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
3836 dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
3838 dsi_vc_write_long_header(dsidev, channel, MIPI_DSI_DCS_LONG_WRITE,
3841 if (dsi->te_enabled)
3842 l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
3844 l = FLD_MOD(l, 1, 31, 31); /* TE_START */
3845 dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
3847 /* We put SIDLEMODE to no-idle for the duration of the transfer,
3848 * because DSS interrupts are not capable of waking up the CPU and the
3849 * framedone interrupt could be delayed for quite a long time. I think
3850 * the same goes for any DSS interrupts, but for some reason I have not
3851 * seen the problem anywhere else than here.
3853 dispc_disable_sidle();
3855 dsi_perf_mark_start(dsidev);
3857 r = schedule_delayed_work(&dsi->framedone_timeout_work,
3858 msecs_to_jiffies(250));
3861 dss_start_update(dssdev);
3863 if (dsi->te_enabled) {
3864 /* disable LP_RX_TO, so that we can receive TE. Time to wait
3865 * for TE is longer than the timer allows */
3866 REG_FLD_MOD(dsidev, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
3868 dsi_vc_send_bta(dsidev, channel);
3870 #ifdef DSI_CATCH_MISSING_TE
3871 mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250));
3876 #ifdef DSI_CATCH_MISSING_TE
3877 static void dsi_te_timeout(unsigned long arg)
3879 DSSERR("TE not received for 250ms!\n");
3883 static void dsi_handle_framedone(struct platform_device *dsidev, int error)
3885 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3887 /* SIDLEMODE back to smart-idle */
3888 dispc_enable_sidle();
3890 if (dsi->te_enabled) {
3891 /* enable LP_RX_TO again after the TE */
3892 REG_FLD_MOD(dsidev, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
3895 dsi->framedone_callback(error, dsi->framedone_data);
3898 dsi_perf_show(dsidev, "DISPC");
3901 static void dsi_framedone_timeout_work_callback(struct work_struct *work)
3903 struct dsi_data *dsi = container_of(work, struct dsi_data,
3904 framedone_timeout_work.work);
3905 /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after
3906 * 250ms which would conflict with this timeout work. What should be
3907 * done is first cancel the transfer on the HW, and then cancel the
3908 * possibly scheduled framedone work. However, cancelling the transfer
3909 * on the HW is buggy, and would probably require resetting the whole
3912 DSSERR("Framedone not received for 250ms!\n");
3914 dsi_handle_framedone(dsi->pdev, -ETIMEDOUT);
3917 static void dsi_framedone_irq_callback(void *data, u32 mask)
3919 struct omap_dss_device *dssdev = (struct omap_dss_device *) data;
3920 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3921 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3923 /* Note: We get FRAMEDONE when DISPC has finished sending pixels and
3924 * turns itself off. However, DSI still has the pixels in its buffers,
3925 * and is sending the data.
3928 __cancel_delayed_work(&dsi->framedone_timeout_work);
3930 dsi_handle_framedone(dsidev, 0);
3932 #ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
3933 dispc_fake_vsync_irq();
3937 int omap_dsi_prepare_update(struct omap_dss_device *dssdev,
3938 u16 *x, u16 *y, u16 *w, u16 *h,
3939 bool enlarge_update_area)
3941 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3944 dssdev->driver->get_resolution(dssdev, &dw, &dh);
3946 if (*x > dw || *y > dh)
3958 if (*w == 0 || *h == 0)
3961 dsi_perf_mark_setup(dsidev);
3963 dss_setup_partial_planes(dssdev, x, y, w, h,
3964 enlarge_update_area);
3965 dispc_mgr_set_lcd_size(dssdev->manager->id, *w, *h);
3969 EXPORT_SYMBOL(omap_dsi_prepare_update);
3971 int omap_dsi_update(struct omap_dss_device *dssdev,
3973 u16 x, u16 y, u16 w, u16 h,
3974 void (*callback)(int, void *), void *data)
3976 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3977 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3979 dsi->update_channel = channel;
3981 /* OMAP DSS cannot send updates of odd widths.
3982 * omap_dsi_prepare_update() makes the widths even, but add a BUG_ON
3983 * here to make sure we catch erroneous updates. Otherwise we'll only
3984 * see rather obscure HW error happening, as DSS halts. */
3987 dsi->framedone_callback = callback;
3988 dsi->framedone_data = data;
3990 dsi->update_region.x = x;
3991 dsi->update_region.y = y;
3992 dsi->update_region.w = w;
3993 dsi->update_region.h = h;
3994 dsi->update_region.device = dssdev;
3996 dsi_update_screen_dispc(dssdev, x, y, w, h);
4000 EXPORT_SYMBOL(omap_dsi_update);
4004 static int dsi_display_init_dispc(struct omap_dss_device *dssdev)
4009 irq = dssdev->manager->id == OMAP_DSS_CHANNEL_LCD ?
4010 DISPC_IRQ_FRAMEDONE : DISPC_IRQ_FRAMEDONE2;
4012 r = omap_dispc_register_isr(dsi_framedone_irq_callback, (void *) dssdev,
4015 DSSERR("can't get FRAMEDONE irq\n");
4019 dispc_mgr_set_lcd_display_type(dssdev->manager->id,
4020 OMAP_DSS_LCD_DISPLAY_TFT);
4022 dispc_mgr_enable_stallmode(dssdev->manager->id, true);
4023 dispc_mgr_enable_fifohandcheck(dssdev->manager->id, 1);
4025 dispc_mgr_set_tft_data_lines(dssdev->manager->id,
4026 dssdev->ctrl.pixel_size);
4029 struct omap_video_timings timings = {
4038 dispc_mgr_set_lcd_timings(dssdev->manager->id, &timings);
4044 static void dsi_display_uninit_dispc(struct omap_dss_device *dssdev)
4048 irq = dssdev->manager->id == OMAP_DSS_CHANNEL_LCD ?
4049 DISPC_IRQ_FRAMEDONE : DISPC_IRQ_FRAMEDONE2;
4051 omap_dispc_unregister_isr(dsi_framedone_irq_callback, (void *) dssdev,
4055 static int dsi_configure_dsi_clocks(struct omap_dss_device *dssdev)
4057 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4058 struct dsi_clock_info cinfo;
4061 /* we always use DSS_CLK_SYSCK as input clock */
4062 cinfo.use_sys_clk = true;
4063 cinfo.regn = dssdev->clocks.dsi.regn;
4064 cinfo.regm = dssdev->clocks.dsi.regm;
4065 cinfo.regm_dispc = dssdev->clocks.dsi.regm_dispc;
4066 cinfo.regm_dsi = dssdev->clocks.dsi.regm_dsi;
4067 r = dsi_calc_clock_rates(dssdev, &cinfo);
4069 DSSERR("Failed to calc dsi clocks\n");
4073 r = dsi_pll_set_clock_div(dsidev, &cinfo);
4075 DSSERR("Failed to set dsi clocks\n");
4082 static int dsi_configure_dispc_clocks(struct omap_dss_device *dssdev)
4084 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4085 struct dispc_clock_info dispc_cinfo;
4087 unsigned long long fck;
4089 fck = dsi_get_pll_hsdiv_dispc_rate(dsidev);
4091 dispc_cinfo.lck_div = dssdev->clocks.dispc.channel.lck_div;
4092 dispc_cinfo.pck_div = dssdev->clocks.dispc.channel.pck_div;
4094 r = dispc_calc_clock_rates(fck, &dispc_cinfo);
4096 DSSERR("Failed to calc dispc clocks\n");
4100 r = dispc_mgr_set_clock_div(dssdev->manager->id, &dispc_cinfo);
4102 DSSERR("Failed to set dispc clocks\n");
4109 static int dsi_display_init_dsi(struct omap_dss_device *dssdev)
4111 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4112 int dsi_module = dsi_get_dsidev_id(dsidev);
4115 r = dsi_pll_init(dsidev, true, true);
4119 r = dsi_configure_dsi_clocks(dssdev);
4123 dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src);
4124 dss_select_dsi_clk_source(dsi_module, dssdev->clocks.dsi.dsi_fclk_src);
4125 dss_select_lcd_clk_source(dssdev->manager->id,
4126 dssdev->clocks.dispc.channel.lcd_clk_src);
4130 r = dsi_configure_dispc_clocks(dssdev);
4134 r = dsi_cio_init(dssdev);
4138 _dsi_print_reset_status(dsidev);
4140 dsi_proto_timings(dssdev);
4141 dsi_set_lp_clk_divisor(dssdev);
4144 _dsi_print_reset_status(dsidev);
4146 r = dsi_proto_config(dssdev);
4150 /* enable interface */
4151 dsi_vc_enable(dsidev, 0, 1);
4152 dsi_vc_enable(dsidev, 1, 1);
4153 dsi_vc_enable(dsidev, 2, 1);
4154 dsi_vc_enable(dsidev, 3, 1);
4155 dsi_if_enable(dsidev, 1);
4156 dsi_force_tx_stop_mode_io(dsidev);
4160 dsi_cio_uninit(dssdev);
4162 dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
4163 dss_select_dsi_clk_source(dsi_module, OMAP_DSS_CLK_SRC_FCK);
4164 dss_select_lcd_clk_source(dssdev->manager->id, OMAP_DSS_CLK_SRC_FCK);
4167 dsi_pll_uninit(dsidev, true);
4172 static void dsi_display_uninit_dsi(struct omap_dss_device *dssdev,
4173 bool disconnect_lanes, bool enter_ulps)
4175 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4176 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4177 int dsi_module = dsi_get_dsidev_id(dsidev);
4179 if (enter_ulps && !dsi->ulps_enabled)
4180 dsi_enter_ulps(dsidev);
4182 /* disable interface */
4183 dsi_if_enable(dsidev, 0);
4184 dsi_vc_enable(dsidev, 0, 0);
4185 dsi_vc_enable(dsidev, 1, 0);
4186 dsi_vc_enable(dsidev, 2, 0);
4187 dsi_vc_enable(dsidev, 3, 0);
4189 dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
4190 dss_select_dsi_clk_source(dsi_module, OMAP_DSS_CLK_SRC_FCK);
4191 dss_select_lcd_clk_source(dssdev->manager->id, OMAP_DSS_CLK_SRC_FCK);
4192 dsi_cio_uninit(dssdev);
4193 dsi_pll_uninit(dsidev, disconnect_lanes);
4196 int omapdss_dsi_display_enable(struct omap_dss_device *dssdev)
4198 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4199 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4202 DSSDBG("dsi_display_enable\n");
4204 WARN_ON(!dsi_bus_is_locked(dsidev));
4206 mutex_lock(&dsi->lock);
4208 if (dssdev->manager == NULL) {
4209 DSSERR("failed to enable display: no manager\n");
4214 r = omap_dss_start_device(dssdev);
4216 DSSERR("failed to start device\n");
4220 r = dsi_runtime_get(dsidev);
4224 dsi_enable_pll_clock(dsidev, 1);
4226 _dsi_initialize_irq(dsidev);
4228 r = dsi_display_init_dispc(dssdev);
4230 goto err_init_dispc;
4232 r = dsi_display_init_dsi(dssdev);
4236 mutex_unlock(&dsi->lock);
4241 dsi_display_uninit_dispc(dssdev);
4243 dsi_enable_pll_clock(dsidev, 0);
4244 dsi_runtime_put(dsidev);
4246 omap_dss_stop_device(dssdev);
4248 mutex_unlock(&dsi->lock);
4249 DSSDBG("dsi_display_enable FAILED\n");
4252 EXPORT_SYMBOL(omapdss_dsi_display_enable);
4254 void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
4255 bool disconnect_lanes, bool enter_ulps)
4257 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4258 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4260 DSSDBG("dsi_display_disable\n");
4262 WARN_ON(!dsi_bus_is_locked(dsidev));
4264 mutex_lock(&dsi->lock);
4266 dsi_sync_vc(dsidev, 0);
4267 dsi_sync_vc(dsidev, 1);
4268 dsi_sync_vc(dsidev, 2);
4269 dsi_sync_vc(dsidev, 3);
4271 dsi_display_uninit_dispc(dssdev);
4273 dsi_display_uninit_dsi(dssdev, disconnect_lanes, enter_ulps);
4275 dsi_runtime_put(dsidev);
4276 dsi_enable_pll_clock(dsidev, 0);
4278 omap_dss_stop_device(dssdev);
4280 mutex_unlock(&dsi->lock);
4282 EXPORT_SYMBOL(omapdss_dsi_display_disable);
4284 int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable)
4286 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4287 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4289 dsi->te_enabled = enable;
4292 EXPORT_SYMBOL(omapdss_dsi_enable_te);
4294 void dsi_get_overlay_fifo_thresholds(enum omap_plane plane,
4295 u32 fifo_size, u32 burst_size,
4296 u32 *fifo_low, u32 *fifo_high)
4298 *fifo_high = fifo_size - burst_size;
4299 *fifo_low = fifo_size - burst_size * 2;
4302 int dsi_init_display(struct omap_dss_device *dssdev)
4304 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4305 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4306 int dsi_module = dsi_get_dsidev_id(dsidev);
4308 DSSDBG("DSI init\n");
4310 if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) {
4311 dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE |
4312 OMAP_DSS_DISPLAY_CAP_TEAR_ELIM;
4315 if (dsi->vdds_dsi_reg == NULL) {
4316 struct regulator *vdds_dsi;
4318 vdds_dsi = regulator_get(&dsi->pdev->dev, "vdds_dsi");
4320 if (IS_ERR(vdds_dsi)) {
4321 DSSERR("can't get VDDS_DSI regulator\n");
4322 return PTR_ERR(vdds_dsi);
4325 dsi->vdds_dsi_reg = vdds_dsi;
4328 if (dsi_get_num_data_lanes_dssdev(dssdev) > dsi->num_data_lanes) {
4329 DSSERR("DSI%d can't support more than %d data lanes\n",
4330 dsi_module + 1, dsi->num_data_lanes);
4337 int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel)
4339 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4340 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4343 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
4344 if (!dsi->vc[i].dssdev) {
4345 dsi->vc[i].dssdev = dssdev;
4351 DSSERR("cannot get VC for display %s", dssdev->name);
4354 EXPORT_SYMBOL(omap_dsi_request_vc);
4356 int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id)
4358 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4359 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4361 if (vc_id < 0 || vc_id > 3) {
4362 DSSERR("VC ID out of range\n");
4366 if (channel < 0 || channel > 3) {
4367 DSSERR("Virtual Channel out of range\n");
4371 if (dsi->vc[channel].dssdev != dssdev) {
4372 DSSERR("Virtual Channel not allocated to display %s\n",
4377 dsi->vc[channel].vc_id = vc_id;
4381 EXPORT_SYMBOL(omap_dsi_set_vc_id);
4383 void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel)
4385 struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4386 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4388 if ((channel >= 0 && channel <= 3) &&
4389 dsi->vc[channel].dssdev == dssdev) {
4390 dsi->vc[channel].dssdev = NULL;
4391 dsi->vc[channel].vc_id = 0;
4394 EXPORT_SYMBOL(omap_dsi_release_vc);
4396 void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev)
4398 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 7, 1) != 1)
4399 DSSERR("%s (%s) not active\n",
4400 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
4401 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC));
4404 void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev)
4406 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 8, 1) != 1)
4407 DSSERR("%s (%s) not active\n",
4408 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
4409 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI));
4412 static void dsi_calc_clock_param_ranges(struct platform_device *dsidev)
4414 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4416 dsi->regn_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGN);
4417 dsi->regm_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM);
4418 dsi->regm_dispc_max =
4419 dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DISPC);
4420 dsi->regm_dsi_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DSI);
4421 dsi->fint_min = dss_feat_get_param_min(FEAT_PARAM_DSIPLL_FINT);
4422 dsi->fint_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_FINT);
4423 dsi->lpdiv_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV);
4426 static int dsi_get_clocks(struct platform_device *dsidev)
4428 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4431 clk = clk_get(&dsidev->dev, "fck");
4433 DSSERR("can't get fck\n");
4434 return PTR_ERR(clk);
4439 clk = clk_get(&dsidev->dev, "sys_clk");
4441 DSSERR("can't get sys_clk\n");
4442 clk_put(dsi->dss_clk);
4443 dsi->dss_clk = NULL;
4444 return PTR_ERR(clk);
4452 static void dsi_put_clocks(struct platform_device *dsidev)
4454 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4457 clk_put(dsi->dss_clk);
4459 clk_put(dsi->sys_clk);
4462 /* DSI1 HW IP initialisation */
4463 static int omap_dsihw_probe(struct platform_device *dsidev)
4465 struct omap_display_platform_data *dss_plat_data;
4466 struct omap_dss_board_info *board_info;
4468 int r, i, dsi_module = dsi_get_dsidev_id(dsidev);
4469 struct resource *dsi_mem;
4470 struct dsi_data *dsi;
4472 dsi = kzalloc(sizeof(*dsi), GFP_KERNEL);
4479 dsi_pdev_map[dsi_module] = dsidev;
4480 dev_set_drvdata(&dsidev->dev, dsi);
4482 dss_plat_data = dsidev->dev.platform_data;
4483 board_info = dss_plat_data->board_data;
4484 dsi->enable_pads = board_info->dsi_enable_pads;
4485 dsi->disable_pads = board_info->dsi_disable_pads;
4487 spin_lock_init(&dsi->irq_lock);
4488 spin_lock_init(&dsi->errors_lock);
4491 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
4492 spin_lock_init(&dsi->irq_stats_lock);
4493 dsi->irq_stats.last_reset = jiffies;
4496 mutex_init(&dsi->lock);
4497 sema_init(&dsi->bus_lock, 1);
4499 r = dsi_get_clocks(dsidev);
4503 pm_runtime_enable(&dsidev->dev);
4505 INIT_DELAYED_WORK_DEFERRABLE(&dsi->framedone_timeout_work,
4506 dsi_framedone_timeout_work_callback);
4508 #ifdef DSI_CATCH_MISSING_TE
4509 init_timer(&dsi->te_timer);
4510 dsi->te_timer.function = dsi_te_timeout;
4511 dsi->te_timer.data = 0;
4513 dsi_mem = platform_get_resource(dsi->pdev, IORESOURCE_MEM, 0);
4515 DSSERR("can't get IORESOURCE_MEM DSI\n");
4519 dsi->base = ioremap(dsi_mem->start, resource_size(dsi_mem));
4521 DSSERR("can't ioremap DSI\n");
4525 dsi->irq = platform_get_irq(dsi->pdev, 0);
4527 DSSERR("platform_get_irq failed\n");
4532 r = request_irq(dsi->irq, omap_dsi_irq_handler, IRQF_SHARED,
4533 dev_name(&dsidev->dev), dsi->pdev);
4535 DSSERR("request_irq failed\n");
4539 /* DSI VCs initialization */
4540 for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
4541 dsi->vc[i].source = DSI_VC_SOURCE_L4;
4542 dsi->vc[i].dssdev = NULL;
4543 dsi->vc[i].vc_id = 0;
4546 dsi_calc_clock_param_ranges(dsidev);
4548 r = dsi_runtime_get(dsidev);
4552 rev = dsi_read_reg(dsidev, DSI_REVISION);
4553 dev_dbg(&dsidev->dev, "OMAP DSI rev %d.%d\n",
4554 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
4556 dsi->num_data_lanes = dsi_get_num_data_lanes(dsidev);
4558 dsi_runtime_put(dsidev);
4563 free_irq(dsi->irq, dsi->pdev);
4567 pm_runtime_disable(&dsidev->dev);
4574 static int omap_dsihw_remove(struct platform_device *dsidev)
4576 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4578 WARN_ON(dsi->scp_clk_refcount > 0);
4580 pm_runtime_disable(&dsidev->dev);
4582 dsi_put_clocks(dsidev);
4584 if (dsi->vdds_dsi_reg != NULL) {
4585 if (dsi->vdds_dsi_enabled) {
4586 regulator_disable(dsi->vdds_dsi_reg);
4587 dsi->vdds_dsi_enabled = false;
4590 regulator_put(dsi->vdds_dsi_reg);
4591 dsi->vdds_dsi_reg = NULL;
4594 free_irq(dsi->irq, dsi->pdev);
4602 static int dsi_runtime_suspend(struct device *dev)
4604 dispc_runtime_put();
4610 static int dsi_runtime_resume(struct device *dev)
4614 r = dss_runtime_get();
4618 r = dispc_runtime_get();
4630 static const struct dev_pm_ops dsi_pm_ops = {
4631 .runtime_suspend = dsi_runtime_suspend,
4632 .runtime_resume = dsi_runtime_resume,
4635 static struct platform_driver omap_dsihw_driver = {
4636 .probe = omap_dsihw_probe,
4637 .remove = omap_dsihw_remove,
4639 .name = "omapdss_dsi",
4640 .owner = THIS_MODULE,
4645 int dsi_init_platform_driver(void)
4647 return platform_driver_register(&omap_dsihw_driver);
4650 void dsi_uninit_platform_driver(void)
4652 return platform_driver_unregister(&omap_dsihw_driver);