drivers/video/omap2/dss/dsi.c

   1 /*
   2  * linux/drivers/video/omap2/dss/dsi.c
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 as published by
   9  * the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #define DSS_SUBSYS_NAME "DSI"
  21
  22 #include <linux/kernel.h>
  23 #include <linux/io.h>
  24 #include <linux/clk.h>
  25 #include <linux/device.h>
  26 #include <linux/err.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/delay.h>
  29 #include <linux/mutex.h>
  30 #include <linux/module.h>
  31 #include <linux/semaphore.h>
  32 #include <linux/seq_file.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/regulator/consumer.h>
  35 #include <linux/wait.h>
  36 #include <linux/workqueue.h>
  37 #include <linux/sched.h>
  38 #include <linux/slab.h>
  39 #include <linux/debugfs.h>
  40 #include <linux/pm_runtime.h>
  41
  42 #include <video/omapdss.h>
  43 #include <video/mipi_display.h>
  44 #include <plat/clock.h>
  45
  46 #include "dss.h"
  47 #include "dss_features.h"
  48
  49 /*#define VERBOSE_IRQ*/
  50 #define DSI_CATCH_MISSING_TE
  51
  52 struct dsi_reg { u16 idx; };
  53
  54 #define DSI_REG(idx)            ((const struct dsi_reg) { idx })
  55
  56 #define DSI_SZ_REGS             SZ_1K
  57 /* DSI Protocol Engine */
  58
  59 #define DSI_REVISION                    DSI_REG(0x0000)
  60 #define DSI_SYSCONFIG                   DSI_REG(0x0010)
  61 #define DSI_SYSSTATUS                   DSI_REG(0x0014)
  62 #define DSI_IRQSTATUS                   DSI_REG(0x0018)
  63 #define DSI_IRQENABLE                   DSI_REG(0x001C)
  64 #define DSI_CTRL                        DSI_REG(0x0040)
  65 #define DSI_GNQ                         DSI_REG(0x0044)
  66 #define DSI_COMPLEXIO_CFG1              DSI_REG(0x0048)
  67 #define DSI_COMPLEXIO_IRQ_STATUS        DSI_REG(0x004C)
  68 #define DSI_COMPLEXIO_IRQ_ENABLE        DSI_REG(0x0050)
  69 #define DSI_CLK_CTRL                    DSI_REG(0x0054)
  70 #define DSI_TIMING1                     DSI_REG(0x0058)
  71 #define DSI_TIMING2                     DSI_REG(0x005C)
  72 #define DSI_VM_TIMING1                  DSI_REG(0x0060)
  73 #define DSI_VM_TIMING2                  DSI_REG(0x0064)
  74 #define DSI_VM_TIMING3                  DSI_REG(0x0068)
  75 #define DSI_CLK_TIMING                  DSI_REG(0x006C)
  76 #define DSI_TX_FIFO_VC_SIZE             DSI_REG(0x0070)
  77 #define DSI_RX_FIFO_VC_SIZE             DSI_REG(0x0074)
  78 #define DSI_COMPLEXIO_CFG2              DSI_REG(0x0078)
  79 #define DSI_RX_FIFO_VC_FULLNESS         DSI_REG(0x007C)
  80 #define DSI_VM_TIMING4                  DSI_REG(0x0080)
  81 #define DSI_TX_FIFO_VC_EMPTINESS        DSI_REG(0x0084)
  82 #define DSI_VM_TIMING5                  DSI_REG(0x0088)
  83 #define DSI_VM_TIMING6                  DSI_REG(0x008C)
  84 #define DSI_VM_TIMING7                  DSI_REG(0x0090)
  85 #define DSI_STOPCLK_TIMING              DSI_REG(0x0094)
  86 #define DSI_VC_CTRL(n)                  DSI_REG(0x0100 + (n * 0x20))
  87 #define DSI_VC_TE(n)                    DSI_REG(0x0104 + (n * 0x20))
  88 #define DSI_VC_LONG_PACKET_HEADER(n)    DSI_REG(0x0108 + (n * 0x20))
  89 #define DSI_VC_LONG_PACKET_PAYLOAD(n)   DSI_REG(0x010C + (n * 0x20))
  90 #define DSI_VC_SHORT_PACKET_HEADER(n)   DSI_REG(0x0110 + (n * 0x20))
  91 #define DSI_VC_IRQSTATUS(n)             DSI_REG(0x0118 + (n * 0x20))
  92 #define DSI_VC_IRQENABLE(n)             DSI_REG(0x011C + (n * 0x20))
  93
  94 /* DSIPHY_SCP */
  95
  96 #define DSI_DSIPHY_CFG0                 DSI_REG(0x200 + 0x0000)
  97 #define DSI_DSIPHY_CFG1                 DSI_REG(0x200 + 0x0004)
  98 #define DSI_DSIPHY_CFG2                 DSI_REG(0x200 + 0x0008)
  99 #define DSI_DSIPHY_CFG5                 DSI_REG(0x200 + 0x0014)
 100 #define DSI_DSIPHY_CFG10                DSI_REG(0x200 + 0x0028)
 101
 102 /* DSI_PLL_CTRL_SCP */
 103
 104 #define DSI_PLL_CONTROL                 DSI_REG(0x300 + 0x0000)
 105 #define DSI_PLL_STATUS                  DSI_REG(0x300 + 0x0004)
 106 #define DSI_PLL_GO                      DSI_REG(0x300 + 0x0008)
 107 #define DSI_PLL_CONFIGURATION1          DSI_REG(0x300 + 0x000C)
 108 #define DSI_PLL_CONFIGURATION2          DSI_REG(0x300 + 0x0010)
 109
 110 #define REG_GET(dsidev, idx, start, end) \
 111         FLD_GET(dsi_read_reg(dsidev, idx), start, end)
 112
 113 #define REG_FLD_MOD(dsidev, idx, val, start, end) \
 114         dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end))
 115
 116 /* Global interrupts */
 117 #define DSI_IRQ_VC0             (1 << 0)
 118 #define DSI_IRQ_VC1             (1 << 1)
 119 #define DSI_IRQ_VC2             (1 << 2)
 120 #define DSI_IRQ_VC3             (1 << 3)
 121 #define DSI_IRQ_WAKEUP          (1 << 4)
 122 #define DSI_IRQ_RESYNC          (1 << 5)
 123 #define DSI_IRQ_PLL_LOCK        (1 << 7)
 124 #define DSI_IRQ_PLL_UNLOCK      (1 << 8)
 125 #define DSI_IRQ_PLL_RECALL      (1 << 9)
 126 #define DSI_IRQ_COMPLEXIO_ERR   (1 << 10)
 127 #define DSI_IRQ_HS_TX_TIMEOUT   (1 << 14)
 128 #define DSI_IRQ_LP_RX_TIMEOUT   (1 << 15)
 129 #define DSI_IRQ_TE_TRIGGER      (1 << 16)
 130 #define DSI_IRQ_ACK_TRIGGER     (1 << 17)
 131 #define DSI_IRQ_SYNC_LOST       (1 << 18)
 132 #define DSI_IRQ_LDO_POWER_GOOD  (1 << 19)
 133 #define DSI_IRQ_TA_TIMEOUT      (1 << 20)
 134 #define DSI_IRQ_ERROR_MASK \
 135         (DSI_IRQ_HS_TX_TIMEOUT | DSI_IRQ_LP_RX_TIMEOUT | DSI_IRQ_SYNC_LOST | \
 136         DSI_IRQ_TA_TIMEOUT | DSI_IRQ_SYNC_LOST)
 137 #define DSI_IRQ_CHANNEL_MASK    0xf
 138
 139 /* Virtual channel interrupts */
 140 #define DSI_VC_IRQ_CS           (1 << 0)
 141 #define DSI_VC_IRQ_ECC_CORR     (1 << 1)
 142 #define DSI_VC_IRQ_PACKET_SENT  (1 << 2)
 143 #define DSI_VC_IRQ_FIFO_TX_OVF  (1 << 3)
 144 #define DSI_VC_IRQ_FIFO_RX_OVF  (1 << 4)
 145 #define DSI_VC_IRQ_BTA          (1 << 5)
 146 #define DSI_VC_IRQ_ECC_NO_CORR  (1 << 6)
 147 #define DSI_VC_IRQ_FIFO_TX_UDF  (1 << 7)
 148 #define DSI_VC_IRQ_PP_BUSY_CHANGE (1 << 8)
 149 #define DSI_VC_IRQ_ERROR_MASK \
 150         (DSI_VC_IRQ_CS | DSI_VC_IRQ_ECC_CORR | DSI_VC_IRQ_FIFO_TX_OVF | \
 151         DSI_VC_IRQ_FIFO_RX_OVF | DSI_VC_IRQ_ECC_NO_CORR | \
 152         DSI_VC_IRQ_FIFO_TX_UDF)
 153
 154 /* ComplexIO interrupts */
 155 #define DSI_CIO_IRQ_ERRSYNCESC1         (1 << 0)
 156 #define DSI_CIO_IRQ_ERRSYNCESC2         (1 << 1)
 157 #define DSI_CIO_IRQ_ERRSYNCESC3         (1 << 2)
 158 #define DSI_CIO_IRQ_ERRSYNCESC4         (1 << 3)
 159 #define DSI_CIO_IRQ_ERRSYNCESC5         (1 << 4)
 160 #define DSI_CIO_IRQ_ERRESC1             (1 << 5)
 161 #define DSI_CIO_IRQ_ERRESC2             (1 << 6)
 162 #define DSI_CIO_IRQ_ERRESC3             (1 << 7)
 163 #define DSI_CIO_IRQ_ERRESC4             (1 << 8)
 164 #define DSI_CIO_IRQ_ERRESC5             (1 << 9)
 165 #define DSI_CIO_IRQ_ERRCONTROL1         (1 << 10)
 166 #define DSI_CIO_IRQ_ERRCONTROL2         (1 << 11)
 167 #define DSI_CIO_IRQ_ERRCONTROL3         (1 << 12)
 168 #define DSI_CIO_IRQ_ERRCONTROL4         (1 << 13)
 169 #define DSI_CIO_IRQ_ERRCONTROL5         (1 << 14)
 170 #define DSI_CIO_IRQ_STATEULPS1          (1 << 15)
 171 #define DSI_CIO_IRQ_STATEULPS2          (1 << 16)
 172 #define DSI_CIO_IRQ_STATEULPS3          (1 << 17)
 173 #define DSI_CIO_IRQ_STATEULPS4          (1 << 18)
 174 #define DSI_CIO_IRQ_STATEULPS5          (1 << 19)
 175 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_1  (1 << 20)
 176 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_1  (1 << 21)
 177 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_2  (1 << 22)
 178 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_2  (1 << 23)
 179 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_3  (1 << 24)
 180 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_3  (1 << 25)
 181 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_4  (1 << 26)
 182 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_4  (1 << 27)
 183 #define DSI_CIO_IRQ_ERRCONTENTIONLP0_5  (1 << 28)
 184 #define DSI_CIO_IRQ_ERRCONTENTIONLP1_5  (1 << 29)
 185 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0  (1 << 30)
 186 #define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1  (1 << 31)
 187 #define DSI_CIO_IRQ_ERROR_MASK \
 188         (DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \
 189          DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \
 190          DSI_CIO_IRQ_ERRSYNCESC5 | \
 191          DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \
 192          DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \
 193          DSI_CIO_IRQ_ERRESC5 | \
 194          DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \
 195          DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \
 196          DSI_CIO_IRQ_ERRCONTROL5 | \
 197          DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \
 198          DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \
 199          DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \
 200          DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \
 201          DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5)
 202
 203 typedef void (*omap_dsi_isr_t) (void *arg, u32 mask);
 204
 205 #define DSI_MAX_NR_ISRS                2
 206 #define DSI_MAX_NR_LANES        5
 207
 208 enum dsi_lane_function {
 209         DSI_LANE_UNUSED = 0,
 210         DSI_LANE_CLK,
 211         DSI_LANE_DATA1,
 212         DSI_LANE_DATA2,
 213         DSI_LANE_DATA3,
 214         DSI_LANE_DATA4,
 215 };
 216
 217 struct dsi_lane_config {
 218         enum dsi_lane_function function;
 219         u8 polarity;
 220 };
 221
 222 struct dsi_isr_data {
 223         omap_dsi_isr_t  isr;
 224         void            *arg;
 225         u32             mask;
 226 };
 227
 228 enum fifo_size {
 229         DSI_FIFO_SIZE_0         = 0,
 230         DSI_FIFO_SIZE_32        = 1,
 231         DSI_FIFO_SIZE_64        = 2,
 232         DSI_FIFO_SIZE_96        = 3,
 233         DSI_FIFO_SIZE_128       = 4,
 234 };
 235
 236 enum dsi_vc_source {
 237         DSI_VC_SOURCE_L4 = 0,
 238         DSI_VC_SOURCE_VP,
 239 };
 240
 241 struct dsi_irq_stats {
 242         unsigned long last_reset;
 243         unsigned irq_count;
 244         unsigned dsi_irqs[32];
 245         unsigned vc_irqs[4][32];
 246         unsigned cio_irqs[32];
 247 };
 248
 249 struct dsi_isr_tables {
 250         struct dsi_isr_data isr_table[DSI_MAX_NR_ISRS];
 251         struct dsi_isr_data isr_table_vc[4][DSI_MAX_NR_ISRS];
 252         struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS];
 253 };
 254
 255 struct dsi_data {
 256         struct platform_device *pdev;
 257         void __iomem    *base;
 258
 259         int irq;
 260
 261         struct clk *dss_clk;
 262         struct clk *sys_clk;
 263
 264         struct dsi_clock_info current_cinfo;
 265
 266         bool vdds_dsi_enabled;
 267         struct regulator *vdds_dsi_reg;
 268
 269         struct {
 270                 enum dsi_vc_source source;
 271                 struct omap_dss_device *dssdev;
 272                 enum fifo_size fifo_size;
 273                 int vc_id;
 274         } vc[4];
 275
 276         struct mutex lock;
 277         struct semaphore bus_lock;
 278
 279         unsigned pll_locked;
 280
 281         spinlock_t irq_lock;
 282         struct dsi_isr_tables isr_tables;
 283         /* space for a copy used by the interrupt handler */
 284         struct dsi_isr_tables isr_tables_copy;
 285
 286         int update_channel;
 287 #ifdef DEBUG
 288         unsigned update_bytes;
 289 #endif
 290
 291         bool te_enabled;
 292         bool ulps_enabled;
 293
 294         void (*framedone_callback)(int, void *);
 295         void *framedone_data;
 296
 297         struct delayed_work framedone_timeout_work;
 298
 299 #ifdef DSI_CATCH_MISSING_TE
 300         struct timer_list te_timer;
 301 #endif
 302
 303         unsigned long cache_req_pck;
 304         unsigned long cache_clk_freq;
 305         struct dsi_clock_info cache_cinfo;
 306
 307         u32             errors;
 308         spinlock_t      errors_lock;
 309 #ifdef DEBUG
 310         ktime_t perf_setup_time;
 311         ktime_t perf_start_time;
 312 #endif
 313         int debug_read;
 314         int debug_write;
 315
 316 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
 317         spinlock_t irq_stats_lock;
 318         struct dsi_irq_stats irq_stats;
 319 #endif
 320         /* DSI PLL Parameter Ranges */
 321         unsigned long regm_max, regn_max;
 322         unsigned long  regm_dispc_max, regm_dsi_max;
 323         unsigned long  fint_min, fint_max;
 324         unsigned long lpdiv_max;
 325
 326         unsigned num_lanes_supported;
 327
 328         struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
 329         unsigned num_lanes_used;
 330
 331         unsigned scp_clk_refcount;
 332 };
 333
 334 struct dsi_packet_sent_handler_data {
 335         struct platform_device *dsidev;
 336         struct completion *completion;
 337 };
 338
 339 static struct platform_device *dsi_pdev_map[MAX_NUM_DSI];
 340
 341 #ifdef DEBUG
 342 static bool dsi_perf;
 343 module_param(dsi_perf, bool, 0644);
 344 #endif
 345
 346 static inline struct dsi_data *dsi_get_dsidrv_data(struct platform_device *dsidev)
 347 {
 348         return dev_get_drvdata(&dsidev->dev);
 349 }
 350
 351 static inline struct platform_device *dsi_get_dsidev_from_dssdev(struct omap_dss_device *dssdev)
 352 {
 353         return dsi_pdev_map[dssdev->phy.dsi.module];
 354 }
 355
 356 struct platform_device *dsi_get_dsidev_from_id(int module)
 357 {
 358         return dsi_pdev_map[module];
 359 }
 360
 361 static inline int dsi_get_dsidev_id(struct platform_device *dsidev)
 362 {
 363         return dsidev->id;
 364 }
 365
 366 static inline void dsi_write_reg(struct platform_device *dsidev,
 367                 const struct dsi_reg idx, u32 val)
 368 {
 369         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 370
 371         __raw_writel(val, dsi->base + idx.idx);
 372 }
 373
 374 static inline u32 dsi_read_reg(struct platform_device *dsidev,
 375                 const struct dsi_reg idx)
 376 {
 377         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 378
 379         return __raw_readl(dsi->base + idx.idx);
 380 }
 381
 382 void dsi_bus_lock(struct omap_dss_device *dssdev)
 383 {
 384         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
 385         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 386
 387         down(&dsi->bus_lock);
 388 }
 389 EXPORT_SYMBOL(dsi_bus_lock);
 390
 391 void dsi_bus_unlock(struct omap_dss_device *dssdev)
 392 {
 393         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
 394         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 395
 396         up(&dsi->bus_lock);
 397 }
 398 EXPORT_SYMBOL(dsi_bus_unlock);
 399
 400 static bool dsi_bus_is_locked(struct platform_device *dsidev)
 401 {
 402         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 403
 404         return dsi->bus_lock.count == 0;
 405 }
 406
 407 static void dsi_completion_handler(void *data, u32 mask)
 408 {
 409         complete((struct completion *)data);
 410 }
 411
 412 static inline int wait_for_bit_change(struct platform_device *dsidev,
 413                 const struct dsi_reg idx, int bitnum, int value)
 414 {
 415         unsigned long timeout;
 416         ktime_t wait;
 417         int t;
 418
 419         /* first busyloop to see if the bit changes right away */
 420         t = 100;
 421         while (t-- > 0) {
 422                 if (REG_GET(dsidev, idx, bitnum, bitnum) == value)
 423                         return value;
 424         }
 425
 426         /* then loop for 500ms, sleeping for 1ms in between */
 427         timeout = jiffies + msecs_to_jiffies(500);
 428         while (time_before(jiffies, timeout)) {
 429                 if (REG_GET(dsidev, idx, bitnum, bitnum) == value)
 430                         return value;
 431
 432                 wait = ns_to_ktime(1000 * 1000);
 433                 set_current_state(TASK_UNINTERRUPTIBLE);
 434                 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
 435         }
 436
 437         return !value;
 438 }
 439
 440 u8 dsi_get_pixel_size(enum omap_dss_dsi_pixel_format fmt)
 441 {
 442         switch (fmt) {
 443         case OMAP_DSS_DSI_FMT_RGB888:
 444         case OMAP_DSS_DSI_FMT_RGB666:
 445                 return 24;
 446         case OMAP_DSS_DSI_FMT_RGB666_PACKED:
 447                 return 18;
 448         case OMAP_DSS_DSI_FMT_RGB565:
 449                 return 16;
 450         default:
 451                 BUG();
 452         }
 453 }
 454
 455 #ifdef DEBUG
 456 static void dsi_perf_mark_setup(struct platform_device *dsidev)
 457 {
 458         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 459         dsi->perf_setup_time = ktime_get();
 460 }
 461
 462 static void dsi_perf_mark_start(struct platform_device *dsidev)
 463 {
 464         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 465         dsi->perf_start_time = ktime_get();
 466 }
 467
 468 static void dsi_perf_show(struct platform_device *dsidev, const char *name)
 469 {
 470         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 471         ktime_t t, setup_time, trans_time;
 472         u32 total_bytes;
 473         u32 setup_us, trans_us, total_us;
 474
 475         if (!dsi_perf)
 476                 return;
 477
 478         t = ktime_get();
 479
 480         setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time);
 481         setup_us = (u32)ktime_to_us(setup_time);
 482         if (setup_us == 0)
 483                 setup_us = 1;
 484
 485         trans_time = ktime_sub(t, dsi->perf_start_time);
 486         trans_us = (u32)ktime_to_us(trans_time);
 487         if (trans_us == 0)
 488                 trans_us = 1;
 489
 490         total_us = setup_us + trans_us;
 491
 492         total_bytes = dsi->update_bytes;
 493
 494         printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), "
 495                         "%u bytes, %u kbytes/sec\n",
 496                         name,
 497                         setup_us,
 498                         trans_us,
 499                         total_us,
 500                         1000*1000 / total_us,
 501                         total_bytes,
 502                         total_bytes * 1000 / total_us);
 503 }
 504 #else
 505 static inline void dsi_perf_mark_setup(struct platform_device *dsidev)
 506 {
 507 }
 508
 509 static inline void dsi_perf_mark_start(struct platform_device *dsidev)
 510 {
 511 }
 512
 513 static inline void dsi_perf_show(struct platform_device *dsidev,
 514                 const char *name)
 515 {
 516 }
 517 #endif
 518
 519 static void print_irq_status(u32 status)
 520 {
 521         if (status == 0)
 522                 return;
 523
 524 #ifndef VERBOSE_IRQ
 525         if ((status & ~DSI_IRQ_CHANNEL_MASK) == 0)
 526                 return;
 527 #endif
 528         printk(KERN_DEBUG "DSI IRQ: 0x%x: ", status);
 529
 530 #define PIS(x) \
 531         if (status & DSI_IRQ_##x) \
 532                 printk(#x " ");
 533 #ifdef VERBOSE_IRQ
 534         PIS(VC0);
 535         PIS(VC1);
 536         PIS(VC2);
 537         PIS(VC3);
 538 #endif
 539         PIS(WAKEUP);
 540         PIS(RESYNC);
 541         PIS(PLL_LOCK);
 542         PIS(PLL_UNLOCK);
 543         PIS(PLL_RECALL);
 544         PIS(COMPLEXIO_ERR);
 545         PIS(HS_TX_TIMEOUT);
 546         PIS(LP_RX_TIMEOUT);
 547         PIS(TE_TRIGGER);
 548         PIS(ACK_TRIGGER);
 549         PIS(SYNC_LOST);
 550         PIS(LDO_POWER_GOOD);
 551         PIS(TA_TIMEOUT);
 552 #undef PIS
 553
 554         printk("\n");
 555 }
 556
 557 static void print_irq_status_vc(int channel, u32 status)
 558 {
 559         if (status == 0)
 560                 return;
 561
 562 #ifndef VERBOSE_IRQ
 563         if ((status & ~DSI_VC_IRQ_PACKET_SENT) == 0)
 564                 return;
 565 #endif
 566         printk(KERN_DEBUG "DSI VC(%d) IRQ 0x%x: ", channel, status);
 567
 568 #define PIS(x) \
 569         if (status & DSI_VC_IRQ_##x) \
 570                 printk(#x " ");
 571         PIS(CS);
 572         PIS(ECC_CORR);
 573 #ifdef VERBOSE_IRQ
 574         PIS(PACKET_SENT);
 575 #endif
 576         PIS(FIFO_TX_OVF);
 577         PIS(FIFO_RX_OVF);
 578         PIS(BTA);
 579         PIS(ECC_NO_CORR);
 580         PIS(FIFO_TX_UDF);
 581         PIS(PP_BUSY_CHANGE);
 582 #undef PIS
 583         printk("\n");
 584 }
 585
 586 static void print_irq_status_cio(u32 status)
 587 {
 588         if (status == 0)
 589                 return;
 590
 591         printk(KERN_DEBUG "DSI CIO IRQ 0x%x: ", status);
 592
 593 #define PIS(x) \
 594         if (status & DSI_CIO_IRQ_##x) \
 595                 printk(#x " ");
 596         PIS(ERRSYNCESC1);
 597         PIS(ERRSYNCESC2);
 598         PIS(ERRSYNCESC3);
 599         PIS(ERRESC1);
 600         PIS(ERRESC2);
 601         PIS(ERRESC3);
 602         PIS(ERRCONTROL1);
 603         PIS(ERRCONTROL2);
 604         PIS(ERRCONTROL3);
 605         PIS(STATEULPS1);
 606         PIS(STATEULPS2);
 607         PIS(STATEULPS3);
 608         PIS(ERRCONTENTIONLP0_1);
 609         PIS(ERRCONTENTIONLP1_1);
 610         PIS(ERRCONTENTIONLP0_2);
 611         PIS(ERRCONTENTIONLP1_2);
 612         PIS(ERRCONTENTIONLP0_3);
 613         PIS(ERRCONTENTIONLP1_3);
 614         PIS(ULPSACTIVENOT_ALL0);
 615         PIS(ULPSACTIVENOT_ALL1);
 616 #undef PIS
 617
 618         printk("\n");
 619 }
 620
 621 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
 622 static void dsi_collect_irq_stats(struct platform_device *dsidev, u32 irqstatus,
 623                 u32 *vcstatus, u32 ciostatus)
 624 {
 625         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 626         int i;
 627
 628         spin_lock(&dsi->irq_stats_lock);
 629
 630         dsi->irq_stats.irq_count++;
 631         dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs);
 632
 633         for (i = 0; i < 4; ++i)
 634                 dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]);
 635
 636         dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs);
 637
 638         spin_unlock(&dsi->irq_stats_lock);
 639 }
 640 #else
 641 #define dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus)
 642 #endif
 643
 644 static int debug_irq;
 645
 646 static void dsi_handle_irq_errors(struct platform_device *dsidev, u32 irqstatus,
 647                 u32 *vcstatus, u32 ciostatus)
 648 {
 649         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 650         int i;
 651
 652         if (irqstatus & DSI_IRQ_ERROR_MASK) {
 653                 DSSERR("DSI error, irqstatus %x\n", irqstatus);
 654                 print_irq_status(irqstatus);
 655                 spin_lock(&dsi->errors_lock);
 656                 dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK;
 657                 spin_unlock(&dsi->errors_lock);
 658         } else if (debug_irq) {
 659                 print_irq_status(irqstatus);
 660         }
 661
 662         for (i = 0; i < 4; ++i) {
 663                 if (vcstatus[i] & DSI_VC_IRQ_ERROR_MASK) {
 664                         DSSERR("DSI VC(%d) error, vc irqstatus %x\n",
 665                                        i, vcstatus[i]);
 666                         print_irq_status_vc(i, vcstatus[i]);
 667                 } else if (debug_irq) {
 668                         print_irq_status_vc(i, vcstatus[i]);
 669                 }
 670         }
 671
 672         if (ciostatus & DSI_CIO_IRQ_ERROR_MASK) {
 673                 DSSERR("DSI CIO error, cio irqstatus %x\n", ciostatus);
 674                 print_irq_status_cio(ciostatus);
 675         } else if (debug_irq) {
 676                 print_irq_status_cio(ciostatus);
 677         }
 678 }
 679
 680 static void dsi_call_isrs(struct dsi_isr_data *isr_array,
 681                 unsigned isr_array_size, u32 irqstatus)
 682 {
 683         struct dsi_isr_data *isr_data;
 684         int i;
 685
 686         for (i = 0; i < isr_array_size; i++) {
 687                 isr_data = &isr_array[i];
 688                 if (isr_data->isr && isr_data->mask & irqstatus)
 689                         isr_data->isr(isr_data->arg, irqstatus);
 690         }
 691 }
 692
 693 static void dsi_handle_isrs(struct dsi_isr_tables *isr_tables,
 694                 u32 irqstatus, u32 *vcstatus, u32 ciostatus)
 695 {
 696         int i;
 697
 698         dsi_call_isrs(isr_tables->isr_table,
 699                         ARRAY_SIZE(isr_tables->isr_table),
 700                         irqstatus);
 701
 702         for (i = 0; i < 4; ++i) {
 703                 if (vcstatus[i] == 0)
 704                         continue;
 705                 dsi_call_isrs(isr_tables->isr_table_vc[i],
 706                                 ARRAY_SIZE(isr_tables->isr_table_vc[i]),
 707                                 vcstatus[i]);
 708         }
 709
 710         if (ciostatus != 0)
 711                 dsi_call_isrs(isr_tables->isr_table_cio,
 712                                 ARRAY_SIZE(isr_tables->isr_table_cio),
 713                                 ciostatus);
 714 }
 715
 716 static irqreturn_t omap_dsi_irq_handler(int irq, void *arg)
 717 {
 718         struct platform_device *dsidev;
 719         struct dsi_data *dsi;
 720         u32 irqstatus, vcstatus[4], ciostatus;
 721         int i;
 722
 723         dsidev = (struct platform_device *) arg;
 724         dsi = dsi_get_dsidrv_data(dsidev);
 725
 726         spin_lock(&dsi->irq_lock);
 727
 728         irqstatus = dsi_read_reg(dsidev, DSI_IRQSTATUS);
 729
 730         /* IRQ is not for us */
 731         if (!irqstatus) {
 732                 spin_unlock(&dsi->irq_lock);
 733                 return IRQ_NONE;
 734         }
 735
 736         dsi_write_reg(dsidev, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
 737         /* flush posted write */
 738         dsi_read_reg(dsidev, DSI_IRQSTATUS);
 739
 740         for (i = 0; i < 4; ++i) {
 741                 if ((irqstatus & (1 << i)) == 0) {
 742                         vcstatus[i] = 0;
 743                         continue;
 744                 }
 745
 746                 vcstatus[i] = dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
 747
 748                 dsi_write_reg(dsidev, DSI_VC_IRQSTATUS(i), vcstatus[i]);
 749                 /* flush posted write */
 750                 dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
 751         }
 752
 753         if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
 754                 ciostatus = dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
 755
 756                 dsi_write_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
 757                 /* flush posted write */
 758                 dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
 759         } else {
 760                 ciostatus = 0;
 761         }
 762
 763 #ifdef DSI_CATCH_MISSING_TE
 764         if (irqstatus & DSI_IRQ_TE_TRIGGER)
 765                 del_timer(&dsi->te_timer);
 766 #endif
 767
 768         /* make a copy and unlock, so that isrs can unregister
 769          * themselves */
 770         memcpy(&dsi->isr_tables_copy, &dsi->isr_tables,
 771                 sizeof(dsi->isr_tables));
 772
 773         spin_unlock(&dsi->irq_lock);
 774
 775         dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus);
 776
 777         dsi_handle_irq_errors(dsidev, irqstatus, vcstatus, ciostatus);
 778
 779         dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus);
 780
 781         return IRQ_HANDLED;
 782 }
 783
 784 /* dsi->irq_lock has to be locked by the caller */
 785 static void _omap_dsi_configure_irqs(struct platform_device *dsidev,
 786                 struct dsi_isr_data *isr_array,
 787                 unsigned isr_array_size, u32 default_mask,
 788                 const struct dsi_reg enable_reg,
 789                 const struct dsi_reg status_reg)
 790 {
 791         struct dsi_isr_data *isr_data;
 792         u32 mask;
 793         u32 old_mask;
 794         int i;
 795
 796         mask = default_mask;
 797
 798         for (i = 0; i < isr_array_size; i++) {
 799                 isr_data = &isr_array[i];
 800
 801                 if (isr_data->isr == NULL)
 802                         continue;
 803
 804                 mask |= isr_data->mask;
 805         }
 806
 807         old_mask = dsi_read_reg(dsidev, enable_reg);
 808         /* clear the irqstatus for newly enabled irqs */
 809         dsi_write_reg(dsidev, status_reg, (mask ^ old_mask) & mask);
 810         dsi_write_reg(dsidev, enable_reg, mask);
 811
 812         /* flush posted writes */
 813         dsi_read_reg(dsidev, enable_reg);
 814         dsi_read_reg(dsidev, status_reg);
 815 }
 816
 817 /* dsi->irq_lock has to be locked by the caller */
 818 static void _omap_dsi_set_irqs(struct platform_device *dsidev)
 819 {
 820         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 821         u32 mask = DSI_IRQ_ERROR_MASK;
 822 #ifdef DSI_CATCH_MISSING_TE
 823         mask |= DSI_IRQ_TE_TRIGGER;
 824 #endif
 825         _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table,
 826                         ARRAY_SIZE(dsi->isr_tables.isr_table), mask,
 827                         DSI_IRQENABLE, DSI_IRQSTATUS);
 828 }
 829
 830 /* dsi->irq_lock has to be locked by the caller */
 831 static void _omap_dsi_set_irqs_vc(struct platform_device *dsidev, int vc)
 832 {
 833         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 834
 835         _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_vc[vc],
 836                         ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]),
 837                         DSI_VC_IRQ_ERROR_MASK,
 838                         DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc));
 839 }
 840
 841 /* dsi->irq_lock has to be locked by the caller */
 842 static void _omap_dsi_set_irqs_cio(struct platform_device *dsidev)
 843 {
 844         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 845
 846         _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_cio,
 847                         ARRAY_SIZE(dsi->isr_tables.isr_table_cio),
 848                         DSI_CIO_IRQ_ERROR_MASK,
 849                         DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS);
 850 }
 851
 852 static void _dsi_initialize_irq(struct platform_device *dsidev)
 853 {
 854         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 855         unsigned long flags;
 856         int vc;
 857
 858         spin_lock_irqsave(&dsi->irq_lock, flags);
 859
 860         memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables));
 861
 862         _omap_dsi_set_irqs(dsidev);
 863         for (vc = 0; vc < 4; ++vc)
 864                 _omap_dsi_set_irqs_vc(dsidev, vc);
 865         _omap_dsi_set_irqs_cio(dsidev);
 866
 867         spin_unlock_irqrestore(&dsi->irq_lock, flags);
 868 }
 869
 870 static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
 871                 struct dsi_isr_data *isr_array, unsigned isr_array_size)
 872 {
 873         struct dsi_isr_data *isr_data;
 874         int free_idx;
 875         int i;
 876
 877         BUG_ON(isr == NULL);
 878
 879         /* check for duplicate entry and find a free slot */
 880         free_idx = -1;
 881         for (i = 0; i < isr_array_size; i++) {
 882                 isr_data = &isr_array[i];
 883
 884                 if (isr_data->isr == isr && isr_data->arg == arg &&
 885                                 isr_data->mask == mask) {
 886                         return -EINVAL;
 887                 }
 888
 889                 if (isr_data->isr == NULL && free_idx == -1)
 890                         free_idx = i;
 891         }
 892
 893         if (free_idx == -1)
 894                 return -EBUSY;
 895
 896         isr_data = &isr_array[free_idx];
 897         isr_data->isr = isr;
 898         isr_data->arg = arg;
 899         isr_data->mask = mask;
 900
 901         return 0;
 902 }
 903
 904 static int _dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
 905                 struct dsi_isr_data *isr_array, unsigned isr_array_size)
 906 {
 907         struct dsi_isr_data *isr_data;
 908         int i;
 909
 910         for (i = 0; i < isr_array_size; i++) {
 911                 isr_data = &isr_array[i];
 912                 if (isr_data->isr != isr || isr_data->arg != arg ||
 913                                 isr_data->mask != mask)
 914                         continue;
 915
 916                 isr_data->isr = NULL;
 917                 isr_data->arg = NULL;
 918                 isr_data->mask = 0;
 919
 920                 return 0;
 921         }
 922
 923         return -EINVAL;
 924 }
 925
 926 static int dsi_register_isr(struct platform_device *dsidev, omap_dsi_isr_t isr,
 927                 void *arg, u32 mask)
 928 {
 929         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 930         unsigned long flags;
 931         int r;
 932
 933         spin_lock_irqsave(&dsi->irq_lock, flags);
 934
 935         r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table,
 936                         ARRAY_SIZE(dsi->isr_tables.isr_table));
 937
 938         if (r == 0)
 939                 _omap_dsi_set_irqs(dsidev);
 940
 941         spin_unlock_irqrestore(&dsi->irq_lock, flags);
 942
 943         return r;
 944 }
 945
 946 static int dsi_unregister_isr(struct platform_device *dsidev,
 947                 omap_dsi_isr_t isr, void *arg, u32 mask)
 948 {
 949         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 950         unsigned long flags;
 951         int r;
 952
 953         spin_lock_irqsave(&dsi->irq_lock, flags);
 954
 955         r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table,
 956                         ARRAY_SIZE(dsi->isr_tables.isr_table));
 957
 958         if (r == 0)
 959                 _omap_dsi_set_irqs(dsidev);
 960
 961         spin_unlock_irqrestore(&dsi->irq_lock, flags);
 962
 963         return r;
 964 }
 965
 966 static int dsi_register_isr_vc(struct platform_device *dsidev, int channel,
 967                 omap_dsi_isr_t isr, void *arg, u32 mask)
 968 {
 969         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 970         unsigned long flags;
 971         int r;
 972
 973         spin_lock_irqsave(&dsi->irq_lock, flags);
 974
 975         r = _dsi_register_isr(isr, arg, mask,
 976                         dsi->isr_tables.isr_table_vc[channel],
 977                         ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
 978
 979         if (r == 0)
 980                 _omap_dsi_set_irqs_vc(dsidev, channel);
 981
 982         spin_unlock_irqrestore(&dsi->irq_lock, flags);
 983
 984         return r;
 985 }
 986
 987 static int dsi_unregister_isr_vc(struct platform_device *dsidev, int channel,
 988                 omap_dsi_isr_t isr, void *arg, u32 mask)
 989 {
 990         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
 991         unsigned long flags;
 992         int r;
 993
 994         spin_lock_irqsave(&dsi->irq_lock, flags);
 995
 996         r = _dsi_unregister_isr(isr, arg, mask,
 997                         dsi->isr_tables.isr_table_vc[channel],
 998                         ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
 999
1000         if (r == 0)
1001                 _omap_dsi_set_irqs_vc(dsidev, channel);
1002
1003         spin_unlock_irqrestore(&dsi->irq_lock, flags);
1004
1005         return r;
1006 }
1007
1008 static int dsi_register_isr_cio(struct platform_device *dsidev,
1009                 omap_dsi_isr_t isr, void *arg, u32 mask)
1010 {
1011         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1012         unsigned long flags;
1013         int r;
1014
1015         spin_lock_irqsave(&dsi->irq_lock, flags);
1016
1017         r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1018                         ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1019
1020         if (r == 0)
1021                 _omap_dsi_set_irqs_cio(dsidev);
1022
1023         spin_unlock_irqrestore(&dsi->irq_lock, flags);
1024
1025         return r;
1026 }
1027
1028 static int dsi_unregister_isr_cio(struct platform_device *dsidev,
1029                 omap_dsi_isr_t isr, void *arg, u32 mask)
1030 {
1031         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1032         unsigned long flags;
1033         int r;
1034
1035         spin_lock_irqsave(&dsi->irq_lock, flags);
1036
1037         r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
1038                         ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
1039
1040         if (r == 0)
1041                 _omap_dsi_set_irqs_cio(dsidev);
1042
1043         spin_unlock_irqrestore(&dsi->irq_lock, flags);
1044
1045         return r;
1046 }
1047
1048 static u32 dsi_get_errors(struct platform_device *dsidev)
1049 {
1050         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1051         unsigned long flags;
1052         u32 e;
1053         spin_lock_irqsave(&dsi->errors_lock, flags);
1054         e = dsi->errors;
1055         dsi->errors = 0;
1056         spin_unlock_irqrestore(&dsi->errors_lock, flags);
1057         return e;
1058 }
1059
1060 int dsi_runtime_get(struct platform_device *dsidev)
1061 {
1062         int r;
1063         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1064
1065         DSSDBG("dsi_runtime_get\n");
1066
1067         r = pm_runtime_get_sync(&dsi->pdev->dev);
1068         WARN_ON(r < 0);
1069         return r < 0 ? r : 0;
1070 }
1071
1072 void dsi_runtime_put(struct platform_device *dsidev)
1073 {
1074         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1075         int r;
1076
1077         DSSDBG("dsi_runtime_put\n");
1078
1079         r = pm_runtime_put_sync(&dsi->pdev->dev);
1080         WARN_ON(r < 0);
1081 }
1082
1083 /* source clock for DSI PLL. this could also be PCLKFREE */
1084 static inline void dsi_enable_pll_clock(struct platform_device *dsidev,
1085                 bool enable)
1086 {
1087         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1088
1089         if (enable)
1090                 clk_enable(dsi->sys_clk);
1091         else
1092                 clk_disable(dsi->sys_clk);
1093
1094         if (enable && dsi->pll_locked) {
1095                 if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1)
1096                         DSSERR("cannot lock PLL when enabling clocks\n");
1097         }
1098 }
1099
1100 #ifdef DEBUG
1101 static void _dsi_print_reset_status(struct platform_device *dsidev)
1102 {
1103         u32 l;
1104         int b0, b1, b2;
1105
1106         if (!dss_debug)
1107                 return;
1108
1109         /* A dummy read using the SCP interface to any DSIPHY register is
1110          * required after DSIPHY reset to complete the reset of the DSI complex
1111          * I/O. */
1112         l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
1113
1114         printk(KERN_DEBUG "DSI resets: ");
1115
1116         l = dsi_read_reg(dsidev, DSI_PLL_STATUS);
1117         printk("PLL (%d) ", FLD_GET(l, 0, 0));
1118
1119         l = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1);
1120         printk("CIO (%d) ", FLD_GET(l, 29, 29));
1121
1122         if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) {
1123                 b0 = 28;
1124                 b1 = 27;
1125                 b2 = 26;
1126         } else {
1127                 b0 = 24;
1128                 b1 = 25;
1129                 b2 = 26;
1130         }
1131
1132         l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
1133         printk("PHY (%x%x%x, %d, %d, %d)\n",
1134                         FLD_GET(l, b0, b0),
1135                         FLD_GET(l, b1, b1),
1136                         FLD_GET(l, b2, b2),
1137                         FLD_GET(l, 29, 29),
1138                         FLD_GET(l, 30, 30),
1139                         FLD_GET(l, 31, 31));
1140 }
1141 #else
1142 #define _dsi_print_reset_status(x)
1143 #endif
1144
1145 static inline int dsi_if_enable(struct platform_device *dsidev, bool enable)
1146 {
1147         DSSDBG("dsi_if_enable(%d)\n", enable);
1148
1149         enable = enable ? 1 : 0;
1150         REG_FLD_MOD(dsidev, DSI_CTRL, enable, 0, 0); /* IF_EN */
1151
1152         if (wait_for_bit_change(dsidev, DSI_CTRL, 0, enable) != enable) {
1153                         DSSERR("Failed to set dsi_if_enable to %d\n", enable);
1154                         return -EIO;
1155         }
1156
1157         return 0;
1158 }
1159
1160 unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev)
1161 {
1162         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1163
1164         return dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk;
1165 }
1166
1167 static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct platform_device *dsidev)
1168 {
1169         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1170
1171         return dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk;
1172 }
1173
1174 static unsigned long dsi_get_txbyteclkhs(struct platform_device *dsidev)
1175 {
1176         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1177
1178         return dsi->current_cinfo.clkin4ddr / 16;
1179 }
1180
1181 static unsigned long dsi_fclk_rate(struct platform_device *dsidev)
1182 {
1183         unsigned long r;
1184         int dsi_module = dsi_get_dsidev_id(dsidev);
1185         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1186
1187         if (dss_get_dsi_clk_source(dsi_module) == OMAP_DSS_CLK_SRC_FCK) {
1188                 /* DSI FCLK source is DSS_CLK_FCK */
1189                 r = clk_get_rate(dsi->dss_clk);
1190         } else {
1191                 /* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */
1192                 r = dsi_get_pll_hsdiv_dsi_rate(dsidev);
1193         }
1194
1195         return r;
1196 }
1197
1198 static int dsi_set_lp_clk_divisor(struct omap_dss_device *dssdev)
1199 {
1200         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
1201         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1202         unsigned long dsi_fclk;
1203         unsigned lp_clk_div;
1204         unsigned long lp_clk;
1205
1206         lp_clk_div = dssdev->clocks.dsi.lp_clk_div;
1207
1208         if (lp_clk_div == 0 || lp_clk_div > dsi->lpdiv_max)
1209                 return -EINVAL;
1210
1211         dsi_fclk = dsi_fclk_rate(dsidev);
1212
1213         lp_clk = dsi_fclk / 2 / lp_clk_div;
1214
1215         DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk);
1216         dsi->current_cinfo.lp_clk = lp_clk;
1217         dsi->current_cinfo.lp_clk_div = lp_clk_div;
1218
1219         /* LP_CLK_DIVISOR */
1220         REG_FLD_MOD(dsidev, DSI_CLK_CTRL, lp_clk_div, 12, 0);
1221
1222         /* LP_RX_SYNCHRO_ENABLE */
1223         REG_FLD_MOD(dsidev, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21);
1224
1225         return 0;
1226 }
1227
1228 static void dsi_enable_scp_clk(struct platform_device *dsidev)
1229 {
1230         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1231
1232         if (dsi->scp_clk_refcount++ == 0)
1233                 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */
1234 }
1235
1236 static void dsi_disable_scp_clk(struct platform_device *dsidev)
1237 {
1238         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1239
1240         WARN_ON(dsi->scp_clk_refcount == 0);
1241         if (--dsi->scp_clk_refcount == 0)
1242                 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */
1243 }
1244
1245 enum dsi_pll_power_state {
1246         DSI_PLL_POWER_OFF       = 0x0,
1247         DSI_PLL_POWER_ON_HSCLK  = 0x1,
1248         DSI_PLL_POWER_ON_ALL    = 0x2,
1249         DSI_PLL_POWER_ON_DIV    = 0x3,
1250 };
1251
1252 static int dsi_pll_power(struct platform_device *dsidev,
1253                 enum dsi_pll_power_state state)
1254 {
1255         int t = 0;
1256
1257         /* DSI-PLL power command 0x3 is not working */
1258         if (dss_has_feature(FEAT_DSI_PLL_PWR_BUG) &&
1259                         state == DSI_PLL_POWER_ON_DIV)
1260                 state = DSI_PLL_POWER_ON_ALL;
1261
1262         /* PLL_PWR_CMD */
1263         REG_FLD_MOD(dsidev, DSI_CLK_CTRL, state, 31, 30);
1264
1265         /* PLL_PWR_STATUS */
1266         while (FLD_GET(dsi_read_reg(dsidev, DSI_CLK_CTRL), 29, 28) != state) {
1267                 if (++t > 1000) {
1268                         DSSERR("Failed to set DSI PLL power mode to %d\n",
1269                                         state);
1270                         return -ENODEV;
1271                 }
1272                 udelay(1);
1273         }
1274
1275         return 0;
1276 }
1277
1278 /* calculate clock rates using dividers in cinfo */
1279 static int dsi_calc_clock_rates(struct platform_device *dsidev,
1280                 struct dsi_clock_info *cinfo)
1281 {
1282         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1283
1284         if (cinfo->regn == 0 || cinfo->regn > dsi->regn_max)
1285                 return -EINVAL;
1286
1287         if (cinfo->regm == 0 || cinfo->regm > dsi->regm_max)
1288                 return -EINVAL;
1289
1290         if (cinfo->regm_dispc > dsi->regm_dispc_max)
1291                 return -EINVAL;
1292
1293         if (cinfo->regm_dsi > dsi->regm_dsi_max)
1294                 return -EINVAL;
1295
1296         cinfo->clkin = clk_get_rate(dsi->sys_clk);
1297         cinfo->fint = cinfo->clkin / cinfo->regn;
1298
1299         if (cinfo->fint > dsi->fint_max || cinfo->fint < dsi->fint_min)
1300                 return -EINVAL;
1301
1302         cinfo->clkin4ddr = 2 * cinfo->regm * cinfo->fint;
1303
1304         if (cinfo->clkin4ddr > 1800 * 1000 * 1000)
1305                 return -EINVAL;
1306
1307         if (cinfo->regm_dispc > 0)
1308                 cinfo->dsi_pll_hsdiv_dispc_clk =
1309                         cinfo->clkin4ddr / cinfo->regm_dispc;
1310         else
1311                 cinfo->dsi_pll_hsdiv_dispc_clk = 0;
1312
1313         if (cinfo->regm_dsi > 0)
1314                 cinfo->dsi_pll_hsdiv_dsi_clk =
1315                         cinfo->clkin4ddr / cinfo->regm_dsi;
1316         else
1317                 cinfo->dsi_pll_hsdiv_dsi_clk = 0;
1318
1319         return 0;
1320 }
1321
1322 int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev, bool is_tft,
1323                 unsigned long req_pck, struct dsi_clock_info *dsi_cinfo,
1324                 struct dispc_clock_info *dispc_cinfo)
1325 {
1326         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1327         struct dsi_clock_info cur, best;
1328         struct dispc_clock_info best_dispc;
1329         int min_fck_per_pck;
1330         int match = 0;
1331         unsigned long dss_sys_clk, max_dss_fck;
1332
1333         dss_sys_clk = clk_get_rate(dsi->sys_clk);
1334
1335         max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
1336
1337         if (req_pck == dsi->cache_req_pck &&
1338                         dsi->cache_cinfo.clkin == dss_sys_clk) {
1339                 DSSDBG("DSI clock info found from cache\n");
1340                 *dsi_cinfo = dsi->cache_cinfo;
1341                 dispc_find_clk_divs(is_tft, req_pck,
1342                         dsi_cinfo->dsi_pll_hsdiv_dispc_clk, dispc_cinfo);
1343                 return 0;
1344         }
1345
1346         min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
1347
1348         if (min_fck_per_pck &&
1349                 req_pck * min_fck_per_pck > max_dss_fck) {
1350                 DSSERR("Requested pixel clock not possible with the current "
1351                                 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
1352                                 "the constraint off.\n");
1353                 min_fck_per_pck = 0;
1354         }
1355
1356         DSSDBG("dsi_pll_calc\n");
1357
1358 retry:
1359         memset(&best, 0, sizeof(best));
1360         memset(&best_dispc, 0, sizeof(best_dispc));
1361
1362         memset(&cur, 0, sizeof(cur));
1363         cur.clkin = dss_sys_clk;
1364
1365         /* 0.75MHz < Fint = clkin / regn < 2.1MHz */
1366         /* To reduce PLL lock time, keep Fint high (around 2 MHz) */
1367         for (cur.regn = 1; cur.regn < dsi->regn_max; ++cur.regn) {
1368                 cur.fint = cur.clkin / cur.regn;
1369
1370                 if (cur.fint > dsi->fint_max || cur.fint < dsi->fint_min)
1371                         continue;
1372
1373                 /* DSIPHY(MHz) = (2 * regm / regn) * clkin */
1374                 for (cur.regm = 1; cur.regm < dsi->regm_max; ++cur.regm) {
1375                         unsigned long a, b;
1376
1377                         a = 2 * cur.regm * (cur.clkin/1000);
1378                         b = cur.regn;
1379                         cur.clkin4ddr = a / b * 1000;
1380
1381                         if (cur.clkin4ddr > 1800 * 1000 * 1000)
1382                                 break;
1383
1384                         /* dsi_pll_hsdiv_dispc_clk(MHz) =
1385                          * DSIPHY(MHz) / regm_dispc  < 173MHz/186Mhz */
1386                         for (cur.regm_dispc = 1; cur.regm_dispc <
1387                                         dsi->regm_dispc_max; ++cur.regm_dispc) {
1388                                 struct dispc_clock_info cur_dispc;
1389                                 cur.dsi_pll_hsdiv_dispc_clk =
1390                                         cur.clkin4ddr / cur.regm_dispc;
1391
1392                                 /* this will narrow down the search a bit,
1393                                  * but still give pixclocks below what was
1394                                  * requested */
1395                                 if (cur.dsi_pll_hsdiv_dispc_clk  < req_pck)
1396                                         break;
1397
1398                                 if (cur.dsi_pll_hsdiv_dispc_clk > max_dss_fck)
1399                                         continue;
1400
1401                                 if (min_fck_per_pck &&
1402                                         cur.dsi_pll_hsdiv_dispc_clk <
1403                                                 req_pck * min_fck_per_pck)
1404                                         continue;
1405
1406                                 match = 1;
1407
1408                                 dispc_find_clk_divs(is_tft, req_pck,
1409                                                 cur.dsi_pll_hsdiv_dispc_clk,
1410                                                 &cur_dispc);
1411
1412                                 if (abs(cur_dispc.pck - req_pck) <
1413                                                 abs(best_dispc.pck - req_pck)) {
1414                                         best = cur;
1415                                         best_dispc = cur_dispc;
1416
1417                                         if (cur_dispc.pck == req_pck)
1418                                                 goto found;
1419                                 }
1420                         }
1421                 }
1422         }
1423 found:
1424         if (!match) {
1425                 if (min_fck_per_pck) {
1426                         DSSERR("Could not find suitable clock settings.\n"
1427                                         "Turning FCK/PCK constraint off and"
1428                                         "trying again.\n");
1429                         min_fck_per_pck = 0;
1430                         goto retry;
1431                 }
1432
1433                 DSSERR("Could not find suitable clock settings.\n");
1434
1435                 return -EINVAL;
1436         }
1437
1438         /* dsi_pll_hsdiv_dsi_clk (regm_dsi) is not used */
1439         best.regm_dsi = 0;
1440         best.dsi_pll_hsdiv_dsi_clk = 0;
1441
1442         if (dsi_cinfo)
1443                 *dsi_cinfo = best;
1444         if (dispc_cinfo)
1445                 *dispc_cinfo = best_dispc;
1446
1447         dsi->cache_req_pck = req_pck;
1448         dsi->cache_clk_freq = 0;
1449         dsi->cache_cinfo = best;
1450
1451         return 0;
1452 }
1453
1454 int dsi_pll_set_clock_div(struct platform_device *dsidev,
1455                 struct dsi_clock_info *cinfo)
1456 {
1457         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1458         int r = 0;
1459         u32 l;
1460         int f = 0;
1461         u8 regn_start, regn_end, regm_start, regm_end;
1462         u8 regm_dispc_start, regm_dispc_end, regm_dsi_start, regm_dsi_end;
1463
1464         DSSDBGF();
1465
1466         dsi->current_cinfo.clkin = cinfo->clkin;
1467         dsi->current_cinfo.fint = cinfo->fint;
1468         dsi->current_cinfo.clkin4ddr = cinfo->clkin4ddr;
1469         dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk =
1470                         cinfo->dsi_pll_hsdiv_dispc_clk;
1471         dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk =
1472                         cinfo->dsi_pll_hsdiv_dsi_clk;
1473
1474         dsi->current_cinfo.regn = cinfo->regn;
1475         dsi->current_cinfo.regm = cinfo->regm;
1476         dsi->current_cinfo.regm_dispc = cinfo->regm_dispc;
1477         dsi->current_cinfo.regm_dsi = cinfo->regm_dsi;
1478
1479         DSSDBG("DSI Fint %ld\n", cinfo->fint);
1480
1481         DSSDBG("clkin rate %ld\n", cinfo->clkin);
1482
1483         /* DSIPHY == CLKIN4DDR */
1484         DSSDBG("CLKIN4DDR = 2 * %d / %d * %lu = %lu\n",
1485                         cinfo->regm,
1486                         cinfo->regn,
1487                         cinfo->clkin,
1488                         cinfo->clkin4ddr);
1489
1490         DSSDBG("Data rate on 1 DSI lane %ld Mbps\n",
1491                         cinfo->clkin4ddr / 1000 / 1000 / 2);
1492
1493         DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4);
1494
1495         DSSDBG("regm_dispc = %d, %s (%s) = %lu\n", cinfo->regm_dispc,
1496                 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
1497                 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
1498                 cinfo->dsi_pll_hsdiv_dispc_clk);
1499         DSSDBG("regm_dsi = %d, %s (%s) = %lu\n", cinfo->regm_dsi,
1500                 dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
1501                 dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
1502                 cinfo->dsi_pll_hsdiv_dsi_clk);
1503
1504         dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGN, &regn_start, &regn_end);
1505         dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM, &regm_start, &regm_end);
1506         dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DISPC, &regm_dispc_start,
1507                         &regm_dispc_end);
1508         dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DSI, &regm_dsi_start,
1509                         &regm_dsi_end);
1510
1511         /* DSI_PLL_AUTOMODE = manual */
1512         REG_FLD_MOD(dsidev, DSI_PLL_CONTROL, 0, 0, 0);
1513
1514         l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION1);
1515         l = FLD_MOD(l, 1, 0, 0);                /* DSI_PLL_STOPMODE */
1516         /* DSI_PLL_REGN */
1517         l = FLD_MOD(l, cinfo->regn - 1, regn_start, regn_end);
1518         /* DSI_PLL_REGM */
1519         l = FLD_MOD(l, cinfo->regm, regm_start, regm_end);
1520         /* DSI_CLOCK_DIV */
1521         l = FLD_MOD(l, cinfo->regm_dispc > 0 ? cinfo->regm_dispc - 1 : 0,
1522                         regm_dispc_start, regm_dispc_end);
1523         /* DSIPROTO_CLOCK_DIV */
1524         l = FLD_MOD(l, cinfo->regm_dsi > 0 ? cinfo->regm_dsi - 1 : 0,
1525                         regm_dsi_start, regm_dsi_end);
1526         dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION1, l);
1527
1528         BUG_ON(cinfo->fint < dsi->fint_min || cinfo->fint > dsi->fint_max);
1529
1530         if (dss_has_feature(FEAT_DSI_PLL_FREQSEL)) {
1531                 f = cinfo->fint < 1000000 ? 0x3 :
1532                         cinfo->fint < 1250000 ? 0x4 :
1533                         cinfo->fint < 1500000 ? 0x5 :
1534                         cinfo->fint < 1750000 ? 0x6 :
1535                         0x7;
1536         }
1537
1538         l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2);
1539
1540         if (dss_has_feature(FEAT_DSI_PLL_FREQSEL))
1541                 l = FLD_MOD(l, f, 4, 1);        /* DSI_PLL_FREQSEL */
1542         l = FLD_MOD(l, 1, 13, 13);              /* DSI_PLL_REFEN */
1543         l = FLD_MOD(l, 0, 14, 14);              /* DSIPHY_CLKINEN */
1544         l = FLD_MOD(l, 1, 20, 20);              /* DSI_HSDIVBYPASS */
1545         dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l);
1546
1547         REG_FLD_MOD(dsidev, DSI_PLL_GO, 1, 0, 0);       /* DSI_PLL_GO */
1548
1549         if (wait_for_bit_change(dsidev, DSI_PLL_GO, 0, 0) != 0) {
1550                 DSSERR("dsi pll go bit not going down.\n");
1551                 r = -EIO;
1552                 goto err;
1553         }
1554
1555         if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1) {
1556                 DSSERR("cannot lock PLL\n");
1557                 r = -EIO;
1558                 goto err;
1559         }
1560
1561         dsi->pll_locked = 1;
1562
1563         l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2);
1564         l = FLD_MOD(l, 0, 0, 0);        /* DSI_PLL_IDLE */
1565         l = FLD_MOD(l, 0, 5, 5);        /* DSI_PLL_PLLLPMODE */
1566         l = FLD_MOD(l, 0, 6, 6);        /* DSI_PLL_LOWCURRSTBY */
1567         l = FLD_MOD(l, 0, 7, 7);        /* DSI_PLL_TIGHTPHASELOCK */
1568         l = FLD_MOD(l, 0, 8, 8);        /* DSI_PLL_DRIFTGUARDEN */
1569         l = FLD_MOD(l, 0, 10, 9);       /* DSI_PLL_LOCKSEL */
1570         l = FLD_MOD(l, 1, 13, 13);      /* DSI_PLL_REFEN */
1571         l = FLD_MOD(l, 1, 14, 14);      /* DSIPHY_CLKINEN */
1572         l = FLD_MOD(l, 0, 15, 15);      /* DSI_BYPASSEN */
1573         l = FLD_MOD(l, 1, 16, 16);      /* DSS_CLOCK_EN */
1574         l = FLD_MOD(l, 0, 17, 17);      /* DSS_CLOCK_PWDN */
1575         l = FLD_MOD(l, 1, 18, 18);      /* DSI_PROTO_CLOCK_EN */
1576         l = FLD_MOD(l, 0, 19, 19);      /* DSI_PROTO_CLOCK_PWDN */
1577         l = FLD_MOD(l, 0, 20, 20);      /* DSI_HSDIVBYPASS */
1578         dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l);
1579
1580         DSSDBG("PLL config done\n");
1581 err:
1582         return r;
1583 }
1584
1585 int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk,
1586                 bool enable_hsdiv)
1587 {
1588         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1589         int r = 0;
1590         enum dsi_pll_power_state pwstate;
1591
1592         DSSDBG("PLL init\n");
1593
1594         if (dsi->vdds_dsi_reg == NULL) {
1595                 struct regulator *vdds_dsi;
1596
1597                 vdds_dsi = regulator_get(&dsi->pdev->dev, "vdds_dsi");
1598
1599                 if (IS_ERR(vdds_dsi)) {
1600                         DSSERR("can't get VDDS_DSI regulator\n");
1601                         return PTR_ERR(vdds_dsi);
1602                 }
1603
1604                 dsi->vdds_dsi_reg = vdds_dsi;
1605         }
1606
1607         dsi_enable_pll_clock(dsidev, 1);
1608         /*
1609          * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4.
1610          */
1611         dsi_enable_scp_clk(dsidev);
1612
1613         if (!dsi->vdds_dsi_enabled) {
1614                 r = regulator_enable(dsi->vdds_dsi_reg);
1615                 if (r)
1616                         goto err0;
1617                 dsi->vdds_dsi_enabled = true;
1618         }
1619
1620         /* XXX PLL does not come out of reset without this... */
1621         dispc_pck_free_enable(1);
1622
1623         if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 0, 1) != 1) {
1624                 DSSERR("PLL not coming out of reset.\n");
1625                 r = -ENODEV;
1626                 dispc_pck_free_enable(0);
1627                 goto err1;
1628         }
1629
1630         /* XXX ... but if left on, we get problems when planes do not
1631          * fill the whole display. No idea about this */
1632         dispc_pck_free_enable(0);
1633
1634         if (enable_hsclk && enable_hsdiv)
1635                 pwstate = DSI_PLL_POWER_ON_ALL;
1636         else if (enable_hsclk)
1637                 pwstate = DSI_PLL_POWER_ON_HSCLK;
1638         else if (enable_hsdiv)
1639                 pwstate = DSI_PLL_POWER_ON_DIV;
1640         else
1641                 pwstate = DSI_PLL_POWER_OFF;
1642
1643         r = dsi_pll_power(dsidev, pwstate);
1644
1645         if (r)
1646                 goto err1;
1647
1648         DSSDBG("PLL init done\n");
1649
1650         return 0;
1651 err1:
1652         if (dsi->vdds_dsi_enabled) {
1653                 regulator_disable(dsi->vdds_dsi_reg);
1654                 dsi->vdds_dsi_enabled = false;
1655         }
1656 err0:
1657         dsi_disable_scp_clk(dsidev);
1658         dsi_enable_pll_clock(dsidev, 0);
1659         return r;
1660 }
1661
1662 void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes)
1663 {
1664         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1665
1666         dsi->pll_locked = 0;
1667         dsi_pll_power(dsidev, DSI_PLL_POWER_OFF);
1668         if (disconnect_lanes) {
1669                 WARN_ON(!dsi->vdds_dsi_enabled);
1670                 regulator_disable(dsi->vdds_dsi_reg);
1671                 dsi->vdds_dsi_enabled = false;
1672         }
1673
1674         dsi_disable_scp_clk(dsidev);
1675         dsi_enable_pll_clock(dsidev, 0);
1676
1677         DSSDBG("PLL uninit done\n");
1678 }
1679
1680 static void dsi_dump_dsidev_clocks(struct platform_device *dsidev,
1681                 struct seq_file *s)
1682 {
1683         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1684         struct dsi_clock_info *cinfo = &dsi->current_cinfo;
1685         enum omap_dss_clk_source dispc_clk_src, dsi_clk_src;
1686         int dsi_module = dsi_get_dsidev_id(dsidev);
1687
1688         dispc_clk_src = dss_get_dispc_clk_source();
1689         dsi_clk_src = dss_get_dsi_clk_source(dsi_module);
1690
1691         if (dsi_runtime_get(dsidev))
1692                 return;
1693
1694         seq_printf(s,   "- DSI%d PLL -\n", dsi_module + 1);
1695
1696         seq_printf(s,   "dsi pll clkin\t%lu\n", cinfo->clkin);
1697
1698         seq_printf(s,   "Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn);
1699
1700         seq_printf(s,   "CLKIN4DDR\t%-16luregm %u\n",
1701                         cinfo->clkin4ddr, cinfo->regm);
1702
1703         seq_printf(s,   "DSI_PLL_HSDIV_DISPC (%s)\t%-16luregm_dispc %u\t(%s)\n",
1704                         dss_feat_get_clk_source_name(dsi_module == 0 ?
1705                                 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC :
1706                                 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC),
1707                         cinfo->dsi_pll_hsdiv_dispc_clk,
1708                         cinfo->regm_dispc,
1709                         dispc_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1710                         "off" : "on");
1711
1712         seq_printf(s,   "DSI_PLL_HSDIV_DSI (%s)\t%-16luregm_dsi %u\t(%s)\n",
1713                         dss_feat_get_clk_source_name(dsi_module == 0 ?
1714                                 OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI :
1715                                 OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI),
1716                         cinfo->dsi_pll_hsdiv_dsi_clk,
1717                         cinfo->regm_dsi,
1718                         dsi_clk_src == OMAP_DSS_CLK_SRC_FCK ?
1719                         "off" : "on");
1720
1721         seq_printf(s,   "- DSI%d -\n", dsi_module + 1);
1722
1723         seq_printf(s,   "dsi fclk source = %s (%s)\n",
1724                         dss_get_generic_clk_source_name(dsi_clk_src),
1725                         dss_feat_get_clk_source_name(dsi_clk_src));
1726
1727         seq_printf(s,   "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsidev));
1728
1729         seq_printf(s,   "DDR_CLK\t\t%lu\n",
1730                         cinfo->clkin4ddr / 4);
1731
1732         seq_printf(s,   "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsidev));
1733
1734         seq_printf(s,   "LP_CLK\t\t%lu\n", cinfo->lp_clk);
1735
1736         dsi_runtime_put(dsidev);
1737 }
1738
1739 void dsi_dump_clocks(struct seq_file *s)
1740 {
1741         struct platform_device *dsidev;
1742         int i;
1743
1744         for  (i = 0; i < MAX_NUM_DSI; i++) {
1745                 dsidev = dsi_get_dsidev_from_id(i);
1746                 if (dsidev)
1747                         dsi_dump_dsidev_clocks(dsidev, s);
1748         }
1749 }
1750
1751 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
1752 static void dsi_dump_dsidev_irqs(struct platform_device *dsidev,
1753                 struct seq_file *s)
1754 {
1755         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
1756         unsigned long flags;
1757         struct dsi_irq_stats stats;
1758         int dsi_module = dsi_get_dsidev_id(dsidev);
1759
1760         spin_lock_irqsave(&dsi->irq_stats_lock, flags);
1761
1762         stats = dsi->irq_stats;
1763         memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats));
1764         dsi->irq_stats.last_reset = jiffies;
1765
1766         spin_unlock_irqrestore(&dsi->irq_stats_lock, flags);
1767
1768         seq_printf(s, "period %u ms\n",
1769                         jiffies_to_msecs(jiffies - stats.last_reset));
1770
1771         seq_printf(s, "irqs %d\n", stats.irq_count);
1772 #define PIS(x) \
1773         seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]);
1774
1775         seq_printf(s, "-- DSI%d interrupts --\n", dsi_module + 1);
1776         PIS(VC0);
1777         PIS(VC1);
1778         PIS(VC2);
1779         PIS(VC3);
1780         PIS(WAKEUP);
1781         PIS(RESYNC);
1782         PIS(PLL_LOCK);
1783         PIS(PLL_UNLOCK);
1784         PIS(PLL_RECALL);
1785         PIS(COMPLEXIO_ERR);
1786         PIS(HS_TX_TIMEOUT);
1787         PIS(LP_RX_TIMEOUT);
1788         PIS(TE_TRIGGER);
1789         PIS(ACK_TRIGGER);
1790         PIS(SYNC_LOST);
1791         PIS(LDO_POWER_GOOD);
1792         PIS(TA_TIMEOUT);
1793 #undef PIS
1794
1795 #define PIS(x) \
1796         seq_printf(s, "%-20s %10d %10d %10d %10d\n", #x, \
1797                         stats.vc_irqs[0][ffs(DSI_VC_IRQ_##x)-1], \
1798                         stats.vc_irqs[1][ffs(DSI_VC_IRQ_##x)-1], \
1799                         stats.vc_irqs[2][ffs(DSI_VC_IRQ_##x)-1], \
1800                         stats.vc_irqs[3][ffs(DSI_VC_IRQ_##x)-1]);
1801
1802         seq_printf(s, "-- VC interrupts --\n");
1803         PIS(CS);
1804         PIS(ECC_CORR);
1805         PIS(PACKET_SENT);
1806         PIS(FIFO_TX_OVF);
1807         PIS(FIFO_RX_OVF);
1808         PIS(BTA);
1809         PIS(ECC_NO_CORR);
1810         PIS(FIFO_TX_UDF);
1811         PIS(PP_BUSY_CHANGE);
1812 #undef PIS
1813
1814 #define PIS(x) \
1815         seq_printf(s, "%-20s %10d\n", #x, \
1816                         stats.cio_irqs[ffs(DSI_CIO_IRQ_##x)-1]);
1817
1818         seq_printf(s, "-- CIO interrupts --\n");
1819         PIS(ERRSYNCESC1);
1820         PIS(ERRSYNCESC2);
1821         PIS(ERRSYNCESC3);
1822         PIS(ERRESC1);
1823         PIS(ERRESC2);
1824         PIS(ERRESC3);
1825         PIS(ERRCONTROL1);
1826         PIS(ERRCONTROL2);
1827         PIS(ERRCONTROL3);
1828         PIS(STATEULPS1);
1829         PIS(STATEULPS2);
1830         PIS(STATEULPS3);
1831         PIS(ERRCONTENTIONLP0_1);
1832         PIS(ERRCONTENTIONLP1_1);
1833         PIS(ERRCONTENTIONLP0_2);
1834         PIS(ERRCONTENTIONLP1_2);
1835         PIS(ERRCONTENTIONLP0_3);
1836         PIS(ERRCONTENTIONLP1_3);
1837         PIS(ULPSACTIVENOT_ALL0);
1838         PIS(ULPSACTIVENOT_ALL1);
1839 #undef PIS
1840 }
1841
1842 static void dsi1_dump_irqs(struct seq_file *s)
1843 {
1844         struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
1845
1846         dsi_dump_dsidev_irqs(dsidev, s);
1847 }
1848
1849 static void dsi2_dump_irqs(struct seq_file *s)
1850 {
1851         struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
1852
1853         dsi_dump_dsidev_irqs(dsidev, s);
1854 }
1855 #endif
1856
1857 static void dsi_dump_dsidev_regs(struct platform_device *dsidev,
1858                 struct seq_file *s)
1859 {
1860 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsidev, r))
1861
1862         if (dsi_runtime_get(dsidev))
1863                 return;
1864         dsi_enable_scp_clk(dsidev);
1865
1866         DUMPREG(DSI_REVISION);
1867         DUMPREG(DSI_SYSCONFIG);
1868         DUMPREG(DSI_SYSSTATUS);
1869         DUMPREG(DSI_IRQSTATUS);
1870         DUMPREG(DSI_IRQENABLE);
1871         DUMPREG(DSI_CTRL);
1872         DUMPREG(DSI_COMPLEXIO_CFG1);
1873         DUMPREG(DSI_COMPLEXIO_IRQ_STATUS);
1874         DUMPREG(DSI_COMPLEXIO_IRQ_ENABLE);
1875         DUMPREG(DSI_CLK_CTRL);
1876         DUMPREG(DSI_TIMING1);
1877         DUMPREG(DSI_TIMING2);
1878         DUMPREG(DSI_VM_TIMING1);
1879         DUMPREG(DSI_VM_TIMING2);
1880         DUMPREG(DSI_VM_TIMING3);
1881         DUMPREG(DSI_CLK_TIMING);
1882         DUMPREG(DSI_TX_FIFO_VC_SIZE);
1883         DUMPREG(DSI_RX_FIFO_VC_SIZE);
1884         DUMPREG(DSI_COMPLEXIO_CFG2);
1885         DUMPREG(DSI_RX_FIFO_VC_FULLNESS);
1886         DUMPREG(DSI_VM_TIMING4);
1887         DUMPREG(DSI_TX_FIFO_VC_EMPTINESS);
1888         DUMPREG(DSI_VM_TIMING5);
1889         DUMPREG(DSI_VM_TIMING6);
1890         DUMPREG(DSI_VM_TIMING7);
1891         DUMPREG(DSI_STOPCLK_TIMING);
1892
1893         DUMPREG(DSI_VC_CTRL(0));
1894         DUMPREG(DSI_VC_TE(0));
1895         DUMPREG(DSI_VC_LONG_PACKET_HEADER(0));
1896         DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(0));
1897         DUMPREG(DSI_VC_SHORT_PACKET_HEADER(0));
1898         DUMPREG(DSI_VC_IRQSTATUS(0));
1899         DUMPREG(DSI_VC_IRQENABLE(0));
1900
1901         DUMPREG(DSI_VC_CTRL(1));
1902         DUMPREG(DSI_VC_TE(1));
1903         DUMPREG(DSI_VC_LONG_PACKET_HEADER(1));
1904         DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(1));
1905         DUMPREG(DSI_VC_SHORT_PACKET_HEADER(1));
1906         DUMPREG(DSI_VC_IRQSTATUS(1));
1907         DUMPREG(DSI_VC_IRQENABLE(1));
1908
1909         DUMPREG(DSI_VC_CTRL(2));
1910         DUMPREG(DSI_VC_TE(2));
1911         DUMPREG(DSI_VC_LONG_PACKET_HEADER(2));
1912         DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(2));
1913         DUMPREG(DSI_VC_SHORT_PACKET_HEADER(2));
1914         DUMPREG(DSI_VC_IRQSTATUS(2));
1915         DUMPREG(DSI_VC_IRQENABLE(2));
1916
1917         DUMPREG(DSI_VC_CTRL(3));
1918         DUMPREG(DSI_VC_TE(3));
1919         DUMPREG(DSI_VC_LONG_PACKET_HEADER(3));
1920         DUMPREG(DSI_VC_LONG_PACKET_PAYLOAD(3));
1921         DUMPREG(DSI_VC_SHORT_PACKET_HEADER(3));
1922         DUMPREG(DSI_VC_IRQSTATUS(3));
1923         DUMPREG(DSI_VC_IRQENABLE(3));
1924
1925         DUMPREG(DSI_DSIPHY_CFG0);
1926         DUMPREG(DSI_DSIPHY_CFG1);
1927         DUMPREG(DSI_DSIPHY_CFG2);
1928         DUMPREG(DSI_DSIPHY_CFG5);
1929
1930         DUMPREG(DSI_PLL_CONTROL);
1931         DUMPREG(DSI_PLL_STATUS);
1932         DUMPREG(DSI_PLL_GO);
1933         DUMPREG(DSI_PLL_CONFIGURATION1);
1934         DUMPREG(DSI_PLL_CONFIGURATION2);
1935
1936         dsi_disable_scp_clk(dsidev);
1937         dsi_runtime_put(dsidev);
1938 #undef DUMPREG
1939 }
1940
1941 static void dsi1_dump_regs(struct seq_file *s)
1942 {
1943         struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
1944
1945         dsi_dump_dsidev_regs(dsidev, s);
1946 }
1947
1948 static void dsi2_dump_regs(struct seq_file *s)
1949 {
1950         struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
1951
1952         dsi_dump_dsidev_regs(dsidev, s);
1953 }
1954
1955 enum dsi_cio_power_state {
1956         DSI_COMPLEXIO_POWER_OFF         = 0x0,
1957         DSI_COMPLEXIO_POWER_ON          = 0x1,
1958         DSI_COMPLEXIO_POWER_ULPS        = 0x2,
1959 };
1960
1961 static int dsi_cio_power(struct platform_device *dsidev,
1962                 enum dsi_cio_power_state state)
1963 {
1964         int t = 0;
1965
1966         /* PWR_CMD */
1967         REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG1, state, 28, 27);
1968
1969         /* PWR_STATUS */
1970         while (FLD_GET(dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1),
1971                         26, 25) != state) {
1972                 if (++t > 1000) {
1973                         DSSERR("failed to set complexio power state to "
1974                                         "%d\n", state);
1975                         return -ENODEV;
1976                 }
1977                 udelay(1);
1978         }
1979
1980         return 0;
1981 }
1982
1983 static unsigned dsi_get_line_buf_size(struct platform_device *dsidev)
1984 {
1985         int val;
1986
1987         /* line buffer on OMAP3 is 1024 x 24bits */
1988         /* XXX: for some reason using full buffer size causes
1989          * considerable TX slowdown with update sizes that fill the
1990          * whole buffer */
1991         if (!dss_has_feature(FEAT_DSI_GNQ))
1992                 return 1023 * 3;
1993
1994         val = REG_GET(dsidev, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */
1995
1996         switch (val) {
1997         case 1:
1998                 return 512 * 3;         /* 512x24 bits */
1999         case 2:
2000                 return 682 * 3;         /* 682x24 bits */
2001         case 3:
2002                 return 853 * 3;         /* 853x24 bits */
2003         case 4:
2004                 return 1024 * 3;        /* 1024x24 bits */
2005         case 5:
2006                 return 1194 * 3;        /* 1194x24 bits */
2007         case 6:
2008                 return 1365 * 3;        /* 1365x24 bits */
2009         default:
2010                 BUG();
2011         }
2012 }
2013
2014 static int dsi_set_lane_config(struct omap_dss_device *dssdev)
2015 {
2016         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2017         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2018         static const u8 offsets[] = { 0, 4, 8, 12, 16 };
2019         static const enum dsi_lane_function functions[] = {
2020                 DSI_LANE_CLK,
2021                 DSI_LANE_DATA1,
2022                 DSI_LANE_DATA2,
2023                 DSI_LANE_DATA3,
2024                 DSI_LANE_DATA4,
2025         };
2026         u32 r;
2027         int i;
2028
2029         r = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1);
2030
2031         for (i = 0; i < dsi->num_lanes_used; ++i) {
2032                 unsigned offset = offsets[i];
2033                 unsigned polarity, lane_number;
2034                 unsigned t;
2035
2036                 for (t = 0; t < dsi->num_lanes_supported; ++t)
2037                         if (dsi->lanes[t].function == functions[i])
2038                                 break;
2039
2040                 if (t == dsi->num_lanes_supported)
2041                         return -EINVAL;
2042
2043                 lane_number = t;
2044                 polarity = dsi->lanes[t].polarity;
2045
2046                 r = FLD_MOD(r, lane_number + 1, offset + 2, offset);
2047                 r = FLD_MOD(r, polarity, offset + 3, offset + 3);
2048         }
2049
2050         /* clear the unused lanes */
2051         for (; i < dsi->num_lanes_supported; ++i) {
2052                 unsigned offset = offsets[i];
2053
2054                 r = FLD_MOD(r, 0, offset + 2, offset);
2055                 r = FLD_MOD(r, 0, offset + 3, offset + 3);
2056         }
2057
2058         dsi_write_reg(dsidev, DSI_COMPLEXIO_CFG1, r);
2059
2060         return 0;
2061 }
2062
2063 static inline unsigned ns2ddr(struct platform_device *dsidev, unsigned ns)
2064 {
2065         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2066
2067         /* convert time in ns to ddr ticks, rounding up */
2068         unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4;
2069         return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000;
2070 }
2071
2072 static inline unsigned ddr2ns(struct platform_device *dsidev, unsigned ddr)
2073 {
2074         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2075
2076         unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4;
2077         return ddr * 1000 * 1000 / (ddr_clk / 1000);
2078 }
2079
2080 static void dsi_cio_timings(struct platform_device *dsidev)
2081 {
2082         u32 r;
2083         u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
2084         u32 tlpx_half, tclk_trail, tclk_zero;
2085         u32 tclk_prepare;
2086
2087         /* calculate timings */
2088
2089         /* 1 * DDR_CLK = 2 * UI */
2090
2091         /* min 40ns + 4*UI      max 85ns + 6*UI */
2092         ths_prepare = ns2ddr(dsidev, 70) + 2;
2093
2094         /* min 145ns + 10*UI */
2095         ths_prepare_ths_zero = ns2ddr(dsidev, 175) + 2;
2096
2097         /* min max(8*UI, 60ns+4*UI) */
2098         ths_trail = ns2ddr(dsidev, 60) + 5;
2099
2100         /* min 100ns */
2101         ths_exit = ns2ddr(dsidev, 145);
2102
2103         /* tlpx min 50n */
2104         tlpx_half = ns2ddr(dsidev, 25);
2105
2106         /* min 60ns */
2107         tclk_trail = ns2ddr(dsidev, 60) + 2;
2108
2109         /* min 38ns, max 95ns */
2110         tclk_prepare = ns2ddr(dsidev, 65);
2111
2112         /* min tclk-prepare + tclk-zero = 300ns */
2113         tclk_zero = ns2ddr(dsidev, 260);
2114
2115         DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
2116                 ths_prepare, ddr2ns(dsidev, ths_prepare),
2117                 ths_prepare_ths_zero, ddr2ns(dsidev, ths_prepare_ths_zero));
2118         DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
2119                         ths_trail, ddr2ns(dsidev, ths_trail),
2120                         ths_exit, ddr2ns(dsidev, ths_exit));
2121
2122         DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
2123                         "tclk_zero %u (%uns)\n",
2124                         tlpx_half, ddr2ns(dsidev, tlpx_half),
2125                         tclk_trail, ddr2ns(dsidev, tclk_trail),
2126                         tclk_zero, ddr2ns(dsidev, tclk_zero));
2127         DSSDBG("tclk_prepare %u (%uns)\n",
2128                         tclk_prepare, ddr2ns(dsidev, tclk_prepare));
2129
2130         /* program timings */
2131
2132         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
2133         r = FLD_MOD(r, ths_prepare, 31, 24);
2134         r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
2135         r = FLD_MOD(r, ths_trail, 15, 8);
2136         r = FLD_MOD(r, ths_exit, 7, 0);
2137         dsi_write_reg(dsidev, DSI_DSIPHY_CFG0, r);
2138
2139         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
2140         r = FLD_MOD(r, tlpx_half, 22, 16);
2141         r = FLD_MOD(r, tclk_trail, 15, 8);
2142         r = FLD_MOD(r, tclk_zero, 7, 0);
2143         dsi_write_reg(dsidev, DSI_DSIPHY_CFG1, r);
2144
2145         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
2146         r = FLD_MOD(r, tclk_prepare, 7, 0);
2147         dsi_write_reg(dsidev, DSI_DSIPHY_CFG2, r);
2148 }
2149
2150 /* lane masks have lane 0 at lsb. mask_p for positive lines, n for negative */
2151 static void dsi_cio_enable_lane_override(struct omap_dss_device *dssdev,
2152                 unsigned mask_p, unsigned mask_n)
2153 {
2154         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2155         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2156         int i;
2157         u32 l;
2158         u8 lptxscp_start = dsi->num_lanes_supported == 3 ? 22 : 26;
2159
2160         l = 0;
2161
2162         for (i = 0; i < dsi->num_lanes_supported; ++i) {
2163                 unsigned p = dsi->lanes[i].polarity;
2164
2165                 if (mask_p & (1 << i))
2166                         l |= 1 << (i * 2 + (p ? 0 : 1));
2167
2168                 if (mask_n & (1 << i))
2169                         l |= 1 << (i * 2 + (p ? 1 : 0));
2170         }
2171
2172         /*
2173          * Bits in REGLPTXSCPDAT4TO0DXDY:
2174          * 17: DY0 18: DX0
2175          * 19: DY1 20: DX1
2176          * 21: DY2 22: DX2
2177          * 23: DY3 24: DX3
2178          * 25: DY4 26: DX4
2179          */
2180
2181         /* Set the lane override configuration */
2182
2183         /* REGLPTXSCPDAT4TO0DXDY */
2184         REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, l, lptxscp_start, 17);
2185
2186         /* Enable lane override */
2187
2188         /* ENLPTXSCPDAT */
2189         REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 1, 27, 27);
2190 }
2191
2192 static void dsi_cio_disable_lane_override(struct platform_device *dsidev)
2193 {
2194         /* Disable lane override */
2195         REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */
2196         /* Reset the lane override configuration */
2197         /* REGLPTXSCPDAT4TO0DXDY */
2198         REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 22, 17);
2199 }
2200
2201 static int dsi_cio_wait_tx_clk_esc_reset(struct omap_dss_device *dssdev)
2202 {
2203         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2204         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2205         int t, i;
2206         bool in_use[DSI_MAX_NR_LANES];
2207         static const u8 offsets_old[] = { 28, 27, 26 };
2208         static const u8 offsets_new[] = { 24, 25, 26, 27, 28 };
2209         const u8 *offsets;
2210
2211         if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC))
2212                 offsets = offsets_old;
2213         else
2214                 offsets = offsets_new;
2215
2216         for (i = 0; i < dsi->num_lanes_supported; ++i)
2217                 in_use[i] = dsi->lanes[i].function != DSI_LANE_UNUSED;
2218
2219         t = 100000;
2220         while (true) {
2221                 u32 l;
2222                 int ok;
2223
2224                 l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2225
2226                 ok = 0;
2227                 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2228                         if (!in_use[i] || (l & (1 << offsets[i])))
2229                                 ok++;
2230                 }
2231
2232                 if (ok == dsi->num_lanes_supported)
2233                         break;
2234
2235                 if (--t == 0) {
2236                         for (i = 0; i < dsi->num_lanes_supported; ++i) {
2237                                 if (!in_use[i] || (l & (1 << offsets[i])))
2238                                         continue;
2239
2240                                 DSSERR("CIO TXCLKESC%d domain not coming " \
2241                                                 "out of reset\n", i);
2242                         }
2243                         return -EIO;
2244                 }
2245         }
2246
2247         return 0;
2248 }
2249
2250 /* return bitmask of enabled lanes, lane0 being the lsb */
2251 static unsigned dsi_get_lane_mask(struct omap_dss_device *dssdev)
2252 {
2253         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2254         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2255         unsigned mask = 0;
2256         int i;
2257
2258         for (i = 0; i < dsi->num_lanes_supported; ++i) {
2259                 if (dsi->lanes[i].function != DSI_LANE_UNUSED)
2260                         mask |= 1 << i;
2261         }
2262
2263         return mask;
2264 }
2265
2266 static int dsi_cio_init(struct omap_dss_device *dssdev)
2267 {
2268         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2269         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2270         int r;
2271         u32 l;
2272
2273         DSSDBGF();
2274
2275         r = dss_dsi_enable_pads(dsi_get_dsidev_id(dsidev), dsi_get_lane_mask(dssdev));
2276         if (r)
2277                 return r;
2278
2279         dsi_enable_scp_clk(dsidev);
2280
2281         /* A dummy read using the SCP interface to any DSIPHY register is
2282          * required after DSIPHY reset to complete the reset of the DSI complex
2283          * I/O. */
2284         dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
2285
2286         if (wait_for_bit_change(dsidev, DSI_DSIPHY_CFG5, 30, 1) != 1) {
2287                 DSSERR("CIO SCP Clock domain not coming out of reset.\n");
2288                 r = -EIO;
2289                 goto err_scp_clk_dom;
2290         }
2291
2292         r = dsi_set_lane_config(dssdev);
2293         if (r)
2294                 goto err_scp_clk_dom;
2295
2296         /* set TX STOP MODE timer to maximum for this operation */
2297         l = dsi_read_reg(dsidev, DSI_TIMING1);
2298         l = FLD_MOD(l, 1, 15, 15);      /* FORCE_TX_STOP_MODE_IO */
2299         l = FLD_MOD(l, 1, 14, 14);      /* STOP_STATE_X16_IO */
2300         l = FLD_MOD(l, 1, 13, 13);      /* STOP_STATE_X4_IO */
2301         l = FLD_MOD(l, 0x1fff, 12, 0);  /* STOP_STATE_COUNTER_IO */
2302         dsi_write_reg(dsidev, DSI_TIMING1, l);
2303
2304         if (dsi->ulps_enabled) {
2305                 unsigned mask_p;
2306                 int i;
2307
2308                 DSSDBG("manual ulps exit\n");
2309
2310                 /* ULPS is exited by Mark-1 state for 1ms, followed by
2311                  * stop state. DSS HW cannot do this via the normal
2312                  * ULPS exit sequence, as after reset the DSS HW thinks
2313                  * that we are not in ULPS mode, and refuses to send the
2314                  * sequence. So we need to send the ULPS exit sequence
2315                  * manually by setting positive lines high and negative lines
2316                  * low for 1ms.
2317                  */
2318
2319                 mask_p = 0;
2320
2321                 for (i = 0; i < dsi->num_lanes_supported; ++i) {
2322                         if (dsi->lanes[i].function == DSI_LANE_UNUSED)
2323                                 continue;
2324                         mask_p |= 1 << i;
2325                 }
2326
2327                 dsi_cio_enable_lane_override(dssdev, mask_p, 0);
2328         }
2329
2330         r = dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ON);
2331         if (r)
2332                 goto err_cio_pwr;
2333
2334         if (wait_for_bit_change(dsidev, DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
2335                 DSSERR("CIO PWR clock domain not coming out of reset.\n");
2336                 r = -ENODEV;
2337                 goto err_cio_pwr_dom;
2338         }
2339
2340         dsi_if_enable(dsidev, true);
2341         dsi_if_enable(dsidev, false);
2342         REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
2343
2344         r = dsi_cio_wait_tx_clk_esc_reset(dssdev);
2345         if (r)
2346                 goto err_tx_clk_esc_rst;
2347
2348         if (dsi->ulps_enabled) {
2349                 /* Keep Mark-1 state for 1ms (as per DSI spec) */
2350                 ktime_t wait = ns_to_ktime(1000 * 1000);
2351                 set_current_state(TASK_UNINTERRUPTIBLE);
2352                 schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
2353
2354                 /* Disable the override. The lanes should be set to Mark-11
2355                  * state by the HW */
2356                 dsi_cio_disable_lane_override(dsidev);
2357         }
2358
2359         /* FORCE_TX_STOP_MODE_IO */
2360         REG_FLD_MOD(dsidev, DSI_TIMING1, 0, 15, 15);
2361
2362         dsi_cio_timings(dsidev);
2363
2364         if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
2365                 /* DDR_CLK_ALWAYS_ON */
2366                 REG_FLD_MOD(dsidev, DSI_CLK_CTRL,
2367                         dssdev->panel.dsi_vm_data.ddr_clk_always_on, 13, 13);
2368         }
2369
2370         dsi->ulps_enabled = false;
2371
2372         DSSDBG("CIO init done\n");
2373
2374         return 0;
2375
2376 err_tx_clk_esc_rst:
2377         REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */
2378 err_cio_pwr_dom:
2379         dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2380 err_cio_pwr:
2381         if (dsi->ulps_enabled)
2382                 dsi_cio_disable_lane_override(dsidev);
2383 err_scp_clk_dom:
2384         dsi_disable_scp_clk(dsidev);
2385         dss_dsi_disable_pads(dsi_get_dsidev_id(dsidev), dsi_get_lane_mask(dssdev));
2386         return r;
2387 }
2388
2389 static void dsi_cio_uninit(struct omap_dss_device *dssdev)
2390 {
2391         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2392
2393         /* DDR_CLK_ALWAYS_ON */
2394         REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13);
2395
2396         dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
2397         dsi_disable_scp_clk(dsidev);
2398         dss_dsi_disable_pads(dsi_get_dsidev_id(dsidev), dsi_get_lane_mask(dssdev));
2399 }
2400
2401 static void dsi_config_tx_fifo(struct platform_device *dsidev,
2402                 enum fifo_size size1, enum fifo_size size2,
2403                 enum fifo_size size3, enum fifo_size size4)
2404 {
2405         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2406         u32 r = 0;
2407         int add = 0;
2408         int i;
2409
2410         dsi->vc[0].fifo_size = size1;
2411         dsi->vc[1].fifo_size = size2;
2412         dsi->vc[2].fifo_size = size3;
2413         dsi->vc[3].fifo_size = size4;
2414
2415         for (i = 0; i < 4; i++) {
2416                 u8 v;
2417                 int size = dsi->vc[i].fifo_size;
2418
2419                 if (add + size > 4) {
2420                         DSSERR("Illegal FIFO configuration\n");
2421                         BUG();
2422                 }
2423
2424                 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2425                 r |= v << (8 * i);
2426                 /*DSSDBG("TX FIFO vc %d: size %d, add %d\n", i, size, add); */
2427                 add += size;
2428         }
2429
2430         dsi_write_reg(dsidev, DSI_TX_FIFO_VC_SIZE, r);
2431 }
2432
2433 static void dsi_config_rx_fifo(struct platform_device *dsidev,
2434                 enum fifo_size size1, enum fifo_size size2,
2435                 enum fifo_size size3, enum fifo_size size4)
2436 {
2437         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2438         u32 r = 0;
2439         int add = 0;
2440         int i;
2441
2442         dsi->vc[0].fifo_size = size1;
2443         dsi->vc[1].fifo_size = size2;
2444         dsi->vc[2].fifo_size = size3;
2445         dsi->vc[3].fifo_size = size4;
2446
2447         for (i = 0; i < 4; i++) {
2448                 u8 v;
2449                 int size = dsi->vc[i].fifo_size;
2450
2451                 if (add + size > 4) {
2452                         DSSERR("Illegal FIFO configuration\n");
2453                         BUG();
2454                 }
2455
2456                 v = FLD_VAL(add, 2, 0) | FLD_VAL(size, 7, 4);
2457                 r |= v << (8 * i);
2458                 /*DSSDBG("RX FIFO vc %d: size %d, add %d\n", i, size, add); */
2459                 add += size;
2460         }
2461
2462         dsi_write_reg(dsidev, DSI_RX_FIFO_VC_SIZE, r);
2463 }
2464
2465 static int dsi_force_tx_stop_mode_io(struct platform_device *dsidev)
2466 {
2467         u32 r;
2468
2469         r = dsi_read_reg(dsidev, DSI_TIMING1);
2470         r = FLD_MOD(r, 1, 15, 15);      /* FORCE_TX_STOP_MODE_IO */
2471         dsi_write_reg(dsidev, DSI_TIMING1, r);
2472
2473         if (wait_for_bit_change(dsidev, DSI_TIMING1, 15, 0) != 0) {
2474                 DSSERR("TX_STOP bit not going down\n");
2475                 return -EIO;
2476         }
2477
2478         return 0;
2479 }
2480
2481 static bool dsi_vc_is_enabled(struct platform_device *dsidev, int channel)
2482 {
2483         return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0);
2484 }
2485
2486 static void dsi_packet_sent_handler_vp(void *data, u32 mask)
2487 {
2488         struct dsi_packet_sent_handler_data *vp_data =
2489                 (struct dsi_packet_sent_handler_data *) data;
2490         struct dsi_data *dsi = dsi_get_dsidrv_data(vp_data->dsidev);
2491         const int channel = dsi->update_channel;
2492         u8 bit = dsi->te_enabled ? 30 : 31;
2493
2494         if (REG_GET(vp_data->dsidev, DSI_VC_TE(channel), bit, bit) == 0)
2495                 complete(vp_data->completion);
2496 }
2497
2498 static int dsi_sync_vc_vp(struct platform_device *dsidev, int channel)
2499 {
2500         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2501         DECLARE_COMPLETION_ONSTACK(completion);
2502         struct dsi_packet_sent_handler_data vp_data = { dsidev, &completion };
2503         int r = 0;
2504         u8 bit;
2505
2506         bit = dsi->te_enabled ? 30 : 31;
2507
2508         r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2509                 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2510         if (r)
2511                 goto err0;
2512
2513         /* Wait for completion only if TE_EN/TE_START is still set */
2514         if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit)) {
2515                 if (wait_for_completion_timeout(&completion,
2516                                 msecs_to_jiffies(10)) == 0) {
2517                         DSSERR("Failed to complete previous frame transfer\n");
2518                         r = -EIO;
2519                         goto err1;
2520                 }
2521         }
2522
2523         dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2524                 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2525
2526         return 0;
2527 err1:
2528         dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
2529                 &vp_data, DSI_VC_IRQ_PACKET_SENT);
2530 err0:
2531         return r;
2532 }
2533
2534 static void dsi_packet_sent_handler_l4(void *data, u32 mask)
2535 {
2536         struct dsi_packet_sent_handler_data *l4_data =
2537                 (struct dsi_packet_sent_handler_data *) data;
2538         struct dsi_data *dsi = dsi_get_dsidrv_data(l4_data->dsidev);
2539         const int channel = dsi->update_channel;
2540
2541         if (REG_GET(l4_data->dsidev, DSI_VC_CTRL(channel), 5, 5) == 0)
2542                 complete(l4_data->completion);
2543 }
2544
2545 static int dsi_sync_vc_l4(struct platform_device *dsidev, int channel)
2546 {
2547         DECLARE_COMPLETION_ONSTACK(completion);
2548         struct dsi_packet_sent_handler_data l4_data = { dsidev, &completion };
2549         int r = 0;
2550
2551         r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2552                 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2553         if (r)
2554                 goto err0;
2555
2556         /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */
2557         if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) {
2558                 if (wait_for_completion_timeout(&completion,
2559                                 msecs_to_jiffies(10)) == 0) {
2560                         DSSERR("Failed to complete previous l4 transfer\n");
2561                         r = -EIO;
2562                         goto err1;
2563                 }
2564         }
2565
2566         dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2567                 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2568
2569         return 0;
2570 err1:
2571         dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
2572                 &l4_data, DSI_VC_IRQ_PACKET_SENT);
2573 err0:
2574         return r;
2575 }
2576
2577 static int dsi_sync_vc(struct platform_device *dsidev, int channel)
2578 {
2579         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2580
2581         WARN_ON(!dsi_bus_is_locked(dsidev));
2582
2583         WARN_ON(in_interrupt());
2584
2585         if (!dsi_vc_is_enabled(dsidev, channel))
2586                 return 0;
2587
2588         switch (dsi->vc[channel].source) {
2589         case DSI_VC_SOURCE_VP:
2590                 return dsi_sync_vc_vp(dsidev, channel);
2591         case DSI_VC_SOURCE_L4:
2592                 return dsi_sync_vc_l4(dsidev, channel);
2593         default:
2594                 BUG();
2595         }
2596 }
2597
2598 static int dsi_vc_enable(struct platform_device *dsidev, int channel,
2599                 bool enable)
2600 {
2601         DSSDBG("dsi_vc_enable channel %d, enable %d\n",
2602                         channel, enable);
2603
2604         enable = enable ? 1 : 0;
2605
2606         REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 0, 0);
2607
2608         if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel),
2609                 0, enable) != enable) {
2610                         DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
2611                         return -EIO;
2612         }
2613
2614         return 0;
2615 }
2616
2617 static void dsi_vc_initial_config(struct platform_device *dsidev, int channel)
2618 {
2619         u32 r;
2620
2621         DSSDBGF("%d", channel);
2622
2623         r = dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
2624
2625         if (FLD_GET(r, 15, 15)) /* VC_BUSY */
2626                 DSSERR("VC(%d) busy when trying to configure it!\n",
2627                                 channel);
2628
2629         r = FLD_MOD(r, 0, 1, 1); /* SOURCE, 0 = L4 */
2630         r = FLD_MOD(r, 0, 2, 2); /* BTA_SHORT_EN  */
2631         r = FLD_MOD(r, 0, 3, 3); /* BTA_LONG_EN */
2632         r = FLD_MOD(r, 0, 4, 4); /* MODE, 0 = command */
2633         r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
2634         r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
2635         r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
2636         if (dss_has_feature(FEAT_DSI_VC_OCP_WIDTH))
2637                 r = FLD_MOD(r, 3, 11, 10);      /* OCP_WIDTH = 32 bit */
2638
2639         r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
2640         r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
2641
2642         dsi_write_reg(dsidev, DSI_VC_CTRL(channel), r);
2643 }
2644
2645 static int dsi_vc_config_source(struct platform_device *dsidev, int channel,
2646                 enum dsi_vc_source source)
2647 {
2648         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2649
2650         if (dsi->vc[channel].source == source)
2651                 return 0;
2652
2653         DSSDBGF("%d", channel);
2654
2655         dsi_sync_vc(dsidev, channel);
2656
2657         dsi_vc_enable(dsidev, channel, 0);
2658
2659         /* VC_BUSY */
2660         if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 15, 0) != 0) {
2661                 DSSERR("vc(%d) busy when trying to config for VP\n", channel);
2662                 return -EIO;
2663         }
2664
2665         /* SOURCE, 0 = L4, 1 = video port */
2666         REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), source, 1, 1);
2667
2668         /* DCS_CMD_ENABLE */
2669         if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
2670                 bool enable = source == DSI_VC_SOURCE_VP;
2671                 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 30, 30);
2672         }
2673
2674         dsi_vc_enable(dsidev, channel, 1);
2675
2676         dsi->vc[channel].source = source;
2677
2678         return 0;
2679 }
2680
2681 void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
2682                 bool enable)
2683 {
2684         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2685
2686         DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
2687
2688         WARN_ON(!dsi_bus_is_locked(dsidev));
2689
2690         dsi_vc_enable(dsidev, channel, 0);
2691         dsi_if_enable(dsidev, 0);
2692
2693         REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 9, 9);
2694
2695         dsi_vc_enable(dsidev, channel, 1);
2696         dsi_if_enable(dsidev, 1);
2697
2698         dsi_force_tx_stop_mode_io(dsidev);
2699
2700         /* start the DDR clock by sending a NULL packet */
2701         if (dssdev->panel.dsi_vm_data.ddr_clk_always_on && enable)
2702                 dsi_vc_send_null(dssdev, channel);
2703 }
2704 EXPORT_SYMBOL(omapdss_dsi_vc_enable_hs);
2705
2706 static void dsi_vc_flush_long_data(struct platform_device *dsidev, int channel)
2707 {
2708         while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2709                 u32 val;
2710                 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2711                 DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
2712                                 (val >> 0) & 0xff,
2713                                 (val >> 8) & 0xff,
2714                                 (val >> 16) & 0xff,
2715                                 (val >> 24) & 0xff);
2716         }
2717 }
2718
2719 static void dsi_show_rx_ack_with_err(u16 err)
2720 {
2721         DSSERR("\tACK with ERROR (%#x):\n", err);
2722         if (err & (1 << 0))
2723                 DSSERR("\t\tSoT Error\n");
2724         if (err & (1 << 1))
2725                 DSSERR("\t\tSoT Sync Error\n");
2726         if (err & (1 << 2))
2727                 DSSERR("\t\tEoT Sync Error\n");
2728         if (err & (1 << 3))
2729                 DSSERR("\t\tEscape Mode Entry Command Error\n");
2730         if (err & (1 << 4))
2731                 DSSERR("\t\tLP Transmit Sync Error\n");
2732         if (err & (1 << 5))
2733                 DSSERR("\t\tHS Receive Timeout Error\n");
2734         if (err & (1 << 6))
2735                 DSSERR("\t\tFalse Control Error\n");
2736         if (err & (1 << 7))
2737                 DSSERR("\t\t(reserved7)\n");
2738         if (err & (1 << 8))
2739                 DSSERR("\t\tECC Error, single-bit (corrected)\n");
2740         if (err & (1 << 9))
2741                 DSSERR("\t\tECC Error, multi-bit (not corrected)\n");
2742         if (err & (1 << 10))
2743                 DSSERR("\t\tChecksum Error\n");
2744         if (err & (1 << 11))
2745                 DSSERR("\t\tData type not recognized\n");
2746         if (err & (1 << 12))
2747                 DSSERR("\t\tInvalid VC ID\n");
2748         if (err & (1 << 13))
2749                 DSSERR("\t\tInvalid Transmission Length\n");
2750         if (err & (1 << 14))
2751                 DSSERR("\t\t(reserved14)\n");
2752         if (err & (1 << 15))
2753                 DSSERR("\t\tDSI Protocol Violation\n");
2754 }
2755
2756 static u16 dsi_vc_flush_receive_data(struct platform_device *dsidev,
2757                 int channel)
2758 {
2759         /* RX_FIFO_NOT_EMPTY */
2760         while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2761                 u32 val;
2762                 u8 dt;
2763                 val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
2764                 DSSERR("\trawval %#08x\n", val);
2765                 dt = FLD_GET(val, 5, 0);
2766                 if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
2767                         u16 err = FLD_GET(val, 23, 8);
2768                         dsi_show_rx_ack_with_err(err);
2769                 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE) {
2770                         DSSERR("\tDCS short response, 1 byte: %#x\n",
2771                                         FLD_GET(val, 23, 8));
2772                 } else if (dt == MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE) {
2773                         DSSERR("\tDCS short response, 2 byte: %#x\n",
2774                                         FLD_GET(val, 23, 8));
2775                 } else if (dt == MIPI_DSI_RX_DCS_LONG_READ_RESPONSE) {
2776                         DSSERR("\tDCS long response, len %d\n",
2777                                         FLD_GET(val, 23, 8));
2778                         dsi_vc_flush_long_data(dsidev, channel);
2779                 } else {
2780                         DSSERR("\tunknown datatype 0x%02x\n", dt);
2781                 }
2782         }
2783         return 0;
2784 }
2785
2786 static int dsi_vc_send_bta(struct platform_device *dsidev, int channel)
2787 {
2788         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2789
2790         if (dsi->debug_write || dsi->debug_read)
2791                 DSSDBG("dsi_vc_send_bta %d\n", channel);
2792
2793         WARN_ON(!dsi_bus_is_locked(dsidev));
2794
2795         /* RX_FIFO_NOT_EMPTY */
2796         if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
2797                 DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
2798                 dsi_vc_flush_receive_data(dsidev, channel);
2799         }
2800
2801         REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
2802
2803         /* flush posted write */
2804         dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
2805
2806         return 0;
2807 }
2808
2809 int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel)
2810 {
2811         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2812         DECLARE_COMPLETION_ONSTACK(completion);
2813         int r = 0;
2814         u32 err;
2815
2816         r = dsi_register_isr_vc(dsidev, channel, dsi_completion_handler,
2817                         &completion, DSI_VC_IRQ_BTA);
2818         if (r)
2819                 goto err0;
2820
2821         r = dsi_register_isr(dsidev, dsi_completion_handler, &completion,
2822                         DSI_IRQ_ERROR_MASK);
2823         if (r)
2824                 goto err1;
2825
2826         r = dsi_vc_send_bta(dsidev, channel);
2827         if (r)
2828                 goto err2;
2829
2830         if (wait_for_completion_timeout(&completion,
2831                                 msecs_to_jiffies(500)) == 0) {
2832                 DSSERR("Failed to receive BTA\n");
2833                 r = -EIO;
2834                 goto err2;
2835         }
2836
2837         err = dsi_get_errors(dsidev);
2838         if (err) {
2839                 DSSERR("Error while sending BTA: %x\n", err);
2840                 r = -EIO;
2841                 goto err2;
2842         }
2843 err2:
2844         dsi_unregister_isr(dsidev, dsi_completion_handler, &completion,
2845                         DSI_IRQ_ERROR_MASK);
2846 err1:
2847         dsi_unregister_isr_vc(dsidev, channel, dsi_completion_handler,
2848                         &completion, DSI_VC_IRQ_BTA);
2849 err0:
2850         return r;
2851 }
2852 EXPORT_SYMBOL(dsi_vc_send_bta_sync);
2853
2854 static inline void dsi_vc_write_long_header(struct platform_device *dsidev,
2855                 int channel, u8 data_type, u16 len, u8 ecc)
2856 {
2857         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2858         u32 val;
2859         u8 data_id;
2860
2861         WARN_ON(!dsi_bus_is_locked(dsidev));
2862
2863         data_id = data_type | dsi->vc[channel].vc_id << 6;
2864
2865         val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
2866                 FLD_VAL(ecc, 31, 24);
2867
2868         dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_HEADER(channel), val);
2869 }
2870
2871 static inline void dsi_vc_write_long_payload(struct platform_device *dsidev,
2872                 int channel, u8 b1, u8 b2, u8 b3, u8 b4)
2873 {
2874         u32 val;
2875
2876         val = b4 << 24 | b3 << 16 | b2 << 8  | b1 << 0;
2877
2878 /*      DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
2879                         b1, b2, b3, b4, val); */
2880
2881         dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
2882 }
2883
2884 static int dsi_vc_send_long(struct platform_device *dsidev, int channel,
2885                 u8 data_type, u8 *data, u16 len, u8 ecc)
2886 {
2887         /*u32 val; */
2888         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2889         int i;
2890         u8 *p;
2891         int r = 0;
2892         u8 b1, b2, b3, b4;
2893
2894         if (dsi->debug_write)
2895                 DSSDBG("dsi_vc_send_long, %d bytes\n", len);
2896
2897         /* len + header */
2898         if (dsi->vc[channel].fifo_size * 32 * 4 < len + 4) {
2899                 DSSERR("unable to send long packet: packet too long.\n");
2900                 return -EINVAL;
2901         }
2902
2903         dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
2904
2905         dsi_vc_write_long_header(dsidev, channel, data_type, len, ecc);
2906
2907         p = data;
2908         for (i = 0; i < len >> 2; i++) {
2909                 if (dsi->debug_write)
2910                         DSSDBG("\tsending full packet %d\n", i);
2911
2912                 b1 = *p++;
2913                 b2 = *p++;
2914                 b3 = *p++;
2915                 b4 = *p++;
2916
2917                 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, b4);
2918         }
2919
2920         i = len % 4;
2921         if (i) {
2922                 b1 = 0; b2 = 0; b3 = 0;
2923
2924                 if (dsi->debug_write)
2925                         DSSDBG("\tsending remainder bytes %d\n", i);
2926
2927                 switch (i) {
2928                 case 3:
2929                         b1 = *p++;
2930                         b2 = *p++;
2931                         b3 = *p++;
2932                         break;
2933                 case 2:
2934                         b1 = *p++;
2935                         b2 = *p++;
2936                         break;
2937                 case 1:
2938                         b1 = *p++;
2939                         break;
2940                 }
2941
2942                 dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, 0);
2943         }
2944
2945         return r;
2946 }
2947
2948 static int dsi_vc_send_short(struct platform_device *dsidev, int channel,
2949                 u8 data_type, u16 data, u8 ecc)
2950 {
2951         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
2952         u32 r;
2953         u8 data_id;
2954
2955         WARN_ON(!dsi_bus_is_locked(dsidev));
2956
2957         if (dsi->debug_write)
2958                 DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
2959                                 channel,
2960                                 data_type, data & 0xff, (data >> 8) & 0xff);
2961
2962         dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_L4);
2963
2964         if (FLD_GET(dsi_read_reg(dsidev, DSI_VC_CTRL(channel)), 16, 16)) {
2965                 DSSERR("ERROR FIFO FULL, aborting transfer\n");
2966                 return -EINVAL;
2967         }
2968
2969         data_id = data_type | dsi->vc[channel].vc_id << 6;
2970
2971         r = (data_id << 0) | (data << 8) | (ecc << 24);
2972
2973         dsi_write_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel), r);
2974
2975         return 0;
2976 }
2977
2978 int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel)
2979 {
2980         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2981
2982         return dsi_vc_send_long(dsidev, channel, MIPI_DSI_NULL_PACKET, NULL,
2983                 0, 0);
2984 }
2985 EXPORT_SYMBOL(dsi_vc_send_null);
2986
2987 static int dsi_vc_write_nosync_common(struct omap_dss_device *dssdev,
2988                 int channel, u8 *data, int len, enum dss_dsi_content_type type)
2989 {
2990         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
2991         int r;
2992
2993         if (len == 0) {
2994                 BUG_ON(type == DSS_DSI_CONTENT_DCS);
2995                 r = dsi_vc_send_short(dsidev, channel,
2996                                 MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM, 0, 0);
2997         } else if (len == 1) {
2998                 r = dsi_vc_send_short(dsidev, channel,
2999                                 type == DSS_DSI_CONTENT_GENERIC ?
3000                                 MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM :
3001                                 MIPI_DSI_DCS_SHORT_WRITE, data[0], 0);
3002         } else if (len == 2) {
3003                 r = dsi_vc_send_short(dsidev, channel,
3004                                 type == DSS_DSI_CONTENT_GENERIC ?
3005                                 MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM :
3006                                 MIPI_DSI_DCS_SHORT_WRITE_PARAM,
3007                                 data[0] | (data[1] << 8), 0);
3008         } else {
3009                 r = dsi_vc_send_long(dsidev, channel,
3010                                 type == DSS_DSI_CONTENT_GENERIC ?
3011                                 MIPI_DSI_GENERIC_LONG_WRITE :
3012                                 MIPI_DSI_DCS_LONG_WRITE, data, len, 0);
3013         }
3014
3015         return r;
3016 }
3017
3018 int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
3019                 u8 *data, int len)
3020 {
3021         return dsi_vc_write_nosync_common(dssdev, channel, data, len,
3022                         DSS_DSI_CONTENT_DCS);
3023 }
3024 EXPORT_SYMBOL(dsi_vc_dcs_write_nosync);
3025
3026 int dsi_vc_generic_write_nosync(struct omap_dss_device *dssdev, int channel,
3027                 u8 *data, int len)
3028 {
3029         return dsi_vc_write_nosync_common(dssdev, channel, data, len,
3030                         DSS_DSI_CONTENT_GENERIC);
3031 }
3032 EXPORT_SYMBOL(dsi_vc_generic_write_nosync);
3033
3034 static int dsi_vc_write_common(struct omap_dss_device *dssdev, int channel,
3035                 u8 *data, int len, enum dss_dsi_content_type type)
3036 {
3037         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3038         int r;
3039
3040         r = dsi_vc_write_nosync_common(dssdev, channel, data, len, type);
3041         if (r)
3042                 goto err;
3043
3044         r = dsi_vc_send_bta_sync(dssdev, channel);
3045         if (r)
3046                 goto err;
3047
3048         /* RX_FIFO_NOT_EMPTY */
3049         if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
3050                 DSSERR("rx fifo not empty after write, dumping data:\n");
3051                 dsi_vc_flush_receive_data(dsidev, channel);
3052                 r = -EIO;
3053                 goto err;
3054         }
3055
3056         return 0;
3057 err:
3058         DSSERR("dsi_vc_write_common(ch %d, cmd 0x%02x, len %d) failed\n",
3059                         channel, data[0], len);
3060         return r;
3061 }
3062
3063 int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
3064                 int len)
3065 {
3066         return dsi_vc_write_common(dssdev, channel, data, len,
3067                         DSS_DSI_CONTENT_DCS);
3068 }
3069 EXPORT_SYMBOL(dsi_vc_dcs_write);
3070
3071 int dsi_vc_generic_write(struct omap_dss_device *dssdev, int channel, u8 *data,
3072                 int len)
3073 {
3074         return dsi_vc_write_common(dssdev, channel, data, len,
3075                         DSS_DSI_CONTENT_GENERIC);
3076 }
3077 EXPORT_SYMBOL(dsi_vc_generic_write);
3078
3079 int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd)
3080 {
3081         return dsi_vc_dcs_write(dssdev, channel, &dcs_cmd, 1);
3082 }
3083 EXPORT_SYMBOL(dsi_vc_dcs_write_0);
3084
3085 int dsi_vc_generic_write_0(struct omap_dss_device *dssdev, int channel)
3086 {
3087         return dsi_vc_generic_write(dssdev, channel, NULL, 0);
3088 }
3089 EXPORT_SYMBOL(dsi_vc_generic_write_0);
3090
3091 int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3092                 u8 param)
3093 {
3094         u8 buf[2];
3095         buf[0] = dcs_cmd;
3096         buf[1] = param;
3097         return dsi_vc_dcs_write(dssdev, channel, buf, 2);
3098 }
3099 EXPORT_SYMBOL(dsi_vc_dcs_write_1);
3100
3101 int dsi_vc_generic_write_1(struct omap_dss_device *dssdev, int channel,
3102                 u8 param)
3103 {
3104         return dsi_vc_generic_write(dssdev, channel, &param, 1);
3105 }
3106 EXPORT_SYMBOL(dsi_vc_generic_write_1);
3107
3108 int dsi_vc_generic_write_2(struct omap_dss_device *dssdev, int channel,
3109                 u8 param1, u8 param2)
3110 {
3111         u8 buf[2];
3112         buf[0] = param1;
3113         buf[1] = param2;
3114         return dsi_vc_generic_write(dssdev, channel, buf, 2);
3115 }
3116 EXPORT_SYMBOL(dsi_vc_generic_write_2);
3117
3118 static int dsi_vc_dcs_send_read_request(struct omap_dss_device *dssdev,
3119                 int channel, u8 dcs_cmd)
3120 {
3121         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3122         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3123         int r;
3124
3125         if (dsi->debug_read)
3126                 DSSDBG("dsi_vc_dcs_send_read_request(ch%d, dcs_cmd %x)\n",
3127                         channel, dcs_cmd);
3128
3129         r = dsi_vc_send_short(dsidev, channel, MIPI_DSI_DCS_READ, dcs_cmd, 0);
3130         if (r) {
3131                 DSSERR("dsi_vc_dcs_send_read_request(ch %d, cmd 0x%02x)"
3132                         " failed\n", channel, dcs_cmd);
3133                 return r;
3134         }
3135
3136         return 0;
3137 }
3138
3139 static int dsi_vc_generic_send_read_request(struct omap_dss_device *dssdev,
3140                 int channel, u8 *reqdata, int reqlen)
3141 {
3142         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3143         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3144         u16 data;
3145         u8 data_type;
3146         int r;
3147
3148         if (dsi->debug_read)
3149                 DSSDBG("dsi_vc_generic_send_read_request(ch %d, reqlen %d)\n",
3150                         channel, reqlen);
3151
3152         if (reqlen == 0) {
3153                 data_type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM;
3154                 data = 0;
3155         } else if (reqlen == 1) {
3156                 data_type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM;
3157                 data = reqdata[0];
3158         } else if (reqlen == 2) {
3159                 data_type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM;
3160                 data = reqdata[0] | (reqdata[1] << 8);
3161         } else {
3162                 BUG();
3163         }
3164
3165         r = dsi_vc_send_short(dsidev, channel, data_type, data, 0);
3166         if (r) {
3167                 DSSERR("dsi_vc_generic_send_read_request(ch %d, reqlen %d)"
3168                         " failed\n", channel, reqlen);
3169                 return r;
3170         }
3171
3172         return 0;
3173 }
3174
3175 static int dsi_vc_read_rx_fifo(struct platform_device *dsidev, int channel,
3176                 u8 *buf, int buflen, enum dss_dsi_content_type type)
3177 {
3178         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3179         u32 val;
3180         u8 dt;
3181         int r;
3182
3183         /* RX_FIFO_NOT_EMPTY */
3184         if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20) == 0) {
3185                 DSSERR("RX fifo empty when trying to read.\n");
3186                 r = -EIO;
3187                 goto err;
3188         }
3189
3190         val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
3191         if (dsi->debug_read)
3192                 DSSDBG("\theader: %08x\n", val);
3193         dt = FLD_GET(val, 5, 0);
3194         if (dt == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) {
3195                 u16 err = FLD_GET(val, 23, 8);
3196                 dsi_show_rx_ack_with_err(err);
3197                 r = -EIO;
3198                 goto err;
3199
3200         } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3201                         MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE :
3202                         MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE)) {
3203                 u8 data = FLD_GET(val, 15, 8);
3204                 if (dsi->debug_read)
3205                         DSSDBG("\t%s short response, 1 byte: %02x\n",
3206                                 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3207                                 "DCS", data);
3208
3209                 if (buflen < 1) {
3210                         r = -EIO;
3211                         goto err;
3212                 }
3213
3214                 buf[0] = data;
3215
3216                 return 1;
3217         } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3218                         MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE :
3219                         MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE)) {
3220                 u16 data = FLD_GET(val, 23, 8);
3221                 if (dsi->debug_read)
3222                         DSSDBG("\t%s short response, 2 byte: %04x\n",
3223                                 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3224                                 "DCS", data);
3225
3226                 if (buflen < 2) {
3227                         r = -EIO;
3228                         goto err;
3229                 }
3230
3231                 buf[0] = data & 0xff;
3232                 buf[1] = (data >> 8) & 0xff;
3233
3234                 return 2;
3235         } else if (dt == (type == DSS_DSI_CONTENT_GENERIC ?
3236                         MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE :
3237                         MIPI_DSI_RX_DCS_LONG_READ_RESPONSE)) {
3238                 int w;
3239                 int len = FLD_GET(val, 23, 8);
3240                 if (dsi->debug_read)
3241                         DSSDBG("\t%s long response, len %d\n",
3242                                 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" :
3243                                 "DCS", len);
3244
3245                 if (len > buflen) {
3246                         r = -EIO;
3247                         goto err;
3248                 }
3249
3250                 /* two byte checksum ends the packet, not included in len */
3251                 for (w = 0; w < len + 2;) {
3252                         int b;
3253                         val = dsi_read_reg(dsidev,
3254                                 DSI_VC_SHORT_PACKET_HEADER(channel));
3255                         if (dsi->debug_read)
3256                                 DSSDBG("\t\t%02x %02x %02x %02x\n",
3257                                                 (val >> 0) & 0xff,
3258                                                 (val >> 8) & 0xff,
3259                                                 (val >> 16) & 0xff,
3260                                                 (val >> 24) & 0xff);
3261
3262                         for (b = 0; b < 4; ++b) {
3263                                 if (w < len)
3264                                         buf[w] = (val >> (b * 8)) & 0xff;
3265                                 /* we discard the 2 byte checksum */
3266                                 ++w;
3267                         }
3268                 }
3269
3270                 return len;
3271         } else {
3272                 DSSERR("\tunknown datatype 0x%02x\n", dt);
3273                 r = -EIO;
3274                 goto err;
3275         }
3276
3277         BUG();
3278 err:
3279         DSSERR("dsi_vc_read_rx_fifo(ch %d type %s) failed\n", channel,
3280                 type == DSS_DSI_CONTENT_GENERIC ? "GENERIC" : "DCS");
3281
3282         return r;
3283 }
3284
3285 int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
3286                 u8 *buf, int buflen)
3287 {
3288         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3289         int r;
3290
3291         r = dsi_vc_dcs_send_read_request(dssdev, channel, dcs_cmd);
3292         if (r)
3293                 goto err;
3294
3295         r = dsi_vc_send_bta_sync(dssdev, channel);
3296         if (r)
3297                 goto err;
3298
3299         r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
3300                 DSS_DSI_CONTENT_DCS);
3301         if (r < 0)
3302                 goto err;
3303
3304         if (r != buflen) {
3305                 r = -EIO;
3306                 goto err;
3307         }
3308
3309         return 0;
3310 err:
3311         DSSERR("dsi_vc_dcs_read(ch %d, cmd 0x%02x) failed\n", channel, dcs_cmd);
3312         return r;
3313 }
3314 EXPORT_SYMBOL(dsi_vc_dcs_read);
3315
3316 static int dsi_vc_generic_read(struct omap_dss_device *dssdev, int channel,
3317                 u8 *reqdata, int reqlen, u8 *buf, int buflen)
3318 {
3319         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3320         int r;
3321
3322         r = dsi_vc_generic_send_read_request(dssdev, channel, reqdata, reqlen);
3323         if (r)
3324                 return r;
3325
3326         r = dsi_vc_send_bta_sync(dssdev, channel);
3327         if (r)
3328                 return r;
3329
3330         r = dsi_vc_read_rx_fifo(dsidev, channel, buf, buflen,
3331                 DSS_DSI_CONTENT_GENERIC);
3332         if (r < 0)
3333                 return r;
3334
3335         if (r != buflen) {
3336                 r = -EIO;
3337                 return r;
3338         }
3339
3340         return 0;
3341 }
3342
3343 int dsi_vc_generic_read_0(struct omap_dss_device *dssdev, int channel, u8 *buf,
3344                 int buflen)
3345 {
3346         int r;
3347
3348         r = dsi_vc_generic_read(dssdev, channel, NULL, 0, buf, buflen);
3349         if (r) {
3350                 DSSERR("dsi_vc_generic_read_0(ch %d) failed\n", channel);
3351                 return r;
3352         }
3353
3354         return 0;
3355 }
3356 EXPORT_SYMBOL(dsi_vc_generic_read_0);
3357
3358 int dsi_vc_generic_read_1(struct omap_dss_device *dssdev, int channel, u8 param,
3359                 u8 *buf, int buflen)
3360 {
3361         int r;
3362
3363         r = dsi_vc_generic_read(dssdev, channel, &param, 1, buf, buflen);
3364         if (r) {
3365                 DSSERR("dsi_vc_generic_read_1(ch %d) failed\n", channel);
3366                 return r;
3367         }
3368
3369         return 0;
3370 }
3371 EXPORT_SYMBOL(dsi_vc_generic_read_1);
3372
3373 int dsi_vc_generic_read_2(struct omap_dss_device *dssdev, int channel,
3374                 u8 param1, u8 param2, u8 *buf, int buflen)
3375 {
3376         int r;
3377         u8 reqdata[2];
3378
3379         reqdata[0] = param1;
3380         reqdata[1] = param2;
3381
3382         r = dsi_vc_generic_read(dssdev, channel, reqdata, 2, buf, buflen);
3383         if (r) {
3384                 DSSERR("dsi_vc_generic_read_2(ch %d) failed\n", channel);
3385                 return r;
3386         }
3387
3388         return 0;
3389 }
3390 EXPORT_SYMBOL(dsi_vc_generic_read_2);
3391
3392 int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
3393                 u16 len)
3394 {
3395         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3396
3397         return dsi_vc_send_short(dsidev, channel,
3398                         MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, len, 0);
3399 }
3400 EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size);
3401
3402 static int dsi_enter_ulps(struct platform_device *dsidev)
3403 {
3404         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3405         DECLARE_COMPLETION_ONSTACK(completion);
3406         int r, i;
3407         unsigned mask;
3408
3409         DSSDBGF();
3410
3411         WARN_ON(!dsi_bus_is_locked(dsidev));
3412
3413         WARN_ON(dsi->ulps_enabled);
3414
3415         if (dsi->ulps_enabled)
3416                 return 0;
3417
3418         /* DDR_CLK_ALWAYS_ON */
3419         if (REG_GET(dsidev, DSI_CLK_CTRL, 13, 13)) {
3420                 dsi_if_enable(dsidev, 0);
3421                 REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 13, 13);
3422                 dsi_if_enable(dsidev, 1);
3423         }
3424
3425         dsi_sync_vc(dsidev, 0);
3426         dsi_sync_vc(dsidev, 1);
3427         dsi_sync_vc(dsidev, 2);
3428         dsi_sync_vc(dsidev, 3);
3429
3430         dsi_force_tx_stop_mode_io(dsidev);
3431
3432         dsi_vc_enable(dsidev, 0, false);
3433         dsi_vc_enable(dsidev, 1, false);
3434         dsi_vc_enable(dsidev, 2, false);
3435         dsi_vc_enable(dsidev, 3, false);
3436
3437         if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 16, 16)) {      /* HS_BUSY */
3438                 DSSERR("HS busy when enabling ULPS\n");
3439                 return -EIO;
3440         }
3441
3442         if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 17, 17)) {      /* LP_BUSY */
3443                 DSSERR("LP busy when enabling ULPS\n");
3444                 return -EIO;
3445         }
3446
3447         r = dsi_register_isr_cio(dsidev, dsi_completion_handler, &completion,
3448                         DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3449         if (r)
3450                 return r;
3451
3452         mask = 0;
3453
3454         for (i = 0; i < dsi->num_lanes_supported; ++i) {
3455                 if (dsi->lanes[i].function == DSI_LANE_UNUSED)
3456                         continue;
3457                 mask |= 1 << i;
3458         }
3459         /* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */
3460         /* LANEx_ULPS_SIG2 */
3461         REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, mask, 9, 5);
3462
3463         /* flush posted write and wait for SCP interface to finish the write */
3464         dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
3465
3466         if (wait_for_completion_timeout(&completion,
3467                                 msecs_to_jiffies(1000)) == 0) {
3468                 DSSERR("ULPS enable timeout\n");
3469                 r = -EIO;
3470                 goto err;
3471         }
3472
3473         dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3474                         DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3475
3476         /* Reset LANEx_ULPS_SIG2 */
3477         REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, 0, 9, 5);
3478
3479         /* flush posted write and wait for SCP interface to finish the write */
3480         dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG2);
3481
3482         dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ULPS);
3483
3484         dsi_if_enable(dsidev, false);
3485
3486         dsi->ulps_enabled = true;
3487
3488         return 0;
3489
3490 err:
3491         dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
3492                         DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
3493         return r;
3494 }
3495
3496 static void dsi_set_lp_rx_timeout(struct platform_device *dsidev,
3497                 unsigned ticks, bool x4, bool x16)
3498 {
3499         unsigned long fck;
3500         unsigned long total_ticks;
3501         u32 r;
3502
3503         BUG_ON(ticks > 0x1fff);
3504
3505         /* ticks in DSI_FCK */
3506         fck = dsi_fclk_rate(dsidev);
3507
3508         r = dsi_read_reg(dsidev, DSI_TIMING2);
3509         r = FLD_MOD(r, 1, 15, 15);      /* LP_RX_TO */
3510         r = FLD_MOD(r, x16 ? 1 : 0, 14, 14);    /* LP_RX_TO_X16 */
3511         r = FLD_MOD(r, x4 ? 1 : 0, 13, 13);     /* LP_RX_TO_X4 */
3512         r = FLD_MOD(r, ticks, 12, 0);   /* LP_RX_COUNTER */
3513         dsi_write_reg(dsidev, DSI_TIMING2, r);
3514
3515         total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3516
3517         DSSDBG("LP_RX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3518                         total_ticks,
3519                         ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3520                         (total_ticks * 1000) / (fck / 1000 / 1000));
3521 }
3522
3523 static void dsi_set_ta_timeout(struct platform_device *dsidev, unsigned ticks,
3524                 bool x8, bool x16)
3525 {
3526         unsigned long fck;
3527         unsigned long total_ticks;
3528         u32 r;
3529
3530         BUG_ON(ticks > 0x1fff);
3531
3532         /* ticks in DSI_FCK */
3533         fck = dsi_fclk_rate(dsidev);
3534
3535         r = dsi_read_reg(dsidev, DSI_TIMING1);
3536         r = FLD_MOD(r, 1, 31, 31);      /* TA_TO */
3537         r = FLD_MOD(r, x16 ? 1 : 0, 30, 30);    /* TA_TO_X16 */
3538         r = FLD_MOD(r, x8 ? 1 : 0, 29, 29);     /* TA_TO_X8 */
3539         r = FLD_MOD(r, ticks, 28, 16);  /* TA_TO_COUNTER */
3540         dsi_write_reg(dsidev, DSI_TIMING1, r);
3541
3542         total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1);
3543
3544         DSSDBG("TA_TO %lu ticks (%#x%s%s) = %lu ns\n",
3545                         total_ticks,
3546                         ticks, x8 ? " x8" : "", x16 ? " x16" : "",
3547                         (total_ticks * 1000) / (fck / 1000 / 1000));
3548 }
3549
3550 static void dsi_set_stop_state_counter(struct platform_device *dsidev,
3551                 unsigned ticks, bool x4, bool x16)
3552 {
3553         unsigned long fck;
3554         unsigned long total_ticks;
3555         u32 r;
3556
3557         BUG_ON(ticks > 0x1fff);
3558
3559         /* ticks in DSI_FCK */
3560         fck = dsi_fclk_rate(dsidev);
3561
3562         r = dsi_read_reg(dsidev, DSI_TIMING1);
3563         r = FLD_MOD(r, 1, 15, 15);      /* FORCE_TX_STOP_MODE_IO */
3564         r = FLD_MOD(r, x16 ? 1 : 0, 14, 14);    /* STOP_STATE_X16_IO */
3565         r = FLD_MOD(r, x4 ? 1 : 0, 13, 13);     /* STOP_STATE_X4_IO */
3566         r = FLD_MOD(r, ticks, 12, 0);   /* STOP_STATE_COUNTER_IO */
3567         dsi_write_reg(dsidev, DSI_TIMING1, r);
3568
3569         total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3570
3571         DSSDBG("STOP_STATE_COUNTER %lu ticks (%#x%s%s) = %lu ns\n",
3572                         total_ticks,
3573                         ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3574                         (total_ticks * 1000) / (fck / 1000 / 1000));
3575 }
3576
3577 static void dsi_set_hs_tx_timeout(struct platform_device *dsidev,
3578                 unsigned ticks, bool x4, bool x16)
3579 {
3580         unsigned long fck;
3581         unsigned long total_ticks;
3582         u32 r;
3583
3584         BUG_ON(ticks > 0x1fff);
3585
3586         /* ticks in TxByteClkHS */
3587         fck = dsi_get_txbyteclkhs(dsidev);
3588
3589         r = dsi_read_reg(dsidev, DSI_TIMING2);
3590         r = FLD_MOD(r, 1, 31, 31);      /* HS_TX_TO */
3591         r = FLD_MOD(r, x16 ? 1 : 0, 30, 30);    /* HS_TX_TO_X16 */
3592         r = FLD_MOD(r, x4 ? 1 : 0, 29, 29);     /* HS_TX_TO_X8 (4 really) */
3593         r = FLD_MOD(r, ticks, 28, 16);  /* HS_TX_TO_COUNTER */
3594         dsi_write_reg(dsidev, DSI_TIMING2, r);
3595
3596         total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
3597
3598         DSSDBG("HS_TX_TO %lu ticks (%#x%s%s) = %lu ns\n",
3599                         total_ticks,
3600                         ticks, x4 ? " x4" : "", x16 ? " x16" : "",
3601                         (total_ticks * 1000) / (fck / 1000 / 1000));
3602 }
3603
3604 static void dsi_config_vp_num_line_buffers(struct omap_dss_device *dssdev)
3605 {
3606         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3607         int num_line_buffers;
3608
3609         if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
3610                 int bpp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt);
3611                 unsigned line_buf_size = dsi_get_line_buf_size(dsidev);
3612                 struct omap_video_timings *timings = &dssdev->panel.timings;
3613                 /*
3614                  * Don't use line buffers if width is greater than the video
3615                  * port's line buffer size
3616                  */
3617                 if (line_buf_size <= timings->x_res * bpp / 8)
3618                         num_line_buffers = 0;
3619                 else
3620                         num_line_buffers = 2;
3621         } else {
3622                 /* Use maximum number of line buffers in command mode */
3623                 num_line_buffers = 2;
3624         }
3625
3626         /* LINE_BUFFER */
3627         REG_FLD_MOD(dsidev, DSI_CTRL, num_line_buffers, 13, 12);
3628 }
3629
3630 static void dsi_config_vp_sync_events(struct omap_dss_device *dssdev)
3631 {
3632         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3633         int de_pol = dssdev->panel.dsi_vm_data.vp_de_pol;
3634         int hsync_pol = dssdev->panel.dsi_vm_data.vp_hsync_pol;
3635         int vsync_pol = dssdev->panel.dsi_vm_data.vp_vsync_pol;
3636         bool vsync_end = dssdev->panel.dsi_vm_data.vp_vsync_end;
3637         bool hsync_end = dssdev->panel.dsi_vm_data.vp_hsync_end;
3638         u32 r;
3639
3640         r = dsi_read_reg(dsidev, DSI_CTRL);
3641         r = FLD_MOD(r, de_pol, 9, 9);           /* VP_DE_POL */
3642         r = FLD_MOD(r, hsync_pol, 10, 10);      /* VP_HSYNC_POL */
3643         r = FLD_MOD(r, vsync_pol, 11, 11);      /* VP_VSYNC_POL */
3644         r = FLD_MOD(r, 1, 15, 15);              /* VP_VSYNC_START */
3645         r = FLD_MOD(r, vsync_end, 16, 16);      /* VP_VSYNC_END */
3646         r = FLD_MOD(r, 1, 17, 17);              /* VP_HSYNC_START */
3647         r = FLD_MOD(r, hsync_end, 18, 18);      /* VP_HSYNC_END */
3648         dsi_write_reg(dsidev, DSI_CTRL, r);
3649 }
3650
3651 static void dsi_config_blanking_modes(struct omap_dss_device *dssdev)
3652 {
3653         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3654         int blanking_mode = dssdev->panel.dsi_vm_data.blanking_mode;
3655         int hfp_blanking_mode = dssdev->panel.dsi_vm_data.hfp_blanking_mode;
3656         int hbp_blanking_mode = dssdev->panel.dsi_vm_data.hbp_blanking_mode;
3657         int hsa_blanking_mode = dssdev->panel.dsi_vm_data.hsa_blanking_mode;
3658         u32 r;
3659
3660         /*
3661          * 0 = TX FIFO packets sent or LPS in corresponding blanking periods
3662          * 1 = Long blanking packets are sent in corresponding blanking periods
3663          */
3664         r = dsi_read_reg(dsidev, DSI_CTRL);
3665         r = FLD_MOD(r, blanking_mode, 20, 20);          /* BLANKING_MODE */
3666         r = FLD_MOD(r, hfp_blanking_mode, 21, 21);      /* HFP_BLANKING */
3667         r = FLD_MOD(r, hbp_blanking_mode, 22, 22);      /* HBP_BLANKING */
3668         r = FLD_MOD(r, hsa_blanking_mode, 23, 23);      /* HSA_BLANKING */
3669         dsi_write_reg(dsidev, DSI_CTRL, r);
3670 }
3671
3672 static int dsi_proto_config(struct omap_dss_device *dssdev)
3673 {
3674         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3675         u32 r;
3676         int buswidth = 0;
3677
3678         dsi_config_tx_fifo(dsidev, DSI_FIFO_SIZE_32,
3679                         DSI_FIFO_SIZE_32,
3680                         DSI_FIFO_SIZE_32,
3681                         DSI_FIFO_SIZE_32);
3682
3683         dsi_config_rx_fifo(dsidev, DSI_FIFO_SIZE_32,
3684                         DSI_FIFO_SIZE_32,
3685                         DSI_FIFO_SIZE_32,
3686                         DSI_FIFO_SIZE_32);
3687
3688         /* XXX what values for the timeouts? */
3689         dsi_set_stop_state_counter(dsidev, 0x1000, false, false);
3690         dsi_set_ta_timeout(dsidev, 0x1fff, true, true);
3691         dsi_set_lp_rx_timeout(dsidev, 0x1fff, true, true);
3692         dsi_set_hs_tx_timeout(dsidev, 0x1fff, true, true);
3693
3694         switch (dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt)) {
3695         case 16:
3696                 buswidth = 0;
3697                 break;
3698         case 18:
3699                 buswidth = 1;
3700                 break;
3701         case 24:
3702                 buswidth = 2;
3703                 break;
3704         default:
3705                 BUG();
3706         }
3707
3708         r = dsi_read_reg(dsidev, DSI_CTRL);
3709         r = FLD_MOD(r, 1, 1, 1);        /* CS_RX_EN */
3710         r = FLD_MOD(r, 1, 2, 2);        /* ECC_RX_EN */
3711         r = FLD_MOD(r, 1, 3, 3);        /* TX_FIFO_ARBITRATION */
3712         r = FLD_MOD(r, 1, 4, 4);        /* VP_CLK_RATIO, always 1, see errata*/
3713         r = FLD_MOD(r, buswidth, 7, 6); /* VP_DATA_BUS_WIDTH */
3714         r = FLD_MOD(r, 0, 8, 8);        /* VP_CLK_POL */
3715         r = FLD_MOD(r, 1, 14, 14);      /* TRIGGER_RESET_MODE */
3716         r = FLD_MOD(r, 1, 19, 19);      /* EOT_ENABLE */
3717         if (!dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
3718                 r = FLD_MOD(r, 1, 24, 24);      /* DCS_CMD_ENABLE */
3719                 /* DCS_CMD_CODE, 1=start, 0=continue */
3720                 r = FLD_MOD(r, 0, 25, 25);
3721         }
3722
3723         dsi_write_reg(dsidev, DSI_CTRL, r);
3724
3725         dsi_config_vp_num_line_buffers(dssdev);
3726
3727         if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
3728                 dsi_config_vp_sync_events(dssdev);
3729                 dsi_config_blanking_modes(dssdev);
3730         }
3731
3732         dsi_vc_initial_config(dsidev, 0);
3733         dsi_vc_initial_config(dsidev, 1);
3734         dsi_vc_initial_config(dsidev, 2);
3735         dsi_vc_initial_config(dsidev, 3);
3736
3737         return 0;
3738 }
3739
3740 static void dsi_proto_timings(struct omap_dss_device *dssdev)
3741 {
3742         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3743         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3744         unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail;
3745         unsigned tclk_pre, tclk_post;
3746         unsigned ths_prepare, ths_prepare_ths_zero, ths_zero;
3747         unsigned ths_trail, ths_exit;
3748         unsigned ddr_clk_pre, ddr_clk_post;
3749         unsigned enter_hs_mode_lat, exit_hs_mode_lat;
3750         unsigned ths_eot;
3751         int ndl = dsi->num_lanes_used - 1;
3752         u32 r;
3753
3754         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
3755         ths_prepare = FLD_GET(r, 31, 24);
3756         ths_prepare_ths_zero = FLD_GET(r, 23, 16);
3757         ths_zero = ths_prepare_ths_zero - ths_prepare;
3758         ths_trail = FLD_GET(r, 15, 8);
3759         ths_exit = FLD_GET(r, 7, 0);
3760
3761         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
3762         tlpx = FLD_GET(r, 22, 16) * 2;
3763         tclk_trail = FLD_GET(r, 15, 8);
3764         tclk_zero = FLD_GET(r, 7, 0);
3765
3766         r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
3767         tclk_prepare = FLD_GET(r, 7, 0);
3768
3769         /* min 8*UI */
3770         tclk_pre = 20;
3771         /* min 60ns + 52*UI */
3772         tclk_post = ns2ddr(dsidev, 60) + 26;
3773
3774         ths_eot = DIV_ROUND_UP(4, ndl);
3775
3776         ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
3777                         4);
3778         ddr_clk_post = DIV_ROUND_UP(tclk_post + ths_trail, 4) + ths_eot;
3779
3780         BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
3781         BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);
3782
3783         r = dsi_read_reg(dsidev, DSI_CLK_TIMING);
3784         r = FLD_MOD(r, ddr_clk_pre, 15, 8);
3785         r = FLD_MOD(r, ddr_clk_post, 7, 0);
3786         dsi_write_reg(dsidev, DSI_CLK_TIMING, r);
3787
3788         DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
3789                         ddr_clk_pre,
3790                         ddr_clk_post);
3791
3792         enter_hs_mode_lat = 1 + DIV_ROUND_UP(tlpx, 4) +
3793                 DIV_ROUND_UP(ths_prepare, 4) +
3794                 DIV_ROUND_UP(ths_zero + 3, 4);
3795
3796         exit_hs_mode_lat = DIV_ROUND_UP(ths_trail + ths_exit, 4) + 1 + ths_eot;
3797
3798         r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
3799                 FLD_VAL(exit_hs_mode_lat, 15, 0);
3800         dsi_write_reg(dsidev, DSI_VM_TIMING7, r);
3801
3802         DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
3803                         enter_hs_mode_lat, exit_hs_mode_lat);
3804
3805          if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
3806                 /* TODO: Implement a video mode check_timings function */
3807                 int hsa = dssdev->panel.dsi_vm_data.hsa;
3808                 int hfp = dssdev->panel.dsi_vm_data.hfp;
3809                 int hbp = dssdev->panel.dsi_vm_data.hbp;
3810                 int vsa = dssdev->panel.dsi_vm_data.vsa;
3811                 int vfp = dssdev->panel.dsi_vm_data.vfp;
3812                 int vbp = dssdev->panel.dsi_vm_data.vbp;
3813                 int window_sync = dssdev->panel.dsi_vm_data.window_sync;
3814                 bool hsync_end = dssdev->panel.dsi_vm_data.vp_hsync_end;
3815                 struct omap_video_timings *timings = &dssdev->panel.timings;
3816                 int bpp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt);
3817                 int tl, t_he, width_bytes;
3818
3819                 t_he = hsync_end ?
3820                         ((hsa == 0 && ndl == 3) ? 1 : DIV_ROUND_UP(4, ndl)) : 0;
3821
3822                 width_bytes = DIV_ROUND_UP(timings->x_res * bpp, 8);
3823
3824                 /* TL = t_HS + HSA + t_HE + HFP + ceil((WC + 6) / NDL) + HBP */
3825                 tl = DIV_ROUND_UP(4, ndl) + (hsync_end ? hsa : 0) + t_he + hfp +
3826                         DIV_ROUND_UP(width_bytes + 6, ndl) + hbp;
3827
3828                 DSSDBG("HBP: %d, HFP: %d, HSA: %d, TL: %d TXBYTECLKHS\n", hbp,
3829                         hfp, hsync_end ? hsa : 0, tl);
3830                 DSSDBG("VBP: %d, VFP: %d, VSA: %d, VACT: %d lines\n", vbp, vfp,
3831                         vsa, timings->y_res);
3832
3833                 r = dsi_read_reg(dsidev, DSI_VM_TIMING1);
3834                 r = FLD_MOD(r, hbp, 11, 0);     /* HBP */
3835                 r = FLD_MOD(r, hfp, 23, 12);    /* HFP */
3836                 r = FLD_MOD(r, hsync_end ? hsa : 0, 31, 24);    /* HSA */
3837                 dsi_write_reg(dsidev, DSI_VM_TIMING1, r);
3838
3839                 r = dsi_read_reg(dsidev, DSI_VM_TIMING2);
3840                 r = FLD_MOD(r, vbp, 7, 0);      /* VBP */
3841                 r = FLD_MOD(r, vfp, 15, 8);     /* VFP */
3842                 r = FLD_MOD(r, vsa, 23, 16);    /* VSA */
3843                 r = FLD_MOD(r, window_sync, 27, 24);    /* WINDOW_SYNC */
3844                 dsi_write_reg(dsidev, DSI_VM_TIMING2, r);
3845
3846                 r = dsi_read_reg(dsidev, DSI_VM_TIMING3);
3847                 r = FLD_MOD(r, timings->y_res, 14, 0);  /* VACT */
3848                 r = FLD_MOD(r, tl, 31, 16);             /* TL */
3849                 dsi_write_reg(dsidev, DSI_VM_TIMING3, r);
3850         }
3851 }
3852
3853 int omapdss_dsi_configure_pins(struct omap_dss_device *dssdev,
3854                 const struct omap_dsi_pin_config *pin_cfg)
3855 {
3856         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3857         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
3858         int num_pins;
3859         const int *pins;
3860         struct dsi_lane_config lanes[DSI_MAX_NR_LANES];
3861         int num_lanes;
3862         int i;
3863
3864         static const enum dsi_lane_function functions[] = {
3865                 DSI_LANE_CLK,
3866                 DSI_LANE_DATA1,
3867                 DSI_LANE_DATA2,
3868                 DSI_LANE_DATA3,
3869                 DSI_LANE_DATA4,
3870         };
3871
3872         num_pins = pin_cfg->num_pins;
3873         pins = pin_cfg->pins;
3874
3875         if (num_pins < 4 || num_pins > dsi->num_lanes_supported * 2
3876                         || num_pins % 2 != 0)
3877                 return -EINVAL;
3878
3879         for (i = 0; i < DSI_MAX_NR_LANES; ++i)
3880                 lanes[i].function = DSI_LANE_UNUSED;
3881
3882         num_lanes = 0;
3883
3884         for (i = 0; i < num_pins; i += 2) {
3885                 u8 lane, pol;
3886                 int dx, dy;
3887
3888                 dx = pins[i];
3889                 dy = pins[i + 1];
3890
3891                 if (dx < 0 || dx >= dsi->num_lanes_supported * 2)
3892                         return -EINVAL;
3893
3894                 if (dy < 0 || dy >= dsi->num_lanes_supported * 2)
3895                         return -EINVAL;
3896
3897                 if (dx & 1) {
3898                         if (dy != dx - 1)
3899                                 return -EINVAL;
3900                         pol = 1;
3901                 } else {
3902                         if (dy != dx + 1)
3903                                 return -EINVAL;
3904                         pol = 0;
3905                 }
3906
3907                 lane = dx / 2;
3908
3909                 lanes[lane].function = functions[i / 2];
3910                 lanes[lane].polarity = pol;
3911                 num_lanes++;
3912         }
3913
3914         memcpy(dsi->lanes, lanes, sizeof(dsi->lanes));
3915         dsi->num_lanes_used = num_lanes;
3916
3917         return 0;
3918 }
3919 EXPORT_SYMBOL(omapdss_dsi_configure_pins);
3920
3921 int dsi_enable_video_output(struct omap_dss_device *dssdev, int channel)
3922 {
3923         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3924         int bpp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt);
3925         u8 data_type;
3926         u16 word_count;
3927         int r;
3928
3929         if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
3930                 switch (dssdev->panel.dsi_pix_fmt) {
3931                 case OMAP_DSS_DSI_FMT_RGB888:
3932                         data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24;
3933                         break;
3934                 case OMAP_DSS_DSI_FMT_RGB666:
3935                         data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
3936                         break;
3937                 case OMAP_DSS_DSI_FMT_RGB666_PACKED:
3938                         data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18;
3939                         break;
3940                 case OMAP_DSS_DSI_FMT_RGB565:
3941                         data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16;
3942                         break;
3943                 default:
3944                         BUG();
3945                 };
3946
3947                 dsi_if_enable(dsidev, false);
3948                 dsi_vc_enable(dsidev, channel, false);
3949
3950                 /* MODE, 1 = video mode */
3951                 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 4, 4);
3952
3953                 word_count = DIV_ROUND_UP(dssdev->panel.timings.x_res * bpp, 8);
3954
3955                 dsi_vc_write_long_header(dsidev, channel, data_type,
3956                                 word_count, 0);
3957
3958                 dsi_vc_enable(dsidev, channel, true);
3959                 dsi_if_enable(dsidev, true);
3960         }
3961
3962         r = dss_mgr_enable(dssdev->manager);
3963         if (r) {
3964                 if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
3965                         dsi_if_enable(dsidev, false);
3966                         dsi_vc_enable(dsidev, channel, false);
3967                 }
3968
3969                 return r;
3970         }
3971
3972         return 0;
3973 }
3974 EXPORT_SYMBOL(dsi_enable_video_output);
3975
3976 void dsi_disable_video_output(struct omap_dss_device *dssdev, int channel)
3977 {
3978         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3979
3980         if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_VIDEO_MODE) {
3981                 dsi_if_enable(dsidev, false);
3982                 dsi_vc_enable(dsidev, channel, false);
3983
3984                 /* MODE, 0 = command mode */
3985                 REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 0, 4, 4);
3986
3987                 dsi_vc_enable(dsidev, channel, true);
3988                 dsi_if_enable(dsidev, true);
3989         }
3990
3991         dss_mgr_disable(dssdev->manager);
3992 }
3993 EXPORT_SYMBOL(dsi_disable_video_output);
3994
3995 static void dsi_update_screen_dispc(struct omap_dss_device *dssdev,
3996                 u16 w, u16 h)
3997 {
3998         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
3999         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4000         unsigned bytespp;
4001         unsigned bytespl;
4002         unsigned bytespf;
4003         unsigned total_len;
4004         unsigned packet_payload;
4005         unsigned packet_len;
4006         u32 l;
4007         int r;
4008         const unsigned channel = dsi->update_channel;
4009         const unsigned line_buf_size = dsi_get_line_buf_size(dsidev);
4010
4011         DSSDBG("dsi_update_screen_dispc(%dx%d)\n", w, h);
4012
4013         dsi_vc_config_source(dsidev, channel, DSI_VC_SOURCE_VP);
4014
4015         bytespp = dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt) / 8;
4016         bytespl = w * bytespp;
4017         bytespf = bytespl * h;
4018
4019         /* NOTE: packet_payload has to be equal to N * bytespl, where N is
4020          * number of lines in a packet.  See errata about VP_CLK_RATIO */
4021
4022         if (bytespf < line_buf_size)
4023                 packet_payload = bytespf;
4024         else
4025                 packet_payload = (line_buf_size) / bytespl * bytespl;
4026
4027         packet_len = packet_payload + 1;        /* 1 byte for DCS cmd */
4028         total_len = (bytespf / packet_payload) * packet_len;
4029
4030         if (bytespf % packet_payload)
4031                 total_len += (bytespf % packet_payload) + 1;
4032
4033         l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
4034         dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
4035
4036         dsi_vc_write_long_header(dsidev, channel, MIPI_DSI_DCS_LONG_WRITE,
4037                 packet_len, 0);
4038
4039         if (dsi->te_enabled)
4040                 l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
4041         else
4042                 l = FLD_MOD(l, 1, 31, 31); /* TE_START */
4043         dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
4044
4045         /* We put SIDLEMODE to no-idle for the duration of the transfer,
4046          * because DSS interrupts are not capable of waking up the CPU and the
4047          * framedone interrupt could be delayed for quite a long time. I think
4048          * the same goes for any DSS interrupts, but for some reason I have not
4049          * seen the problem anywhere else than here.
4050          */
4051         dispc_disable_sidle();
4052
4053         dsi_perf_mark_start(dsidev);
4054
4055         r = schedule_delayed_work(&dsi->framedone_timeout_work,
4056                 msecs_to_jiffies(250));
4057         BUG_ON(r == 0);
4058
4059         dss_mgr_start_update(dssdev->manager);
4060
4061         if (dsi->te_enabled) {
4062                 /* disable LP_RX_TO, so that we can receive TE.  Time to wait
4063                  * for TE is longer than the timer allows */
4064                 REG_FLD_MOD(dsidev, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
4065
4066                 dsi_vc_send_bta(dsidev, channel);
4067
4068 #ifdef DSI_CATCH_MISSING_TE
4069                 mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250));
4070 #endif
4071         }
4072 }
4073
4074 #ifdef DSI_CATCH_MISSING_TE
4075 static void dsi_te_timeout(unsigned long arg)
4076 {
4077         DSSERR("TE not received for 250ms!\n");
4078 }
4079 #endif
4080
4081 static void dsi_handle_framedone(struct platform_device *dsidev, int error)
4082 {
4083         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4084
4085         /* SIDLEMODE back to smart-idle */
4086         dispc_enable_sidle();
4087
4088         if (dsi->te_enabled) {
4089                 /* enable LP_RX_TO again after the TE */
4090                 REG_FLD_MOD(dsidev, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
4091         }
4092
4093         dsi->framedone_callback(error, dsi->framedone_data);
4094
4095         if (!error)
4096                 dsi_perf_show(dsidev, "DISPC");
4097 }
4098
4099 static void dsi_framedone_timeout_work_callback(struct work_struct *work)
4100 {
4101         struct dsi_data *dsi = container_of(work, struct dsi_data,
4102                         framedone_timeout_work.work);
4103         /* XXX While extremely unlikely, we could get FRAMEDONE interrupt after
4104          * 250ms which would conflict with this timeout work. What should be
4105          * done is first cancel the transfer on the HW, and then cancel the
4106          * possibly scheduled framedone work. However, cancelling the transfer
4107          * on the HW is buggy, and would probably require resetting the whole
4108          * DSI */
4109
4110         DSSERR("Framedone not received for 250ms!\n");
4111
4112         dsi_handle_framedone(dsi->pdev, -ETIMEDOUT);
4113 }
4114
4115 static void dsi_framedone_irq_callback(void *data, u32 mask)
4116 {
4117         struct omap_dss_device *dssdev = (struct omap_dss_device *) data;
4118         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4119         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4120
4121         /* Note: We get FRAMEDONE when DISPC has finished sending pixels and
4122          * turns itself off. However, DSI still has the pixels in its buffers,
4123          * and is sending the data.
4124          */
4125
4126         __cancel_delayed_work(&dsi->framedone_timeout_work);
4127
4128         dsi_handle_framedone(dsidev, 0);
4129 }
4130
4131 int omap_dsi_update(struct omap_dss_device *dssdev, int channel,
4132                 void (*callback)(int, void *), void *data)
4133 {
4134         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4135         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4136         u16 dw, dh;
4137
4138         dsi_perf_mark_setup(dsidev);
4139
4140         dsi->update_channel = channel;
4141
4142         dsi->framedone_callback = callback;
4143         dsi->framedone_data = data;
4144
4145         dssdev->driver->get_resolution(dssdev, &dw, &dh);
4146
4147 #ifdef DEBUG
4148         dsi->update_bytes = dw * dh *
4149                 dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt) / 8;
4150 #endif
4151         dsi_update_screen_dispc(dssdev, dw, dh);
4152
4153         return 0;
4154 }
4155 EXPORT_SYMBOL(omap_dsi_update);
4156
4157 /* Display funcs */
4158
4159 static int dsi_display_init_dispc(struct omap_dss_device *dssdev)
4160 {
4161         int r;
4162
4163         if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) {
4164                 u16 dw, dh;
4165                 u32 irq;
4166                 struct omap_video_timings timings = {
4167                         .hsw            = 1,
4168                         .hfp            = 1,
4169                         .hbp            = 1,
4170                         .vsw            = 1,
4171                         .vfp            = 0,
4172                         .vbp            = 0,
4173                 };
4174
4175                 dssdev->driver->get_resolution(dssdev, &dw, &dh);
4176                 timings.x_res = dw;
4177                 timings.y_res = dh;
4178
4179                 irq = dssdev->manager->id == OMAP_DSS_CHANNEL_LCD ?
4180                         DISPC_IRQ_FRAMEDONE : DISPC_IRQ_FRAMEDONE2;
4181
4182                 r = omap_dispc_register_isr(dsi_framedone_irq_callback,
4183                         (void *) dssdev, irq);
4184                 if (r) {
4185                         DSSERR("can't get FRAMEDONE irq\n");
4186                         return r;
4187                 }
4188
4189                 dispc_mgr_enable_stallmode(dssdev->manager->id, true);
4190                 dispc_mgr_enable_fifohandcheck(dssdev->manager->id, 1);
4191
4192                 dss_mgr_set_timings(dssdev->manager, &timings);
4193         } else {
4194                 dispc_mgr_enable_stallmode(dssdev->manager->id, false);
4195                 dispc_mgr_enable_fifohandcheck(dssdev->manager->id, 0);
4196
4197                 dss_mgr_set_timings(dssdev->manager, &dssdev->panel.timings);
4198         }
4199
4200                 dispc_mgr_set_lcd_display_type(dssdev->manager->id,
4201                         OMAP_DSS_LCD_DISPLAY_TFT);
4202                 dispc_mgr_set_tft_data_lines(dssdev->manager->id,
4203                         dsi_get_pixel_size(dssdev->panel.dsi_pix_fmt));
4204         return 0;
4205 }
4206
4207 static void dsi_display_uninit_dispc(struct omap_dss_device *dssdev)
4208 {
4209         if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) {
4210                 u32 irq;
4211
4212                 irq = dssdev->manager->id == OMAP_DSS_CHANNEL_LCD ?
4213                         DISPC_IRQ_FRAMEDONE : DISPC_IRQ_FRAMEDONE2;
4214
4215                 omap_dispc_unregister_isr(dsi_framedone_irq_callback,
4216                         (void *) dssdev, irq);
4217         }
4218 }
4219
4220 static int dsi_configure_dsi_clocks(struct omap_dss_device *dssdev)
4221 {
4222         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4223         struct dsi_clock_info cinfo;
4224         int r;
4225
4226         cinfo.regn  = dssdev->clocks.dsi.regn;
4227         cinfo.regm  = dssdev->clocks.dsi.regm;
4228         cinfo.regm_dispc = dssdev->clocks.dsi.regm_dispc;
4229         cinfo.regm_dsi = dssdev->clocks.dsi.regm_dsi;
4230         r = dsi_calc_clock_rates(dsidev, &cinfo);
4231         if (r) {
4232                 DSSERR("Failed to calc dsi clocks\n");
4233                 return r;
4234         }
4235
4236         r = dsi_pll_set_clock_div(dsidev, &cinfo);
4237         if (r) {
4238                 DSSERR("Failed to set dsi clocks\n");
4239                 return r;
4240         }
4241
4242         return 0;
4243 }
4244
4245 static int dsi_configure_dispc_clocks(struct omap_dss_device *dssdev)
4246 {
4247         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4248         struct dispc_clock_info dispc_cinfo;
4249         int r;
4250         unsigned long long fck;
4251
4252         fck = dsi_get_pll_hsdiv_dispc_rate(dsidev);
4253
4254         dispc_cinfo.lck_div = dssdev->clocks.dispc.channel.lck_div;
4255         dispc_cinfo.pck_div = dssdev->clocks.dispc.channel.pck_div;
4256
4257         r = dispc_calc_clock_rates(fck, &dispc_cinfo);
4258         if (r) {
4259                 DSSERR("Failed to calc dispc clocks\n");
4260                 return r;
4261         }
4262
4263         r = dispc_mgr_set_clock_div(dssdev->manager->id, &dispc_cinfo);
4264         if (r) {
4265                 DSSERR("Failed to set dispc clocks\n");
4266                 return r;
4267         }
4268
4269         return 0;
4270 }
4271
4272 static int dsi_display_init_dsi(struct omap_dss_device *dssdev)
4273 {
4274         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4275         int dsi_module = dsi_get_dsidev_id(dsidev);
4276         int r;
4277
4278         r = dsi_pll_init(dsidev, true, true);
4279         if (r)
4280                 goto err0;
4281
4282         r = dsi_configure_dsi_clocks(dssdev);
4283         if (r)
4284                 goto err1;
4285
4286         dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src);
4287         dss_select_dsi_clk_source(dsi_module, dssdev->clocks.dsi.dsi_fclk_src);
4288         dss_select_lcd_clk_source(dssdev->manager->id,
4289                         dssdev->clocks.dispc.channel.lcd_clk_src);
4290
4291         DSSDBG("PLL OK\n");
4292
4293         r = dsi_configure_dispc_clocks(dssdev);
4294         if (r)
4295                 goto err2;
4296
4297         r = dsi_cio_init(dssdev);
4298         if (r)
4299                 goto err2;
4300
4301         _dsi_print_reset_status(dsidev);
4302
4303         dsi_proto_timings(dssdev);
4304         dsi_set_lp_clk_divisor(dssdev);
4305
4306         if (1)
4307                 _dsi_print_reset_status(dsidev);
4308
4309         r = dsi_proto_config(dssdev);
4310         if (r)
4311                 goto err3;
4312
4313         /* enable interface */
4314         dsi_vc_enable(dsidev, 0, 1);
4315         dsi_vc_enable(dsidev, 1, 1);
4316         dsi_vc_enable(dsidev, 2, 1);
4317         dsi_vc_enable(dsidev, 3, 1);
4318         dsi_if_enable(dsidev, 1);
4319         dsi_force_tx_stop_mode_io(dsidev);
4320
4321         return 0;
4322 err3:
4323         dsi_cio_uninit(dssdev);
4324 err2:
4325         dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
4326         dss_select_dsi_clk_source(dsi_module, OMAP_DSS_CLK_SRC_FCK);
4327         dss_select_lcd_clk_source(dssdev->manager->id, OMAP_DSS_CLK_SRC_FCK);
4328
4329 err1:
4330         dsi_pll_uninit(dsidev, true);
4331 err0:
4332         return r;
4333 }
4334
4335 static void dsi_display_uninit_dsi(struct omap_dss_device *dssdev,
4336                 bool disconnect_lanes, bool enter_ulps)
4337 {
4338         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4339         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4340         int dsi_module = dsi_get_dsidev_id(dsidev);
4341
4342         if (enter_ulps && !dsi->ulps_enabled)
4343                 dsi_enter_ulps(dsidev);
4344
4345         /* disable interface */
4346         dsi_if_enable(dsidev, 0);
4347         dsi_vc_enable(dsidev, 0, 0);
4348         dsi_vc_enable(dsidev, 1, 0);
4349         dsi_vc_enable(dsidev, 2, 0);
4350         dsi_vc_enable(dsidev, 3, 0);
4351
4352         dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
4353         dss_select_dsi_clk_source(dsi_module, OMAP_DSS_CLK_SRC_FCK);
4354         dss_select_lcd_clk_source(dssdev->manager->id, OMAP_DSS_CLK_SRC_FCK);
4355         dsi_cio_uninit(dssdev);
4356         dsi_pll_uninit(dsidev, disconnect_lanes);
4357 }
4358
4359 int omapdss_dsi_display_enable(struct omap_dss_device *dssdev)
4360 {
4361         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4362         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4363         int r = 0;
4364
4365         DSSDBG("dsi_display_enable\n");
4366
4367         WARN_ON(!dsi_bus_is_locked(dsidev));
4368
4369         mutex_lock(&dsi->lock);
4370
4371         if (dssdev->manager == NULL) {
4372                 DSSERR("failed to enable display: no manager\n");
4373                 r = -ENODEV;
4374                 goto err_start_dev;
4375         }
4376
4377         r = omap_dss_start_device(dssdev);
4378         if (r) {
4379                 DSSERR("failed to start device\n");
4380                 goto err_start_dev;
4381         }
4382
4383         r = dsi_runtime_get(dsidev);
4384         if (r)
4385                 goto err_get_dsi;
4386
4387         dsi_enable_pll_clock(dsidev, 1);
4388
4389         _dsi_initialize_irq(dsidev);
4390
4391         r = dsi_display_init_dispc(dssdev);
4392         if (r)
4393                 goto err_init_dispc;
4394
4395         r = dsi_display_init_dsi(dssdev);
4396         if (r)
4397                 goto err_init_dsi;
4398
4399         mutex_unlock(&dsi->lock);
4400
4401         return 0;
4402
4403 err_init_dsi:
4404         dsi_display_uninit_dispc(dssdev);
4405 err_init_dispc:
4406         dsi_enable_pll_clock(dsidev, 0);
4407         dsi_runtime_put(dsidev);
4408 err_get_dsi:
4409         omap_dss_stop_device(dssdev);
4410 err_start_dev:
4411         mutex_unlock(&dsi->lock);
4412         DSSDBG("dsi_display_enable FAILED\n");
4413         return r;
4414 }
4415 EXPORT_SYMBOL(omapdss_dsi_display_enable);
4416
4417 void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
4418                 bool disconnect_lanes, bool enter_ulps)
4419 {
4420         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4421         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4422
4423         DSSDBG("dsi_display_disable\n");
4424
4425         WARN_ON(!dsi_bus_is_locked(dsidev));
4426
4427         mutex_lock(&dsi->lock);
4428
4429         dsi_sync_vc(dsidev, 0);
4430         dsi_sync_vc(dsidev, 1);
4431         dsi_sync_vc(dsidev, 2);
4432         dsi_sync_vc(dsidev, 3);
4433
4434         dsi_display_uninit_dispc(dssdev);
4435
4436         dsi_display_uninit_dsi(dssdev, disconnect_lanes, enter_ulps);
4437
4438         dsi_runtime_put(dsidev);
4439         dsi_enable_pll_clock(dsidev, 0);
4440
4441         omap_dss_stop_device(dssdev);
4442
4443         mutex_unlock(&dsi->lock);
4444 }
4445 EXPORT_SYMBOL(omapdss_dsi_display_disable);
4446
4447 int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable)
4448 {
4449         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4450         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4451
4452         dsi->te_enabled = enable;
4453         return 0;
4454 }
4455 EXPORT_SYMBOL(omapdss_dsi_enable_te);
4456
4457 int dsi_init_display(struct omap_dss_device *dssdev)
4458 {
4459         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4460         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4461
4462         DSSDBG("DSI init\n");
4463
4464         if (dssdev->panel.dsi_mode == OMAP_DSS_DSI_CMD_MODE) {
4465                 dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE |
4466                         OMAP_DSS_DISPLAY_CAP_TEAR_ELIM;
4467         }
4468
4469         if (dsi->vdds_dsi_reg == NULL) {
4470                 struct regulator *vdds_dsi;
4471
4472                 vdds_dsi = regulator_get(&dsi->pdev->dev, "vdds_dsi");
4473
4474                 if (IS_ERR(vdds_dsi)) {
4475                         DSSERR("can't get VDDS_DSI regulator\n");
4476                         return PTR_ERR(vdds_dsi);
4477                 }
4478
4479                 dsi->vdds_dsi_reg = vdds_dsi;
4480         }
4481
4482         return 0;
4483 }
4484
4485 int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel)
4486 {
4487         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4488         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4489         int i;
4490
4491         for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
4492                 if (!dsi->vc[i].dssdev) {
4493                         dsi->vc[i].dssdev = dssdev;
4494                         *channel = i;
4495                         return 0;
4496                 }
4497         }
4498
4499         DSSERR("cannot get VC for display %s", dssdev->name);
4500         return -ENOSPC;
4501 }
4502 EXPORT_SYMBOL(omap_dsi_request_vc);
4503
4504 int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id)
4505 {
4506         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4507         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4508
4509         if (vc_id < 0 || vc_id > 3) {
4510                 DSSERR("VC ID out of range\n");
4511                 return -EINVAL;
4512         }
4513
4514         if (channel < 0 || channel > 3) {
4515                 DSSERR("Virtual Channel out of range\n");
4516                 return -EINVAL;
4517         }
4518
4519         if (dsi->vc[channel].dssdev != dssdev) {
4520                 DSSERR("Virtual Channel not allocated to display %s\n",
4521                         dssdev->name);
4522                 return -EINVAL;
4523         }
4524
4525         dsi->vc[channel].vc_id = vc_id;
4526
4527         return 0;
4528 }
4529 EXPORT_SYMBOL(omap_dsi_set_vc_id);
4530
4531 void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel)
4532 {
4533         struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
4534         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4535
4536         if ((channel >= 0 && channel <= 3) &&
4537                 dsi->vc[channel].dssdev == dssdev) {
4538                 dsi->vc[channel].dssdev = NULL;
4539                 dsi->vc[channel].vc_id = 0;
4540         }
4541 }
4542 EXPORT_SYMBOL(omap_dsi_release_vc);
4543
4544 void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev)
4545 {
4546         if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 7, 1) != 1)
4547                 DSSERR("%s (%s) not active\n",
4548                         dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
4549                         dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC));
4550 }
4551
4552 void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev)
4553 {
4554         if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 8, 1) != 1)
4555                 DSSERR("%s (%s) not active\n",
4556                         dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
4557                         dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI));
4558 }
4559
4560 static void dsi_calc_clock_param_ranges(struct platform_device *dsidev)
4561 {
4562         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4563
4564         dsi->regn_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGN);
4565         dsi->regm_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM);
4566         dsi->regm_dispc_max =
4567                 dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DISPC);
4568         dsi->regm_dsi_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DSI);
4569         dsi->fint_min = dss_feat_get_param_min(FEAT_PARAM_DSIPLL_FINT);
4570         dsi->fint_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_FINT);
4571         dsi->lpdiv_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV);
4572 }
4573
4574 static int dsi_get_clocks(struct platform_device *dsidev)
4575 {
4576         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4577         struct clk *clk;
4578
4579         clk = clk_get(&dsidev->dev, "fck");
4580         if (IS_ERR(clk)) {
4581                 DSSERR("can't get fck\n");
4582                 return PTR_ERR(clk);
4583         }
4584
4585         dsi->dss_clk = clk;
4586
4587         clk = clk_get(&dsidev->dev, "sys_clk");
4588         if (IS_ERR(clk)) {
4589                 DSSERR("can't get sys_clk\n");
4590                 clk_put(dsi->dss_clk);
4591                 dsi->dss_clk = NULL;
4592                 return PTR_ERR(clk);
4593         }
4594
4595         dsi->sys_clk = clk;
4596
4597         return 0;
4598 }
4599
4600 static void dsi_put_clocks(struct platform_device *dsidev)
4601 {
4602         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4603
4604         if (dsi->dss_clk)
4605                 clk_put(dsi->dss_clk);
4606         if (dsi->sys_clk)
4607                 clk_put(dsi->sys_clk);
4608 }
4609
4610 /* DSI1 HW IP initialisation */
4611 static int omap_dsihw_probe(struct platform_device *dsidev)
4612 {
4613         u32 rev;
4614         int r, i, dsi_module = dsi_get_dsidev_id(dsidev);
4615         struct resource *dsi_mem;
4616         struct dsi_data *dsi;
4617
4618         dsi = devm_kzalloc(&dsidev->dev, sizeof(*dsi), GFP_KERNEL);
4619         if (!dsi)
4620                 return -ENOMEM;
4621
4622         dsi->pdev = dsidev;
4623         dsi_pdev_map[dsi_module] = dsidev;
4624         dev_set_drvdata(&dsidev->dev, dsi);
4625
4626         spin_lock_init(&dsi->irq_lock);
4627         spin_lock_init(&dsi->errors_lock);
4628         dsi->errors = 0;
4629
4630 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
4631         spin_lock_init(&dsi->irq_stats_lock);
4632         dsi->irq_stats.last_reset = jiffies;
4633 #endif
4634
4635         mutex_init(&dsi->lock);
4636         sema_init(&dsi->bus_lock, 1);
4637
4638         INIT_DELAYED_WORK_DEFERRABLE(&dsi->framedone_timeout_work,
4639                         dsi_framedone_timeout_work_callback);
4640
4641 #ifdef DSI_CATCH_MISSING_TE
4642         init_timer(&dsi->te_timer);
4643         dsi->te_timer.function = dsi_te_timeout;
4644         dsi->te_timer.data = 0;
4645 #endif
4646         dsi_mem = platform_get_resource(dsi->pdev, IORESOURCE_MEM, 0);
4647         if (!dsi_mem) {
4648                 DSSERR("can't get IORESOURCE_MEM DSI\n");
4649                 return -EINVAL;
4650         }
4651
4652         dsi->base = devm_ioremap(&dsidev->dev, dsi_mem->start,
4653                                  resource_size(dsi_mem));
4654         if (!dsi->base) {
4655                 DSSERR("can't ioremap DSI\n");
4656                 return -ENOMEM;
4657         }
4658
4659         dsi->irq = platform_get_irq(dsi->pdev, 0);
4660         if (dsi->irq < 0) {
4661                 DSSERR("platform_get_irq failed\n");
4662                 return -ENODEV;
4663         }
4664
4665         r = devm_request_irq(&dsidev->dev, dsi->irq, omap_dsi_irq_handler,
4666                              IRQF_SHARED, dev_name(&dsidev->dev), dsi->pdev);
4667         if (r < 0) {
4668                 DSSERR("request_irq failed\n");
4669                 return r;
4670         }
4671
4672         /* DSI VCs initialization */
4673         for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
4674                 dsi->vc[i].source = DSI_VC_SOURCE_L4;
4675                 dsi->vc[i].dssdev = NULL;
4676                 dsi->vc[i].vc_id = 0;
4677         }
4678
4679         dsi_calc_clock_param_ranges(dsidev);
4680
4681         r = dsi_get_clocks(dsidev);
4682         if (r)
4683                 return r;
4684
4685         pm_runtime_enable(&dsidev->dev);
4686
4687         r = dsi_runtime_get(dsidev);
4688         if (r)
4689                 goto err_runtime_get;
4690
4691         rev = dsi_read_reg(dsidev, DSI_REVISION);
4692         dev_dbg(&dsidev->dev, "OMAP DSI rev %d.%d\n",
4693                FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
4694
4695         /* DSI on OMAP3 doesn't have register DSI_GNQ, set number
4696          * of data to 3 by default */
4697         if (dss_has_feature(FEAT_DSI_GNQ))
4698                 /* NB_DATA_LANES */
4699                 dsi->num_lanes_supported = 1 + REG_GET(dsidev, DSI_GNQ, 11, 9);
4700         else
4701                 dsi->num_lanes_supported = 3;
4702
4703         dsi_runtime_put(dsidev);
4704
4705         if (dsi_module == 0)
4706                 dss_debugfs_create_file("dsi1_regs", dsi1_dump_regs);
4707         else if (dsi_module == 1)
4708                 dss_debugfs_create_file("dsi2_regs", dsi2_dump_regs);
4709
4710 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
4711         if (dsi_module == 0)
4712                 dss_debugfs_create_file("dsi1_irqs", dsi1_dump_irqs);
4713         else if (dsi_module == 1)
4714                 dss_debugfs_create_file("dsi2_irqs", dsi2_dump_irqs);
4715 #endif
4716         return 0;
4717
4718 err_runtime_get:
4719         pm_runtime_disable(&dsidev->dev);
4720         dsi_put_clocks(dsidev);
4721         return r;
4722 }
4723
4724 static int omap_dsihw_remove(struct platform_device *dsidev)
4725 {
4726         struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
4727
4728         WARN_ON(dsi->scp_clk_refcount > 0);
4729
4730         pm_runtime_disable(&dsidev->dev);
4731
4732         dsi_put_clocks(dsidev);
4733
4734         if (dsi->vdds_dsi_reg != NULL) {
4735                 if (dsi->vdds_dsi_enabled) {
4736                         regulator_disable(dsi->vdds_dsi_reg);
4737                         dsi->vdds_dsi_enabled = false;
4738                 }
4739
4740                 regulator_put(dsi->vdds_dsi_reg);
4741                 dsi->vdds_dsi_reg = NULL;
4742         }
4743
4744         return 0;
4745 }
4746
4747 static int dsi_runtime_suspend(struct device *dev)
4748 {
4749         dispc_runtime_put();
4750
4751         return 0;
4752 }
4753
4754 static int dsi_runtime_resume(struct device *dev)
4755 {
4756         int r;
4757
4758         r = dispc_runtime_get();
4759         if (r)
4760                 return r;
4761
4762         return 0;
4763 }
4764
4765 static const struct dev_pm_ops dsi_pm_ops = {
4766         .runtime_suspend = dsi_runtime_suspend,
4767         .runtime_resume = dsi_runtime_resume,
4768 };
4769
4770 static struct platform_driver omap_dsihw_driver = {
4771         .remove         = omap_dsihw_remove,
4772         .driver         = {
4773                 .name   = "omapdss_dsi",
4774                 .owner  = THIS_MODULE,
4775                 .pm     = &dsi_pm_ops,
4776         },
4777 };
4778
4779 int dsi_init_platform_driver(void)
4780 {
4781         return platform_driver_probe(&omap_dsihw_driver, omap_dsihw_probe);
4782 }
4783
4784 void dsi_uninit_platform_driver(void)
4785 {
4786         platform_driver_unregister(&omap_dsihw_driver);
4787 }