drivers/video/omap2/dss/dss.c

   1 /*
   2  * linux/drivers/video/omap2/dss/dss.c
   3  *
   4  * Copyright (C) 2009 Nokia Corporation
   5  * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
   6  *
   7  * Some code and ideas taken from drivers/video/omap/ driver
   8  * by Imre Deak.
   9  *
  10  * This program is free software; you can redistribute it and/or modify it
  11  * under the terms of the GNU General Public License version 2 as published by
  12  * the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful, but WITHOUT
  15  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  16  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  17  * more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along with
  20  * this program.  If not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #define DSS_SUBSYS_NAME "DSS"
  24
  25 #include <linux/kernel.h>
  26 #include <linux/io.h>
  27 #include <linux/export.h>
  28 #include <linux/err.h>
  29 #include <linux/delay.h>
  30 #include <linux/seq_file.h>
  31 #include <linux/clk.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/pm_runtime.h>
  34
  35 #include <video/omapdss.h>
  36
  37 #include <plat/cpu.h>
  38 #include <plat/clock.h>
  39
  40 #include "dss.h"
  41 #include "dss_features.h"
  42
  43 #define DSS_SZ_REGS                     SZ_512
  44
  45 struct dss_reg {
  46         u16 idx;
  47 };
  48
  49 #define DSS_REG(idx)                    ((const struct dss_reg) { idx })
  50
  51 #define DSS_REVISION                    DSS_REG(0x0000)
  52 #define DSS_SYSCONFIG                   DSS_REG(0x0010)
  53 #define DSS_SYSSTATUS                   DSS_REG(0x0014)
  54 #define DSS_CONTROL                     DSS_REG(0x0040)
  55 #define DSS_SDI_CONTROL                 DSS_REG(0x0044)
  56 #define DSS_PLL_CONTROL                 DSS_REG(0x0048)
  57 #define DSS_SDI_STATUS                  DSS_REG(0x005C)
  58
  59 #define REG_GET(idx, start, end) \
  60         FLD_GET(dss_read_reg(idx), start, end)
  61
  62 #define REG_FLD_MOD(idx, val, start, end) \
  63         dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end))
  64
  65 static struct {
  66         struct platform_device *pdev;
  67         void __iomem    *base;
  68
  69         struct clk      *dpll4_m4_ck;
  70         struct clk      *dss_clk;
  71
  72         unsigned long   cache_req_pck;
  73         unsigned long   cache_prate;
  74         struct dss_clock_info cache_dss_cinfo;
  75         struct dispc_clock_info cache_dispc_cinfo;
  76
  77         enum omap_dss_clk_source dsi_clk_source[MAX_NUM_DSI];
  78         enum omap_dss_clk_source dispc_clk_source;
  79         enum omap_dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS];
  80
  81         bool            ctx_valid;
  82         u32             ctx[DSS_SZ_REGS / sizeof(u32)];
  83 } dss;
  84
  85 static const char * const dss_generic_clk_source_names[] = {
  86         [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC]  = "DSI_PLL_HSDIV_DISPC",
  87         [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI]    = "DSI_PLL_HSDIV_DSI",
  88         [OMAP_DSS_CLK_SRC_FCK]                  = "DSS_FCK",
  89 };
  90
  91 static inline void dss_write_reg(const struct dss_reg idx, u32 val)
  92 {
  93         __raw_writel(val, dss.base + idx.idx);
  94 }
  95
  96 static inline u32 dss_read_reg(const struct dss_reg idx)
  97 {
  98         return __raw_readl(dss.base + idx.idx);
  99 }
 100
 101 #define SR(reg) \
 102         dss.ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(DSS_##reg)
 103 #define RR(reg) \
 104         dss_write_reg(DSS_##reg, dss.ctx[(DSS_##reg).idx / sizeof(u32)])
 105
 106 static void dss_save_context(void)
 107 {
 108         DSSDBG("dss_save_context\n");
 109
 110         SR(CONTROL);
 111
 112         if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
 113                         OMAP_DISPLAY_TYPE_SDI) {
 114                 SR(SDI_CONTROL);
 115                 SR(PLL_CONTROL);
 116         }
 117
 118         dss.ctx_valid = true;
 119
 120         DSSDBG("context saved\n");
 121 }
 122
 123 static void dss_restore_context(void)
 124 {
 125         DSSDBG("dss_restore_context\n");
 126
 127         if (!dss.ctx_valid)
 128                 return;
 129
 130         RR(CONTROL);
 131
 132         if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
 133                         OMAP_DISPLAY_TYPE_SDI) {
 134                 RR(SDI_CONTROL);
 135                 RR(PLL_CONTROL);
 136         }
 137
 138         DSSDBG("context restored\n");
 139 }
 140
 141 #undef SR
 142 #undef RR
 143
 144 void dss_sdi_init(u8 datapairs)
 145 {
 146         u32 l;
 147
 148         BUG_ON(datapairs > 3 || datapairs < 1);
 149
 150         l = dss_read_reg(DSS_SDI_CONTROL);
 151         l = FLD_MOD(l, 0xf, 19, 15);            /* SDI_PDIV */
 152         l = FLD_MOD(l, datapairs-1, 3, 2);      /* SDI_PRSEL */
 153         l = FLD_MOD(l, 2, 1, 0);                /* SDI_BWSEL */
 154         dss_write_reg(DSS_SDI_CONTROL, l);
 155
 156         l = dss_read_reg(DSS_PLL_CONTROL);
 157         l = FLD_MOD(l, 0x7, 25, 22);    /* SDI_PLL_FREQSEL */
 158         l = FLD_MOD(l, 0xb, 16, 11);    /* SDI_PLL_REGN */
 159         l = FLD_MOD(l, 0xb4, 10, 1);    /* SDI_PLL_REGM */
 160         dss_write_reg(DSS_PLL_CONTROL, l);
 161 }
 162
 163 int dss_sdi_enable(void)
 164 {
 165         unsigned long timeout;
 166
 167         dispc_pck_free_enable(1);
 168
 169         /* Reset SDI PLL */
 170         REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */
 171         udelay(1);      /* wait 2x PCLK */
 172
 173         /* Lock SDI PLL */
 174         REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */
 175
 176         /* Waiting for PLL lock request to complete */
 177         timeout = jiffies + msecs_to_jiffies(500);
 178         while (dss_read_reg(DSS_SDI_STATUS) & (1 << 6)) {
 179                 if (time_after_eq(jiffies, timeout)) {
 180                         DSSERR("PLL lock request timed out\n");
 181                         goto err1;
 182                 }
 183         }
 184
 185         /* Clearing PLL_GO bit */
 186         REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28);
 187
 188         /* Waiting for PLL to lock */
 189         timeout = jiffies + msecs_to_jiffies(500);
 190         while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5))) {
 191                 if (time_after_eq(jiffies, timeout)) {
 192                         DSSERR("PLL lock timed out\n");
 193                         goto err1;
 194                 }
 195         }
 196
 197         dispc_lcd_enable_signal(1);
 198
 199         /* Waiting for SDI reset to complete */
 200         timeout = jiffies + msecs_to_jiffies(500);
 201         while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 2))) {
 202                 if (time_after_eq(jiffies, timeout)) {
 203                         DSSERR("SDI reset timed out\n");
 204                         goto err2;
 205                 }
 206         }
 207
 208         return 0;
 209
 210  err2:
 211         dispc_lcd_enable_signal(0);
 212  err1:
 213         /* Reset SDI PLL */
 214         REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
 215
 216         dispc_pck_free_enable(0);
 217
 218         return -ETIMEDOUT;
 219 }
 220
 221 void dss_sdi_disable(void)
 222 {
 223         dispc_lcd_enable_signal(0);
 224
 225         dispc_pck_free_enable(0);
 226
 227         /* Reset SDI PLL */
 228         REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
 229 }
 230
 231 const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src)
 232 {
 233         return dss_generic_clk_source_names[clk_src];
 234 }
 235
 236
 237 void dss_dump_clocks(struct seq_file *s)
 238 {
 239         unsigned long dpll4_ck_rate;
 240         unsigned long dpll4_m4_ck_rate;
 241         const char *fclk_name, *fclk_real_name;
 242         unsigned long fclk_rate;
 243
 244         if (dss_runtime_get())
 245                 return;
 246
 247         seq_printf(s, "- DSS -\n");
 248
 249         fclk_name = dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_FCK);
 250         fclk_real_name = dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_FCK);
 251         fclk_rate = clk_get_rate(dss.dss_clk);
 252
 253         if (dss.dpll4_m4_ck) {
 254                 dpll4_ck_rate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
 255                 dpll4_m4_ck_rate = clk_get_rate(dss.dpll4_m4_ck);
 256
 257                 seq_printf(s, "dpll4_ck %lu\n", dpll4_ck_rate);
 258
 259                 if (cpu_is_omap3630() || cpu_is_omap44xx())
 260                         seq_printf(s, "%s (%s) = %lu / %lu  = %lu\n",
 261                                         fclk_name, fclk_real_name,
 262                                         dpll4_ck_rate,
 263                                         dpll4_ck_rate / dpll4_m4_ck_rate,
 264                                         fclk_rate);
 265                 else
 266                         seq_printf(s, "%s (%s) = %lu / %lu * 2 = %lu\n",
 267                                         fclk_name, fclk_real_name,
 268                                         dpll4_ck_rate,
 269                                         dpll4_ck_rate / dpll4_m4_ck_rate,
 270                                         fclk_rate);
 271         } else {
 272                 seq_printf(s, "%s (%s) = %lu\n",
 273                                 fclk_name, fclk_real_name,
 274                                 fclk_rate);
 275         }
 276
 277         dss_runtime_put();
 278 }
 279
 280 void dss_dump_regs(struct seq_file *s)
 281 {
 282 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r))
 283
 284         if (dss_runtime_get())
 285                 return;
 286
 287         DUMPREG(DSS_REVISION);
 288         DUMPREG(DSS_SYSCONFIG);
 289         DUMPREG(DSS_SYSSTATUS);
 290         DUMPREG(DSS_CONTROL);
 291
 292         if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
 293                         OMAP_DISPLAY_TYPE_SDI) {
 294                 DUMPREG(DSS_SDI_CONTROL);
 295                 DUMPREG(DSS_PLL_CONTROL);
 296                 DUMPREG(DSS_SDI_STATUS);
 297         }
 298
 299         dss_runtime_put();
 300 #undef DUMPREG
 301 }
 302
 303 void dss_select_dispc_clk_source(enum omap_dss_clk_source clk_src)
 304 {
 305         struct platform_device *dsidev;
 306         int b;
 307         u8 start, end;
 308
 309         switch (clk_src) {
 310         case OMAP_DSS_CLK_SRC_FCK:
 311                 b = 0;
 312                 break;
 313         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
 314                 b = 1;
 315                 dsidev = dsi_get_dsidev_from_id(0);
 316                 dsi_wait_pll_hsdiv_dispc_active(dsidev);
 317                 break;
 318         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
 319                 b = 2;
 320                 dsidev = dsi_get_dsidev_from_id(1);
 321                 dsi_wait_pll_hsdiv_dispc_active(dsidev);
 322                 break;
 323         default:
 324                 BUG();
 325         }
 326
 327         dss_feat_get_reg_field(FEAT_REG_DISPC_CLK_SWITCH, &start, &end);
 328
 329         REG_FLD_MOD(DSS_CONTROL, b, start, end);        /* DISPC_CLK_SWITCH */
 330
 331         dss.dispc_clk_source = clk_src;
 332 }
 333
 334 void dss_select_dsi_clk_source(int dsi_module,
 335                 enum omap_dss_clk_source clk_src)
 336 {
 337         struct platform_device *dsidev;
 338         int b, pos;
 339
 340         switch (clk_src) {
 341         case OMAP_DSS_CLK_SRC_FCK:
 342                 b = 0;
 343                 break;
 344         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI:
 345                 BUG_ON(dsi_module != 0);
 346                 b = 1;
 347                 dsidev = dsi_get_dsidev_from_id(0);
 348                 dsi_wait_pll_hsdiv_dsi_active(dsidev);
 349                 break;
 350         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI:
 351                 BUG_ON(dsi_module != 1);
 352                 b = 1;
 353                 dsidev = dsi_get_dsidev_from_id(1);
 354                 dsi_wait_pll_hsdiv_dsi_active(dsidev);
 355                 break;
 356         default:
 357                 BUG();
 358         }
 359
 360         pos = dsi_module == 0 ? 1 : 10;
 361         REG_FLD_MOD(DSS_CONTROL, b, pos, pos);  /* DSIx_CLK_SWITCH */
 362
 363         dss.dsi_clk_source[dsi_module] = clk_src;
 364 }
 365
 366 void dss_select_lcd_clk_source(enum omap_channel channel,
 367                 enum omap_dss_clk_source clk_src)
 368 {
 369         struct platform_device *dsidev;
 370         int b, ix, pos;
 371
 372         if (!dss_has_feature(FEAT_LCD_CLK_SRC))
 373                 return;
 374
 375         switch (clk_src) {
 376         case OMAP_DSS_CLK_SRC_FCK:
 377                 b = 0;
 378                 break;
 379         case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
 380                 BUG_ON(channel != OMAP_DSS_CHANNEL_LCD);
 381                 b = 1;
 382                 dsidev = dsi_get_dsidev_from_id(0);
 383                 dsi_wait_pll_hsdiv_dispc_active(dsidev);
 384                 break;
 385         case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
 386                 BUG_ON(channel != OMAP_DSS_CHANNEL_LCD2);
 387                 b = 1;
 388                 dsidev = dsi_get_dsidev_from_id(1);
 389                 dsi_wait_pll_hsdiv_dispc_active(dsidev);
 390                 break;
 391         default:
 392                 BUG();
 393         }
 394
 395         pos = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 12;
 396         REG_FLD_MOD(DSS_CONTROL, b, pos, pos);  /* LCDx_CLK_SWITCH */
 397
 398         ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 1;
 399         dss.lcd_clk_source[ix] = clk_src;
 400 }
 401
 402 enum omap_dss_clk_source dss_get_dispc_clk_source(void)
 403 {
 404         return dss.dispc_clk_source;
 405 }
 406
 407 enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module)
 408 {
 409         return dss.dsi_clk_source[dsi_module];
 410 }
 411
 412 enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel)
 413 {
 414         if (dss_has_feature(FEAT_LCD_CLK_SRC)) {
 415                 int ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 1;
 416                 return dss.lcd_clk_source[ix];
 417         } else {
 418                 /* LCD_CLK source is the same as DISPC_FCLK source for
 419                  * OMAP2 and OMAP3 */
 420                 return dss.dispc_clk_source;
 421         }
 422 }
 423
 424 /* calculate clock rates using dividers in cinfo */
 425 int dss_calc_clock_rates(struct dss_clock_info *cinfo)
 426 {
 427         if (dss.dpll4_m4_ck) {
 428                 unsigned long prate;
 429                 u16 fck_div_max = 16;
 430
 431                 if (cpu_is_omap3630() || cpu_is_omap44xx())
 432                         fck_div_max = 32;
 433
 434                 if (cinfo->fck_div > fck_div_max || cinfo->fck_div == 0)
 435                         return -EINVAL;
 436
 437                 prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
 438
 439                 cinfo->fck = prate / cinfo->fck_div;
 440         } else {
 441                 if (cinfo->fck_div != 0)
 442                         return -EINVAL;
 443                 cinfo->fck = clk_get_rate(dss.dss_clk);
 444         }
 445
 446         return 0;
 447 }
 448
 449 int dss_set_clock_div(struct dss_clock_info *cinfo)
 450 {
 451         if (dss.dpll4_m4_ck) {
 452                 unsigned long prate;
 453                 int r;
 454
 455                 prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
 456                 DSSDBG("dpll4_m4 = %ld\n", prate);
 457
 458                 r = clk_set_rate(dss.dpll4_m4_ck, prate / cinfo->fck_div);
 459                 if (r)
 460                         return r;
 461         } else {
 462                 if (cinfo->fck_div != 0)
 463                         return -EINVAL;
 464         }
 465
 466         DSSDBG("fck = %ld (%d)\n", cinfo->fck, cinfo->fck_div);
 467
 468         return 0;
 469 }
 470
 471 int dss_get_clock_div(struct dss_clock_info *cinfo)
 472 {
 473         cinfo->fck = clk_get_rate(dss.dss_clk);
 474
 475         if (dss.dpll4_m4_ck) {
 476                 unsigned long prate;
 477
 478                 prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
 479
 480                 if (cpu_is_omap3630() || cpu_is_omap44xx())
 481                         cinfo->fck_div = prate / (cinfo->fck);
 482                 else
 483                         cinfo->fck_div = prate / (cinfo->fck / 2);
 484         } else {
 485                 cinfo->fck_div = 0;
 486         }
 487
 488         return 0;
 489 }
 490
 491 unsigned long dss_get_dpll4_rate(void)
 492 {
 493         if (dss.dpll4_m4_ck)
 494                 return clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
 495         else
 496                 return 0;
 497 }
 498
 499 int dss_calc_clock_div(bool is_tft, unsigned long req_pck,
 500                 struct dss_clock_info *dss_cinfo,
 501                 struct dispc_clock_info *dispc_cinfo)
 502 {
 503         unsigned long prate;
 504         struct dss_clock_info best_dss;
 505         struct dispc_clock_info best_dispc;
 506
 507         unsigned long fck, max_dss_fck;
 508
 509         u16 fck_div, fck_div_max = 16;
 510
 511         int match = 0;
 512         int min_fck_per_pck;
 513
 514         prate = dss_get_dpll4_rate();
 515
 516         max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
 517
 518         fck = clk_get_rate(dss.dss_clk);
 519         if (req_pck == dss.cache_req_pck &&
 520                         ((cpu_is_omap34xx() && prate == dss.cache_prate) ||
 521                          dss.cache_dss_cinfo.fck == fck)) {
 522                 DSSDBG("dispc clock info found from cache.\n");
 523                 *dss_cinfo = dss.cache_dss_cinfo;
 524                 *dispc_cinfo = dss.cache_dispc_cinfo;
 525                 return 0;
 526         }
 527
 528         min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
 529
 530         if (min_fck_per_pck &&
 531                 req_pck * min_fck_per_pck > max_dss_fck) {
 532                 DSSERR("Requested pixel clock not possible with the current "
 533                                 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
 534                                 "the constraint off.\n");
 535                 min_fck_per_pck = 0;
 536         }
 537
 538 retry:
 539         memset(&best_dss, 0, sizeof(best_dss));
 540         memset(&best_dispc, 0, sizeof(best_dispc));
 541
 542         if (dss.dpll4_m4_ck == NULL) {
 543                 struct dispc_clock_info cur_dispc;
 544                 /* XXX can we change the clock on omap2? */
 545                 fck = clk_get_rate(dss.dss_clk);
 546                 fck_div = 1;
 547
 548                 dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc);
 549                 match = 1;
 550
 551                 best_dss.fck = fck;
 552                 best_dss.fck_div = fck_div;
 553
 554                 best_dispc = cur_dispc;
 555
 556                 goto found;
 557         } else {
 558                 if (cpu_is_omap3630() || cpu_is_omap44xx())
 559                         fck_div_max = 32;
 560
 561                 for (fck_div = fck_div_max; fck_div > 0; --fck_div) {
 562                         struct dispc_clock_info cur_dispc;
 563
 564                         if (fck_div_max == 32)
 565                                 fck = prate / fck_div;
 566                         else
 567                                 fck = prate / fck_div * 2;
 568
 569                         if (fck > max_dss_fck)
 570                                 continue;
 571
 572                         if (min_fck_per_pck &&
 573                                         fck < req_pck * min_fck_per_pck)
 574                                 continue;
 575
 576                         match = 1;
 577
 578                         dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc);
 579
 580                         if (abs(cur_dispc.pck - req_pck) <
 581                                         abs(best_dispc.pck - req_pck)) {
 582
 583                                 best_dss.fck = fck;
 584                                 best_dss.fck_div = fck_div;
 585
 586                                 best_dispc = cur_dispc;
 587
 588                                 if (cur_dispc.pck == req_pck)
 589                                         goto found;
 590                         }
 591                 }
 592         }
 593
 594 found:
 595         if (!match) {
 596                 if (min_fck_per_pck) {
 597                         DSSERR("Could not find suitable clock settings.\n"
 598                                         "Turning FCK/PCK constraint off and"
 599                                         "trying again.\n");
 600                         min_fck_per_pck = 0;
 601                         goto retry;
 602                 }
 603
 604                 DSSERR("Could not find suitable clock settings.\n");
 605
 606                 return -EINVAL;
 607         }
 608
 609         if (dss_cinfo)
 610                 *dss_cinfo = best_dss;
 611         if (dispc_cinfo)
 612                 *dispc_cinfo = best_dispc;
 613
 614         dss.cache_req_pck = req_pck;
 615         dss.cache_prate = prate;
 616         dss.cache_dss_cinfo = best_dss;
 617         dss.cache_dispc_cinfo = best_dispc;
 618
 619         return 0;
 620 }
 621
 622 void dss_set_venc_output(enum omap_dss_venc_type type)
 623 {
 624         int l = 0;
 625
 626         if (type == OMAP_DSS_VENC_TYPE_COMPOSITE)
 627                 l = 0;
 628         else if (type == OMAP_DSS_VENC_TYPE_SVIDEO)
 629                 l = 1;
 630         else
 631                 BUG();
 632
 633         /* venc out selection. 0 = comp, 1 = svideo */
 634         REG_FLD_MOD(DSS_CONTROL, l, 6, 6);
 635 }
 636
 637 void dss_set_dac_pwrdn_bgz(bool enable)
 638 {
 639         REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */
 640 }
 641
 642 void dss_select_hdmi_venc_clk_source(enum dss_hdmi_venc_clk_source_select hdmi)
 643 {
 644         REG_FLD_MOD(DSS_CONTROL, hdmi, 15, 15); /* VENC_HDMI_SWITCH */
 645 }
 646
 647 enum dss_hdmi_venc_clk_source_select dss_get_hdmi_venc_clk_source(void)
 648 {
 649         enum omap_display_type displays;
 650
 651         displays = dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_DIGIT);
 652         if ((displays & OMAP_DISPLAY_TYPE_HDMI) == 0)
 653                 return DSS_VENC_TV_CLK;
 654
 655         return REG_GET(DSS_CONTROL, 15, 15);
 656 }
 657
 658 static int dss_get_clocks(void)
 659 {
 660         struct clk *clk;
 661         int r;
 662
 663         clk = clk_get(&dss.pdev->dev, "fck");
 664         if (IS_ERR(clk)) {
 665                 DSSERR("can't get clock fck\n");
 666                 r = PTR_ERR(clk);
 667                 goto err;
 668         }
 669
 670         dss.dss_clk = clk;
 671
 672         if (cpu_is_omap34xx()) {
 673                 clk = clk_get(NULL, "dpll4_m4_ck");
 674                 if (IS_ERR(clk)) {
 675                         DSSERR("Failed to get dpll4_m4_ck\n");
 676                         r = PTR_ERR(clk);
 677                         goto err;
 678                 }
 679         } else if (cpu_is_omap44xx()) {
 680                 clk = clk_get(NULL, "dpll_per_m5x2_ck");
 681                 if (IS_ERR(clk)) {
 682                         DSSERR("Failed to get dpll_per_m5x2_ck\n");
 683                         r = PTR_ERR(clk);
 684                         goto err;
 685                 }
 686         } else { /* omap24xx */
 687                 clk = NULL;
 688         }
 689
 690         dss.dpll4_m4_ck = clk;
 691
 692         return 0;
 693
 694 err:
 695         if (dss.dss_clk)
 696                 clk_put(dss.dss_clk);
 697         if (dss.dpll4_m4_ck)
 698                 clk_put(dss.dpll4_m4_ck);
 699
 700         return r;
 701 }
 702
 703 static void dss_put_clocks(void)
 704 {
 705         if (dss.dpll4_m4_ck)
 706                 clk_put(dss.dpll4_m4_ck);
 707         clk_put(dss.dss_clk);
 708 }
 709
 710 int dss_runtime_get(void)
 711 {
 712         int r;
 713
 714         DSSDBG("dss_runtime_get\n");
 715
 716         r = pm_runtime_get_sync(&dss.pdev->dev);
 717         WARN_ON(r < 0);
 718         return r < 0 ? r : 0;
 719 }
 720
 721 void dss_runtime_put(void)
 722 {
 723         int r;
 724
 725         DSSDBG("dss_runtime_put\n");
 726
 727         r = pm_runtime_put_sync(&dss.pdev->dev);
 728         WARN_ON(r < 0);
 729 }
 730
 731 /* DEBUGFS */
 732 #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
 733 void dss_debug_dump_clocks(struct seq_file *s)
 734 {
 735         dss_dump_clocks(s);
 736         dispc_dump_clocks(s);
 737 #ifdef CONFIG_OMAP2_DSS_DSI
 738         dsi_dump_clocks(s);
 739 #endif
 740 }
 741 #endif
 742
 743 /* DSS HW IP initialisation */
 744 static int omap_dsshw_probe(struct platform_device *pdev)
 745 {
 746         struct resource *dss_mem;
 747         u32 rev;
 748         int r;
 749
 750         dss.pdev = pdev;
 751
 752         dss_mem = platform_get_resource(dss.pdev, IORESOURCE_MEM, 0);
 753         if (!dss_mem) {
 754                 DSSERR("can't get IORESOURCE_MEM DSS\n");
 755                 return -EINVAL;
 756         }
 757
 758         dss.base = devm_ioremap(&pdev->dev, dss_mem->start,
 759                                 resource_size(dss_mem));
 760         if (!dss.base) {
 761                 DSSERR("can't ioremap DSS\n");
 762                 return -ENOMEM;
 763         }
 764
 765         r = dss_get_clocks();
 766         if (r)
 767                 return r;
 768
 769         pm_runtime_enable(&pdev->dev);
 770
 771         r = dss_runtime_get();
 772         if (r)
 773                 goto err_runtime_get;
 774
 775         /* Select DPLL */
 776         REG_FLD_MOD(DSS_CONTROL, 0, 0, 0);
 777
 778 #ifdef CONFIG_OMAP2_DSS_VENC
 779         REG_FLD_MOD(DSS_CONTROL, 1, 4, 4);      /* venc dac demen */
 780         REG_FLD_MOD(DSS_CONTROL, 1, 3, 3);      /* venc clock 4x enable */
 781         REG_FLD_MOD(DSS_CONTROL, 0, 2, 2);      /* venc clock mode = normal */
 782 #endif
 783         dss.dsi_clk_source[0] = OMAP_DSS_CLK_SRC_FCK;
 784         dss.dsi_clk_source[1] = OMAP_DSS_CLK_SRC_FCK;
 785         dss.dispc_clk_source = OMAP_DSS_CLK_SRC_FCK;
 786         dss.lcd_clk_source[0] = OMAP_DSS_CLK_SRC_FCK;
 787         dss.lcd_clk_source[1] = OMAP_DSS_CLK_SRC_FCK;
 788
 789         rev = dss_read_reg(DSS_REVISION);
 790         printk(KERN_INFO "OMAP DSS rev %d.%d\n",
 791                         FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
 792
 793         dss_runtime_put();
 794
 795         return 0;
 796
 797 err_runtime_get:
 798         pm_runtime_disable(&pdev->dev);
 799         dss_put_clocks();
 800         return r;
 801 }
 802
 803 static int omap_dsshw_remove(struct platform_device *pdev)
 804 {
 805         pm_runtime_disable(&pdev->dev);
 806
 807         dss_put_clocks();
 808
 809         return 0;
 810 }
 811
 812 static int dss_runtime_suspend(struct device *dev)
 813 {
 814         dss_save_context();
 815         dss_set_min_bus_tput(dev, 0);
 816         return 0;
 817 }
 818
 819 static int dss_runtime_resume(struct device *dev)
 820 {
 821         int r;
 822         /*
 823          * Set an arbitrarily high tput request to ensure OPP100.
 824          * What we should really do is to make a request to stay in OPP100,
 825          * without any tput requirements, but that is not currently possible
 826          * via the PM layer.
 827          */
 828
 829         r = dss_set_min_bus_tput(dev, 1000000000);
 830         if (r)
 831                 return r;
 832
 833         dss_restore_context();
 834         return 0;
 835 }
 836
 837 static const struct dev_pm_ops dss_pm_ops = {
 838         .runtime_suspend = dss_runtime_suspend,
 839         .runtime_resume = dss_runtime_resume,
 840 };
 841
 842 static struct platform_driver omap_dsshw_driver = {
 843         .remove         = omap_dsshw_remove,
 844         .driver         = {
 845                 .name   = "omapdss_dss",
 846                 .owner  = THIS_MODULE,
 847                 .pm     = &dss_pm_ops,
 848         },
 849 };
 850
 851 int dss_init_platform_driver(void)
 852 {
 853         return platform_driver_probe(&omap_dsshw_driver, omap_dsshw_probe);
 854 }
 855
 856 void dss_uninit_platform_driver(void)
 857 {
 858         platform_driver_unregister(&omap_dsshw_driver);
 859 }