2 * linux/drivers/video/omap2/dss/dss.c
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * Some code and ideas taken from drivers/video/omap/ driver
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
23 #define DSS_SUBSYS_NAME "DSS"
25 #include <linux/kernel.h>
27 #include <linux/err.h>
28 #include <linux/delay.h>
29 #include <linux/seq_file.h>
30 #include <linux/clk.h>
32 #include <plat/display.h>
33 #include <plat/clock.h>
35 #include "dss_features.h"
37 #define DSS_SZ_REGS SZ_512
43 #define DSS_REG(idx) ((const struct dss_reg) { idx })
45 #define DSS_REVISION DSS_REG(0x0000)
46 #define DSS_SYSCONFIG DSS_REG(0x0010)
47 #define DSS_SYSSTATUS DSS_REG(0x0014)
48 #define DSS_IRQSTATUS DSS_REG(0x0018)
49 #define DSS_CONTROL DSS_REG(0x0040)
50 #define DSS_SDI_CONTROL DSS_REG(0x0044)
51 #define DSS_PLL_CONTROL DSS_REG(0x0048)
52 #define DSS_SDI_STATUS DSS_REG(0x005C)
54 #define REG_GET(idx, start, end) \
55 FLD_GET(dss_read_reg(idx), start, end)
57 #define REG_FLD_MOD(idx, val, start, end) \
58 dss_write_reg(idx, FLD_MOD(dss_read_reg(idx), val, start, end))
61 struct platform_device *pdev;
65 struct clk *dpll4_m4_ck;
68 struct clk *dss_sys_clk;
69 struct clk *dss_tv_fck;
70 struct clk *dss_video_fck;
71 unsigned num_clks_enabled;
73 unsigned long cache_req_pck;
74 unsigned long cache_prate;
75 struct dss_clock_info cache_dss_cinfo;
76 struct dispc_clock_info cache_dispc_cinfo;
78 enum dss_clk_source dsi_clk_source;
79 enum dss_clk_source dispc_clk_source;
81 u32 ctx[DSS_SZ_REGS / sizeof(u32)];
84 static const struct dss_clk_source_name dss_generic_clk_source_names[] = {
85 { DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, "DSI_PLL_HSDIV_DISPC" },
86 { DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, "DSI_PLL_HSDIV_DSI" },
87 { DSS_CLK_SRC_FCK, "DSS_FCK" },
90 static void dss_clk_enable_all_no_ctx(void);
91 static void dss_clk_disable_all_no_ctx(void);
92 static void dss_clk_enable_no_ctx(enum dss_clock clks);
93 static void dss_clk_disable_no_ctx(enum dss_clock clks);
95 static int _omap_dss_wait_reset(void);
97 static inline void dss_write_reg(const struct dss_reg idx, u32 val)
99 __raw_writel(val, dss.base + idx.idx);
102 static inline u32 dss_read_reg(const struct dss_reg idx)
104 return __raw_readl(dss.base + idx.idx);
108 dss.ctx[(DSS_##reg).idx / sizeof(u32)] = dss_read_reg(DSS_##reg)
110 dss_write_reg(DSS_##reg, dss.ctx[(DSS_##reg).idx / sizeof(u32)])
112 void dss_save_context(void)
114 if (cpu_is_omap24xx())
120 if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
121 OMAP_DISPLAY_TYPE_SDI) {
127 void dss_restore_context(void)
129 if (_omap_dss_wait_reset())
130 DSSERR("DSS not coming out of reset after sleep\n");
135 if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
136 OMAP_DISPLAY_TYPE_SDI) {
145 void dss_sdi_init(u8 datapairs)
149 BUG_ON(datapairs > 3 || datapairs < 1);
151 l = dss_read_reg(DSS_SDI_CONTROL);
152 l = FLD_MOD(l, 0xf, 19, 15); /* SDI_PDIV */
153 l = FLD_MOD(l, datapairs-1, 3, 2); /* SDI_PRSEL */
154 l = FLD_MOD(l, 2, 1, 0); /* SDI_BWSEL */
155 dss_write_reg(DSS_SDI_CONTROL, l);
157 l = dss_read_reg(DSS_PLL_CONTROL);
158 l = FLD_MOD(l, 0x7, 25, 22); /* SDI_PLL_FREQSEL */
159 l = FLD_MOD(l, 0xb, 16, 11); /* SDI_PLL_REGN */
160 l = FLD_MOD(l, 0xb4, 10, 1); /* SDI_PLL_REGM */
161 dss_write_reg(DSS_PLL_CONTROL, l);
164 int dss_sdi_enable(void)
166 unsigned long timeout;
168 dispc_pck_free_enable(1);
171 REG_FLD_MOD(DSS_PLL_CONTROL, 1, 18, 18); /* SDI_PLL_SYSRESET */
172 udelay(1); /* wait 2x PCLK */
175 REG_FLD_MOD(DSS_PLL_CONTROL, 1, 28, 28); /* SDI_PLL_GOBIT */
177 /* Waiting for PLL lock request to complete */
178 timeout = jiffies + msecs_to_jiffies(500);
179 while (dss_read_reg(DSS_SDI_STATUS) & (1 << 6)) {
180 if (time_after_eq(jiffies, timeout)) {
181 DSSERR("PLL lock request timed out\n");
186 /* Clearing PLL_GO bit */
187 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 28, 28);
189 /* Waiting for PLL to lock */
190 timeout = jiffies + msecs_to_jiffies(500);
191 while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 5))) {
192 if (time_after_eq(jiffies, timeout)) {
193 DSSERR("PLL lock timed out\n");
198 dispc_lcd_enable_signal(1);
200 /* Waiting for SDI reset to complete */
201 timeout = jiffies + msecs_to_jiffies(500);
202 while (!(dss_read_reg(DSS_SDI_STATUS) & (1 << 2))) {
203 if (time_after_eq(jiffies, timeout)) {
204 DSSERR("SDI reset timed out\n");
212 dispc_lcd_enable_signal(0);
215 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
217 dispc_pck_free_enable(0);
222 void dss_sdi_disable(void)
224 dispc_lcd_enable_signal(0);
226 dispc_pck_free_enable(0);
229 REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
232 const char *dss_get_generic_clk_source_name(enum dss_clk_source clk_src)
234 return dss_generic_clk_source_names[clk_src].clksrc_name;
237 void dss_dump_clocks(struct seq_file *s)
239 unsigned long dpll4_ck_rate;
240 unsigned long dpll4_m4_ck_rate;
242 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
244 dpll4_ck_rate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
245 dpll4_m4_ck_rate = clk_get_rate(dss.dpll4_m4_ck);
247 seq_printf(s, "- DSS -\n");
249 seq_printf(s, "dpll4_ck %lu\n", dpll4_ck_rate);
251 if (cpu_is_omap3630())
252 seq_printf(s, "%s (%s) = %lu / %lu = %lu\n",
253 dss_get_generic_clk_source_name(DSS_CLK_SRC_FCK),
254 dss_feat_get_clk_source_name(DSS_CLK_SRC_FCK),
256 dpll4_ck_rate / dpll4_m4_ck_rate,
257 dss_clk_get_rate(DSS_CLK_FCK));
259 seq_printf(s, "%s (%s) = %lu / %lu * 2 = %lu\n",
260 dss_get_generic_clk_source_name(DSS_CLK_SRC_FCK),
261 dss_feat_get_clk_source_name(DSS_CLK_SRC_FCK),
263 dpll4_ck_rate / dpll4_m4_ck_rate,
264 dss_clk_get_rate(DSS_CLK_FCK));
266 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
269 void dss_dump_regs(struct seq_file *s)
271 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dss_read_reg(r))
273 dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
275 DUMPREG(DSS_REVISION);
276 DUMPREG(DSS_SYSCONFIG);
277 DUMPREG(DSS_SYSSTATUS);
278 DUMPREG(DSS_IRQSTATUS);
279 DUMPREG(DSS_CONTROL);
281 if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
282 OMAP_DISPLAY_TYPE_SDI) {
283 DUMPREG(DSS_SDI_CONTROL);
284 DUMPREG(DSS_PLL_CONTROL);
285 DUMPREG(DSS_SDI_STATUS);
288 dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
292 void dss_select_dispc_clk_source(enum dss_clk_source clk_src)
296 BUG_ON(clk_src != DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC &&
297 clk_src != DSS_CLK_SRC_FCK);
299 b = clk_src == DSS_CLK_SRC_FCK ? 0 : 1;
301 if (clk_src == DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC)
302 dsi_wait_dsi1_pll_active();
304 REG_FLD_MOD(DSS_CONTROL, b, 0, 0); /* DISPC_CLK_SWITCH */
306 dss.dispc_clk_source = clk_src;
309 void dss_select_dsi_clk_source(enum dss_clk_source clk_src)
313 BUG_ON(clk_src != DSS_CLK_SRC_DSI_PLL_HSDIV_DSI &&
314 clk_src != DSS_CLK_SRC_FCK);
316 b = clk_src == DSS_CLK_SRC_FCK ? 0 : 1;
318 if (clk_src == DSS_CLK_SRC_DSI_PLL_HSDIV_DSI)
319 dsi_wait_dsi2_pll_active();
321 REG_FLD_MOD(DSS_CONTROL, b, 1, 1); /* DSI_CLK_SWITCH */
323 dss.dsi_clk_source = clk_src;
326 enum dss_clk_source dss_get_dispc_clk_source(void)
328 return dss.dispc_clk_source;
331 enum dss_clk_source dss_get_dsi_clk_source(void)
333 return dss.dsi_clk_source;
336 /* calculate clock rates using dividers in cinfo */
337 int dss_calc_clock_rates(struct dss_clock_info *cinfo)
341 if (cinfo->fck_div > (cpu_is_omap3630() ? 32 : 16) ||
345 prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
347 cinfo->fck = prate / cinfo->fck_div;
352 int dss_set_clock_div(struct dss_clock_info *cinfo)
357 if (cpu_is_omap34xx()) {
358 prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
359 DSSDBG("dpll4_m4 = %ld\n", prate);
361 r = clk_set_rate(dss.dpll4_m4_ck, prate / cinfo->fck_div);
366 DSSDBG("fck = %ld (%d)\n", cinfo->fck, cinfo->fck_div);
371 int dss_get_clock_div(struct dss_clock_info *cinfo)
373 cinfo->fck = dss_clk_get_rate(DSS_CLK_FCK);
375 if (cpu_is_omap34xx()) {
377 prate = clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
378 if (cpu_is_omap3630())
379 cinfo->fck_div = prate / (cinfo->fck);
381 cinfo->fck_div = prate / (cinfo->fck / 2);
389 unsigned long dss_get_dpll4_rate(void)
391 if (cpu_is_omap34xx())
392 return clk_get_rate(clk_get_parent(dss.dpll4_m4_ck));
397 int dss_calc_clock_div(bool is_tft, unsigned long req_pck,
398 struct dss_clock_info *dss_cinfo,
399 struct dispc_clock_info *dispc_cinfo)
402 struct dss_clock_info best_dss;
403 struct dispc_clock_info best_dispc;
405 unsigned long fck, max_dss_fck;
412 prate = dss_get_dpll4_rate();
414 max_dss_fck = dss_feat_get_max_dss_fck();
416 fck = dss_clk_get_rate(DSS_CLK_FCK);
417 if (req_pck == dss.cache_req_pck &&
418 ((cpu_is_omap34xx() && prate == dss.cache_prate) ||
419 dss.cache_dss_cinfo.fck == fck)) {
420 DSSDBG("dispc clock info found from cache.\n");
421 *dss_cinfo = dss.cache_dss_cinfo;
422 *dispc_cinfo = dss.cache_dispc_cinfo;
426 min_fck_per_pck = CONFIG_OMAP2_DSS_MIN_FCK_PER_PCK;
428 if (min_fck_per_pck &&
429 req_pck * min_fck_per_pck > max_dss_fck) {
430 DSSERR("Requested pixel clock not possible with the current "
431 "OMAP2_DSS_MIN_FCK_PER_PCK setting. Turning "
432 "the constraint off.\n");
437 memset(&best_dss, 0, sizeof(best_dss));
438 memset(&best_dispc, 0, sizeof(best_dispc));
440 if (cpu_is_omap24xx()) {
441 struct dispc_clock_info cur_dispc;
442 /* XXX can we change the clock on omap2? */
443 fck = dss_clk_get_rate(DSS_CLK_FCK);
446 dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc);
450 best_dss.fck_div = fck_div;
452 best_dispc = cur_dispc;
455 } else if (cpu_is_omap34xx()) {
456 for (fck_div = (cpu_is_omap3630() ? 32 : 16);
457 fck_div > 0; --fck_div) {
458 struct dispc_clock_info cur_dispc;
460 if (cpu_is_omap3630())
461 fck = prate / fck_div;
463 fck = prate / fck_div * 2;
465 if (fck > max_dss_fck)
468 if (min_fck_per_pck &&
469 fck < req_pck * min_fck_per_pck)
474 dispc_find_clk_divs(is_tft, req_pck, fck, &cur_dispc);
476 if (abs(cur_dispc.pck - req_pck) <
477 abs(best_dispc.pck - req_pck)) {
480 best_dss.fck_div = fck_div;
482 best_dispc = cur_dispc;
484 if (cur_dispc.pck == req_pck)
494 if (min_fck_per_pck) {
495 DSSERR("Could not find suitable clock settings.\n"
496 "Turning FCK/PCK constraint off and"
502 DSSERR("Could not find suitable clock settings.\n");
508 *dss_cinfo = best_dss;
510 *dispc_cinfo = best_dispc;
512 dss.cache_req_pck = req_pck;
513 dss.cache_prate = prate;
514 dss.cache_dss_cinfo = best_dss;
515 dss.cache_dispc_cinfo = best_dispc;
520 static int _omap_dss_wait_reset(void)
524 while (REG_GET(DSS_SYSSTATUS, 0, 0) == 0) {
526 DSSERR("soft reset failed\n");
535 static int _omap_dss_reset(void)
538 REG_FLD_MOD(DSS_SYSCONFIG, 1, 1, 1);
539 return _omap_dss_wait_reset();
542 void dss_set_venc_output(enum omap_dss_venc_type type)
546 if (type == OMAP_DSS_VENC_TYPE_COMPOSITE)
548 else if (type == OMAP_DSS_VENC_TYPE_SVIDEO)
553 /* venc out selection. 0 = comp, 1 = svideo */
554 REG_FLD_MOD(DSS_CONTROL, l, 6, 6);
557 void dss_set_dac_pwrdn_bgz(bool enable)
559 REG_FLD_MOD(DSS_CONTROL, enable, 5, 5); /* DAC Power-Down Control */
562 static int dss_init(bool skip_init)
566 struct resource *dss_mem;
568 dss_mem = platform_get_resource(dss.pdev, IORESOURCE_MEM, 0);
570 DSSERR("can't get IORESOURCE_MEM DSS\n");
574 dss.base = ioremap(dss_mem->start, resource_size(dss_mem));
576 DSSERR("can't ioremap DSS\n");
582 /* disable LCD and DIGIT output. This seems to fix the synclost
583 * problem that we get, if the bootloader starts the DSS and
584 * the kernel resets it */
585 omap_writel(omap_readl(0x48050440) & ~0x3, 0x48050440);
587 /* We need to wait here a bit, otherwise we sometimes start to
588 * get synclost errors, and after that only power cycle will
589 * restore DSS functionality. I have no idea why this happens.
590 * And we have to wait _before_ resetting the DSS, but after
599 REG_FLD_MOD(DSS_SYSCONFIG, 1, 0, 0);
602 REG_FLD_MOD(DSS_CONTROL, 0, 0, 0);
604 #ifdef CONFIG_OMAP2_DSS_VENC
605 REG_FLD_MOD(DSS_CONTROL, 1, 4, 4); /* venc dac demen */
606 REG_FLD_MOD(DSS_CONTROL, 1, 3, 3); /* venc clock 4x enable */
607 REG_FLD_MOD(DSS_CONTROL, 0, 2, 2); /* venc clock mode = normal */
610 if (cpu_is_omap34xx()) {
611 dss.dpll4_m4_ck = clk_get(NULL, "dpll4_m4_ck");
612 if (IS_ERR(dss.dpll4_m4_ck)) {
613 DSSERR("Failed to get dpll4_m4_ck\n");
614 r = PTR_ERR(dss.dpll4_m4_ck);
619 dss.dsi_clk_source = DSS_CLK_SRC_FCK;
620 dss.dispc_clk_source = DSS_CLK_SRC_FCK;
624 rev = dss_read_reg(DSS_REVISION);
625 printk(KERN_INFO "OMAP DSS rev %d.%d\n",
626 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
636 static void dss_exit(void)
638 if (cpu_is_omap34xx())
639 clk_put(dss.dpll4_m4_ck);
645 static int dss_get_ctx_id(void)
647 struct omap_display_platform_data *pdata = dss.pdev->dev.platform_data;
650 if (!pdata->board_data->get_last_off_on_transaction_id)
652 r = pdata->board_data->get_last_off_on_transaction_id(&dss.pdev->dev);
654 dev_err(&dss.pdev->dev, "getting transaction ID failed, "
655 "will force context restore\n");
661 int dss_need_ctx_restore(void)
663 int id = dss_get_ctx_id();
665 if (id < 0 || id != dss.ctx_id) {
666 DSSDBG("ctx id %d -> id %d\n",
675 static void save_all_ctx(void)
677 DSSDBG("save context\n");
679 dss_clk_enable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK);
682 dispc_save_context();
683 #ifdef CONFIG_OMAP2_DSS_DSI
687 dss_clk_disable_no_ctx(DSS_CLK_ICK | DSS_CLK_FCK);
690 static void restore_all_ctx(void)
692 DSSDBG("restore context\n");
694 dss_clk_enable_all_no_ctx();
696 dss_restore_context();
697 dispc_restore_context();
698 #ifdef CONFIG_OMAP2_DSS_DSI
699 dsi_restore_context();
702 dss_clk_disable_all_no_ctx();
705 static int dss_get_clock(struct clk **clock, const char *clk_name)
709 clk = clk_get(&dss.pdev->dev, clk_name);
712 DSSERR("can't get clock %s", clk_name);
718 DSSDBG("clk %s, rate %ld\n", clk_name, clk_get_rate(clk));
723 static int dss_get_clocks(void)
726 struct omap_display_platform_data *pdata = dss.pdev->dev.platform_data;
730 dss.dss_sys_clk = NULL;
731 dss.dss_tv_fck = NULL;
732 dss.dss_video_fck = NULL;
734 r = dss_get_clock(&dss.dss_ick, "ick");
738 r = dss_get_clock(&dss.dss_fck, "fck");
742 if (!pdata->opt_clock_available) {
747 if (pdata->opt_clock_available("sys_clk")) {
748 r = dss_get_clock(&dss.dss_sys_clk, "sys_clk");
753 if (pdata->opt_clock_available("tv_clk")) {
754 r = dss_get_clock(&dss.dss_tv_fck, "tv_clk");
759 if (pdata->opt_clock_available("video_clk")) {
760 r = dss_get_clock(&dss.dss_video_fck, "video_clk");
769 clk_put(dss.dss_ick);
771 clk_put(dss.dss_fck);
773 clk_put(dss.dss_sys_clk);
775 clk_put(dss.dss_tv_fck);
776 if (dss.dss_video_fck)
777 clk_put(dss.dss_video_fck);
782 static void dss_put_clocks(void)
784 if (dss.dss_video_fck)
785 clk_put(dss.dss_video_fck);
787 clk_put(dss.dss_tv_fck);
789 clk_put(dss.dss_sys_clk);
790 clk_put(dss.dss_fck);
791 clk_put(dss.dss_ick);
794 unsigned long dss_clk_get_rate(enum dss_clock clk)
798 return clk_get_rate(dss.dss_ick);
800 return clk_get_rate(dss.dss_fck);
802 return clk_get_rate(dss.dss_sys_clk);
804 return clk_get_rate(dss.dss_tv_fck);
806 return clk_get_rate(dss.dss_video_fck);
813 static unsigned count_clk_bits(enum dss_clock clks)
815 unsigned num_clks = 0;
817 if (clks & DSS_CLK_ICK)
819 if (clks & DSS_CLK_FCK)
821 if (clks & DSS_CLK_SYSCK)
823 if (clks & DSS_CLK_TVFCK)
825 if (clks & DSS_CLK_VIDFCK)
831 static void dss_clk_enable_no_ctx(enum dss_clock clks)
833 unsigned num_clks = count_clk_bits(clks);
835 if (clks & DSS_CLK_ICK)
836 clk_enable(dss.dss_ick);
837 if (clks & DSS_CLK_FCK)
838 clk_enable(dss.dss_fck);
839 if ((clks & DSS_CLK_SYSCK) && dss.dss_sys_clk)
840 clk_enable(dss.dss_sys_clk);
841 if ((clks & DSS_CLK_TVFCK) && dss.dss_tv_fck)
842 clk_enable(dss.dss_tv_fck);
843 if ((clks & DSS_CLK_VIDFCK) && dss.dss_video_fck)
844 clk_enable(dss.dss_video_fck);
846 dss.num_clks_enabled += num_clks;
849 void dss_clk_enable(enum dss_clock clks)
851 bool check_ctx = dss.num_clks_enabled == 0;
853 dss_clk_enable_no_ctx(clks);
855 if (check_ctx && cpu_is_omap34xx() && dss_need_ctx_restore())
859 static void dss_clk_disable_no_ctx(enum dss_clock clks)
861 unsigned num_clks = count_clk_bits(clks);
863 if (clks & DSS_CLK_ICK)
864 clk_disable(dss.dss_ick);
865 if (clks & DSS_CLK_FCK)
866 clk_disable(dss.dss_fck);
867 if ((clks & DSS_CLK_SYSCK) && dss.dss_sys_clk)
868 clk_disable(dss.dss_sys_clk);
869 if ((clks & DSS_CLK_TVFCK) && dss.dss_tv_fck)
870 clk_disable(dss.dss_tv_fck);
871 if ((clks & DSS_CLK_VIDFCK) && dss.dss_video_fck)
872 clk_disable(dss.dss_video_fck);
874 dss.num_clks_enabled -= num_clks;
877 void dss_clk_disable(enum dss_clock clks)
879 if (cpu_is_omap34xx()) {
880 unsigned num_clks = count_clk_bits(clks);
882 BUG_ON(dss.num_clks_enabled < num_clks);
884 if (dss.num_clks_enabled == num_clks)
888 dss_clk_disable_no_ctx(clks);
891 static void dss_clk_enable_all_no_ctx(void)
895 clks = DSS_CLK_ICK | DSS_CLK_FCK | DSS_CLK_SYSCK | DSS_CLK_TVFCK;
896 if (cpu_is_omap34xx())
897 clks |= DSS_CLK_VIDFCK;
898 dss_clk_enable_no_ctx(clks);
901 static void dss_clk_disable_all_no_ctx(void)
905 clks = DSS_CLK_ICK | DSS_CLK_FCK | DSS_CLK_SYSCK | DSS_CLK_TVFCK;
906 if (cpu_is_omap34xx())
907 clks |= DSS_CLK_VIDFCK;
908 dss_clk_disable_no_ctx(clks);
911 #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
913 static void core_dump_clocks(struct seq_file *s)
916 struct clk *clocks[5] = {
924 seq_printf(s, "- CORE -\n");
926 seq_printf(s, "internal clk count\t\t%u\n", dss.num_clks_enabled);
928 for (i = 0; i < 5; i++) {
931 seq_printf(s, "%-15s\t%lu\t%d\n",
933 clk_get_rate(clocks[i]),
934 clocks[i]->usecount);
937 #endif /* defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT) */
940 #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
941 void dss_debug_dump_clocks(struct seq_file *s)
945 dispc_dump_clocks(s);
946 #ifdef CONFIG_OMAP2_DSS_DSI
953 /* DSS HW IP initialisation */
954 static int omap_dsshw_probe(struct platform_device *pdev)
961 r = dss_get_clocks();
965 dss_clk_enable_all_no_ctx();
967 dss.ctx_id = dss_get_ctx_id();
968 DSSDBG("initial ctx id %u\n", dss.ctx_id);
970 #ifdef CONFIG_FB_OMAP_BOOTLOADER_INIT
972 if (omap_readl(0x48050440) & 1) /* LCD enabled? */
976 r = dss_init(skip_init);
978 DSSERR("Failed to initialize DSS\n");
982 dss_clk_disable_all_no_ctx();
986 dss_clk_disable_all_no_ctx();
992 static int omap_dsshw_remove(struct platform_device *pdev)
998 * As part of hwmod changes, DSS is not the only controller of dss
999 * clocks; hwmod framework itself will also enable clocks during hwmod
1000 * init for dss, and autoidle is set in h/w for DSS. Hence, there's no
1001 * need to disable clocks if their usecounts > 1.
1003 WARN_ON(dss.num_clks_enabled > 0);
1009 static struct platform_driver omap_dsshw_driver = {
1010 .probe = omap_dsshw_probe,
1011 .remove = omap_dsshw_remove,
1013 .name = "omapdss_dss",
1014 .owner = THIS_MODULE,
1018 int dss_init_platform_driver(void)
1020 return platform_driver_register(&omap_dsshw_driver);
1023 void dss_uninit_platform_driver(void)
1025 return platform_driver_unregister(&omap_dsshw_driver);