2 * linux/drivers/video/omap2/dss/dss.h
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * Some code and ideas taken from drivers/video/omap/ driver
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
26 #ifdef CONFIG_OMAP2_DSS_DEBUG_SUPPORT
31 extern unsigned int dss_debug;
32 #ifdef DSS_SUBSYS_NAME
33 #define DSSDBG(format, ...) \
35 printk(KERN_DEBUG "omapdss " DSS_SUBSYS_NAME ": " format, \
38 #define DSSDBG(format, ...) \
40 printk(KERN_DEBUG "omapdss: " format, ## __VA_ARGS__)
43 #ifdef DSS_SUBSYS_NAME
44 #define DSSDBGF(format, ...) \
46 printk(KERN_DEBUG "omapdss " DSS_SUBSYS_NAME \
47 ": %s(" format ")\n", \
51 #define DSSDBGF(format, ...) \
53 printk(KERN_DEBUG "omapdss: " \
54 ": %s(" format ")\n", \
60 #define DSSDBG(format, ...)
61 #define DSSDBGF(format, ...)
65 #ifdef DSS_SUBSYS_NAME
66 #define DSSERR(format, ...) \
67 printk(KERN_ERR "omapdss " DSS_SUBSYS_NAME " error: " format, \
70 #define DSSERR(format, ...) \
71 printk(KERN_ERR "omapdss error: " format, ## __VA_ARGS__)
74 #ifdef DSS_SUBSYS_NAME
75 #define DSSINFO(format, ...) \
76 printk(KERN_INFO "omapdss " DSS_SUBSYS_NAME ": " format, \
79 #define DSSINFO(format, ...) \
80 printk(KERN_INFO "omapdss: " format, ## __VA_ARGS__)
83 #ifdef DSS_SUBSYS_NAME
84 #define DSSWARN(format, ...) \
85 printk(KERN_WARNING "omapdss " DSS_SUBSYS_NAME ": " format, \
88 #define DSSWARN(format, ...) \
89 printk(KERN_WARNING "omapdss: " format, ## __VA_ARGS__)
92 /* OMAP TRM gives bitfields as start:end, where start is the higher bit
93 number. For example 7:0 */
94 #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
95 #define FLD_VAL(val, start, end) (((val) << (end)) & FLD_MASK(start, end))
96 #define FLD_GET(val, start, end) (((val) & FLD_MASK(start, end)) >> (end))
97 #define FLD_MOD(orig, val, start, end) \
98 (((orig) & ~FLD_MASK(start, end)) | FLD_VAL(val, start, end))
100 #define DISPC_MAX_FCK 173000000
102 enum omap_burst_size {
103 OMAP_DSS_BURST_4x32 = 0,
104 OMAP_DSS_BURST_8x32 = 1,
105 OMAP_DSS_BURST_16x32 = 2,
108 enum omap_parallel_interface_mode {
109 OMAP_DSS_PARALLELMODE_BYPASS, /* MIPI DPI */
110 OMAP_DSS_PARALLELMODE_RFBI, /* MIPI DBI */
111 OMAP_DSS_PARALLELMODE_DSI,
115 DSS_CLK_ICK = 1 << 0, /* DSS_L3_ICLK and DSS_L4_ICLK */
116 DSS_CLK_FCK = 1 << 1, /* DSS1_ALWON_FCLK */
117 DSS_CLK_SYSCK = 1 << 2, /* DSS2_ALWON_FCLK */
118 DSS_CLK_TVFCK = 1 << 3, /* DSS_TV_FCLK */
119 DSS_CLK_VIDFCK = 1 << 4, /* DSS_96M_FCLK*/
122 enum dss_clk_source {
123 DSS_SRC_DSI1_PLL_FCLK,
124 DSS_SRC_DSI2_PLL_FCLK,
125 DSS_SRC_DSS1_ALWON_FCLK,
128 struct dss_clock_info {
129 /* rates that we get with dividers below */
136 struct dispc_clock_info {
137 /* rates that we get with dividers below */
146 struct dsi_clock_info {
147 /* rates that we get with dividers below */
149 unsigned long clkin4ddr;
151 unsigned long dsi1_pll_fclk;
152 unsigned long dsi2_pll_fclk;
154 unsigned long lp_clk;
169 struct platform_device;
172 struct bus_type *dss_get_bus(void);
173 struct regulator *dss_get_vdds_dsi(void);
174 struct regulator *dss_get_vdds_sdi(void);
177 int dss_suspend_all_devices(void);
178 int dss_resume_all_devices(void);
179 void dss_disable_all_devices(void);
181 void dss_init_device(struct platform_device *pdev,
182 struct omap_dss_device *dssdev);
183 void dss_uninit_device(struct platform_device *pdev,
184 struct omap_dss_device *dssdev);
185 bool dss_use_replication(struct omap_dss_device *dssdev,
186 enum omap_color_mode mode);
187 void default_get_overlay_fifo_thresholds(enum omap_plane plane,
188 u32 fifo_size, enum omap_burst_size *burst_size,
189 u32 *fifo_low, u32 *fifo_high);
192 int dss_init_overlay_managers(struct platform_device *pdev);
193 void dss_uninit_overlay_managers(struct platform_device *pdev);
194 int dss_mgr_wait_for_go_ovl(struct omap_overlay *ovl);
195 void dss_setup_partial_planes(struct omap_dss_device *dssdev,
196 u16 *x, u16 *y, u16 *w, u16 *h,
197 bool enlarge_update_area);
198 void dss_start_update(struct omap_dss_device *dssdev);
201 void dss_init_overlays(struct platform_device *pdev);
202 void dss_uninit_overlays(struct platform_device *pdev);
203 int dss_check_overlay(struct omap_overlay *ovl, struct omap_dss_device *dssdev);
204 void dss_overlay_setup_dispc_manager(struct omap_overlay_manager *mgr);
206 void dss_overlay_setup_l4_manager(struct omap_overlay_manager *mgr);
208 void dss_recheck_connections(struct omap_dss_device *dssdev, bool force);
211 int dss_init_platform_driver(void);
212 void dss_uninit_platform_driver(void);
214 void dss_save_context(void);
215 void dss_restore_context(void);
216 void dss_clk_enable(enum dss_clock clks);
217 void dss_clk_disable(enum dss_clock clks);
218 unsigned long dss_clk_get_rate(enum dss_clock clk);
219 int dss_need_ctx_restore(void);
220 void dss_dump_clocks(struct seq_file *s);
222 void dss_dump_regs(struct seq_file *s);
223 #if defined(CONFIG_DEBUG_FS) && defined(CONFIG_OMAP2_DSS_DEBUG_SUPPORT)
224 void dss_debug_dump_clocks(struct seq_file *s);
227 void dss_sdi_init(u8 datapairs);
228 int dss_sdi_enable(void);
229 void dss_sdi_disable(void);
231 void dss_select_dispc_clk_source(enum dss_clk_source clk_src);
232 void dss_select_dsi_clk_source(enum dss_clk_source clk_src);
233 enum dss_clk_source dss_get_dispc_clk_source(void);
234 enum dss_clk_source dss_get_dsi_clk_source(void);
236 void dss_set_venc_output(enum omap_dss_venc_type type);
237 void dss_set_dac_pwrdn_bgz(bool enable);
239 unsigned long dss_get_dpll4_rate(void);
240 int dss_calc_clock_rates(struct dss_clock_info *cinfo);
241 int dss_set_clock_div(struct dss_clock_info *cinfo);
242 int dss_get_clock_div(struct dss_clock_info *cinfo);
243 int dss_calc_clock_div(bool is_tft, unsigned long req_pck,
244 struct dss_clock_info *dss_cinfo,
245 struct dispc_clock_info *dispc_cinfo);
248 #ifdef CONFIG_OMAP2_DSS_SDI
249 int sdi_init(bool skip_init);
251 int sdi_init_display(struct omap_dss_device *display);
253 static inline int sdi_init(bool skip_init)
257 static inline void sdi_exit(void)
263 #ifdef CONFIG_OMAP2_DSS_DSI
264 int dsi_init_platform_driver(void);
265 void dsi_uninit_platform_driver(void);
267 void dsi_dump_clocks(struct seq_file *s);
268 void dsi_dump_irqs(struct seq_file *s);
269 void dsi_dump_regs(struct seq_file *s);
271 void dsi_save_context(void);
272 void dsi_restore_context(void);
274 int dsi_init_display(struct omap_dss_device *display);
275 void dsi_irq_handler(void);
276 unsigned long dsi_get_dsi1_pll_rate(void);
277 int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo);
278 int dsi_pll_calc_clock_div_pck(bool is_tft, unsigned long req_pck,
279 struct dsi_clock_info *cinfo,
280 struct dispc_clock_info *dispc_cinfo);
281 int dsi_pll_init(struct omap_dss_device *dssdev, bool enable_hsclk,
283 void dsi_pll_uninit(void);
284 void dsi_get_overlay_fifo_thresholds(enum omap_plane plane,
285 u32 fifo_size, enum omap_burst_size *burst_size,
286 u32 *fifo_low, u32 *fifo_high);
287 void dsi_wait_dsi1_pll_active(void);
288 void dsi_wait_dsi2_pll_active(void);
290 static inline int dsi_init_platform_driver(void)
294 static inline void dsi_uninit_platform_driver(void)
297 static inline void dsi_wait_dsi1_pll_active(void)
300 static inline void dsi_wait_dsi2_pll_active(void)
306 #ifdef CONFIG_OMAP2_DSS_DPI
307 int dpi_init(struct platform_device *pdev);
309 int dpi_init_display(struct omap_dss_device *dssdev);
311 static inline int dpi_init(struct platform_device *pdev)
315 static inline void dpi_exit(void)
321 int dispc_init_platform_driver(void);
322 void dispc_uninit_platform_driver(void);
323 void dispc_dump_clocks(struct seq_file *s);
324 void dispc_dump_irqs(struct seq_file *s);
325 void dispc_dump_regs(struct seq_file *s);
326 void dispc_irq_handler(void);
327 void dispc_fake_vsync_irq(void);
329 void dispc_save_context(void);
330 void dispc_restore_context(void);
332 void dispc_enable_sidle(void);
333 void dispc_disable_sidle(void);
335 void dispc_lcd_enable_signal_polarity(bool act_high);
336 void dispc_lcd_enable_signal(bool enable);
337 void dispc_pck_free_enable(bool enable);
338 void dispc_enable_fifohandcheck(enum omap_channel channel, bool enable);
340 void dispc_set_lcd_size(enum omap_channel channel, u16 width, u16 height);
341 void dispc_set_digit_size(u16 width, u16 height);
342 u32 dispc_get_plane_fifo_size(enum omap_plane plane);
343 void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high);
344 void dispc_enable_fifomerge(bool enable);
345 void dispc_set_burst_size(enum omap_plane plane,
346 enum omap_burst_size burst_size);
348 void dispc_set_plane_ba0(enum omap_plane plane, u32 paddr);
349 void dispc_set_plane_ba1(enum omap_plane plane, u32 paddr);
350 void dispc_set_plane_pos(enum omap_plane plane, u16 x, u16 y);
351 void dispc_set_plane_size(enum omap_plane plane, u16 width, u16 height);
352 void dispc_set_channel_out(enum omap_plane plane,
353 enum omap_channel channel_out);
355 int dispc_setup_plane(enum omap_plane plane,
356 u32 paddr, u16 screen_width,
357 u16 pos_x, u16 pos_y,
358 u16 width, u16 height,
359 u16 out_width, u16 out_height,
360 enum omap_color_mode color_mode,
362 enum omap_dss_rotation_type rotation_type,
363 u8 rotation, bool mirror,
364 u8 global_alpha, u8 pre_mult_alpha,
365 enum omap_channel channel);
367 bool dispc_go_busy(enum omap_channel channel);
368 void dispc_go(enum omap_channel channel);
369 void dispc_enable_channel(enum omap_channel channel, bool enable);
370 bool dispc_is_channel_enabled(enum omap_channel channel);
371 int dispc_enable_plane(enum omap_plane plane, bool enable);
372 void dispc_enable_replication(enum omap_plane plane, bool enable);
374 void dispc_set_parallel_interface_mode(enum omap_channel channel,
375 enum omap_parallel_interface_mode mode);
376 void dispc_set_tft_data_lines(enum omap_channel channel, u8 data_lines);
377 void dispc_set_lcd_display_type(enum omap_channel channel,
378 enum omap_lcd_display_type type);
379 void dispc_set_loadmode(enum omap_dss_load_mode mode);
381 void dispc_set_default_color(enum omap_channel channel, u32 color);
382 u32 dispc_get_default_color(enum omap_channel channel);
383 void dispc_set_trans_key(enum omap_channel ch,
384 enum omap_dss_trans_key_type type,
386 void dispc_get_trans_key(enum omap_channel ch,
387 enum omap_dss_trans_key_type *type,
389 void dispc_enable_trans_key(enum omap_channel ch, bool enable);
390 void dispc_enable_alpha_blending(enum omap_channel ch, bool enable);
391 bool dispc_trans_key_enabled(enum omap_channel ch);
392 bool dispc_alpha_blending_enabled(enum omap_channel ch);
394 bool dispc_lcd_timings_ok(struct omap_video_timings *timings);
395 void dispc_set_lcd_timings(enum omap_channel channel,
396 struct omap_video_timings *timings);
397 unsigned long dispc_fclk_rate(void);
398 unsigned long dispc_lclk_rate(enum omap_channel channel);
399 unsigned long dispc_pclk_rate(enum omap_channel channel);
400 void dispc_set_pol_freq(enum omap_channel channel,
401 enum omap_panel_config config, u8 acbi, u8 acb);
402 void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
403 struct dispc_clock_info *cinfo);
404 int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
405 struct dispc_clock_info *cinfo);
406 int dispc_set_clock_div(enum omap_channel channel,
407 struct dispc_clock_info *cinfo);
408 int dispc_get_clock_div(enum omap_channel channel,
409 struct dispc_clock_info *cinfo);
413 #ifdef CONFIG_OMAP2_DSS_VENC
414 int venc_init_platform_driver(void);
415 void venc_uninit_platform_driver(void);
416 void venc_dump_regs(struct seq_file *s);
417 int venc_init_display(struct omap_dss_device *display);
419 static inline int venc_init_platform_driver(void)
423 static inline void venc_uninit_platform_driver(void)
429 #ifdef CONFIG_OMAP2_DSS_RFBI
430 int rfbi_init_platform_driver(void);
431 void rfbi_uninit_platform_driver(void);
432 void rfbi_dump_regs(struct seq_file *s);
434 int rfbi_configure(int rfbi_module, int bpp, int lines);
435 void rfbi_enable_rfbi(bool enable);
436 void rfbi_transfer_area(struct omap_dss_device *dssdev, u16 width,
437 u16 height, void (callback)(void *data), void *data);
438 void rfbi_set_timings(int rfbi_module, struct rfbi_timings *t);
439 unsigned long rfbi_get_max_tx_rate(void);
440 int rfbi_init_display(struct omap_dss_device *display);
442 static inline int rfbi_init_platform_driver(void)
446 static inline void rfbi_uninit_platform_driver(void)
452 #ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
453 static inline void dss_collect_irq_stats(u32 irqstatus, unsigned *irq_arr)
456 for (b = 0; b < 32; ++b) {
457 if (irqstatus & (1 << b))