2 * linux/drivers/video/omap2/dss/sdi.c
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published by
9 * the Free Software Foundation.
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
20 #define DSS_SUBSYS_NAME "SDI"
22 #include <linux/kernel.h>
23 #include <linux/delay.h>
24 #include <linux/err.h>
25 #include <linux/regulator/consumer.h>
26 #include <linux/export.h>
27 #include <linux/platform_device.h>
28 #include <linux/string.h>
30 #include <video/omapdss.h>
34 struct platform_device *pdev;
37 struct regulator *vdds_sdi_reg;
39 struct dss_lcd_mgr_config mgr_config;
40 struct omap_video_timings timings;
43 struct omap_dss_device output;
46 struct sdi_clk_calc_ctx {
47 unsigned long pck_min, pck_max;
49 struct dss_clock_info dss_cinfo;
50 struct dispc_clock_info dispc_cinfo;
53 static bool dpi_calc_dispc_cb(int lckd, int pckd, unsigned long lck,
54 unsigned long pck, void *data)
56 struct sdi_clk_calc_ctx *ctx = data;
58 ctx->dispc_cinfo.lck_div = lckd;
59 ctx->dispc_cinfo.pck_div = pckd;
60 ctx->dispc_cinfo.lck = lck;
61 ctx->dispc_cinfo.pck = pck;
66 static bool dpi_calc_dss_cb(int fckd, unsigned long fck, void *data)
68 struct sdi_clk_calc_ctx *ctx = data;
70 ctx->dss_cinfo.fck = fck;
71 ctx->dss_cinfo.fck_div = fckd;
73 return dispc_div_calc(fck, ctx->pck_min, ctx->pck_max,
74 dpi_calc_dispc_cb, ctx);
77 static int sdi_calc_clock_div(unsigned long pclk,
78 struct dss_clock_info *dss_cinfo,
79 struct dispc_clock_info *dispc_cinfo)
82 struct sdi_clk_calc_ctx ctx;
85 * DSS fclk gives us very few possibilities, so finding a good pixel
86 * clock may not be possible. We try multiple times to find the clock,
87 * each time widening the pixel clock range we look for, up to
91 for (i = 0; i < 10; ++i) {
94 memset(&ctx, 0, sizeof(ctx));
95 if (pclk > 1000 * i * i * i)
96 ctx.pck_min = max(pclk - 1000 * i * i * i, 0lu);
99 ctx.pck_max = pclk + 1000 * i * i * i;
101 ok = dss_div_calc(ctx.pck_min, dpi_calc_dss_cb, &ctx);
103 *dss_cinfo = ctx.dss_cinfo;
104 *dispc_cinfo = ctx.dispc_cinfo;
112 static void sdi_config_lcd_manager(struct omap_dss_device *dssdev)
114 struct omap_overlay_manager *mgr = sdi.output.manager;
116 sdi.mgr_config.io_pad_mode = DSS_IO_PAD_MODE_BYPASS;
118 sdi.mgr_config.stallmode = false;
119 sdi.mgr_config.fifohandcheck = false;
121 sdi.mgr_config.video_port_width = 24;
122 sdi.mgr_config.lcden_sig_polarity = 1;
124 dss_mgr_set_lcd_config(mgr, &sdi.mgr_config);
127 int omapdss_sdi_display_enable(struct omap_dss_device *dssdev)
129 struct omap_dss_device *out = &sdi.output;
130 struct omap_video_timings *t = &sdi.timings;
131 struct dss_clock_info dss_cinfo;
132 struct dispc_clock_info dispc_cinfo;
136 if (out == NULL || out->manager == NULL) {
137 DSSERR("failed to enable display: no output/manager\n");
141 r = regulator_enable(sdi.vdds_sdi_reg);
145 r = dispc_runtime_get();
150 t->data_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
151 t->sync_pclk_edge = OMAPDSS_DRIVE_SIG_RISING_EDGE;
153 r = sdi_calc_clock_div(t->pixel_clock * 1000, &dss_cinfo, &dispc_cinfo);
155 goto err_calc_clock_div;
157 sdi.mgr_config.clock_info = dispc_cinfo;
159 pck = dss_cinfo.fck / dispc_cinfo.lck_div / dispc_cinfo.pck_div / 1000;
161 if (pck != t->pixel_clock) {
162 DSSWARN("Could not find exact pixel clock. Requested %d kHz, "
164 t->pixel_clock, pck);
166 t->pixel_clock = pck;
170 dss_mgr_set_timings(out->manager, t);
172 r = dss_set_clock_div(&dss_cinfo);
174 goto err_set_dss_clock_div;
176 sdi_config_lcd_manager(dssdev);
179 * LCLK and PCLK divisors are located in shadow registers, and we
180 * normally write them to DISPC registers when enabling the output.
181 * However, SDI uses pck-free as source clock for its PLL, and pck-free
182 * is affected by the divisors. And as we need the PLL before enabling
183 * the output, we need to write the divisors early.
185 * It seems just writing to the DISPC register is enough, and we don't
186 * need to care about the shadow register mechanism for pck-free. The
187 * exact reason for this is unknown.
189 dispc_mgr_set_clock_div(out->manager->id, &sdi.mgr_config.clock_info);
191 dss_sdi_init(sdi.datapairs);
192 r = dss_sdi_enable();
197 r = dss_mgr_enable(out->manager);
206 err_set_dss_clock_div:
210 regulator_disable(sdi.vdds_sdi_reg);
214 EXPORT_SYMBOL(omapdss_sdi_display_enable);
216 void omapdss_sdi_display_disable(struct omap_dss_device *dssdev)
218 struct omap_overlay_manager *mgr = sdi.output.manager;
220 dss_mgr_disable(mgr);
226 regulator_disable(sdi.vdds_sdi_reg);
228 EXPORT_SYMBOL(omapdss_sdi_display_disable);
230 void omapdss_sdi_set_timings(struct omap_dss_device *dssdev,
231 struct omap_video_timings *timings)
233 sdi.timings = *timings;
235 EXPORT_SYMBOL(omapdss_sdi_set_timings);
237 static void sdi_get_timings(struct omap_dss_device *dssdev,
238 struct omap_video_timings *timings)
240 *timings = sdi.timings;
243 static int sdi_check_timings(struct omap_dss_device *dssdev,
244 struct omap_video_timings *timings)
246 struct omap_overlay_manager *mgr = sdi.output.manager;
248 if (mgr && !dispc_mgr_timings_ok(mgr->id, timings))
251 if (timings->pixel_clock == 0)
257 void omapdss_sdi_set_datapairs(struct omap_dss_device *dssdev, int datapairs)
259 sdi.datapairs = datapairs;
261 EXPORT_SYMBOL(omapdss_sdi_set_datapairs);
263 static int sdi_init_regulator(void)
265 struct regulator *vdds_sdi;
267 if (sdi.vdds_sdi_reg)
270 vdds_sdi = dss_get_vdds_sdi();
272 if (IS_ERR(vdds_sdi)) {
273 vdds_sdi = devm_regulator_get(&sdi.pdev->dev, "vdds_sdi");
274 if (IS_ERR(vdds_sdi)) {
275 DSSERR("can't get VDDS_SDI regulator\n");
276 return PTR_ERR(vdds_sdi);
280 sdi.vdds_sdi_reg = vdds_sdi;
285 static struct omap_dss_device *sdi_find_dssdev(struct platform_device *pdev)
287 struct omap_dss_board_info *pdata = pdev->dev.platform_data;
288 const char *def_disp_name = omapdss_get_default_display_name();
289 struct omap_dss_device *def_dssdev;
294 for (i = 0; i < pdata->num_devices; ++i) {
295 struct omap_dss_device *dssdev = pdata->devices[i];
297 if (dssdev->type != OMAP_DISPLAY_TYPE_SDI)
300 if (def_dssdev == NULL)
303 if (def_disp_name != NULL &&
304 strcmp(dssdev->name, def_disp_name) == 0) {
313 static int sdi_probe_pdata(struct platform_device *sdidev)
315 struct omap_dss_device *plat_dssdev;
316 struct omap_dss_device *dssdev;
319 plat_dssdev = sdi_find_dssdev(sdidev);
324 dssdev = dss_alloc_and_init_device(&sdidev->dev);
328 dss_copy_device_pdata(dssdev, plat_dssdev);
330 r = sdi_init_regulator();
332 DSSERR("device %s init failed: %d\n", dssdev->name, r);
333 dss_put_device(dssdev);
337 r = omapdss_output_set_device(&sdi.output, dssdev);
339 DSSERR("failed to connect output to new device: %s\n",
341 dss_put_device(dssdev);
345 r = dss_add_device(dssdev);
347 DSSERR("device %s register failed: %d\n", dssdev->name, r);
348 omapdss_output_unset_device(&sdi.output);
349 dss_put_device(dssdev);
356 static int sdi_connect(struct omap_dss_device *dssdev,
357 struct omap_dss_device *dst)
359 struct omap_overlay_manager *mgr;
362 r = sdi_init_regulator();
366 mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel);
370 r = dss_mgr_connect(mgr, dssdev);
374 r = omapdss_output_set_device(dssdev, dst);
376 DSSERR("failed to connect output to new device: %s\n",
378 dss_mgr_disconnect(mgr, dssdev);
385 static void sdi_disconnect(struct omap_dss_device *dssdev,
386 struct omap_dss_device *dst)
388 WARN_ON(dst != dssdev->device);
390 if (dst != dssdev->device)
393 omapdss_output_unset_device(dssdev);
396 dss_mgr_disconnect(dssdev->manager, dssdev);
399 static const struct omapdss_sdi_ops sdi_ops = {
400 .connect = sdi_connect,
401 .disconnect = sdi_disconnect,
403 .enable = omapdss_sdi_display_enable,
404 .disable = omapdss_sdi_display_disable,
406 .check_timings = sdi_check_timings,
407 .set_timings = omapdss_sdi_set_timings,
408 .get_timings = sdi_get_timings,
410 .set_datapairs = omapdss_sdi_set_datapairs,
413 static void sdi_init_output(struct platform_device *pdev)
415 struct omap_dss_device *out = &sdi.output;
417 out->dev = &pdev->dev;
418 out->id = OMAP_DSS_OUTPUT_SDI;
419 out->output_type = OMAP_DISPLAY_TYPE_SDI;
421 out->dispc_channel = OMAP_DSS_CHANNEL_LCD;
422 out->ops.sdi = &sdi_ops;
423 out->owner = THIS_MODULE;
425 omapdss_register_output(out);
428 static void __exit sdi_uninit_output(struct platform_device *pdev)
430 struct omap_dss_device *out = &sdi.output;
432 omapdss_unregister_output(out);
435 static int omap_sdi_probe(struct platform_device *pdev)
441 sdi_init_output(pdev);
443 if (pdev->dev.platform_data) {
444 r = sdi_probe_pdata(pdev);
452 sdi_uninit_output(pdev);
456 static int __exit omap_sdi_remove(struct platform_device *pdev)
458 dss_unregister_child_devices(&pdev->dev);
460 sdi_uninit_output(pdev);
465 static struct platform_driver omap_sdi_driver = {
466 .probe = omap_sdi_probe,
467 .remove = __exit_p(omap_sdi_remove),
469 .name = "omapdss_sdi",
470 .owner = THIS_MODULE,
474 int __init sdi_init_platform_driver(void)
476 return platform_driver_register(&omap_sdi_driver);
479 void __exit sdi_uninit_platform_driver(void)
481 platform_driver_unregister(&omap_sdi_driver);