2 * linux/drivers/video/omap2/dss/venc.c
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
7 * VENC settings from TI's DSS driver
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published by
11 * the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18 * You should have received a copy of the GNU General Public License along with
19 * this program. If not, see <http://www.gnu.org/licenses/>.
22 #define DSS_SUBSYS_NAME "VENC"
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/clk.h>
27 #include <linux/err.h>
29 #include <linux/mutex.h>
30 #include <linux/completion.h>
31 #include <linux/delay.h>
32 #include <linux/string.h>
33 #include <linux/seq_file.h>
34 #include <linux/platform_device.h>
35 #include <linux/regulator/consumer.h>
36 #include <linux/pm_runtime.h>
38 #include <video/omapdss.h>
42 #include "dss_features.h"
45 #define VENC_REV_ID 0x00
46 #define VENC_STATUS 0x04
47 #define VENC_F_CONTROL 0x08
48 #define VENC_VIDOUT_CTRL 0x10
49 #define VENC_SYNC_CTRL 0x14
50 #define VENC_LLEN 0x1C
51 #define VENC_FLENS 0x20
52 #define VENC_HFLTR_CTRL 0x24
53 #define VENC_CC_CARR_WSS_CARR 0x28
54 #define VENC_C_PHASE 0x2C
55 #define VENC_GAIN_U 0x30
56 #define VENC_GAIN_V 0x34
57 #define VENC_GAIN_Y 0x38
58 #define VENC_BLACK_LEVEL 0x3C
59 #define VENC_BLANK_LEVEL 0x40
60 #define VENC_X_COLOR 0x44
61 #define VENC_M_CONTROL 0x48
62 #define VENC_BSTAMP_WSS_DATA 0x4C
63 #define VENC_S_CARR 0x50
64 #define VENC_LINE21 0x54
65 #define VENC_LN_SEL 0x58
66 #define VENC_L21__WC_CTL 0x5C
67 #define VENC_HTRIGGER_VTRIGGER 0x60
68 #define VENC_SAVID__EAVID 0x64
69 #define VENC_FLEN__FAL 0x68
70 #define VENC_LAL__PHASE_RESET 0x6C
71 #define VENC_HS_INT_START_STOP_X 0x70
72 #define VENC_HS_EXT_START_STOP_X 0x74
73 #define VENC_VS_INT_START_X 0x78
74 #define VENC_VS_INT_STOP_X__VS_INT_START_Y 0x7C
75 #define VENC_VS_INT_STOP_Y__VS_EXT_START_X 0x80
76 #define VENC_VS_EXT_STOP_X__VS_EXT_START_Y 0x84
77 #define VENC_VS_EXT_STOP_Y 0x88
78 #define VENC_AVID_START_STOP_X 0x90
79 #define VENC_AVID_START_STOP_Y 0x94
80 #define VENC_FID_INT_START_X__FID_INT_START_Y 0xA0
81 #define VENC_FID_INT_OFFSET_Y__FID_EXT_START_X 0xA4
82 #define VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y 0xA8
83 #define VENC_TVDETGP_INT_START_STOP_X 0xB0
84 #define VENC_TVDETGP_INT_START_STOP_Y 0xB4
85 #define VENC_GEN_CTRL 0xB8
86 #define VENC_OUTPUT_CONTROL 0xC4
87 #define VENC_OUTPUT_TEST 0xC8
88 #define VENC_DAC_B__DAC_C 0xC8
111 u32 htrigger_vtrigger;
114 u32 lal__phase_reset;
115 u32 hs_int_start_stop_x;
116 u32 hs_ext_start_stop_x;
118 u32 vs_int_stop_x__vs_int_start_y;
119 u32 vs_int_stop_y__vs_ext_start_x;
120 u32 vs_ext_stop_x__vs_ext_start_y;
122 u32 avid_start_stop_x;
123 u32 avid_start_stop_y;
124 u32 fid_int_start_x__fid_int_start_y;
125 u32 fid_int_offset_y__fid_ext_start_x;
126 u32 fid_ext_start_y__fid_ext_offset_y;
127 u32 tvdetgp_int_start_stop_x;
128 u32 tvdetgp_int_start_stop_y;
133 static const struct venc_config venc_config_pal_trm = {
137 .llen = 0x35F, /* 863 */
138 .flens = 0x270, /* 624 */
140 .cc_carr_wss_carr = 0x2F7225ED,
149 .bstamp_wss_data = 0x3F,
150 .s_carr = 0x2A098ACB,
152 .ln_sel = 0x01290015,
153 .l21__wc_ctl = 0x0000F603,
154 .htrigger_vtrigger = 0,
156 .savid__eavid = 0x06A70108,
157 .flen__fal = 0x00180270,
158 .lal__phase_reset = 0x00040135,
159 .hs_int_start_stop_x = 0x00880358,
160 .hs_ext_start_stop_x = 0x000F035F,
161 .vs_int_start_x = 0x01A70000,
162 .vs_int_stop_x__vs_int_start_y = 0x000001A7,
163 .vs_int_stop_y__vs_ext_start_x = 0x01AF0000,
164 .vs_ext_stop_x__vs_ext_start_y = 0x000101AF,
165 .vs_ext_stop_y = 0x00000025,
166 .avid_start_stop_x = 0x03530083,
167 .avid_start_stop_y = 0x026C002E,
168 .fid_int_start_x__fid_int_start_y = 0x0001008A,
169 .fid_int_offset_y__fid_ext_start_x = 0x002E0138,
170 .fid_ext_start_y__fid_ext_offset_y = 0x01380001,
172 .tvdetgp_int_start_stop_x = 0x00140001,
173 .tvdetgp_int_start_stop_y = 0x00010001,
174 .gen_ctrl = 0x00FF0000,
178 static const struct venc_config venc_config_ntsc_trm = {
185 .cc_carr_wss_carr = 0x043F2631,
194 .bstamp_wss_data = 0x38,
195 .s_carr = 0x21F07C1F,
197 .ln_sel = 0x01310011,
198 .l21__wc_ctl = 0x0000F003,
199 .htrigger_vtrigger = 0,
201 .savid__eavid = 0x069300F4,
202 .flen__fal = 0x0016020C,
203 .lal__phase_reset = 0x00060107,
204 .hs_int_start_stop_x = 0x008E0350,
205 .hs_ext_start_stop_x = 0x000F0359,
206 .vs_int_start_x = 0x01A00000,
207 .vs_int_stop_x__vs_int_start_y = 0x020701A0,
208 .vs_int_stop_y__vs_ext_start_x = 0x01AC0024,
209 .vs_ext_stop_x__vs_ext_start_y = 0x020D01AC,
210 .vs_ext_stop_y = 0x00000006,
211 .avid_start_stop_x = 0x03480078,
212 .avid_start_stop_y = 0x02060024,
213 .fid_int_start_x__fid_int_start_y = 0x0001008A,
214 .fid_int_offset_y__fid_ext_start_x = 0x01AC0106,
215 .fid_ext_start_y__fid_ext_offset_y = 0x01060006,
217 .tvdetgp_int_start_stop_x = 0x00140001,
218 .tvdetgp_int_start_stop_y = 0x00010001,
219 .gen_ctrl = 0x00F90000,
222 static const struct venc_config venc_config_pal_bdghi = {
230 .htrigger_vtrigger = 0,
231 .tvdetgp_int_start_stop_x = 0x00140001,
232 .tvdetgp_int_start_stop_y = 0x00010001,
233 .gen_ctrl = 0x00FB0000,
237 .cc_carr_wss_carr = 0x2F7625ED,
244 .m_control = 0<<2 | 1<<1,
245 .bstamp_wss_data = 0x42,
246 .s_carr = 0x2a098acb,
247 .l21__wc_ctl = 0<<13 | 0x16<<8 | 0<<0,
248 .savid__eavid = 0x06A70108,
249 .flen__fal = 23<<16 | 624<<0,
250 .lal__phase_reset = 2<<17 | 310<<0,
251 .hs_int_start_stop_x = 0x00920358,
252 .hs_ext_start_stop_x = 0x000F035F,
253 .vs_int_start_x = 0x1a7<<16,
254 .vs_int_stop_x__vs_int_start_y = 0x000601A7,
255 .vs_int_stop_y__vs_ext_start_x = 0x01AF0036,
256 .vs_ext_stop_x__vs_ext_start_y = 0x27101af,
257 .vs_ext_stop_y = 0x05,
258 .avid_start_stop_x = 0x03530082,
259 .avid_start_stop_y = 0x0270002E,
260 .fid_int_start_x__fid_int_start_y = 0x0005008A,
261 .fid_int_offset_y__fid_ext_start_x = 0x002E0138,
262 .fid_ext_start_y__fid_ext_offset_y = 0x01380005,
265 const struct omap_video_timings omap_dss_pal_timings = {
268 .pixel_clock = 13500,
276 EXPORT_SYMBOL(omap_dss_pal_timings);
278 const struct omap_video_timings omap_dss_ntsc_timings = {
281 .pixel_clock = 13500,
289 EXPORT_SYMBOL(omap_dss_ntsc_timings);
292 struct platform_device *pdev;
294 struct mutex venc_lock;
296 struct regulator *vdda_dac_reg;
298 struct clk *tv_dac_clk;
301 static inline void venc_write_reg(int idx, u32 val)
303 __raw_writel(val, venc.base + idx);
306 static inline u32 venc_read_reg(int idx)
308 u32 l = __raw_readl(venc.base + idx);
312 static void venc_write_config(const struct venc_config *config)
314 DSSDBG("write venc conf\n");
316 venc_write_reg(VENC_LLEN, config->llen);
317 venc_write_reg(VENC_FLENS, config->flens);
318 venc_write_reg(VENC_CC_CARR_WSS_CARR, config->cc_carr_wss_carr);
319 venc_write_reg(VENC_C_PHASE, config->c_phase);
320 venc_write_reg(VENC_GAIN_U, config->gain_u);
321 venc_write_reg(VENC_GAIN_V, config->gain_v);
322 venc_write_reg(VENC_GAIN_Y, config->gain_y);
323 venc_write_reg(VENC_BLACK_LEVEL, config->black_level);
324 venc_write_reg(VENC_BLANK_LEVEL, config->blank_level);
325 venc_write_reg(VENC_M_CONTROL, config->m_control);
326 venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data |
328 venc_write_reg(VENC_S_CARR, config->s_carr);
329 venc_write_reg(VENC_L21__WC_CTL, config->l21__wc_ctl);
330 venc_write_reg(VENC_SAVID__EAVID, config->savid__eavid);
331 venc_write_reg(VENC_FLEN__FAL, config->flen__fal);
332 venc_write_reg(VENC_LAL__PHASE_RESET, config->lal__phase_reset);
333 venc_write_reg(VENC_HS_INT_START_STOP_X, config->hs_int_start_stop_x);
334 venc_write_reg(VENC_HS_EXT_START_STOP_X, config->hs_ext_start_stop_x);
335 venc_write_reg(VENC_VS_INT_START_X, config->vs_int_start_x);
336 venc_write_reg(VENC_VS_INT_STOP_X__VS_INT_START_Y,
337 config->vs_int_stop_x__vs_int_start_y);
338 venc_write_reg(VENC_VS_INT_STOP_Y__VS_EXT_START_X,
339 config->vs_int_stop_y__vs_ext_start_x);
340 venc_write_reg(VENC_VS_EXT_STOP_X__VS_EXT_START_Y,
341 config->vs_ext_stop_x__vs_ext_start_y);
342 venc_write_reg(VENC_VS_EXT_STOP_Y, config->vs_ext_stop_y);
343 venc_write_reg(VENC_AVID_START_STOP_X, config->avid_start_stop_x);
344 venc_write_reg(VENC_AVID_START_STOP_Y, config->avid_start_stop_y);
345 venc_write_reg(VENC_FID_INT_START_X__FID_INT_START_Y,
346 config->fid_int_start_x__fid_int_start_y);
347 venc_write_reg(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X,
348 config->fid_int_offset_y__fid_ext_start_x);
349 venc_write_reg(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y,
350 config->fid_ext_start_y__fid_ext_offset_y);
352 venc_write_reg(VENC_DAC_B__DAC_C, venc_read_reg(VENC_DAC_B__DAC_C));
353 venc_write_reg(VENC_VIDOUT_CTRL, config->vidout_ctrl);
354 venc_write_reg(VENC_HFLTR_CTRL, config->hfltr_ctrl);
355 venc_write_reg(VENC_X_COLOR, config->x_color);
356 venc_write_reg(VENC_LINE21, config->line21);
357 venc_write_reg(VENC_LN_SEL, config->ln_sel);
358 venc_write_reg(VENC_HTRIGGER_VTRIGGER, config->htrigger_vtrigger);
359 venc_write_reg(VENC_TVDETGP_INT_START_STOP_X,
360 config->tvdetgp_int_start_stop_x);
361 venc_write_reg(VENC_TVDETGP_INT_START_STOP_Y,
362 config->tvdetgp_int_start_stop_y);
363 venc_write_reg(VENC_GEN_CTRL, config->gen_ctrl);
364 venc_write_reg(VENC_F_CONTROL, config->f_control);
365 venc_write_reg(VENC_SYNC_CTRL, config->sync_ctrl);
368 static void venc_reset(void)
372 venc_write_reg(VENC_F_CONTROL, 1<<8);
373 while (venc_read_reg(VENC_F_CONTROL) & (1<<8)) {
375 DSSERR("Failed to reset venc\n");
380 #ifdef CONFIG_OMAP2_DSS_SLEEP_AFTER_VENC_RESET
381 /* the magical sleep that makes things work */
382 /* XXX more info? What bug this circumvents? */
387 static int venc_runtime_get(void)
391 DSSDBG("venc_runtime_get\n");
393 r = pm_runtime_get_sync(&venc.pdev->dev);
395 return r < 0 ? r : 0;
398 static void venc_runtime_put(void)
402 DSSDBG("venc_runtime_put\n");
404 r = pm_runtime_put_sync(&venc.pdev->dev);
408 static const struct venc_config *venc_timings_to_config(
409 struct omap_video_timings *timings)
411 if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0)
412 return &venc_config_pal_trm;
414 if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0)
415 return &venc_config_ntsc_trm;
420 static int venc_power_on(struct omap_dss_device *dssdev)
424 struct omap_video_timings timings;
427 venc_write_config(venc_timings_to_config(&dssdev->panel.timings));
429 dss_set_venc_output(dssdev->phy.venc.type);
430 dss_set_dac_pwrdn_bgz(1);
434 if (dssdev->phy.venc.type == OMAP_DSS_VENC_TYPE_COMPOSITE)
437 l |= (1 << 0) | (1 << 2);
439 if (dssdev->phy.venc.invert_polarity == false)
442 venc_write_reg(VENC_OUTPUT_CONTROL, l);
444 timings = dssdev->panel.timings;
447 dss_mgr_set_timings(dssdev->manager, &timings);
449 r = regulator_enable(venc.vdda_dac_reg);
453 if (dssdev->platform_enable)
454 dssdev->platform_enable(dssdev);
456 r = dss_mgr_enable(dssdev->manager);
463 venc_write_reg(VENC_OUTPUT_CONTROL, 0);
464 dss_set_dac_pwrdn_bgz(0);
466 if (dssdev->platform_disable)
467 dssdev->platform_disable(dssdev);
469 regulator_disable(venc.vdda_dac_reg);
474 static void venc_power_off(struct omap_dss_device *dssdev)
476 venc_write_reg(VENC_OUTPUT_CONTROL, 0);
477 dss_set_dac_pwrdn_bgz(0);
479 dss_mgr_disable(dssdev->manager);
481 if (dssdev->platform_disable)
482 dssdev->platform_disable(dssdev);
484 regulator_disable(venc.vdda_dac_reg);
487 unsigned long venc_get_pixel_clock(void)
489 /* VENC Pixel Clock in Mhz */
493 static ssize_t display_output_type_show(struct device *dev,
494 struct device_attribute *attr, char *buf)
496 struct omap_dss_device *dssdev = to_dss_device(dev);
499 switch (dssdev->phy.venc.type) {
500 case OMAP_DSS_VENC_TYPE_COMPOSITE:
503 case OMAP_DSS_VENC_TYPE_SVIDEO:
510 return snprintf(buf, PAGE_SIZE, "%s\n", ret);
513 static ssize_t display_output_type_store(struct device *dev,
514 struct device_attribute *attr, const char *buf, size_t size)
516 struct omap_dss_device *dssdev = to_dss_device(dev);
517 enum omap_dss_venc_type new_type;
519 if (sysfs_streq("composite", buf))
520 new_type = OMAP_DSS_VENC_TYPE_COMPOSITE;
521 else if (sysfs_streq("svideo", buf))
522 new_type = OMAP_DSS_VENC_TYPE_SVIDEO;
526 mutex_lock(&venc.venc_lock);
528 if (dssdev->phy.venc.type != new_type) {
529 dssdev->phy.venc.type = new_type;
530 if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) {
531 venc_power_off(dssdev);
532 venc_power_on(dssdev);
536 mutex_unlock(&venc.venc_lock);
541 static DEVICE_ATTR(output_type, S_IRUGO | S_IWUSR,
542 display_output_type_show, display_output_type_store);
545 static int venc_panel_probe(struct omap_dss_device *dssdev)
547 dssdev->panel.timings = omap_dss_pal_timings;
549 return device_create_file(&dssdev->dev, &dev_attr_output_type);
552 static void venc_panel_remove(struct omap_dss_device *dssdev)
554 device_remove_file(&dssdev->dev, &dev_attr_output_type);
557 static int venc_panel_enable(struct omap_dss_device *dssdev)
561 DSSDBG("venc_enable_display\n");
563 mutex_lock(&venc.venc_lock);
565 r = omap_dss_start_device(dssdev);
567 DSSERR("failed to start device\n");
571 if (dssdev->state != OMAP_DSS_DISPLAY_DISABLED) {
576 r = venc_runtime_get();
580 r = venc_power_on(dssdev);
586 dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
588 mutex_unlock(&venc.venc_lock);
593 omap_dss_stop_device(dssdev);
595 mutex_unlock(&venc.venc_lock);
600 static void venc_panel_disable(struct omap_dss_device *dssdev)
602 DSSDBG("venc_disable_display\n");
604 mutex_lock(&venc.venc_lock);
606 if (dssdev->state == OMAP_DSS_DISPLAY_DISABLED)
609 if (dssdev->state == OMAP_DSS_DISPLAY_SUSPENDED) {
610 /* suspended is the same as disabled with venc */
611 dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
615 venc_power_off(dssdev);
619 dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
621 omap_dss_stop_device(dssdev);
623 mutex_unlock(&venc.venc_lock);
626 static int venc_panel_suspend(struct omap_dss_device *dssdev)
628 venc_panel_disable(dssdev);
632 static int venc_panel_resume(struct omap_dss_device *dssdev)
634 return venc_panel_enable(dssdev);
637 static void venc_set_timings(struct omap_dss_device *dssdev,
638 struct omap_video_timings *timings)
640 DSSDBG("venc_set_timings\n");
642 /* Reset WSS data when the TV standard changes. */
643 if (memcmp(&dssdev->panel.timings, timings, sizeof(*timings)))
646 dssdev->panel.timings = *timings;
647 if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) {
648 /* turn the venc off and on to get new timings to use */
649 venc_panel_disable(dssdev);
650 venc_panel_enable(dssdev);
654 static int venc_check_timings(struct omap_dss_device *dssdev,
655 struct omap_video_timings *timings)
657 DSSDBG("venc_check_timings\n");
659 if (memcmp(&omap_dss_pal_timings, timings, sizeof(*timings)) == 0)
662 if (memcmp(&omap_dss_ntsc_timings, timings, sizeof(*timings)) == 0)
668 static u32 venc_get_wss(struct omap_dss_device *dssdev)
670 /* Invert due to VENC_L21_WC_CTL:INV=1 */
671 return (venc.wss_data >> 8) ^ 0xfffff;
674 static int venc_set_wss(struct omap_dss_device *dssdev, u32 wss)
676 const struct venc_config *config;
679 DSSDBG("venc_set_wss\n");
681 mutex_lock(&venc.venc_lock);
683 config = venc_timings_to_config(&dssdev->panel.timings);
685 /* Invert due to VENC_L21_WC_CTL:INV=1 */
686 venc.wss_data = (wss ^ 0xfffff) << 8;
688 r = venc_runtime_get();
692 venc_write_reg(VENC_BSTAMP_WSS_DATA, config->bstamp_wss_data |
698 mutex_unlock(&venc.venc_lock);
703 static struct omap_dss_driver venc_driver = {
704 .probe = venc_panel_probe,
705 .remove = venc_panel_remove,
707 .enable = venc_panel_enable,
708 .disable = venc_panel_disable,
709 .suspend = venc_panel_suspend,
710 .resume = venc_panel_resume,
712 .get_resolution = omapdss_default_get_resolution,
713 .get_recommended_bpp = omapdss_default_get_recommended_bpp,
715 .set_timings = venc_set_timings,
716 .check_timings = venc_check_timings,
718 .get_wss = venc_get_wss,
719 .set_wss = venc_set_wss,
723 .owner = THIS_MODULE,
728 int venc_init_display(struct omap_dss_device *dssdev)
730 DSSDBG("init_display\n");
732 if (venc.vdda_dac_reg == NULL) {
733 struct regulator *vdda_dac;
735 vdda_dac = regulator_get(&venc.pdev->dev, "vdda_dac");
737 if (IS_ERR(vdda_dac)) {
738 DSSERR("can't get VDDA_DAC regulator\n");
739 return PTR_ERR(vdda_dac);
742 venc.vdda_dac_reg = vdda_dac;
748 void venc_dump_regs(struct seq_file *s)
750 #define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, venc_read_reg(r))
752 if (cpu_is_omap44xx()) {
753 seq_printf(s, "VENC currently disabled on OMAP44xx\n");
757 if (venc_runtime_get())
760 DUMPREG(VENC_F_CONTROL);
761 DUMPREG(VENC_VIDOUT_CTRL);
762 DUMPREG(VENC_SYNC_CTRL);
765 DUMPREG(VENC_HFLTR_CTRL);
766 DUMPREG(VENC_CC_CARR_WSS_CARR);
767 DUMPREG(VENC_C_PHASE);
768 DUMPREG(VENC_GAIN_U);
769 DUMPREG(VENC_GAIN_V);
770 DUMPREG(VENC_GAIN_Y);
771 DUMPREG(VENC_BLACK_LEVEL);
772 DUMPREG(VENC_BLANK_LEVEL);
773 DUMPREG(VENC_X_COLOR);
774 DUMPREG(VENC_M_CONTROL);
775 DUMPREG(VENC_BSTAMP_WSS_DATA);
776 DUMPREG(VENC_S_CARR);
777 DUMPREG(VENC_LINE21);
778 DUMPREG(VENC_LN_SEL);
779 DUMPREG(VENC_L21__WC_CTL);
780 DUMPREG(VENC_HTRIGGER_VTRIGGER);
781 DUMPREG(VENC_SAVID__EAVID);
782 DUMPREG(VENC_FLEN__FAL);
783 DUMPREG(VENC_LAL__PHASE_RESET);
784 DUMPREG(VENC_HS_INT_START_STOP_X);
785 DUMPREG(VENC_HS_EXT_START_STOP_X);
786 DUMPREG(VENC_VS_INT_START_X);
787 DUMPREG(VENC_VS_INT_STOP_X__VS_INT_START_Y);
788 DUMPREG(VENC_VS_INT_STOP_Y__VS_EXT_START_X);
789 DUMPREG(VENC_VS_EXT_STOP_X__VS_EXT_START_Y);
790 DUMPREG(VENC_VS_EXT_STOP_Y);
791 DUMPREG(VENC_AVID_START_STOP_X);
792 DUMPREG(VENC_AVID_START_STOP_Y);
793 DUMPREG(VENC_FID_INT_START_X__FID_INT_START_Y);
794 DUMPREG(VENC_FID_INT_OFFSET_Y__FID_EXT_START_X);
795 DUMPREG(VENC_FID_EXT_START_Y__FID_EXT_OFFSET_Y);
796 DUMPREG(VENC_TVDETGP_INT_START_STOP_X);
797 DUMPREG(VENC_TVDETGP_INT_START_STOP_Y);
798 DUMPREG(VENC_GEN_CTRL);
799 DUMPREG(VENC_OUTPUT_CONTROL);
800 DUMPREG(VENC_OUTPUT_TEST);
807 static int venc_get_clocks(struct platform_device *pdev)
811 if (dss_has_feature(FEAT_VENC_REQUIRES_TV_DAC_CLK)) {
812 clk = clk_get(&pdev->dev, "tv_dac_clk");
814 DSSERR("can't get tv_dac_clk\n");
821 venc.tv_dac_clk = clk;
826 static void venc_put_clocks(void)
829 clk_put(venc.tv_dac_clk);
832 /* VENC HW IP initialisation */
833 static int omap_venchw_probe(struct platform_device *pdev)
836 struct resource *venc_mem;
841 mutex_init(&venc.venc_lock);
845 venc_mem = platform_get_resource(venc.pdev, IORESOURCE_MEM, 0);
847 DSSERR("can't get IORESOURCE_MEM VENC\n");
851 venc.base = devm_ioremap(&pdev->dev, venc_mem->start,
852 resource_size(venc_mem));
854 DSSERR("can't ioremap VENC\n");
858 r = venc_get_clocks(pdev);
862 pm_runtime_enable(&pdev->dev);
864 r = venc_runtime_get();
866 goto err_runtime_get;
868 rev_id = (u8)(venc_read_reg(VENC_REV_ID) & 0xff);
869 dev_dbg(&pdev->dev, "OMAP VENC rev %d\n", rev_id);
873 r = omap_dss_register_driver(&venc_driver);
875 goto err_reg_panel_driver;
879 err_reg_panel_driver:
881 pm_runtime_disable(&pdev->dev);
886 static int omap_venchw_remove(struct platform_device *pdev)
888 if (venc.vdda_dac_reg != NULL) {
889 regulator_put(venc.vdda_dac_reg);
890 venc.vdda_dac_reg = NULL;
892 omap_dss_unregister_driver(&venc_driver);
894 pm_runtime_disable(&pdev->dev);
900 static int venc_runtime_suspend(struct device *dev)
903 clk_disable(venc.tv_dac_clk);
911 static int venc_runtime_resume(struct device *dev)
915 r = dss_runtime_get();
919 r = dispc_runtime_get();
924 clk_enable(venc.tv_dac_clk);
934 static const struct dev_pm_ops venc_pm_ops = {
935 .runtime_suspend = venc_runtime_suspend,
936 .runtime_resume = venc_runtime_resume,
939 static struct platform_driver omap_venchw_driver = {
940 .probe = omap_venchw_probe,
941 .remove = omap_venchw_remove,
943 .name = "omapdss_venc",
944 .owner = THIS_MODULE,
949 int venc_init_platform_driver(void)
951 if (cpu_is_omap44xx())
954 return platform_driver_register(&omap_venchw_driver);
957 void venc_uninit_platform_driver(void)
959 if (cpu_is_omap44xx())
962 platform_driver_unregister(&omap_venchw_driver);