2 * linux/drivers/video/riva/fbdev.c - nVidia RIVA 128/TNT/TNT2 fb driver
4 * Maintained by Ani Joshi <ajoshi@shell.unixbox.com>
6 * Copyright 1999-2000 Jeff Garzik
10 * Ani Joshi: Lots of debugging and cleanup work, really helped
11 * get the driver going
13 * Ferenc Bakonyi: Bug fixes, cleanup, modularization
15 * Jindrich Makovicka: Accel code help, hw cursor, mtrr
17 * Paul Richards: Bug fixes, updates
19 * Initial template from skeletonfb.c, created 28 Dec 1997 by Geert Uytterhoeven
20 * Includes riva_hw.c from nVidia, see copyright below.
21 * KGI code provided the basis for state storage, init, and mode switching.
23 * This file is subject to the terms and conditions of the GNU General Public
24 * License. See the file COPYING in the main directory of this archive
27 * Known bugs and issues:
28 * restoring text mode fails
29 * doublescan modes are broken
32 #include <linux/module.h>
33 #include <linux/kernel.h>
34 #include <linux/errno.h>
35 #include <linux/string.h>
37 #include <linux/slab.h>
38 #include <linux/delay.h>
40 #include <linux/init.h>
41 #include <linux/pci.h>
42 #include <linux/backlight.h>
43 #include <linux/bitrev.h>
49 #include <asm/pci-bridge.h>
51 #ifdef CONFIG_PMAC_BACKLIGHT
52 #include <asm/machdep.h>
53 #include <asm/backlight.h>
59 #ifndef CONFIG_PCI /* sanity check */
60 #error This driver requires PCI support.
63 /* version number of this driver */
64 #define RIVAFB_VERSION "0.9.5b"
66 /* ------------------------------------------------------------------------- *
68 * various helpful macros and constants
70 * ------------------------------------------------------------------------- */
71 #ifdef CONFIG_FB_RIVA_DEBUG
72 #define NVTRACE printk
74 #define NVTRACE if(0) printk
77 #define NVTRACE_ENTER(...) NVTRACE("%s START\n", __FUNCTION__)
78 #define NVTRACE_LEAVE(...) NVTRACE("%s END\n", __FUNCTION__)
80 #ifdef CONFIG_FB_RIVA_DEBUG
81 #define assert(expr) \
83 printk( "Assertion failed! %s,%s,%s,line=%d\n",\
84 #expr,__FILE__,__FUNCTION__,__LINE__); \
91 #define PFX "rivafb: "
93 /* macro that allows you to set overflow bits */
94 #define SetBitField(value,from,to) SetBF(to,GetBF(value,from))
95 #define SetBit(n) (1<<(n))
96 #define Set8Bits(value) ((value)&0xff)
98 /* HW cursor parameters */
101 /* ------------------------------------------------------------------------- *
105 * ------------------------------------------------------------------------- */
107 static int rivafb_blank(int blank, struct fb_info *info);
109 /* ------------------------------------------------------------------------- *
111 * card identification
113 * ------------------------------------------------------------------------- */
115 static struct pci_device_id rivafb_pci_tbl[] = {
116 { PCI_VENDOR_ID_NVIDIA_SGS, PCI_DEVICE_ID_NVIDIA_SGS_RIVA128,
117 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
118 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT,
119 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
120 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_TNT2,
121 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
122 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UTNT2,
123 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
124 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_VTNT2,
125 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
126 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_UVTNT2,
127 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
128 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_ITNT2,
129 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
130 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR,
131 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
132 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR,
133 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
134 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO,
135 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
136 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX,
137 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
138 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2,
139 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
140 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO,
141 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
142 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR,
143 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
144 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS,
145 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
146 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2,
147 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
148 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA,
149 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
150 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO,
151 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
152 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460,
153 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
154 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440,
155 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
156 // NF2/IGP version, GeForce 4 MX, NV18
157 { PCI_VENDOR_ID_NVIDIA, 0x01f0,
158 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
159 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420,
160 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
161 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO,
162 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
163 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO,
164 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
165 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32,
166 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
167 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL,
168 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
169 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64,
170 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
171 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_200,
172 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
173 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL,
174 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
175 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL,
176 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
177 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_IGEFORCE2,
178 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
179 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3,
180 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
181 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_1,
182 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
183 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE3_2,
184 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
185 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO_DDC,
186 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
187 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600,
188 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
189 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400,
190 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
191 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200,
192 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
193 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL,
194 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
195 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL,
196 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
197 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL,
198 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
199 { PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO_5200,
200 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
201 { 0, } /* terminate list */
203 MODULE_DEVICE_TABLE(pci, rivafb_pci_tbl);
205 /* ------------------------------------------------------------------------- *
209 * ------------------------------------------------------------------------- */
211 /* command line data, set in rivafb_setup() */
212 static int flatpanel __devinitdata = -1; /* Autodetect later */
213 static int forceCRTC __devinitdata = -1;
214 static int noaccel __devinitdata = 0;
216 static int nomtrr __devinitdata = 0;
219 static char *mode_option __devinitdata = NULL;
220 static int strictmode = 0;
222 static struct fb_fix_screeninfo __devinitdata rivafb_fix = {
223 .type = FB_TYPE_PACKED_PIXELS,
228 static struct fb_var_screeninfo __devinitdata rivafb_default_var = {
238 .activate = FB_ACTIVATE_NOW,
248 .vmode = FB_VMODE_NONINTERLACED
252 static const struct riva_regs reg_template = {
253 {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* ATTR */
254 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
255 0x41, 0x01, 0x0F, 0x00, 0x00},
256 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* CRT */
257 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00,
258 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE3, /* 0x10 */
259 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
260 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x20 */
261 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
262 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 0x30 */
263 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
266 {0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0F, /* GRA */
268 {0x03, 0x01, 0x0F, 0x00, 0x0E}, /* SEQ */
275 #ifdef CONFIG_FB_RIVA_BACKLIGHT
276 /* We do not have any information about which values are allowed, thus
277 * we used safe values.
279 #define MIN_LEVEL 0x158
280 #define MAX_LEVEL 0x534
281 #define LEVEL_STEP ((MAX_LEVEL - MIN_LEVEL) / FB_BACKLIGHT_MAX)
283 static struct backlight_properties riva_bl_data;
285 /* Call with fb_info->bl_mutex held */
286 static int riva_bl_get_level_brightness(struct riva_par *par,
289 struct fb_info *info = pci_get_drvdata(par->pdev);
292 /* Get and convert the value */
293 nlevel = MIN_LEVEL + info->bl_curve[level] * LEVEL_STEP;
297 else if (nlevel < MIN_LEVEL)
299 else if (nlevel > MAX_LEVEL)
305 /* Call with fb_info->bl_mutex held */
306 static int __riva_bl_update_status(struct backlight_device *bd)
308 struct riva_par *par = class_get_devdata(&bd->class_dev);
309 U032 tmp_pcrt, tmp_pmc;
312 if (bd->props->power != FB_BLANK_UNBLANK ||
313 bd->props->fb_blank != FB_BLANK_UNBLANK)
316 level = bd->props->brightness;
318 tmp_pmc = par->riva.PMC[0x10F0/4] & 0x0000FFFF;
319 tmp_pcrt = par->riva.PCRTC0[0x081C/4] & 0xFFFFFFFC;
322 tmp_pmc |= (1 << 31); /* backlight bit */
323 tmp_pmc |= riva_bl_get_level_brightness(par, level) << 16; /* level */
325 par->riva.PCRTC0[0x081C/4] = tmp_pcrt;
326 par->riva.PMC[0x10F0/4] = tmp_pmc;
331 static int riva_bl_update_status(struct backlight_device *bd)
333 struct riva_par *par = class_get_devdata(&bd->class_dev);
334 struct fb_info *info = pci_get_drvdata(par->pdev);
337 mutex_lock(&info->bl_mutex);
338 ret = __riva_bl_update_status(bd);
339 mutex_unlock(&info->bl_mutex);
344 static int riva_bl_get_brightness(struct backlight_device *bd)
346 return bd->props->brightness;
349 static struct backlight_properties riva_bl_data = {
350 .get_brightness = riva_bl_get_brightness,
351 .update_status = riva_bl_update_status,
352 .max_brightness = (FB_BACKLIGHT_LEVELS - 1),
355 static void riva_bl_init(struct riva_par *par)
357 struct fb_info *info = pci_get_drvdata(par->pdev);
358 struct backlight_device *bd;
364 #ifdef CONFIG_PMAC_BACKLIGHT
365 if (!machine_is(powermac) ||
366 !pmac_has_backlight_type("mnca"))
370 snprintf(name, sizeof(name), "rivabl%d", info->node);
372 bd = backlight_device_register(name, info->dev, par, &riva_bl_data);
375 printk(KERN_WARNING "riva: Backlight registration failed\n");
379 mutex_lock(&info->bl_mutex);
381 fb_bl_default_curve(info, 0,
382 MIN_LEVEL * FB_BACKLIGHT_MAX / MAX_LEVEL,
384 mutex_unlock(&info->bl_mutex);
386 bd->props->brightness = riva_bl_data.max_brightness;
387 bd->props->power = FB_BLANK_UNBLANK;
388 backlight_update_status(bd);
390 #ifdef CONFIG_PMAC_BACKLIGHT
391 mutex_lock(&pmac_backlight_mutex);
394 mutex_unlock(&pmac_backlight_mutex);
397 printk("riva: Backlight initialized (%s)\n", name);
405 static void riva_bl_exit(struct riva_par *par)
407 struct fb_info *info = pci_get_drvdata(par->pdev);
409 #ifdef CONFIG_PMAC_BACKLIGHT
410 mutex_lock(&pmac_backlight_mutex);
413 mutex_lock(&info->bl_mutex);
415 #ifdef CONFIG_PMAC_BACKLIGHT
416 if (pmac_backlight == info->bl_dev)
417 pmac_backlight = NULL;
420 backlight_device_unregister(info->bl_dev);
422 printk("riva: Backlight unloaded\n");
424 mutex_unlock(&info->bl_mutex);
426 #ifdef CONFIG_PMAC_BACKLIGHT
427 mutex_unlock(&pmac_backlight_mutex);
431 static inline void riva_bl_init(struct riva_par *par) {}
432 static inline void riva_bl_exit(struct riva_par *par) {}
433 #endif /* CONFIG_FB_RIVA_BACKLIGHT */
435 /* ------------------------------------------------------------------------- *
439 * ------------------------------------------------------------------------- */
441 static inline void CRTCout(struct riva_par *par, unsigned char index,
444 VGA_WR08(par->riva.PCIO, 0x3d4, index);
445 VGA_WR08(par->riva.PCIO, 0x3d5, val);
448 static inline unsigned char CRTCin(struct riva_par *par,
451 VGA_WR08(par->riva.PCIO, 0x3d4, index);
452 return (VGA_RD08(par->riva.PCIO, 0x3d5));
455 static inline void GRAout(struct riva_par *par, unsigned char index,
458 VGA_WR08(par->riva.PVIO, 0x3ce, index);
459 VGA_WR08(par->riva.PVIO, 0x3cf, val);
462 static inline unsigned char GRAin(struct riva_par *par,
465 VGA_WR08(par->riva.PVIO, 0x3ce, index);
466 return (VGA_RD08(par->riva.PVIO, 0x3cf));
469 static inline void SEQout(struct riva_par *par, unsigned char index,
472 VGA_WR08(par->riva.PVIO, 0x3c4, index);
473 VGA_WR08(par->riva.PVIO, 0x3c5, val);
476 static inline unsigned char SEQin(struct riva_par *par,
479 VGA_WR08(par->riva.PVIO, 0x3c4, index);
480 return (VGA_RD08(par->riva.PVIO, 0x3c5));
483 static inline void ATTRout(struct riva_par *par, unsigned char index,
486 VGA_WR08(par->riva.PCIO, 0x3c0, index);
487 VGA_WR08(par->riva.PCIO, 0x3c0, val);
490 static inline unsigned char ATTRin(struct riva_par *par,
493 VGA_WR08(par->riva.PCIO, 0x3c0, index);
494 return (VGA_RD08(par->riva.PCIO, 0x3c1));
497 static inline void MISCout(struct riva_par *par, unsigned char val)
499 VGA_WR08(par->riva.PVIO, 0x3c2, val);
502 static inline unsigned char MISCin(struct riva_par *par)
504 return (VGA_RD08(par->riva.PVIO, 0x3cc));
507 static inline void reverse_order(u32 *l)
510 a[0] = bitrev8(a[0]);
511 a[1] = bitrev8(a[1]);
512 a[2] = bitrev8(a[2]);
513 a[3] = bitrev8(a[3]);
516 /* ------------------------------------------------------------------------- *
520 * ------------------------------------------------------------------------- */
523 * rivafb_load_cursor_image - load cursor image to hardware
524 * @data: address to monochrome bitmap (1 = foreground color, 0 = background)
525 * @par: pointer to private data
526 * @w: width of cursor image in pixels
527 * @h: height of cursor image in scanlines
528 * @bg: background color (ARGB1555) - alpha bit determines opacity
529 * @fg: foreground color (ARGB1555)
532 * Loads cursor image based on a monochrome source and mask bitmap. The
533 * image bits determines the color of the pixel, 0 for background, 1 for
534 * foreground. Only the affected region (as determined by @w and @h
535 * parameters) will be updated.
540 static void rivafb_load_cursor_image(struct riva_par *par, u8 *data8,
541 u16 bg, u16 fg, u32 w, u32 h)
545 u32 *data = (u32 *)data8;
546 bg = le16_to_cpu(bg);
547 fg = le16_to_cpu(fg);
551 for (i = 0; i < h; i++) {
555 for (j = 0; j < w/2; j++) {
557 #if defined (__BIG_ENDIAN)
558 tmp = (b & (1 << 31)) ? fg << 16 : bg << 16;
560 tmp |= (b & (1 << 31)) ? fg : bg;
563 tmp = (b & 1) ? fg : bg;
565 tmp |= (b & 1) ? fg << 16 : bg << 16;
568 writel(tmp, &par->riva.CURSOR[k++]);
570 k += (MAX_CURS - w)/2;
574 /* ------------------------------------------------------------------------- *
576 * general utility functions
578 * ------------------------------------------------------------------------- */
581 * riva_wclut - set CLUT entry
582 * @chip: pointer to RIVA_HW_INST object
583 * @regnum: register number
584 * @red: red component
585 * @green: green component
586 * @blue: blue component
589 * Sets color register @regnum.
594 static void riva_wclut(RIVA_HW_INST *chip,
595 unsigned char regnum, unsigned char red,
596 unsigned char green, unsigned char blue)
598 VGA_WR08(chip->PDIO, 0x3c8, regnum);
599 VGA_WR08(chip->PDIO, 0x3c9, red);
600 VGA_WR08(chip->PDIO, 0x3c9, green);
601 VGA_WR08(chip->PDIO, 0x3c9, blue);
605 * riva_rclut - read fromCLUT register
606 * @chip: pointer to RIVA_HW_INST object
607 * @regnum: register number
608 * @red: red component
609 * @green: green component
610 * @blue: blue component
613 * Reads red, green, and blue from color register @regnum.
618 static void riva_rclut(RIVA_HW_INST *chip,
619 unsigned char regnum, unsigned char *red,
620 unsigned char *green, unsigned char *blue)
623 VGA_WR08(chip->PDIO, 0x3c7, regnum);
624 *red = VGA_RD08(chip->PDIO, 0x3c9);
625 *green = VGA_RD08(chip->PDIO, 0x3c9);
626 *blue = VGA_RD08(chip->PDIO, 0x3c9);
630 * riva_save_state - saves current chip state
631 * @par: pointer to riva_par object containing info for current riva board
632 * @regs: pointer to riva_regs object
635 * Saves current chip state to @regs.
641 static void riva_save_state(struct riva_par *par, struct riva_regs *regs)
646 par->riva.LockUnlock(&par->riva, 0);
648 par->riva.UnloadStateExt(&par->riva, ®s->ext);
650 regs->misc_output = MISCin(par);
652 for (i = 0; i < NUM_CRT_REGS; i++)
653 regs->crtc[i] = CRTCin(par, i);
655 for (i = 0; i < NUM_ATC_REGS; i++)
656 regs->attr[i] = ATTRin(par, i);
658 for (i = 0; i < NUM_GRC_REGS; i++)
659 regs->gra[i] = GRAin(par, i);
661 for (i = 0; i < NUM_SEQ_REGS; i++)
662 regs->seq[i] = SEQin(par, i);
667 * riva_load_state - loads current chip state
668 * @par: pointer to riva_par object containing info for current riva board
669 * @regs: pointer to riva_regs object
672 * Loads chip state from @regs.
675 * riva_load_video_mode()
680 static void riva_load_state(struct riva_par *par, struct riva_regs *regs)
682 RIVA_HW_STATE *state = ®s->ext;
686 CRTCout(par, 0x11, 0x00);
688 par->riva.LockUnlock(&par->riva, 0);
690 par->riva.LoadStateExt(&par->riva, state);
692 MISCout(par, regs->misc_output);
694 for (i = 0; i < NUM_CRT_REGS; i++) {
700 CRTCout(par, i, regs->crtc[i]);
704 for (i = 0; i < NUM_ATC_REGS; i++)
705 ATTRout(par, i, regs->attr[i]);
707 for (i = 0; i < NUM_GRC_REGS; i++)
708 GRAout(par, i, regs->gra[i]);
710 for (i = 0; i < NUM_SEQ_REGS; i++)
711 SEQout(par, i, regs->seq[i]);
716 * riva_load_video_mode - calculate timings
717 * @info: pointer to fb_info object containing info for current riva board
720 * Calculate some timings and then send em off to riva_load_state().
725 static int riva_load_video_mode(struct fb_info *info)
727 int bpp, width, hDisplaySize, hDisplay, hStart,
728 hEnd, hTotal, height, vDisplay, vStart, vEnd, vTotal, dotClock;
729 int hBlankStart, hBlankEnd, vBlankStart, vBlankEnd;
731 struct riva_par *par = info->par;
732 struct riva_regs newmode;
735 /* time to calculate */
736 rivafb_blank(FB_BLANK_NORMAL, info);
738 bpp = info->var.bits_per_pixel;
739 if (bpp == 16 && info->var.green.length == 5)
741 width = info->var.xres_virtual;
742 hDisplaySize = info->var.xres;
743 hDisplay = (hDisplaySize / 8) - 1;
744 hStart = (hDisplaySize + info->var.right_margin) / 8 - 1;
745 hEnd = (hDisplaySize + info->var.right_margin +
746 info->var.hsync_len) / 8 - 1;
747 hTotal = (hDisplaySize + info->var.right_margin +
748 info->var.hsync_len + info->var.left_margin) / 8 - 5;
749 hBlankStart = hDisplay;
750 hBlankEnd = hTotal + 4;
752 height = info->var.yres_virtual;
753 vDisplay = info->var.yres - 1;
754 vStart = info->var.yres + info->var.lower_margin - 1;
755 vEnd = info->var.yres + info->var.lower_margin +
756 info->var.vsync_len - 1;
757 vTotal = info->var.yres + info->var.lower_margin +
758 info->var.vsync_len + info->var.upper_margin + 2;
759 vBlankStart = vDisplay;
760 vBlankEnd = vTotal + 1;
761 dotClock = 1000000000 / info->var.pixclock;
763 memcpy(&newmode, ®_template, sizeof(struct riva_regs));
765 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED)
768 if (par->FlatPanel) {
771 vBlankStart = vStart;
774 hBlankEnd = hTotal + 4;
777 newmode.crtc[0x0] = Set8Bits (hTotal);
778 newmode.crtc[0x1] = Set8Bits (hDisplay);
779 newmode.crtc[0x2] = Set8Bits (hBlankStart);
780 newmode.crtc[0x3] = SetBitField (hBlankEnd, 4: 0, 4:0) | SetBit (7);
781 newmode.crtc[0x4] = Set8Bits (hStart);
782 newmode.crtc[0x5] = SetBitField (hBlankEnd, 5: 5, 7:7)
783 | SetBitField (hEnd, 4: 0, 4:0);
784 newmode.crtc[0x6] = SetBitField (vTotal, 7: 0, 7:0);
785 newmode.crtc[0x7] = SetBitField (vTotal, 8: 8, 0:0)
786 | SetBitField (vDisplay, 8: 8, 1:1)
787 | SetBitField (vStart, 8: 8, 2:2)
788 | SetBitField (vBlankStart, 8: 8, 3:3)
790 | SetBitField (vTotal, 9: 9, 5:5)
791 | SetBitField (vDisplay, 9: 9, 6:6)
792 | SetBitField (vStart, 9: 9, 7:7);
793 newmode.crtc[0x9] = SetBitField (vBlankStart, 9: 9, 5:5)
795 newmode.crtc[0x10] = Set8Bits (vStart);
796 newmode.crtc[0x11] = SetBitField (vEnd, 3: 0, 3:0)
798 newmode.crtc[0x12] = Set8Bits (vDisplay);
799 newmode.crtc[0x13] = (width / 8) * ((bpp + 1) / 8);
800 newmode.crtc[0x15] = Set8Bits (vBlankStart);
801 newmode.crtc[0x16] = Set8Bits (vBlankEnd);
803 newmode.ext.screen = SetBitField(hBlankEnd,6:6,4:4)
804 | SetBitField(vBlankStart,10:10,3:3)
805 | SetBitField(vStart,10:10,2:2)
806 | SetBitField(vDisplay,10:10,1:1)
807 | SetBitField(vTotal,10:10,0:0);
808 newmode.ext.horiz = SetBitField(hTotal,8:8,0:0)
809 | SetBitField(hDisplay,8:8,1:1)
810 | SetBitField(hBlankStart,8:8,2:2)
811 | SetBitField(hStart,8:8,3:3);
812 newmode.ext.extra = SetBitField(vTotal,11:11,0:0)
813 | SetBitField(vDisplay,11:11,2:2)
814 | SetBitField(vStart,11:11,4:4)
815 | SetBitField(vBlankStart,11:11,6:6);
817 if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
818 int tmp = (hTotal >> 1) & ~1;
819 newmode.ext.interlace = Set8Bits(tmp);
820 newmode.ext.horiz |= SetBitField(tmp, 8:8,4:4);
822 newmode.ext.interlace = 0xff; /* interlace off */
824 if (par->riva.Architecture >= NV_ARCH_10)
825 par->riva.CURSOR = (U032 __iomem *)(info->screen_base + par->riva.CursorStart);
827 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT)
828 newmode.misc_output &= ~0x40;
830 newmode.misc_output |= 0x40;
831 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT)
832 newmode.misc_output &= ~0x80;
834 newmode.misc_output |= 0x80;
836 rc = CalcStateExt(&par->riva, &newmode.ext, bpp, width,
837 hDisplaySize, height, dotClock);
841 newmode.ext.scale = NV_RD32(par->riva.PRAMDAC, 0x00000848) &
843 if (par->FlatPanel == 1) {
844 newmode.ext.pixel |= (1 << 7);
845 newmode.ext.scale |= (1 << 8);
847 if (par->SecondCRTC) {
848 newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) &
850 newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) |
852 newmode.ext.crtcOwner = 3;
853 newmode.ext.pllsel |= 0x20000800;
854 newmode.ext.vpll2 = newmode.ext.vpll;
855 } else if (par->riva.twoHeads) {
856 newmode.ext.head = NV_RD32(par->riva.PCRTC0, 0x00000860) |
858 newmode.ext.head2 = NV_RD32(par->riva.PCRTC0, 0x00002860) &
860 newmode.ext.crtcOwner = 0;
861 newmode.ext.vpll2 = NV_RD32(par->riva.PRAMDAC0, 0x00000520);
863 if (par->FlatPanel == 1) {
864 newmode.ext.pixel |= (1 << 7);
865 newmode.ext.scale |= (1 << 8);
867 newmode.ext.cursorConfig = 0x02000100;
868 par->current_state = newmode;
869 riva_load_state(par, &par->current_state);
870 par->riva.LockUnlock(&par->riva, 0); /* important for HW cursor */
873 rivafb_blank(FB_BLANK_UNBLANK, info);
879 static void riva_update_var(struct fb_var_screeninfo *var,
880 const struct fb_videomode *modedb)
883 var->xres = var->xres_virtual = modedb->xres;
884 var->yres = modedb->yres;
885 if (var->yres_virtual < var->yres)
886 var->yres_virtual = var->yres;
887 var->xoffset = var->yoffset = 0;
888 var->pixclock = modedb->pixclock;
889 var->left_margin = modedb->left_margin;
890 var->right_margin = modedb->right_margin;
891 var->upper_margin = modedb->upper_margin;
892 var->lower_margin = modedb->lower_margin;
893 var->hsync_len = modedb->hsync_len;
894 var->vsync_len = modedb->vsync_len;
895 var->sync = modedb->sync;
896 var->vmode = modedb->vmode;
901 * rivafb_do_maximize -
902 * @info: pointer to fb_info object containing info for current riva board
911 * -EINVAL on failure, 0 on success
917 static int rivafb_do_maximize(struct fb_info *info,
918 struct fb_var_screeninfo *var,
934 /* use highest possible virtual resolution */
935 if (var->xres_virtual == -1 && var->yres_virtual == -1) {
936 printk(KERN_WARNING PFX
937 "using maximum available virtual resolution\n");
938 for (i = 0; modes[i].xres != -1; i++) {
939 if (modes[i].xres * nom / den * modes[i].yres <
943 if (modes[i].xres == -1) {
945 "could not find a virtual resolution that fits into video memory!!\n");
946 NVTRACE("EXIT - EINVAL error\n");
949 var->xres_virtual = modes[i].xres;
950 var->yres_virtual = modes[i].yres;
953 "virtual resolution set to maximum of %dx%d\n",
954 var->xres_virtual, var->yres_virtual);
955 } else if (var->xres_virtual == -1) {
956 var->xres_virtual = (info->fix.smem_len * den /
957 (nom * var->yres_virtual)) & ~15;
958 printk(KERN_WARNING PFX
959 "setting virtual X resolution to %d\n", var->xres_virtual);
960 } else if (var->yres_virtual == -1) {
961 var->xres_virtual = (var->xres_virtual + 15) & ~15;
962 var->yres_virtual = info->fix.smem_len * den /
963 (nom * var->xres_virtual);
964 printk(KERN_WARNING PFX
965 "setting virtual Y resolution to %d\n", var->yres_virtual);
967 var->xres_virtual = (var->xres_virtual + 15) & ~15;
968 if (var->xres_virtual * nom / den * var->yres_virtual > info->fix.smem_len) {
970 "mode %dx%dx%d rejected...resolution too high to fit into video memory!\n",
971 var->xres, var->yres, var->bits_per_pixel);
972 NVTRACE("EXIT - EINVAL error\n");
977 if (var->xres_virtual * nom / den >= 8192) {
978 printk(KERN_WARNING PFX
979 "virtual X resolution (%d) is too high, lowering to %d\n",
980 var->xres_virtual, 8192 * den / nom - 16);
981 var->xres_virtual = 8192 * den / nom - 16;
984 if (var->xres_virtual < var->xres) {
986 "virtual X resolution (%d) is smaller than real\n", var->xres_virtual);
990 if (var->yres_virtual < var->yres) {
992 "virtual Y resolution (%d) is smaller than real\n", var->yres_virtual);
995 if (var->yres_virtual > 0x7fff/nom)
996 var->yres_virtual = 0x7fff/nom;
997 if (var->xres_virtual > 0x7fff/nom)
998 var->xres_virtual = 0x7fff/nom;
1004 riva_set_pattern(struct riva_par *par, int clr0, int clr1, int pat0, int pat1)
1006 RIVA_FIFO_FREE(par->riva, Patt, 4);
1007 NV_WR32(&par->riva.Patt->Color0, 0, clr0);
1008 NV_WR32(&par->riva.Patt->Color1, 0, clr1);
1009 NV_WR32(par->riva.Patt->Monochrome, 0, pat0);
1010 NV_WR32(par->riva.Patt->Monochrome, 4, pat1);
1013 /* acceleration routines */
1014 static inline void wait_for_idle(struct riva_par *par)
1016 while (par->riva.Busy(&par->riva));
1020 * Set ROP. Translate X rop into ROP3. Internal routine.
1023 riva_set_rop_solid(struct riva_par *par, int rop)
1025 riva_set_pattern(par, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF);
1026 RIVA_FIFO_FREE(par->riva, Rop, 1);
1027 NV_WR32(&par->riva.Rop->Rop3, 0, rop);
1031 static void riva_setup_accel(struct fb_info *info)
1033 struct riva_par *par = info->par;
1035 RIVA_FIFO_FREE(par->riva, Clip, 2);
1036 NV_WR32(&par->riva.Clip->TopLeft, 0, 0x0);
1037 NV_WR32(&par->riva.Clip->WidthHeight, 0,
1038 (info->var.xres_virtual & 0xffff) |
1039 (info->var.yres_virtual << 16));
1040 riva_set_rop_solid(par, 0xcc);
1045 * riva_get_cmap_len - query current color map length
1046 * @var: standard kernel fb changeable data
1049 * Get current color map length.
1052 * Length of color map
1055 * rivafb_setcolreg()
1057 static int riva_get_cmap_len(const struct fb_var_screeninfo *var)
1059 int rc = 256; /* reasonable default */
1061 switch (var->green.length) {
1063 rc = 256; /* 256 entries (2^8), 8 bpp and RGB8888 */
1066 rc = 32; /* 32 entries (2^5), 16 bpp, RGB555 */
1069 rc = 64; /* 64 entries (2^6), 16 bpp, RGB565 */
1072 /* should not occur */
1078 /* ------------------------------------------------------------------------- *
1080 * framebuffer operations
1082 * ------------------------------------------------------------------------- */
1084 static int rivafb_open(struct fb_info *info, int user)
1086 struct riva_par *par = info->par;
1089 mutex_lock(&par->open_lock);
1090 if (!par->ref_count) {
1092 memset(&par->state, 0, sizeof(struct vgastate));
1093 par->state.flags = VGA_SAVE_MODE | VGA_SAVE_FONTS;
1094 /* save the DAC for Riva128 */
1095 if (par->riva.Architecture == NV_ARCH_03)
1096 par->state.flags |= VGA_SAVE_CMAP;
1097 save_vga(&par->state);
1099 /* vgaHWunlock() + riva unlock (0x7F) */
1100 CRTCout(par, 0x11, 0xFF);
1101 par->riva.LockUnlock(&par->riva, 0);
1103 riva_save_state(par, &par->initial_state);
1106 mutex_unlock(&par->open_lock);
1111 static int rivafb_release(struct fb_info *info, int user)
1113 struct riva_par *par = info->par;
1116 mutex_lock(&par->open_lock);
1117 if (!par->ref_count) {
1118 mutex_unlock(&par->open_lock);
1121 if (par->ref_count == 1) {
1122 par->riva.LockUnlock(&par->riva, 0);
1123 par->riva.LoadStateExt(&par->riva, &par->initial_state.ext);
1124 riva_load_state(par, &par->initial_state);
1126 restore_vga(&par->state);
1128 par->riva.LockUnlock(&par->riva, 1);
1131 mutex_unlock(&par->open_lock);
1136 static int rivafb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1138 const struct fb_videomode *mode;
1139 struct riva_par *par = info->par;
1140 int nom, den; /* translating from pixels->bytes */
1144 switch (var->bits_per_pixel) {
1146 var->red.offset = var->green.offset = var->blue.offset = 0;
1147 var->red.length = var->green.length = var->blue.length = 8;
1148 var->bits_per_pixel = 8;
1152 var->green.length = 5;
1155 var->bits_per_pixel = 16;
1156 /* The Riva128 supports RGB555 only */
1157 if (par->riva.Architecture == NV_ARCH_03)
1158 var->green.length = 5;
1159 if (var->green.length == 5) {
1160 /* 0rrrrrgg gggbbbbb */
1161 var->red.offset = 10;
1162 var->green.offset = 5;
1163 var->blue.offset = 0;
1164 var->red.length = 5;
1165 var->green.length = 5;
1166 var->blue.length = 5;
1168 /* rrrrrggg gggbbbbb */
1169 var->red.offset = 11;
1170 var->green.offset = 5;
1171 var->blue.offset = 0;
1172 var->red.length = 5;
1173 var->green.length = 6;
1174 var->blue.length = 5;
1180 var->red.length = var->green.length = var->blue.length = 8;
1181 var->bits_per_pixel = 32;
1182 var->red.offset = 16;
1183 var->green.offset = 8;
1184 var->blue.offset = 0;
1190 "mode %dx%dx%d rejected...color depth not supported.\n",
1191 var->xres, var->yres, var->bits_per_pixel);
1192 NVTRACE("EXIT, returning -EINVAL\n");
1197 if (!info->monspecs.vfmax || !info->monspecs.hfmax ||
1198 !info->monspecs.dclkmax || !fb_validate_mode(var, info))
1202 /* calculate modeline if supported by monitor */
1203 if (!mode_valid && info->monspecs.gtf) {
1204 if (!fb_get_mode(FB_MAXTIMINGS, 0, var, info))
1209 mode = fb_find_best_mode(var, &info->modelist);
1211 riva_update_var(var, mode);
1216 if (!mode_valid && info->monspecs.modedb_len)
1219 if (var->xres_virtual < var->xres)
1220 var->xres_virtual = var->xres;
1221 if (var->yres_virtual <= var->yres)
1222 var->yres_virtual = -1;
1223 if (rivafb_do_maximize(info, var, nom, den) < 0)
1226 if (var->xoffset < 0)
1228 if (var->yoffset < 0)
1231 /* truncate xoffset and yoffset to maximum if too high */
1232 if (var->xoffset > var->xres_virtual - var->xres)
1233 var->xoffset = var->xres_virtual - var->xres - 1;
1235 if (var->yoffset > var->yres_virtual - var->yres)
1236 var->yoffset = var->yres_virtual - var->yres - 1;
1238 var->red.msb_right =
1239 var->green.msb_right =
1240 var->blue.msb_right =
1241 var->transp.offset = var->transp.length = var->transp.msb_right = 0;
1246 static int rivafb_set_par(struct fb_info *info)
1248 struct riva_par *par = info->par;
1252 /* vgaHWunlock() + riva unlock (0x7F) */
1253 CRTCout(par, 0x11, 0xFF);
1254 par->riva.LockUnlock(&par->riva, 0);
1255 rc = riva_load_video_mode(info);
1258 if(!(info->flags & FBINFO_HWACCEL_DISABLED))
1259 riva_setup_accel(info);
1261 par->cursor_reset = 1;
1262 info->fix.line_length = (info->var.xres_virtual * (info->var.bits_per_pixel >> 3));
1263 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1264 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1266 if (info->flags & FBINFO_HWACCEL_DISABLED)
1267 info->pixmap.scan_align = 1;
1269 info->pixmap.scan_align = 4;
1277 * rivafb_pan_display
1278 * @var: standard kernel fb changeable data
1280 * @info: pointer to fb_info object containing info for current riva board
1283 * Pan (or wrap, depending on the `vmode' field) the display using the
1284 * `xoffset' and `yoffset' fields of the `var' structure.
1285 * If the values don't fit, return -EINVAL.
1287 * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1289 static int rivafb_pan_display(struct fb_var_screeninfo *var,
1290 struct fb_info *info)
1292 struct riva_par *par = info->par;
1296 base = var->yoffset * info->fix.line_length + var->xoffset;
1297 par->riva.SetStartAddress(&par->riva, base);
1302 static int rivafb_blank(int blank, struct fb_info *info)
1304 struct riva_par *par= info->par;
1305 unsigned char tmp, vesa;
1307 tmp = SEQin(par, 0x01) & ~0x20; /* screen on/off */
1308 vesa = CRTCin(par, 0x1a) & ~0xc0; /* sync on/off */
1316 case FB_BLANK_UNBLANK:
1317 case FB_BLANK_NORMAL:
1319 case FB_BLANK_VSYNC_SUSPEND:
1322 case FB_BLANK_HSYNC_SUSPEND:
1325 case FB_BLANK_POWERDOWN:
1330 SEQout(par, 0x01, tmp);
1331 CRTCout(par, 0x1a, vesa);
1340 * @regno: register index
1341 * @red: red component
1342 * @green: green component
1343 * @blue: blue component
1344 * @transp: transparency
1345 * @info: pointer to fb_info object containing info for current riva board
1348 * Set a single color register. The values supplied have a 16 bit
1352 * Return != 0 for invalid regno.
1355 * fbcmap.c:fb_set_cmap()
1357 static int rivafb_setcolreg(unsigned regno, unsigned red, unsigned green,
1358 unsigned blue, unsigned transp,
1359 struct fb_info *info)
1361 struct riva_par *par = info->par;
1362 RIVA_HW_INST *chip = &par->riva;
1365 if (regno >= riva_get_cmap_len(&info->var))
1368 if (info->var.grayscale) {
1369 /* gray = 0.30*R + 0.59*G + 0.11*B */
1370 red = green = blue =
1371 (red * 77 + green * 151 + blue * 28) >> 8;
1374 if (regno < 16 && info->fix.visual == FB_VISUAL_DIRECTCOLOR) {
1375 ((u32 *) info->pseudo_palette)[regno] =
1376 (regno << info->var.red.offset) |
1377 (regno << info->var.green.offset) |
1378 (regno << info->var.blue.offset);
1380 * The Riva128 2D engine requires color information in
1381 * TrueColor format even if framebuffer is in DirectColor
1383 if (par->riva.Architecture == NV_ARCH_03) {
1384 switch (info->var.bits_per_pixel) {
1386 par->palette[regno] = ((red & 0xf800) >> 1) |
1387 ((green & 0xf800) >> 6) |
1388 ((blue & 0xf800) >> 11);
1391 par->palette[regno] = ((red & 0xff00) << 8) |
1392 ((green & 0xff00)) |
1393 ((blue & 0xff00) >> 8);
1399 switch (info->var.bits_per_pixel) {
1401 /* "transparent" stuff is completely ignored. */
1402 riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8);
1405 if (info->var.green.length == 5) {
1406 for (i = 0; i < 8; i++) {
1407 riva_wclut(chip, regno*8+i, red >> 8,
1408 green >> 8, blue >> 8);
1414 for (i = 0; i < 8; i++) {
1415 riva_wclut(chip, regno*8+i,
1416 red >> 8, green >> 8,
1420 riva_rclut(chip, regno*4, &r, &g, &b);
1421 for (i = 0; i < 4; i++)
1422 riva_wclut(chip, regno*4+i, r,
1427 riva_wclut(chip, regno, red >> 8, green >> 8, blue >> 8);
1437 * rivafb_fillrect - hardware accelerated color fill function
1438 * @info: pointer to fb_info structure
1439 * @rect: pointer to fb_fillrect structure
1442 * This function fills up a region of framebuffer memory with a solid
1443 * color with a choice of two different ROP's, copy or invert.
1448 static void rivafb_fillrect(struct fb_info *info, const struct fb_fillrect *rect)
1450 struct riva_par *par = info->par;
1451 u_int color, rop = 0;
1453 if ((info->flags & FBINFO_HWACCEL_DISABLED)) {
1454 cfb_fillrect(info, rect);
1458 if (info->var.bits_per_pixel == 8)
1459 color = rect->color;
1461 if (par->riva.Architecture != NV_ARCH_03)
1462 color = ((u32 *)info->pseudo_palette)[rect->color];
1464 color = par->palette[rect->color];
1467 switch (rect->rop) {
1477 riva_set_rop_solid(par, rop);
1479 RIVA_FIFO_FREE(par->riva, Bitmap, 1);
1480 NV_WR32(&par->riva.Bitmap->Color1A, 0, color);
1482 RIVA_FIFO_FREE(par->riva, Bitmap, 2);
1483 NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].TopLeft, 0,
1484 (rect->dx << 16) | rect->dy);
1486 NV_WR32(&par->riva.Bitmap->UnclippedRectangle[0].WidthHeight, 0,
1487 (rect->width << 16) | rect->height);
1489 riva_set_rop_solid(par, 0xcc);
1494 * rivafb_copyarea - hardware accelerated blit function
1495 * @info: pointer to fb_info structure
1496 * @region: pointer to fb_copyarea structure
1499 * This copies an area of pixels from one location to another
1504 static void rivafb_copyarea(struct fb_info *info, const struct fb_copyarea *region)
1506 struct riva_par *par = info->par;
1508 if ((info->flags & FBINFO_HWACCEL_DISABLED)) {
1509 cfb_copyarea(info, region);
1513 RIVA_FIFO_FREE(par->riva, Blt, 3);
1514 NV_WR32(&par->riva.Blt->TopLeftSrc, 0,
1515 (region->sy << 16) | region->sx);
1516 NV_WR32(&par->riva.Blt->TopLeftDst, 0,
1517 (region->dy << 16) | region->dx);
1519 NV_WR32(&par->riva.Blt->WidthHeight, 0,
1520 (region->height << 16) | region->width);
1524 static inline void convert_bgcolor_16(u32 *col)
1526 *col = ((*col & 0x0000F800) << 8)
1527 | ((*col & 0x00007E0) << 5)
1528 | ((*col & 0x0000001F) << 3)
1534 * rivafb_imageblit: hardware accelerated color expand function
1535 * @info: pointer to fb_info structure
1536 * @image: pointer to fb_image structure
1539 * If the source is a monochrome bitmap, the function fills up a a region
1540 * of framebuffer memory with pixels whose color is determined by the bit
1541 * setting of the bitmap, 1 - foreground, 0 - background.
1543 * If the source is not a monochrome bitmap, color expansion is not done.
1544 * In this case, it is channeled to a software function.
1549 static void rivafb_imageblit(struct fb_info *info,
1550 const struct fb_image *image)
1552 struct riva_par *par = info->par;
1553 u32 fgx = 0, bgx = 0, width, tmp;
1554 u8 *cdat = (u8 *) image->data;
1555 volatile u32 __iomem *d;
1558 if ((info->flags & FBINFO_HWACCEL_DISABLED) || image->depth != 1) {
1559 cfb_imageblit(info, image);
1563 switch (info->var.bits_per_pixel) {
1565 fgx = image->fg_color;
1566 bgx = image->bg_color;
1570 if (par->riva.Architecture != NV_ARCH_03) {
1571 fgx = ((u32 *)info->pseudo_palette)[image->fg_color];
1572 bgx = ((u32 *)info->pseudo_palette)[image->bg_color];
1574 fgx = par->palette[image->fg_color];
1575 bgx = par->palette[image->bg_color];
1577 if (info->var.green.length == 6)
1578 convert_bgcolor_16(&bgx);
1582 RIVA_FIFO_FREE(par->riva, Bitmap, 7);
1583 NV_WR32(&par->riva.Bitmap->ClipE.TopLeft, 0,
1584 (image->dy << 16) | (image->dx & 0xFFFF));
1585 NV_WR32(&par->riva.Bitmap->ClipE.BottomRight, 0,
1586 (((image->dy + image->height) << 16) |
1587 ((image->dx + image->width) & 0xffff)));
1588 NV_WR32(&par->riva.Bitmap->Color0E, 0, bgx);
1589 NV_WR32(&par->riva.Bitmap->Color1E, 0, fgx);
1590 NV_WR32(&par->riva.Bitmap->WidthHeightInE, 0,
1591 (image->height << 16) | ((image->width + 31) & ~31));
1592 NV_WR32(&par->riva.Bitmap->WidthHeightOutE, 0,
1593 (image->height << 16) | ((image->width + 31) & ~31));
1594 NV_WR32(&par->riva.Bitmap->PointE, 0,
1595 (image->dy << 16) | (image->dx & 0xFFFF));
1597 d = &par->riva.Bitmap->MonochromeData01E;
1599 width = (image->width + 31)/32;
1600 size = width * image->height;
1601 while (size >= 16) {
1602 RIVA_FIFO_FREE(par->riva, Bitmap, 16);
1603 for (i = 0; i < 16; i++) {
1604 tmp = *((u32 *)cdat);
1605 cdat = (u8 *)((u32 *)cdat + 1);
1606 reverse_order(&tmp);
1607 NV_WR32(d, i*4, tmp);
1612 RIVA_FIFO_FREE(par->riva, Bitmap, size);
1613 for (i = 0; i < size; i++) {
1614 tmp = *((u32 *) cdat);
1615 cdat = (u8 *)((u32 *)cdat + 1);
1616 reverse_order(&tmp);
1617 NV_WR32(d, i*4, tmp);
1623 * rivafb_cursor - hardware cursor function
1624 * @info: pointer to info structure
1625 * @cursor: pointer to fbcursor structure
1628 * A cursor function that supports displaying a cursor image via hardware.
1629 * Within the kernel, copy and invert rops are supported. If exported
1630 * to user space, only the copy rop will be supported.
1635 static int rivafb_cursor(struct fb_info *info, struct fb_cursor *cursor)
1637 struct riva_par *par = info->par;
1638 u8 data[MAX_CURS * MAX_CURS/8];
1639 int i, set = cursor->set;
1642 if (cursor->image.width > MAX_CURS || cursor->image.height > MAX_CURS)
1645 par->riva.ShowHideCursor(&par->riva, 0);
1647 if (par->cursor_reset) {
1648 set = FB_CUR_SETALL;
1649 par->cursor_reset = 0;
1652 if (set & FB_CUR_SETSIZE)
1653 memset_io(par->riva.CURSOR, 0, MAX_CURS * MAX_CURS * 2);
1655 if (set & FB_CUR_SETPOS) {
1658 yy = cursor->image.dy - info->var.yoffset;
1659 xx = cursor->image.dx - info->var.xoffset;
1663 NV_WR32(par->riva.PRAMDAC, 0x0000300, temp);
1667 if (set & (FB_CUR_SETSHAPE | FB_CUR_SETCMAP | FB_CUR_SETIMAGE)) {
1668 u32 bg_idx = cursor->image.bg_color;
1669 u32 fg_idx = cursor->image.fg_color;
1670 u32 s_pitch = (cursor->image.width+7) >> 3;
1671 u32 d_pitch = MAX_CURS/8;
1672 u8 *dat = (u8 *) cursor->image.data;
1673 u8 *msk = (u8 *) cursor->mask;
1676 src = kmalloc(s_pitch * cursor->image.height, GFP_ATOMIC);
1679 switch (cursor->rop) {
1681 for (i = 0; i < s_pitch * cursor->image.height; i++)
1682 src[i] = dat[i] ^ msk[i];
1686 for (i = 0; i < s_pitch * cursor->image.height; i++)
1687 src[i] = dat[i] & msk[i];
1691 fb_pad_aligned_buffer(data, d_pitch, src, s_pitch,
1692 cursor->image.height);
1694 bg = ((info->cmap.red[bg_idx] & 0xf8) << 7) |
1695 ((info->cmap.green[bg_idx] & 0xf8) << 2) |
1696 ((info->cmap.blue[bg_idx] & 0xf8) >> 3) |
1699 fg = ((info->cmap.red[fg_idx] & 0xf8) << 7) |
1700 ((info->cmap.green[fg_idx] & 0xf8) << 2) |
1701 ((info->cmap.blue[fg_idx] & 0xf8) >> 3) |
1704 par->riva.LockUnlock(&par->riva, 0);
1706 rivafb_load_cursor_image(par, data, bg, fg,
1707 cursor->image.width,
1708 cursor->image.height);
1714 par->riva.ShowHideCursor(&par->riva, 1);
1719 static int rivafb_sync(struct fb_info *info)
1721 struct riva_par *par = info->par;
1727 /* ------------------------------------------------------------------------- *
1729 * initialization helper functions
1731 * ------------------------------------------------------------------------- */
1733 /* kernel interface */
1734 static struct fb_ops riva_fb_ops = {
1735 .owner = THIS_MODULE,
1736 .fb_open = rivafb_open,
1737 .fb_release = rivafb_release,
1738 .fb_check_var = rivafb_check_var,
1739 .fb_set_par = rivafb_set_par,
1740 .fb_setcolreg = rivafb_setcolreg,
1741 .fb_pan_display = rivafb_pan_display,
1742 .fb_blank = rivafb_blank,
1743 .fb_fillrect = rivafb_fillrect,
1744 .fb_copyarea = rivafb_copyarea,
1745 .fb_imageblit = rivafb_imageblit,
1746 .fb_cursor = rivafb_cursor,
1747 .fb_sync = rivafb_sync,
1750 static int __devinit riva_set_fbinfo(struct fb_info *info)
1752 unsigned int cmap_len;
1753 struct riva_par *par = info->par;
1756 info->flags = FBINFO_DEFAULT
1757 | FBINFO_HWACCEL_XPAN
1758 | FBINFO_HWACCEL_YPAN
1759 | FBINFO_HWACCEL_COPYAREA
1760 | FBINFO_HWACCEL_FILLRECT
1761 | FBINFO_HWACCEL_IMAGEBLIT;
1763 /* Accel seems to not work properly on NV30 yet...*/
1764 if ((par->riva.Architecture == NV_ARCH_30) || noaccel) {
1765 printk(KERN_DEBUG PFX "disabling acceleration\n");
1766 info->flags |= FBINFO_HWACCEL_DISABLED;
1769 info->var = rivafb_default_var;
1770 info->fix.visual = (info->var.bits_per_pixel == 8) ?
1771 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1773 info->pseudo_palette = par->pseudo_palette;
1775 cmap_len = riva_get_cmap_len(&info->var);
1776 fb_alloc_cmap(&info->cmap, cmap_len, 0);
1778 info->pixmap.size = 8 * 1024;
1779 info->pixmap.buf_align = 4;
1780 info->pixmap.access_align = 32;
1781 info->pixmap.flags = FB_PIXMAP_SYSTEM;
1782 info->var.yres_virtual = -1;
1784 return (rivafb_check_var(&info->var, info));
1787 #ifdef CONFIG_PPC_OF
1788 static int __devinit riva_get_EDID_OF(struct fb_info *info, struct pci_dev *pd)
1790 struct riva_par *par = info->par;
1791 struct device_node *dp;
1792 const unsigned char *pedid = NULL;
1793 const unsigned char *disptype = NULL;
1794 static char *propnames[] = {
1795 "DFP,EDID", "LCD,EDID", "EDID", "EDID1", "EDID,B", "EDID,A", NULL };
1799 dp = pci_device_to_OF_node(pd);
1800 for (; dp != NULL; dp = dp->child) {
1801 disptype = get_property(dp, "display-type", NULL);
1802 if (disptype == NULL)
1804 if (strncmp(disptype, "LCD", 3) != 0)
1806 for (i = 0; propnames[i] != NULL; ++i) {
1807 pedid = get_property(dp, propnames[i], NULL);
1808 if (pedid != NULL) {
1809 par->EDID = (unsigned char *)pedid;
1810 NVTRACE("LCD found.\n");
1818 #endif /* CONFIG_PPC_OF */
1820 #if defined(CONFIG_FB_RIVA_I2C) && !defined(CONFIG_PPC_OF)
1821 static int __devinit riva_get_EDID_i2c(struct fb_info *info)
1823 struct riva_par *par = info->par;
1824 struct fb_var_screeninfo var;
1828 riva_create_i2c_busses(par);
1829 for (i = 0; i < par->bus; i++) {
1830 riva_probe_i2c_connector(par, i+1, &par->EDID);
1831 if (par->EDID && !fb_parse_edid(par->EDID, &var)) {
1832 printk(PFX "Found EDID Block from BUS %i\n", i);
1838 return (par->EDID) ? 1 : 0;
1840 #endif /* CONFIG_FB_RIVA_I2C */
1842 static void __devinit riva_update_default_var(struct fb_var_screeninfo *var,
1843 struct fb_info *info)
1845 struct fb_monspecs *specs = &info->monspecs;
1846 struct fb_videomode modedb;
1849 /* respect mode options */
1851 fb_find_mode(var, info, mode_option,
1852 specs->modedb, specs->modedb_len,
1854 } else if (specs->modedb != NULL) {
1855 /* get preferred timing */
1856 if (info->monspecs.misc & FB_MISC_1ST_DETAIL) {
1859 for (i = 0; i < specs->modedb_len; i++) {
1860 if (specs->modedb[i].flag & FB_MODE_IS_FIRST) {
1861 modedb = specs->modedb[i];
1866 /* otherwise, get first mode in database */
1867 modedb = specs->modedb[0];
1869 var->bits_per_pixel = 8;
1870 riva_update_var(var, &modedb);
1876 static void __devinit riva_get_EDID(struct fb_info *info, struct pci_dev *pdev)
1879 #ifdef CONFIG_PPC_OF
1880 if (!riva_get_EDID_OF(info, pdev))
1881 printk(PFX "could not retrieve EDID from OF\n");
1882 #elif defined(CONFIG_FB_RIVA_I2C)
1883 if (!riva_get_EDID_i2c(info))
1884 printk(PFX "could not retrieve EDID from DDC/I2C\n");
1890 static void __devinit riva_get_edidinfo(struct fb_info *info)
1892 struct fb_var_screeninfo *var = &rivafb_default_var;
1893 struct riva_par *par = info->par;
1895 fb_edid_to_monspecs(par->EDID, &info->monspecs);
1896 fb_videomode_to_modelist(info->monspecs.modedb, info->monspecs.modedb_len,
1898 riva_update_default_var(var, info);
1900 /* if user specified flatpanel, we respect that */
1901 if (info->monspecs.input & FB_DISP_DDI)
1905 /* ------------------------------------------------------------------------- *
1909 * ------------------------------------------------------------------------- */
1911 static u32 __devinit riva_get_arch(struct pci_dev *pd)
1915 switch (pd->device & 0x0ff0) {
1916 case 0x0100: /* GeForce 256 */
1917 case 0x0110: /* GeForce2 MX */
1918 case 0x0150: /* GeForce2 */
1919 case 0x0170: /* GeForce4 MX */
1920 case 0x0180: /* GeForce4 MX (8x AGP) */
1921 case 0x01A0: /* nForce */
1922 case 0x01F0: /* nForce2 */
1925 case 0x0200: /* GeForce3 */
1926 case 0x0250: /* GeForce4 Ti */
1927 case 0x0280: /* GeForce4 Ti (8x AGP) */
1930 case 0x0300: /* GeForceFX 5800 */
1931 case 0x0310: /* GeForceFX 5600 */
1932 case 0x0320: /* GeForceFX 5200 */
1933 case 0x0330: /* GeForceFX 5900 */
1934 case 0x0340: /* GeForceFX 5700 */
1937 case 0x0020: /* TNT, TNT2 */
1940 case 0x0010: /* Riva128 */
1943 default: /* unknown architecture */
1949 static int __devinit rivafb_probe(struct pci_dev *pd,
1950 const struct pci_device_id *ent)
1952 struct riva_par *default_par;
1953 struct fb_info *info;
1959 info = framebuffer_alloc(sizeof(struct riva_par), &pd->dev);
1961 printk (KERN_ERR PFX "could not allocate memory\n");
1965 default_par = info->par;
1966 default_par->pdev = pd;
1968 info->pixmap.addr = kzalloc(8 * 1024, GFP_KERNEL);
1969 if (info->pixmap.addr == NULL) {
1971 goto err_framebuffer_release;
1974 ret = pci_enable_device(pd);
1976 printk(KERN_ERR PFX "cannot enable PCI device\n");
1977 goto err_free_pixmap;
1980 ret = pci_request_regions(pd, "rivafb");
1982 printk(KERN_ERR PFX "cannot request PCI regions\n");
1983 goto err_disable_device;
1986 mutex_init(&default_par->open_lock);
1987 default_par->riva.Architecture = riva_get_arch(pd);
1989 default_par->Chipset = (pd->vendor << 16) | pd->device;
1990 printk(KERN_INFO PFX "nVidia device/chipset %X\n",default_par->Chipset);
1992 if(default_par->riva.Architecture == 0) {
1993 printk(KERN_ERR PFX "unknown NV_ARCH\n");
1995 goto err_release_region;
1997 if(default_par->riva.Architecture == NV_ARCH_10 ||
1998 default_par->riva.Architecture == NV_ARCH_20 ||
1999 default_par->riva.Architecture == NV_ARCH_30) {
2000 sprintf(rivafb_fix.id, "NV%x", (pd->device & 0x0ff0) >> 4);
2002 sprintf(rivafb_fix.id, "NV%x", default_par->riva.Architecture);
2005 default_par->FlatPanel = flatpanel;
2007 printk(KERN_INFO PFX "flatpanel support enabled\n");
2008 default_par->forceCRTC = forceCRTC;
2010 rivafb_fix.mmio_len = pci_resource_len(pd, 0);
2011 rivafb_fix.smem_len = pci_resource_len(pd, 1);
2014 /* enable IO and mem if not already done */
2017 pci_read_config_word(pd, PCI_COMMAND, &cmd);
2018 cmd |= (PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
2019 pci_write_config_word(pd, PCI_COMMAND, cmd);
2022 rivafb_fix.mmio_start = pci_resource_start(pd, 0);
2023 rivafb_fix.smem_start = pci_resource_start(pd, 1);
2025 default_par->ctrl_base = ioremap(rivafb_fix.mmio_start,
2026 rivafb_fix.mmio_len);
2027 if (!default_par->ctrl_base) {
2028 printk(KERN_ERR PFX "cannot ioremap MMIO base\n");
2030 goto err_release_region;
2033 switch (default_par->riva.Architecture) {
2035 /* Riva128's PRAMIN is in the "framebuffer" space
2036 * Since these cards were never made with more than 8 megabytes
2037 * we can safely allocate this separately.
2039 default_par->riva.PRAMIN = ioremap(rivafb_fix.smem_start + 0x00C00000, 0x00008000);
2040 if (!default_par->riva.PRAMIN) {
2041 printk(KERN_ERR PFX "cannot ioremap PRAMIN region\n");
2043 goto err_iounmap_ctrl_base;
2050 default_par->riva.PCRTC0 =
2051 (u32 __iomem *)(default_par->ctrl_base + 0x00600000);
2052 default_par->riva.PRAMIN =
2053 (u32 __iomem *)(default_par->ctrl_base + 0x00710000);
2056 riva_common_setup(default_par);
2058 if (default_par->riva.Architecture == NV_ARCH_03) {
2059 default_par->riva.PCRTC = default_par->riva.PCRTC0
2060 = default_par->riva.PGRAPH;
2063 rivafb_fix.smem_len = riva_get_memlen(default_par) * 1024;
2064 default_par->dclk_max = riva_get_maxdclk(default_par) * 1000;
2065 info->screen_base = ioremap(rivafb_fix.smem_start,
2066 rivafb_fix.smem_len);
2067 if (!info->screen_base) {
2068 printk(KERN_ERR PFX "cannot ioremap FB base\n");
2070 goto err_iounmap_pramin;
2075 default_par->mtrr.vram = mtrr_add(rivafb_fix.smem_start,
2076 rivafb_fix.smem_len,
2077 MTRR_TYPE_WRCOMB, 1);
2078 if (default_par->mtrr.vram < 0) {
2079 printk(KERN_ERR PFX "unable to setup MTRR\n");
2081 default_par->mtrr.vram_valid = 1;
2082 /* let there be speed */
2083 printk(KERN_INFO PFX "RIVA MTRR set to ON\n");
2086 #endif /* CONFIG_MTRR */
2088 info->fbops = &riva_fb_ops;
2089 info->fix = rivafb_fix;
2090 riva_get_EDID(info, pd);
2091 riva_get_edidinfo(info);
2093 ret=riva_set_fbinfo(info);
2095 printk(KERN_ERR PFX "error setting initial video mode\n");
2096 goto err_iounmap_screen_base;
2099 fb_destroy_modedb(info->monspecs.modedb);
2100 info->monspecs.modedb = NULL;
2102 pci_set_drvdata(pd, info);
2103 riva_bl_init(info->par);
2104 ret = register_framebuffer(info);
2107 "error registering riva framebuffer\n");
2108 goto err_iounmap_screen_base;
2111 printk(KERN_INFO PFX
2112 "PCI nVidia %s framebuffer ver %s (%dMB @ 0x%lX)\n",
2115 info->fix.smem_len / (1024 * 1024),
2116 info->fix.smem_start);
2121 err_iounmap_screen_base:
2122 #ifdef CONFIG_FB_RIVA_I2C
2123 riva_delete_i2c_busses(info->par);
2125 iounmap(info->screen_base);
2127 if (default_par->riva.Architecture == NV_ARCH_03)
2128 iounmap(default_par->riva.PRAMIN);
2129 err_iounmap_ctrl_base:
2130 iounmap(default_par->ctrl_base);
2132 pci_release_regions(pd);
2135 kfree(info->pixmap.addr);
2136 err_framebuffer_release:
2137 framebuffer_release(info);
2142 static void __exit rivafb_remove(struct pci_dev *pd)
2144 struct fb_info *info = pci_get_drvdata(pd);
2145 struct riva_par *par = info->par;
2151 #ifdef CONFIG_FB_RIVA_I2C
2152 riva_delete_i2c_busses(par);
2156 unregister_framebuffer(info);
2158 if (par->mtrr.vram_valid)
2159 mtrr_del(par->mtrr.vram, info->fix.smem_start,
2160 info->fix.smem_len);
2161 #endif /* CONFIG_MTRR */
2163 iounmap(par->ctrl_base);
2164 iounmap(info->screen_base);
2165 if (par->riva.Architecture == NV_ARCH_03)
2166 iounmap(par->riva.PRAMIN);
2167 pci_release_regions(pd);
2168 kfree(info->pixmap.addr);
2169 framebuffer_release(info);
2170 pci_set_drvdata(pd, NULL);
2174 /* ------------------------------------------------------------------------- *
2178 * ------------------------------------------------------------------------- */
2181 static int __init rivafb_setup(char *options)
2186 if (!options || !*options)
2189 while ((this_opt = strsep(&options, ",")) != NULL) {
2190 if (!strncmp(this_opt, "forceCRTC", 9)) {
2194 if (!*p || !*(++p)) continue;
2195 forceCRTC = *p - '0';
2196 if (forceCRTC < 0 || forceCRTC > 1)
2198 } else if (!strncmp(this_opt, "flatpanel", 9)) {
2201 } else if (!strncmp(this_opt, "nomtrr", 6)) {
2204 } else if (!strncmp(this_opt, "strictmode", 10)) {
2206 } else if (!strncmp(this_opt, "noaccel", 7)) {
2209 mode_option = this_opt;
2214 #endif /* !MODULE */
2216 static struct pci_driver rivafb_driver = {
2218 .id_table = rivafb_pci_tbl,
2219 .probe = rivafb_probe,
2220 .remove = __exit_p(rivafb_remove),
2225 /* ------------------------------------------------------------------------- *
2229 * ------------------------------------------------------------------------- */
2231 static int __devinit rivafb_init(void)
2234 char *option = NULL;
2236 if (fb_get_options("rivafb", &option))
2238 rivafb_setup(option);
2240 return pci_register_driver(&rivafb_driver);
2244 module_init(rivafb_init);
2247 static void __exit rivafb_exit(void)
2249 pci_unregister_driver(&rivafb_driver);
2252 module_exit(rivafb_exit);
2255 module_param(noaccel, bool, 0);
2256 MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
2257 module_param(flatpanel, int, 0);
2258 MODULE_PARM_DESC(flatpanel, "Enables experimental flat panel support for some chipsets. (0 or 1=enabled) (default=0)");
2259 module_param(forceCRTC, int, 0);
2260 MODULE_PARM_DESC(forceCRTC, "Forces usage of a particular CRTC in case autodetection fails. (0 or 1) (default=autodetect)");
2262 module_param(nomtrr, bool, 0);
2263 MODULE_PARM_DESC(nomtrr, "Disables MTRR support (0 or 1=disabled) (default=0)");
2265 module_param(strictmode, bool, 0);
2266 MODULE_PARM_DESC(strictmode, "Only use video modes from EDID");
2268 MODULE_AUTHOR("Ani Joshi, maintainer");
2269 MODULE_DESCRIPTION("Framebuffer driver for nVidia Riva 128, TNT, TNT2, and the GeForce series");
2270 MODULE_LICENSE("GPL");