1 /* drivers/video/rk2818_fb.h
3 * Copyright (C) 2010 ROCKCHIP, Inc.
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
16 #ifndef __ARCH_ARM_MACH_RK2818_FB_H
17 #define __ARCH_ARM_MACH_RK2818_FB_H
19 /********************************************************************
21 ********************************************************************/
22 /* ÊäÍùÆÁµÄÊý¾Ý¸ñʽ */
29 #define OUT_S888DUMY 12
30 #define OUT_P16BPP4 24 //Ä£Äⷽʽ,¿ØÖÆÆ÷²¢²»Ö§³Ö
33 #define m_WORDLO (0xffff<<0)
34 #define m_WORDHI (0xffff<<16)
35 #define v_WORDLO(x) (((x)&0xffff)<<0)
36 #define v_WORDHI(x) (((x)&0xffff)<<16)
38 #define m_BIT11LO (0x7ff<<0)
39 #define m_BIT11HI (0x7ff<<16)
40 #define v_BIT11LO(x) (((x)&0x7ff)<<0)
41 #define v_BIT11HI(x) (((x)&0x7ff)<<16)
45 #define m_W1_FORMAT (1<<0)
46 #define m_W0_FORMAT (7<<1)
47 #define m_W1_ROLLER (1<<4)
48 #define m_W0_ROLLER (1<<5)
49 #define m_INTERIACE_EN (1<<6)
50 #define m_MPEG2_I2P_EN (1<<7)
51 #define m_W0_ROTATE (1<<8)
52 #define m_W1_ENABLE (1<<9)
53 #define m_W0_ENABLE (1<<10)
54 #define m_HWC_ENABLE (1<<11)
55 #define m_HWC_RELOAD_EN (1<<12)
56 #define m_W1_INTERLACE_READ (1<<13)
57 #define m_W0_INTERLACE_READ (1<<14)
58 #define m_STANDBY (1<<15)
59 #define m_W1_HWC_INCR (31<<16)
60 #define m_W1_HWC_BURST (7<<21)
61 #define m_W0_INCR (31<<24)
62 #define m_W0_BURST (7<<29)
63 #define v_W1_FORMAT(x) (((x)&1)<<0)
64 #define v_W0_FORMAT(x) (((x)&7)<<1)
65 #define v_W1_ROLLER(x) (((x)&1)<<4)
66 #define v_W0_ROLLER(x) (((x)&1)<<5)
67 #define v_INTERIACE_EN(x) (((x)&1)<<6)
68 #define v_MPEG2_I2P_EN(x) (((x)&1)<<7)
69 #define v_W0_ROTATE(x) (((x)&1)<<8)
70 #define v_W1_ENABLE(x) (((x)&1)<<9)
71 #define v_W0_ENABLE(x) (((x)&1)<<10)
72 #define v_HWC_ENABLE(x) (((x)&1)<<11)
73 #define v_HWC_RELOAD_EN(x) (((x)&1)<<12)
74 #define v_W1_INTERLACE_READ(x) (((x)&1)<<13)
75 #define v_W0_INTERLACE_READ(x) (((x)&1)<<14)
76 #define v_STANDBY(x) (((x)&1)<<15)
77 #define v_W1_HWC_INCR(x) (((x)&31)<<16)
78 #define v_W1_HWC_BURST(x) (((x)&7)<<21)
79 #define v_W0_INCR(x) (((x)&31)<<24)
80 #define v_W0_BURST(x) (((x)&7)<<29)
83 #define m_W1_565_RB_SWAP (1<<0)
84 #define m_W0_565_RB_SWAP (1<<1)
85 #define m_W0_YRGB_M8_SWAP (1<<2)
86 #define m_W0_YRGB_R_SHIFT_SWAP (1<<3)
87 #define m_W0_CBR_R_SHIFT_SWAP (1<<4)
88 #define m_W0_YRGB_16_SWAP (1<<5)
89 #define m_W0_YRGB_8_SWAP (1<<6)
90 #define m_W0_CBR_16_SWAP (1<<7)
91 #define m_W0_CBR_8_SWAP (1<<8)
92 #define m_W1_16_SWAP (1<<9)
93 #define m_W1_8_SWAP (1<<10)
94 #define m_W1_R_SHIFT_SWAP (1<<11)
95 #define m_OUTPUT_BG_SWAP (1<<12)
96 #define m_OUTPUT_RB_SWAP (1<<13)
97 #define m_OUTPUT_RG_SWAP (1<<14)
98 #define m_DELTA_SWAP (1<<15)
99 #define m_DUMMY_SWAP (1<<16)
100 #define m_W0_YRGB_HL8_SWAP (1<<17)
101 #define v_W1_565_RB_SWAP(x) (((x)&1)<<0)
102 #define v_W0_565_RB_SWAP(x) (((x)&1)<<1)
103 #define v_W0_YRGB_M8_SWAP(x) (((x)&1)<<2)
104 #define v_W0_YRGB_R_SHIFT_SWAP(x) (((x)&1)<<3)
105 #define v_W0_CBR_R_SHIFT_SWAP(x) (((x)&1)<<4)
106 #define v_W0_YRGB_16_SWAP(x) (((x)&1)<<5)
107 #define v_W0_YRGB_8_SWAP(x) (((x)&1)<<6)
108 #define v_W0_CBR_16_SWAP(x) (((x)&1)<<7)
109 #define v_W0_CBR_8_SWAP(x) (((x)&1)<<8)
110 #define v_W1_16_SWAP(x) (((x)&1)<<9)
111 #define v_W1_8_SWAP(x) (((x)&1)<<10)
112 #define v_W1_R_SHIFT_SWAP(x) (((x)&1)<<11)
113 #define v_OUTPUT_BG_SWAP(x) (((x)&1)<<12)
114 #define v_OUTPUT_RB_SWAP(x) (((x)&1)<<13)
115 #define v_OUTPUT_RG_SWAP(x) (((x)&1)<<14)
116 #define v_DELTA_SWAP(x) (((x)&1)<<15)
117 #define v_DUMMY_SWAP(x) (((x)&1)<<16)
118 #define v_W0_YRGB_HL8_SWAP(x) (((x)&1)<<17)
120 //LCDC_MCU_TIMING_CTRL
121 #define m_MCU_WRITE_PERIOD (31<<0)
122 #define m_MCU_CS_ST (31<<5)
123 #define m_MCU_CS_END (31<<10)
124 #define m_MCU_RW_ST (31<<15)
125 #define m_MCU_RW_END (31<<20)
126 #define m_MCU_HOLD_STATUS (1<<26)
127 #define m_MCU_HOLDMODE_SELECT (1<<27)
128 #define m_MCU_HOLDMODE_FRAME_ST (1<<28)
129 #define m_MCU_RS_SELECT (1<<29)
130 #define m_MCU_BYPASSMODE_SELECT (1<<30)
131 #define m_MCU_OUTPUT_SELECT (1<<31)
132 #define v_MCU_WRITE_PERIOD(x) (((x)&31)<<0)
133 #define v_MCU_CS_ST(x) (((x)&31)<<5)
134 #define v_MCU_CS_END(x) (((x)&31)<<10)
135 #define v_MCU_RW_ST(x) (((x)&31)<<15)
136 #define v_MCU_RW_END(x) (((x)&31)<<20)
137 #define v_MCU_HOLD_STATUS(x) (((x)&1)<<26)
138 #define v_MCU_HOLDMODE_SELECT(x) (((x)&1)<<27)
139 #define v_MCU_HOLDMODE_FRAME_ST(x) (((x)&1)<<28)
140 #define v_MCU_RS_SELECT(x) (((x)&1)<<29)
141 #define v_MCU_BYPASSMODE_SELECT(x) (((x)&1)<<30)
142 #define v_MCU_OUTPUT_SELECT(x) (((x)&1)<<31)
145 #define m_W1_BLEND_EN (1<<0)
146 #define m_W0_BLEND_EN (1<<1)
147 #define m_HWC_BLEND_EN (1<<2)
148 #define m_W1_BLEND_FACTOR_SELECT (1<<3)
149 #define m_W0_BLEND_FACTOR_SELECT (1<<4)
150 #define m_W0W1_OVERLAY (1<<5)
151 #define m_HWC_BLEND_FACTOR (15<<12)
152 #define m_W1_BLEND_FACTOR (0xff<<16)
153 #define m_W0_BLEND_FACTOR (0xff<<24)
154 #define v_W1_BLEND_EN(x) (((x)&1)<<0)
155 #define v_W0_BLEND_EN(x) (((x)&1)<<1)
156 #define v_HWC_BLEND_EN(x) (((x)&1)<<2)
157 #define v_W1_BLEND_FACTOR_SELECT(x) (((x)&1)<<3)
158 #define v_W0_BLEND_FACTOR_SELECT(x) (((x)&1)<<4)
159 #define v_W0W1_OVERLAY(x) (((x)&1)<<5)
160 #define v_HWC_BLEND_FACTOR(x) (((x)&15)<<12)
161 #define v_W1_BLEND_FACTOR(x) (((x)&0xff)<<16)
162 #define v_W0_BLEND_FACTOR(x) (((x)&0xff)<<24)
164 //LCDC_WIN0_COLOR_KEY_CTRL / LCDC_WIN1_COLOR_KEY_CTRL
165 #define m_KEYCOLOR (0xffffff<<0)
166 #define m_KEYCOLOR_B (0xff<<0)
167 #define m_KEYCOLOR_G (0xff<<8)
168 #define m_KEYCOLOR_R (0xff<<16)
169 #define m_COLORKEY_EN (1<<24)
170 #define v_KEYCOLOR(x) (((x)&0xffffff)<<0)
171 #define v_KEYCOLOR_B(x) (((x)&0xff)<<0)
172 #define v_KEYCOLOR_G(x) (((x)&0xff)<<8)
173 #define v_KEYCOLOR_R(x) (((x)&0xff)<<16)
174 #define v_COLORKEY_EN(x) (((x)&1)<<24)
176 //LCDC_DEFLICKER_SCL_OFFSET
177 #define m_W0_YRGB_VSD_OFFSET (0xff<<0)
178 #define m_W0_YRGB_VSP_OFFSET (0xff<<8)
179 #define m_W1_VSD_OFFSET (0xff<<16)
180 #define m_W1_VSP_OFFSET (0xff<<24)
181 #define v_W0_YRGB_VSD_OFFSET(x) (((x)&0xff)<<0)
182 #define v_W0_YRGB_VSP_OFFSET(x) (((x)&0xff)<<8)
183 #define v_W1_VSD_OFFSET(x) (((x)&0xff)<<16)
184 #define v_W1_VSP_OFFSET(x) (((x)&0xff)<<24)
187 #define m_DISPLAY_FORMAT (0xf<<0)
188 #define m_HSYNC_POLARITY (1<<4)
189 #define m_VSYNC_POLARITY (1<<5)
190 #define m_DEN_POLARITY (1<<6)
191 #define m_DCLK_POLARITY (1<<7)
192 #define m_COLOR_SPACE_CONVERSION (3<<8)
193 #define m_I2P_THRESHOLD_Y (0x3f<<10)
194 #define m_I2P_THRESHOLD_CBR (0x3f<<16)
195 #define m_565_TO_888_REPLICATION_EN (1<<22)
196 #define m_DITHERING_MODE (1<<23)
197 #define m_DITHERING_EN (1<<24)
198 #define m_DROP_LINE_W1 (1<<25)
199 #define m_DROP_LINE_W0 (1<<26)
200 #define m_I2P_CUR_POLARITY (1<<27)
201 #define m_INTERLACE_FIELD_POLARITY (1<<28)
202 #define m_YUV_CLIP_MODE (1<<29)
203 #define m_I2P_FILTER_EN (1<<30)
204 #define m_I2P_FILTER_PARAM (1<<31)
205 #define v_DISPLAY_FORMAT(x) (((x)&0xf)<<0)
206 #define v_HSYNC_POLARITY(x) (((x)&1)<<4)
207 #define v_VSYNC_POLARITY(x) (((x)&1)<<5)
208 #define v_DEN_POLARITY(x) (((x)&1)<<6)
209 #define v_DCLK_POLARITY(x) (((x)&1)<<7)
210 #define v_COLOR_SPACE_CONVERSION(x) (((x)&3)<<8)
211 #define v_I2P_THRESHOLD_Y(x) (((x)&0x3f)<<10)
212 #define v_I2P_THRESHOLD_CBR(x) (((x)&0x3f)<<16)
213 #define v_565_TO_888_REPLICATION_EN(x) (((x)&1)<<22)
214 #define v_DITHERING_MODE(x) (((x)&1)<<23)
215 #define v_DITHERING_EN(x) (((x)&1)<<24)
216 #define v_DROP_LINE_W1(x) (((x)&1)<<25)
217 #define v_DROP_LINE_W0(x) (((x)&1)<<26)
218 #define v_I2P_CUR_POLARITY(x) (((x)&1)<<27)
219 #define v_INTERLACE_FIELD_POLARITY(x) (((x)&1)<<28)
220 #define v_YUV_CLIP_MODE(x) (((x)&1)<<29)
221 #define v_I2P_FILTER_EN(x) (((x)&1)<<30)
222 #define v_I2P_FILTER_PARAM(x) (((x)&1)<<31)
225 #define m_BG_COLOR (0xffffff<<0)
226 #define m_BG_B (0xff<<0)
227 #define m_BG_G (0xff<<8)
228 #define m_BG_R (0xff<<16)
229 #define m_BLANK_MODE (1<<24)
230 #define m_BLACK_MODE (1<<25)
231 #define m_W1_SD_DEFLICKER_EN (1<<26)
232 #define m_W1_SP_DEFLICKER_EN (1<<27)
233 #define m_W0CR_SD_DEFLICKER_EN (1<<28)
234 #define m_W0CR_SP_DEFLICKER_EN (1<<29)
235 #define m_W0YRGB_SD_DEFLICKER_EN (1<<30)
236 #define m_W0YRGB_SP_DEFLICKER_EN (1<<31)
237 #define v_BG_COLOR(x) (((x)&0xffffff)<<0)
238 #define v_BG_B(x) (((x)&0xff)<<0)
239 #define v_BG_G(x) (((x)&0xff)<<8)
240 #define v_BG_R(x) (((x)&0xff)<<16)
241 #define v_BLANK_MODE(x) (((x)&1)<<24)
242 #define v_BLACK_MODE(x) (((x)&1)<<25)
243 #define v_W1_SD_DEFLICKER_EN(x) (((x)&1)<<26)
244 #define v_W1_SP_DEFLICKER_EN(x) (((x)&1)<<27)
245 #define v_W0CR_SD_DEFLICKER_EN(x) (((x)&1)<<28)
246 #define v_W0CR_SP_DEFLICKER_EN(x) (((x)&1)<<29)
247 #define v_W0YRGB_SD_DEFLICKER_EN(x) (((x)&1)<<30)
248 #define v_W0YRGB_SP_DEFLICKER_EN(x) (((x)&1)<<31)
251 #define m_HOR_START (1<<0)
252 #define m_FRM_START (1<<1)
253 #define m_SCANNING_FLAG (1<<2)
254 #define m_HOR_STARTMASK (1<<3)
255 #define m_FRM_STARTMASK (1<<4)
256 #define m_SCANNING_MASK (1<<5)
257 #define m_HOR_STARTCLEAR (1<<6)
258 #define m_FRM_STARTCLEAR (1<<7)
259 #define m_SCANNING_CLEAR (1<<8)
260 #define m_SCAN_LINE_NUM (0x7ff<<9)
261 #define v_HOR_START(x) (((x)&1)<<0)
262 #define v_FRM_START(x) (((x)&1)<<1)
263 #define v_SCANNING_FLAG(x) (((x)&1)<<2)
264 #define v_HOR_STARTMASK(x) (((x)&1)<<3)
265 #define v_FRM_STARTMASK(x) (((x)&1)<<4)
266 #define v_SCANNING_MASK(x) (((x)&1)<<5)
267 #define v_HOR_STARTCLEAR(x) (((x)&1)<<6)
268 #define v_FRM_STARTCLEAR(x) (((x)&1)<<7)
269 #define v_SCANNING_CLEAR(x) (((x)&1)<<8)
270 #define v_SCAN_LINE_NUM(x) (((x)&0x7ff)<<9)
272 #define m_VIRWIDTH (0xffff<<0)
273 #define m_VIRHEIGHT (0xffff<<16)
274 #define v_VIRWIDTH(x) (((x)&0xffff)<<0)
275 #define v_VIRHEIGHT(x) (((x)&0xffff)<<16)
277 #define m_ACTWIDTH (0xffff<<0)
278 #define m_ACTHEIGHT (0xffff<<16)
279 #define v_ACTWIDTH(x) (((x)&0xffff)<<0)
280 #define v_ACTHEIGHT(x) (((x)&0xffff)<<16)
282 #define m_VIRST_X (0xffff<<0)
283 #define m_VIRST_Y (0xffff<<16)
284 #define v_VIRST_X(x) (((x)&0xffff)<<0)
285 #define v_VIRST_Y(x) (((x)&0xffff)<<16)
287 #define m_PANELST_X (0x3ff<<0)
288 #define m_PANELST_Y (0x3ff<<16)
289 #define v_PANELST_X(x) (((x)&0x3ff)<<0)
290 #define v_PANELST_Y(x) (((x)&0x3ff)<<16)
292 #define m_PANELWIDTH (0x3ff<<0)
293 #define m_PANELHEIGHT (0x3ff<<16)
294 #define v_PANELWIDTH(x) (((x)&0x3ff)<<0)
295 #define v_PANELHEIGHT(x) (((x)&0x3ff)<<16)
297 #define m_HWC_B (0xff<<0)
298 #define m_HWC_G (0xff<<8)
299 #define m_HWC_R (0xff<<16)
300 #define m_W0_YRGB_HSP_OFFSET (0xff<<24)
301 #define m_W0_YRGB_HSD_OFFSET (0xff<<24)
302 #define v_HWC_B(x) (((x)&0xff)<<0)
303 #define v_HWC_G(x) (((x)&0xff)<<8)
304 #define v_HWC_R(x) (((x)&0xff)<<16)
305 #define v_W0_YRGB_HSP_OFFSET(x) (((x)&0xff)<<24)
306 #define v_W0_YRGB_HSD_OFFSET(x) (((x)&0xff)<<24)
309 //Panel display scanning
310 #define m_PANEL_HSYNC_WIDTH (0x3ff<<0)
311 #define m_PANEL_HORIZONTAL_PERIOD (0x3ff<<16)
312 #define v_PANEL_HSYNC_WIDTH(x) (((x)&0x3ff)<<0)
313 #define v_PANEL_HORIZONTAL_PERIOD(x) (((x)&0x3ff)<<16)
315 #define m_PANEL_END (0x3ff<<0)
316 #define m_PANEL_START (0x3ff<<16)
317 #define v_PANEL_END(x) (((x)&0x3ff)<<0)
318 #define v_PANEL_START(x) (((x)&0x3ff)<<16)
320 #define m_PANEL_VSYNC_WIDTH (0x3ff<<0)
321 #define m_PANEL_VERTICAL_PERIOD (0x3ff<<16)
322 #define v_PANEL_VSYNC_WIDTH(x) (((x)&0x3ff)<<0)
323 #define v_PANEL_VERTICAL_PERIOD(x) (((x)&0x3ff)<<16)
326 #define m_HSCALE_FACTOR (0xffff<<0)
327 #define m_VSCALE_FACTOR (0xffff<<16)
328 #define v_HSCALE_FACTOR(x) (((x)&0xffff)<<0)
329 #define v_VSCALE_FACTOR(x) (((x)&0xffff)<<16)
331 #define m_W0_CBR_HSD_OFFSET (0xff<<0)
332 #define m_W0_CBR_HSP_OFFSET (0xff<<8)
333 #define m_W0_CBR_VSD_OFFSET (0xff<<16)
334 #define m_W0_CBR_VSP_OFFSET (0xff<<24)
335 #define v_W0_CBR_HSD_OFFSET(x) (((x)&0xff)<<0)
336 #define v_W0_CBR_HSP_OFFSET(x) (((x)&0xff)<<8)
337 #define v_W0_CBR_VSD_OFFSET(x) (((x)&0xff)<<16)
338 #define v_W0_CBR_VSP_OFFSET(x) (((x)&0xff)<<24)
341 #define FB0_IOCTL_STOP_TIMER_FLUSH 0x6001
342 #define FB0_IOCTL_SET_PANEL 0x6002
344 #define FB1_IOCTL_GET_PANEL_SIZE 0x5001
345 #define FB1_IOCTL_SET_YUV_ADDR 0x5002
346 //#define FB1_TOCTL_SET_MCU_DIR 0x5003
347 #define FB1_IOCTL_SET_ROTATE 0x5003
348 #define FB1_IOCTL_SET_I2P_ODD_ADDR 0x5005
349 #define FB1_IOCTL_SET_I2P_EVEN_ADDR 0x5006
352 /********************************************************************
354 ********************************************************************/
355 /* LCDCµÄ¼Ä´æÆ÷½á¹¹ */
356 typedef volatile struct tagLCDC_REG
358 /* offset 0x00~0xc0 */
359 unsigned int SYS_CONFIG; //SYSTEM configure register
360 unsigned int SWAP_CTRL; //Data SWAP control
361 unsigned int MCU_TIMING_CTRL; //MCU TIMING control register
362 unsigned int BLEND_CTRL; //Blending control register
363 unsigned int WIN0_COLOR_KEY_CTRL; //Win0 blending control register
364 unsigned int WIN1_COLOR_KEY_CTRL; //Win1 blending control register
365 unsigned int DEFLICKER_SCL_OFFSET; //Deflick scaling start point offset
366 unsigned int DSP_CTRL0; //Display control register0
367 unsigned int DSP_CTRL1; //Display control register1
368 unsigned int INT_STATUS; //Interrupt status register
369 unsigned int WIN0_VIR; //WIN0 virtual display width/height
370 unsigned int WIN0_YRGB_MST; //Win0 active YRGB memory start address
371 unsigned int WIN0_CBR_MST; //Win0 active Cbr memory start address
372 unsigned int WIN0_ACT_INFO; //Win0 active window width/height
373 unsigned int WIN0_ROLLER_INFO; //Win0 x and y value of start point in roller mode
374 unsigned int WIN0_DSP_ST; //Win0 display start point on panel
375 unsigned int WIN0_DSP_INFO; //Win0 display width/height on panel
376 unsigned int WIN1_VIR; //Win1 virtual display width/height
377 unsigned int WIN1_YRGB_MST; //Win1 active memory start address
378 unsigned int WIN1_ACT_INFO; //Win1 active width /height
379 unsigned int WIN1_ROLLER_INFO; //Win1 x and y value of start point in roller mode
380 unsigned int WIN1_DSP_ST; //Win1 display start point on panel
381 unsigned int WIN1_DSP_INFO; //Win1 display width/height on panel
382 unsigned int HWC_MST; //HWC memory start address
383 unsigned int HWC_DSP_ST; //HWC display start point on panel
384 unsigned int HWC_COLOR_LUT0; //Hardware cursor color 2¡¯b01 look up table 0
385 unsigned int HWC_COLOR_LUT1; //Hardware cursor color 2¡¯b10 look up table 1
386 unsigned int HWC_COLOR_LUT2; //Hardware cursor color 2¡¯b11 look up table 2
387 unsigned int DSP_HTOTAL_HS_END; //Panel scanning horizontal width and hsync pulse end point
388 unsigned int DSP_HACT_ST_END; //Panel active horizontal scanning start/end point
389 unsigned int DSP_VTOTAL_VS_END; //Panel scanning vertical height and vsync pulse end point
390 unsigned int DSP_VACT_ST_END; //Panel active vertical scanning start/end point
391 unsigned int DSP_VS_ST_END_F1; //Vertical scanning start point and vsync pulse end point of even filed in interlace mode
392 unsigned int DSP_VACT_ST_END_F1; //Vertical scanning active start/end point of even filed in interlace mode
393 unsigned int WIN0_SD_FACTOR_Y; //Win0 YRGB scaling down factor setting
394 unsigned int WIN0_SP_FACTOR_Y; //Win0 YRGB scaling up factor setting
395 unsigned int WIN0_CBR_SCL_OFFSET; //Win0 Cbr scaling start point offset
396 unsigned int WIN1_SCL_FACTOR; //Win1 scaling factor setting
397 unsigned int I2P_REF0_MST_Y; //I2P field 0 memory start address
398 unsigned int I2P_REF0_MST_CBR; //I2P field 0 memory start address
399 unsigned int I2P_REF1_MST_Y; //I2P field 2 memory start address
400 unsigned int I2P_REF1_MST_CBR; //I2P field 2 memory start address
401 unsigned int WIN0_YRGB_VIR_MST; //Win0 virtual memory start address
402 unsigned int WIN0_CBR_VIR_MST; //Win0 virtual memory start address
403 unsigned int WIN1_VIR_MST; //Win1 virtual memory start address
404 unsigned int WIN0_SD_FACTOR_CBR; //Win0 CBR scaling down factor setting
405 unsigned int WIN0_SP_FACTOR_CBR; //Win0 CBR scaling up factor setting
406 unsigned int reserved0;
407 unsigned int REG_CFG_DONE; //REGISTER CONFIG FINISH
408 unsigned int reserved1[(0x500-0xc4)/4];
409 unsigned int MCU_BYPASS_WPORT; //MCU BYPASS MODE, DATA Write Port
410 } LCDC_REG, *pLCDC_REG;
413 extern void __init rk2818_add_device_lcdc(void);
414 extern int mcu_ioctl(unsigned int cmd, unsigned long arg);