1 /* drivers/video/rk29_fb.h
3 * Copyright (C) 2010 ROCKCHIP, Inc.
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
16 #ifndef __ARCH_ARM_MACH_RK29_FB_H
17 #define __ARCH_ARM_MACH_RK29_FB_H
19 /********************************************************************
21 ********************************************************************/
22 /* ÊäÍùÆÁµÄÊý¾Ý¸ñʽ */
24 #define OUT_P666 1 //666µÄÆÁ, ½ÓDATA0-17
25 #define OUT_P565 2 //565µÄÆÁ, ½ÓDATA0-15
29 #define OUT_S888DUMY 12
30 #define OUT_P16BPP4 24 //Ä£Äⷽʽ,¿ØÖÆÆ÷²¢²»Ö§³Ö
31 #define OUT_D888_P666 0x21 //666µÄÆÁ, ½ÓDATA2-7, DATA10-15, DATA17-22
32 #define OUT_D888_P565 0x22 //565µÄÆÁ, ½ÓDATA3-7, DATA10-15, DATA18-22
35 #define m_W2_FORMAT (3<<0)
36 #define m_W1_FORMAT (1<<2)
37 #define m_W0_FORMAT (7<<3)
38 #define m_W0_CBR_DEFLICK_EN (1<<6)
39 #define m_W0_YRGB_DEFLICK_EN (1<<7)
40 #define m_INTERIACE_EN (1<<8)
41 #define m_W2_ENABLE (1<<9)
42 #define m_W1_ENABLE (1<<10)
43 #define m_W0_ENABLE (1<<11)
44 #define m_HWC_ENABLE (1<<12)
45 #define m_HWC_RELOAD_EN (1<<13)
46 #define m_W2_INTERLACE_READ (1<<14)
47 #define m_W1_INTERLACE_READ (1<<15)
48 #define m_W0_INTERLACE_READ (1<<16)
49 #define m_STANDBY (1<<17)
50 #define m_HWC_BURST (3<<18)
51 #define m_W2_BURST (3<<20)
52 #define m_W1_BURST (3<<22)
53 #define m_W0_BURST (3<<24)
54 #define m_W2_LUT_CTL (1<<26)
55 #define m_DSIP_LUT_CTL (1<<27)
56 #define m_HWC_REVERSED_COLOR (1<<28)
57 #define m_W1_AXI_OUTSTANDING2 (1<<29)
58 #define m_W0_AXI_OUTSTANDING2 (1<<30)
60 #define v_W2_FORMAT(x) (((x)&3)<<0)
61 #define v_W1_FORMAT(x) (((x)&1)<<2)
62 #define v_W0_FORMAT(x) (((x)&7)<<3)
63 #define v_W0_CBR_DEFLICK_EN(x) (((x)&1)<<6)
64 #define v_W0_YRGB_DEFLICK_EN(x) (((x)&1)<<7)
65 #define v_INTERIACE_EN(x) (((x)&1)<<8)
66 #define v_W2_ENABLE(x) (((x)&)1<<9)
67 #define v_W1_ENABLE(x) (((x)&1)<<10)
68 #define v_W0_ENABLE(x) (((x)&1)<<11)
69 #define v_HWC_ENABLE(x) (((x)&1)<<12)
70 #define v_HWC_RELOAD_EN(x) (((x)&1)<<13)
71 #define v_W2_INTERLACE_READ(x) (((x)&1)<<14)
72 #define v_W1_INTERLACE_READ(x) (((x)&1)<<15)
73 #define v_W0_INTERLACE_READ(x) (((x)&1)<<16)
74 #define v_STANDBY(x) (((x)&1)<<17)
75 #define v_HWC_BURST(x) (((x)&3)<<18)
76 #define v_W2_BURST(x) (((x)&3)<<20)
77 #define v_W1_BURST(x) (((x)&3)<<22)
78 #define v_W0_BURST(x) (((x)&3)<<24)
79 #define v_W2_LUT_CTL(x) (((x)&1)<<26)
80 #define v_DSIP_LUT_CTL(x) (((x)&1)<<27)
81 #define v_HWC_REVERSED_COLOR(x) (((x)&1)<<28)
82 #define v_W1_AXI_OUTSTANDING2(x) (((x)&1)<<29)
83 #define v_W0_AXI_OUTSTANDING2(x) (((x)&1)<<30)
86 #define m_W1_565_RB_SWAP (1<<0)
87 #define m_W0_565_RB_SWAP (1<<1)
88 #define m_W0_YRGB_M8_SWAP (1<<2)
89 #define m_W0_YRGB_R_SHIFT_SWAP (1<<3)
90 #define m_W0_CBR_R_SHIFT_SWAP (1<<4)
91 #define m_W0_YRGB_16_SWAP (1<<5)
92 #define m_W0_YRGB_8_SWAP (1<<6)
93 #define m_W0_CBR_16_SWAP (1<<7)
94 #define m_W0_CBR_8_SWAP (1<<8)
95 #define m_W1_16_SWAP (1<<9)
96 #define m_W1_8_SWAP (1<<10)
97 #define m_W1_R_SHIFT_SWAP (1<<11)
98 #define m_OUTPUT_BG_SWAP (1<<12)
99 #define m_OUTPUT_RB_SWAP (1<<13)
100 #define m_OUTPUT_RG_SWAP (1<<14)
101 #define m_DELTA_SWAP (1<<15)
102 #define m_DUMMY_SWAP (1<<16)
103 #define m_W2_BYTE_SWAP (1<<17)
104 #define v_W1_565_RB_SWAP(x) (((x)&1)<<0)
105 #define v_W0_565_RB_SWAP(x) (((x)&1)<<1)
106 #define v_W0_YRGB_M8_SWAP(x) (((x)&1)<<2)
107 #define v_W0_YRGB_R_SHIFT_SWAP(x) (((x)&1)<<3)
108 #define v_W0_CBR_R_SHIFT_SWAP(x) (((x)&1)<<4)
109 #define v_W0_YRGB_16_SWAP(x) (((x)&1)<<5)
110 #define v_W0_YRGB_8_SWAP(x) (((x)&1)<<6)
111 #define v_W0_CBR_16_SWAP(x) (((x)&1)<<7)
112 #define v_W0_CBR_8_SWAP(x) (((x)&1)<<8)
113 #define v_W1_16_SWAP(x) (((x)&1)<<9)
114 #define v_W1_8_SWAP(x) (((x)&1)<<10)
115 #define v_W1_R_SHIFT_SWAP(x) (((x)&1)<<11)
116 #define v_OUTPUT_BG_SWAP(x) (((x)&1)<<12)
117 #define v_OUTPUT_RB_SWAP(x) (((x)&1)<<13)
118 #define v_OUTPUT_RG_SWAP(x) (((x)&1)<<14)
119 #define v_DELTA_SWAP(x) (((x)&1)<<15)
120 #define v_DUMMY_SWAP(x) (((x)&1)<<16)
121 #define v_W2_BYTE_SWAP(x) (((x)&1)<<17)
123 //LCDC_MCU_TIMING_CTRL
124 #define m_MCU_WRITE_PERIOD (31<<0)
125 #define m_MCU_CS_ST (31<<5)
126 #define m_MCU_CS_END (31<<10)
127 #define m_MCU_RW_ST (31<<15)
128 #define m_MCU_RW_END (31<<20)
129 #define m_MCU_HOLDMODE_SELECT (1<<27)
130 #define m_MCU_HOLDMODE_FRAME_ST (1<<28)
131 #define m_MCU_RS_SELECT (1<<29)
132 #define m_MCU_BYPASSMODE_SELECT (1<<30)
133 #define m_MCU_OUTPUT_SELECT (1<<31)
134 #define v_MCU_WRITE_PERIOD(x) (((x)&31)<<0)
135 #define v_MCU_CS_ST(x) (((x)&31)<<5)
136 #define v_MCU_CS_END(x) (((x)&31)<<10)
137 #define v_MCU_RW_ST(x) (((x)&31)<<15)
138 #define v_MCU_RW_END(x) (((x)&31)<<20)
139 #define v_MCU_HOLD_STATUS(x) (((x)&1)<<26)
140 #define v_MCU_HOLDMODE_SELECT(x) (((x)&1)<<27)
141 #define v_MCU_HOLDMODE_FRAME_ST(x) (((x)&1)<<28)
142 #define v_MCU_RS_SELECT(x) (((x)&1)<<29)
143 #define v_MCU_BYPASSMODE_SELECT(x) (((x)&1)<<30)
144 #define v_MCU_OUTPUT_SELECT(x) (((x)&1)<<31)
147 #define m_HWC_BLEND_EN (1<<0)
148 #define m_W2_BLEND_EN (1<<1)
149 #define m_W1_BLEND_EN (1<<2)
150 #define m_W0_BLEND_EN (1<<3)
151 #define m_HWC_BLEND_FACTOR (15<<4)
152 #define m_W2_BLEND_FACTOR (0xff<<8)
153 #define m_W1_BLEND_FACTOR (0xff<<16)
154 #define m_W0_BLEND_FACTOR (0xff<<24)
156 #define v_HWC_BLEND_EN(x) (((x)&1)<<0)
157 #define v_W2_BLEND_EN(x) (((x)&1)<<1)
158 #define v_W1_BLEND_EN(x) (((x)&1)<<2)
159 #define v_W0_BLEND_EN(x) (((x)&1)<<3)
160 #define v_HWC_BLEND_FACTOR(x) (((x)&15)<<4)
161 #define v_W2_BLEND_FACTOR(x) (((x)&0xff)<<8)
162 #define v_W1_BLEND_FACTOR(x) (((x)&0xff)<<16)
163 #define v_W0_BLEND_FACTOR(x) (((x)&0xff)<<24)
166 //LCDC_WIN0_COLOR_KEY_CTRL / LCDC_WIN1_COLOR_KEY_CTRL
167 #define m_KEYCOLOR (0xffffff<<0)
168 #define m_KEYCOLOR_B (0xff<<0)
169 #define m_KEYCOLOR_G (0xff<<8)
170 #define m_KEYCOLOR_R (0xff<<16)
171 #define m_COLORKEY_EN (1<<24)
172 #define v_KEYCOLOR(x) (((x)&0xffffff)<<0)
173 #define v_KEYCOLOR_B(x) (((x)&0xff)<<0)
174 #define v_KEYCOLOR_G(x) (((x)&0xff)<<8)
175 #define v_KEYCOLOR_R(x) (((x)&0xff)<<16)
176 #define v_COLORKEY_EN(x) (((x)&1)<<24)
178 //LCDC_DEFLICKER_SCL_OFFSET
179 #define m_W0_YRGB_VSD_OFFSET (0xff<<0)
180 #define m_W0_YRGB_VSP_OFFSET (0xff<<8)
181 #define m_W1_VSD_OFFSET (0xff<<16)
182 #define m_W1_VSP_OFFSET (0xff<<24)
183 #define v_W0_YRGB_VSD_OFFSET(x) (((x)&0xff)<<0)
184 #define v_W0_YRGB_VSP_OFFSET(x) (((x)&0xff)<<8)
185 #define v_W1_VSD_OFFSET(x) (((x)&0xff)<<16)
186 #define v_W1_VSP_OFFSET(x) (((x)&0xff)<<24)
189 #define m_DISPLAY_FORMAT (0xf<<0)
190 #define m_HSYNC_POLARITY (1<<4)
191 #define m_VSYNC_POLARITY (1<<5)
192 #define m_DEN_POLARITY (1<<6)
193 #define m_DCLK_POLARITY (1<<7)
194 #define m_COLOR_SPACE_CONVERSION (3<<8)
195 #define m_DITHER_UP_EN (1<<10)
196 #define m_DITHER_DOWN_MODE (1<<11)
197 #define m_DITHER_DOWN_EN (1<<12)
198 #define m_INTERLACE_FIELD_POLARITY (1<<13)
199 #define m_YUV_CLIP (1<<14)
200 #define m_W1_TRANSP_FROM (1<<15)
201 #define m_W0_TRANSP_FROM (1<<16)
202 #define m_W0_ON_TOP (1<<17)
203 #define m_W1_CLIP_EN (1<<18)
204 #define m_W0_CLIP_EN (1<<19)
205 #define m_W0_YCBR_PRIORITY_MODE (1<<20)
206 #define m_CBR_FILTER_656 (1<<21)
207 #define m_W2_CHIP_EN (1<<22)
209 #define v_DISPLAY_FORMAT(x) (((x)&0xf)<<0)
210 #define v_HSYNC_POLARITY(x) (((x)&1)<<4)
211 #define v_VSYNC_POLARITY(x) (((x)&1)<<5)
212 #define v_DEN_POLARITY(x) (((x)&1)<<6)
213 #define v_DCLK_POLARITY(x) (((x)&1)<<7)
214 #define v_COLOR_SPACE_CONVERSION(x) (((x)&3)<<8)
215 #define v_DITHER_UP_EN(x) (((x)&1)<<10)
216 #define v_DITHER_DOWN_MODE(x) (((x)&1)<<11)
217 #define v_DITHER_DOWN_EN(x) (((x)&1)<<12)
218 #define v_INTERLACE_FIELD_POLARITY(x) (((x)&1)<<13)
219 #define v_YUV_CLIP(x) (((x)&1)<<14)
220 #define v_W1_TRANSP_FROM(x) (((x)&1)<<15)
221 #define v_W0_TRANSP_FROM(x) (((x)&1)<<16)
222 #define v_W0_ON_TOP(x) (((x)&1)<<17)
223 #define v_W1_CLIP_EN(x) (((x)&1)<<18)
224 #define v_W0_CLIP_EN(x) (((x)&1)<<19)
225 #define v_W0_YCBR_PRIORITY_MODE(x) (((x)&1)<<20)
226 #define v_CBR_FILTER_656(x) (((x)&1)<<21)
227 #define v_W2_CHIP_EN(x) (((x)&1)<<22)
231 #define m_BG_COLOR (0xffffff<<0)
232 #define m_BG_B (0xff<<0)
233 #define m_BG_G (0xff<<8)
234 #define m_BG_R (0xff<<16)
235 #define m_BLANK_MODE (1<<24)
236 #define m_BLACK_MODE (1<<25)
237 #define m_DISP_FILTER_FACTOR (3<<26)
238 #define m_DISP_FILTER_MODE (1<<28)
239 #define m_DISP_FILTER_EN (1<<29)
240 #define v_BG_COLOR(x) (((x)&0xffffff)<<0)
241 #define v_BG_B(x) (((x)&0xff)<<0)
242 #define v_BG_G(x) (((x)&0xff)<<8)
243 #define v_BG_R(x) (((x)&0xff)<<16)
244 #define v_BLANK_MODE(x) (((x)&1)<<24)
245 #define v_BLACK_MODE(x) (((x)&1)<<25)
246 #define v_DISP_FILTER_FACTOR(x) (((x)&3)<<26)
247 #define v_DISP_FILTER_MODE(x) (((x)&1)<<28)
248 #define v_DISP_FILTER_EN(x) (((x)&1)<<29)
251 #define m_HOR_START (1<<0)
252 #define m_FRM_START (1<<1)
253 #define m_SCANNING_FLAG (1<<2)
254 #define m_HOR_STARTMASK (1<<3)
255 #define m_FRM_STARTMASK (1<<4)
256 #define m_SCANNING_MASK (1<<5)
257 #define m_HOR_STARTCLEAR (1<<6)
258 #define m_FRM_STARTCLEAR (1<<7)
259 #define m_SCANNING_CLEAR (1<<8)
260 #define m_SCAN_LINE_NUM (0x7ff<<9)
261 #define v_HOR_START(x) (((x)&1)<<0)
262 #define v_FRM_START(x) (((x)&1)<<1)
263 #define v_SCANNING_FLAG(x) (((x)&1)<<2)
264 #define v_HOR_STARTMASK(x) (((x)&1)<<3)
265 #define v_FRM_STARTMASK(x) (((x)&1)<<4)
266 #define v_SCANNING_MASK(x) (((x)&1)<<5)
267 #define v_HOR_STARTCLEAR(x) (((x)&1)<<6)
268 #define v_FRM_STARTCLEAR(x) (((x)&1)<<7)
269 #define v_SCANNING_CLEAR(x) (((x)&1)<<8)
270 #define v_SCAN_LINE_NUM(x) (((x)&0x7ff)<<9)
273 #define m_W0_YRGB_CH_ID (0xF<<0)
274 #define m_W0_CBR_CH_ID (0xF<<4)
275 #define m_W1_YRGB_CH_ID (0xF<<8)
276 #define m_W2_CH_ID (0xF<<12)
277 #define m_HWC_CH_ID (0xF<<16)
278 #define v_W0_YRGB_CH_ID(x) (((x)&0xF)<<0)
279 #define v_W0_CBR_CH_ID(x) (((x)&0xF)<<4)
280 #define v_W1_YRGB_CH_ID(x) (((x)&0xF)<<8)
281 #define v_W2_CH_ID(x) (((x)&0xF)<<12)
282 #define v_HWC_CH_ID(x) (((x)&0xF)<<16)
286 #define m_WORDLO (0xffff<<0)
287 #define m_WORDHI (0xffff<<16)
288 #define v_WORDLO(x) (((x)&0xffff)<<0)
289 #define v_WORDHI(x) (((x)&0xffff)<<16)
291 #define m_BIT11LO (0x7ff<<0)
292 #define m_BIT11HI (0x7ff<<16)
293 #define v_BIT11LO(x) (((x)&0x7ff)<<0)
294 #define v_BIT11HI(x) (((x)&0x7ff)<<16)
296 #define m_BIT12LO (0xfff<<0)
297 #define m_BIT12HI (0xfff<<16)
298 #define v_BIT12LO(x) (((x)&0xfff)<<0)
299 #define v_BIT12HI(x) (((x)&0xfff)<<16)
302 #define m_VIRWIDTH (0xffff<<0)
303 #define m_VIRHEIGHT (0xffff<<16)
304 #define v_VIRWIDTH(x) (((x)&0xffff)<<0)
305 #define v_VIRHEIGHT(x) (((x)&0xffff)<<16)
307 #define m_ACTWIDTH (0xffff<<0)
308 #define m_ACTHEIGHT (0xffff<<16)
309 #define v_ACTWIDTH(x) (((x)&0xffff)<<0)
310 #define v_ACTHEIGHT(x) (((x)&0xffff)<<16)
312 #define m_VIRST_X (0xffff<<0)
313 #define m_VIRST_Y (0xffff<<16)
314 #define v_VIRST_X(x) (((x)&0xffff)<<0)
315 #define v_VIRST_Y(x) (((x)&0xffff)<<16)
317 #define m_PANELST_X (0x3ff<<0)
318 #define m_PANELST_Y (0x3ff<<16)
319 #define v_PANELST_X(x) (((x)&0x3ff)<<0)
320 #define v_PANELST_Y(x) (((x)&0x3ff)<<16)
322 #define m_PANELWIDTH (0x3ff<<0)
323 #define m_PANELHEIGHT (0x3ff<<16)
324 #define v_PANELWIDTH(x) (((x)&0x3ff)<<0)
325 #define v_PANELHEIGHT(x) (((x)&0x3ff)<<16)
327 #define m_HWC_B (0xff<<0)
328 #define m_HWC_G (0xff<<8)
329 #define m_HWC_R (0xff<<16)
330 #define m_W0_YRGB_HSP_OFFSET (0xff<<24)
331 #define m_W0_YRGB_HSD_OFFSET (0xff<<24)
332 #define v_HWC_B(x) (((x)&0xff)<<0)
333 #define v_HWC_G(x) (((x)&0xff)<<8)
334 #define v_HWC_R(x) (((x)&0xff)<<16)
335 #define v_W0_YRGB_HSP_OFFSET(x) (((x)&0xff)<<24)
336 #define v_W0_YRGB_HSD_OFFSET(x) (((x)&0xff)<<24)
339 //Panel display scanning
340 #define m_PANEL_HSYNC_WIDTH (0x3ff<<0)
341 #define m_PANEL_HORIZONTAL_PERIOD (0x3ff<<16)
342 #define v_PANEL_HSYNC_WIDTH(x) (((x)&0x3ff)<<0)
343 #define v_PANEL_HORIZONTAL_PERIOD(x) (((x)&0x3ff)<<16)
345 #define m_PANEL_END (0x3ff<<0)
346 #define m_PANEL_START (0x3ff<<16)
347 #define v_PANEL_END(x) (((x)&0x3ff)<<0)
348 #define v_PANEL_START(x) (((x)&0x3ff)<<16)
350 #define m_PANEL_VSYNC_WIDTH (0x3ff<<0)
351 #define m_PANEL_VERTICAL_PERIOD (0x3ff<<16)
352 #define v_PANEL_VSYNC_WIDTH(x) (((x)&0x3ff)<<0)
353 #define v_PANEL_VERTICAL_PERIOD(x) (((x)&0x3ff)<<16)
356 #define m_HSCALE_FACTOR (0xffff<<0)
357 #define m_VSCALE_FACTOR (0xffff<<16)
358 #define v_HSCALE_FACTOR(x) (((x)&0xffff)<<0)
359 #define v_VSCALE_FACTOR(x) (((x)&0xffff)<<16)
361 #define m_W0_CBR_HSD_OFFSET (0xff<<0)
362 #define m_W0_CBR_HSP_OFFSET (0xff<<8)
363 #define m_W0_CBR_VSD_OFFSET (0xff<<16)
364 #define m_W0_CBR_VSP_OFFSET (0xff<<24)
365 #define v_W0_CBR_HSD_OFFSET(x) (((x)&0xff)<<0)
366 #define v_W0_CBR_HSP_OFFSET(x) (((x)&0xff)<<8)
367 #define v_W0_CBR_VSD_OFFSET(x) (((x)&0xff)<<16)
368 #define v_W0_CBR_VSP_OFFSET(x) (((x)&0xff)<<24)
371 #define FB0_IOCTL_STOP_TIMER_FLUSH 0x6001
372 #define FB0_IOCTL_SET_PANEL 0x6002
374 #define FB1_IOCTL_GET_PANEL_SIZE 0x5001
375 #define FB1_IOCTL_SET_YUV_ADDR 0x5002
376 //#define FB1_TOCTL_SET_MCU_DIR 0x5003
377 #define FB1_IOCTL_SET_ROTATE 0x5003
378 #define FB1_IOCTL_SET_I2P_ODD_ADDR 0x5005
379 #define FB1_IOCTL_SET_I2P_EVEN_ADDR 0x5006
380 #define FB1_IOCTL_SET_WIN0_TOP 0x5018
383 /********************************************************************
385 ********************************************************************/
386 /* LCDCµÄ¼Ä´æÆ÷½á¹¹ */
388 typedef volatile struct tagLCDC_REG
390 /* offset 0x00~0xc0 */
391 unsigned int SYS_CONFIG; //0x00 SYSTEM configure register
392 unsigned int SWAP_CTRL; //0x04 Data SWAP control
393 unsigned int MCU_TIMING_CTRL; //0x08 MCU TIMING control register
394 unsigned int BLEND_CTRL; //0x0c Blending control register
395 unsigned int WIN0_COLOR_KEY_CTRL; //0x10 Win0 blending control register
396 unsigned int WIN1_COLOR_KEY_CTRL; //0x14 Win1 blending control register
397 unsigned int WIN2_VIR; //0x18 WIN2 virtual display width
398 unsigned int DSP_CTRL0; //0x1c Display control register0
399 unsigned int DSP_CTRL1; //0x20 Display control register1
400 unsigned int INT_STATUS; //0x24 Interrupt status register
401 unsigned int WIN0_VIR; //0x28 WIN0 virtual display width/height
402 unsigned int WIN0_YRGB_MST; //0x2c Win0 active YRGB memory start address
403 unsigned int WIN0_CBR_MST; //0x30 Win0 active Cbr memory start address
404 unsigned int WIN0_ACT_INFO; //0x34 Win0 active window width/height
405 unsigned int WIN0_DSP_ST; //0x38 Win0 display start point on panel
406 unsigned int WIN0_DSP_INFO; //0x3c Win0 display width/height on panel
407 unsigned int WIN1_VIR; //0x40 Win1 virtual display width/height
408 unsigned int WIN1_YRGB_MST; //0x44 Win1 active memory start address
409 unsigned int WIN1_DSP_INFO; //0x48 Win1 display width/height on panel
410 unsigned int WIN1_DSP_ST; //0x4c Win1 display start point on panel
411 unsigned int WIN2_MST; //0X50 Win2 memory start address
412 unsigned int WIN2_DSP_INFO; //0x54 Win1 display width/height on panel
413 unsigned int WIN2_DSP_ST; //0x58 Win1 display start point on panel
414 unsigned int HWC_MST; //0x5C HWC memory start address
415 unsigned int HWC_DSP_ST; //0x60 HWC display start point on panel
416 unsigned int HWC_COLOR_LUT0; //0x64 Hardware cursor color 2¡¯b01 look up table 0
417 unsigned int HWC_COLOR_LUT1; //0x68 Hardware cursor color 2¡¯b10 look up table 1
418 unsigned int HWC_COLOR_LUT2; //0x6c Hardware cursor color 2¡¯b11 look up table 2
419 unsigned int DSP_HTOTAL_HS_END; //0x70 Panel scanning horizontal width and hsync pulse end point
420 unsigned int DSP_HACT_ST_END; //0x74 Panel active horizontal scanning start/end point
421 unsigned int DSP_VTOTAL_VS_END; //0x78 Panel scanning vertical height and vsync pulse end point
422 unsigned int DSP_VACT_ST_END; //0x7c Panel active vertical scanning start/end point
423 unsigned int DSP_VS_ST_END_F1; //0x80 Vertical scanning start point and vsync pulse end point of even filed in interlace mode
424 unsigned int DSP_VACT_ST_END_F1; //0x84 Vertical scanning active start/end point of even filed in interlace mode
425 unsigned int WIN0_SCL_FACTOR_YRGB; //0x88 Win0 YRGB scaling down factor setting
426 unsigned int WIN0_SCL_FACTOR_CBR; //0x8c Win0 YRGB scaling up factor setting
427 unsigned int WIN0_SCL_OFFSET; //0x90 Win0 Cbr scaling start point offset
428 unsigned int FIFO_WATER_MARK; //0x94 Fifo water mark
429 unsigned int AXI_MS_ID; //0x98 Axi master ID
430 unsigned int reserved0; //0x9c
431 unsigned int REG_CFG_DONE; //0xa0 REGISTER CONFIG FINISH
432 unsigned int reserved1[(0x100-0xa4)/4];
433 unsigned int MCU_BYPASS_WPORT; //0x100 MCU BYPASS MODE, DATA Write Only Port
434 unsigned int reserved2[(0x200-0x104)/4];
435 unsigned int MCU_BYPASS_RPORT; //0x200 MCU BYPASS MODE, DATA Read Only Port
436 } LCDC_REG, *pLCDC_REG;
439 extern void __init rk29_add_device_lcdc(void);
440 extern int mcu_ioctl(unsigned int cmd, unsigned long arg);