4 #include<linux/rk_fb.h>
6 #define LcdReadBit(inf, addr, msk) ((inf->regbak.addr=inf->preg->addr)&(msk))
7 #define LcdWrReg(inf, addr, val) inf->preg->addr=inf->regbak.addr=(val)
8 #define LcdRdReg(inf, addr) (inf->preg->addr)
9 #define LcdSetBit(inf, addr, msk) inf->preg->addr=((inf->regbak.addr) |= (msk))
10 #define LcdClrBit(inf, addr, msk) inf->preg->addr=((inf->regbak.addr) &= ~(msk))
11 #define LcdSetRegBit(inf, addr, msk) inf->preg->addr=((inf->preg->addr) |= (msk))
12 #define LcdMskReg(inf, addr, msk, val) (inf->regbak.addr)&=~(msk); inf->preg->addr=(inf->regbak.addr|=(val))
13 #define LCDC_REG_CFG_DONE() LcdWrReg(lcdc_dev, REG_CFG_DONE, 0x01); dsb()
15 /********************************************************************
17 ********************************************************************/
18 /* LCDCµÄ¼Ä´æÆ÷½á¹¹ */
20 typedef volatile struct tagLCDC_REG
22 /* offset 0x00~0xc0 */
23 unsigned int SYS_CFG; //0x00 system config register
24 unsigned int DSP_CTRL; //0x0c display control register
25 unsigned int BG_COLOR; //back ground color register
26 unsigned int ALPHA_CTRL; //alpha control register
27 unsigned int INT_STATUS; //0x10 Interrupt status register
28 unsigned int WIN0_COLOR_KEY_CTRL; //0x1c Win0 blending control register
29 unsigned int WIN1_COLOR_KEY_CTRL; //0x20 Win1 blending control register
30 unsigned int WIN0_YRGB_MST; //0x28 Win0 active YRGB memory start address0
31 unsigned int WIN0_CBR_MST; //0x2c Win0 active Cbr memory start address0
32 unsigned int WIN_VIR; //0x38 WIN0 virtual display width/height
33 unsigned int WIN0_ACT_INFO; //0x3C Win0 active window width/height
34 unsigned int WIN0_DSP_INFO; //0x40 Win0 display width/height on panel
35 unsigned int WIN0_DSP_ST; //0x44 Win0 display start point on panel
36 unsigned int WIN0_SCL_FACTOR_YRGB; //0x48Win0 YRGB scaling factor setting
37 unsigned int WIN0_SCL_FACTOR_CBR; //0x4c Win0 YRGB scaling factor setting
38 unsigned int WIN0_SCL_OFFSET; //0x50 Win0 Cbr scaling start point offset
39 unsigned int WIN1_RGB_MST; //0x54 Win1 active YRGB memory start address
40 unsigned int WIN1_DSP_INFO; //0x64 Win1 display width/height on panel
41 unsigned int WIN1_DSP_ST; //0x68 Win1 display start point on panel
42 unsigned int HWC_MST; //0x88 HWC memory start address
43 unsigned int HWC_DSP_ST; //0x8C HWC display start point on panel
44 unsigned int HWC_COLOR_LUT0; //0x90 Hardware cursor color 2¡¯b01 look up table 0
45 unsigned int HWC_COLOR_LUT1; //0x94 Hardware cursor color 2¡¯b10 look up table 1
46 unsigned int HWC_COLOR_LUT2; //0x98 Hardware cursor color 2¡¯b11 look up table 2
47 unsigned int DSP_HTOTAL_HS_END; //0x9c Panel scanning horizontal width and hsync pulse end point
48 unsigned int DSP_HACT_ST_END; //0xa0 Panel active horizontal scanning start/end point
49 unsigned int DSP_VTOTAL_VS_END; //0xa4 Panel scanning vertical height and vsync pulse end point
50 unsigned int DSP_VACT_ST_END; //0xa8 Panel active vertical scanning start/end point
51 unsigned int SCL_REG0; //scaler register
52 unsigned int SCL_REG1;
53 unsigned int SCL_REG2;
54 unsigned int SCL_REG3;
55 unsigned int SCL_REG4;
56 unsigned int SCL_REG5;
57 unsigned int SCL_REG6;
58 unsigned int SCL_REG7;
59 unsigned int SCL_REG8;
60 unsigned int reserve[3];
61 unsigned int REG_CFG_DONE; //0xc0 REGISTER CONFIG FINISH
63 } LCDC_REG, *pLCDC_REG;
68 #define m_W0_EN (1<<0)
69 #define m_W1_EN (1<<1)
70 #define m_HWC_EN (1<<2)
71 #define m_W0_FORMAT (7<<3)
72 #define m_W1_FORMAT (7<<6)
74 #define m_W0_AXI_OUTSTANDING_DISABLE (1<<16)
75 #define m_W1_AXI_OUTSTANDING_DISABLE (1<<17)
76 #define m_DMA_BURST_LENGTH (3<<18)
77 #define m_LCDC_STANDBY (1<<22)
79 #define m_LCDC_AXICLK_AUTO_ENABLE (1<<24) //eanble for low power
81 #define v_W0_EN(x) (((x)&1)<<0)
82 #define v_W1_EN(x) (((x)&1)<<1)
83 #define v_HWC_EN(x) (((x)&1)<<2)
84 #define v_W0_FORMAT(x) (((x)&7)<<3)
85 #define v_W1_FORMAT(x) (((x)&7)<<6)
86 #define v_LCDC_STANDBY(x) (((x)&1)<<22)
88 #define v_LCDC_AXICLK_AUTO_ENABLE(x) (((x)&1)<<24)
90 #define v_LCDC_DMA_STOP(x) (((x)&1)<<0)
91 #define v_HWC_RELOAD_EN(x) (((x)&1)<<2)
92 #define v_W0_AXI_OUTSTANDING_DISABLE(x) (((x)&1)<<3)
93 #define v_W1_AXI_OUTSTANDING_DISABLE(x) (((x)&1)<<4)
94 #define v_W2_AXI_OUTSTANDING_DISABLE(x) (((x)&1)<<5)
95 #define v_DMA_BURST_LENGTH(x) (((x)&3)<<6)
96 #define v_WIN0_YRGB_CHANNEL0_ID(x) (((x)&7)<<8)
97 #define v_WIN0_CBR_CHANNEL0_ID(x) (((x)&7)<<11)
98 #define v_WIN0_YRGB_CHANNEL1_ID(x) (((x)&7)<<14)
99 #define v_WIN0_CBR_CHANNEL1_ID(x) (((x)&7)<<17)
100 #define v_WIN1_YRGB_CHANNEL_ID(x) (((x)&7)<<20)
101 #define v_WIN1_CBR_CHANNEL_ID(x) (((x)&7)<<23)
102 #define v_WIN2_CHANNEL_ID(x) (((x)&7)<<26)
103 #define v_HWC_CHANNEL_ID(x) (((x)&7)<<29)
108 #define m_DISPLAY_FORMAT (3<<0)
109 #define m_BLANK_MODE (1<<2)
110 #define m_BLACK_MODE (1<<3)
111 #define m_HSYNC_POLARITY (1<<4)
112 #define m_VSYNC_POLARITY (1<<5)
113 #define m_DEN_POLARITY (1<<6)
114 #define m_DCLK_POLARITY (1<<7)
115 #define m_W0W1_POSITION_SWAP (1<<8)
116 #define m_OUTPUT_BG_SWAP (1<<9)
117 #define m_OUTPUT_RB_SWAP (1<<10)
118 #define m_OUTPUT_RG_SWAP (1<<11)
119 #define m_DITHER_UP_EN (1<<12)
120 #define m_DITHER_DOWN_MODE (1<<13)
121 #define m_DITHER_DOWN_EN (1<<14)
124 #define m_W1_INTERLACE_READ_MODE (1<<15)
125 #define m_W2_INTERLACE_READ_MODE (1<<16)
126 #define m_W0_YRGB_DEFLICK_MODE (1<<17)
127 #define m_W0_CBR_DEFLICK_MODE (1<<18)
128 #define m_W1_YRGB_DEFLICK_MODE (1<<19)
129 #define m_W1_CBR_DEFLICK_MODE (1<<20)
130 #define m_W0_ALPHA_MODE (1<<21)
131 #define m_W1_ALPHA_MODE (1<<22)
132 #define m_W2_ALPHA_MODE (1<<23)
133 #define m_W0_COLOR_SPACE_CONVERSION (3<<24)
134 #define m_W1_COLOR_SPACE_CONVERSION (3<<26)
135 #define m_W2_COLOR_SPACE_CONVERSION (1<<28)
136 #define m_YCRCB_CLIP_EN (1<<29)
137 #define m_CBR_FILTER_656 (1<<30)
139 #define v_DISPLAY_FORMAT(x) (((x)&0x3)<<0)
140 #define v_BLANK_MODE(x) (((x)&1)<<2)
141 #define v_BLACK_MODE(x) (((x)&1)<<2)
142 #define v_HSYNC_POLARITY(x) (((x)&1)<<4)
143 #define v_VSYNC_POLARITY(x) (((x)&1)<<5)
144 #define v_DEN_POLARITY(x) (((x)&1)<<6)
145 #define v_DCLK_POLARITY(x) (((x)&1)<<7)
146 #define v_W0W1_POSITION_SWAP(x) (((x)&1)<<8)
147 #define v_OUTPUT_BG_SWAP(x) (((x)&1)<<9)
148 #define v_OUTPUT_RB_SWAP(x) (((x)&1)<<10)
149 #define v_OUTPUT_RG_SWAP(x) (((x)&1)<<11)
150 #define v_DITHER_UP_EN(x) (((x)&1)<<12)
151 #define v_DITHER_DOWN_MODE(x) (((x)&1)<<13)
152 #define v_DITHER_DOWN_EN(x) (((x)&1)<<14)
154 #define v_INTERLACE_DSP_EN(x) (((x)&1)<<12)
155 #define v_INTERLACE_FIELD_POLARITY(x) (((x)&1)<<13)
156 #define v_W0_INTERLACE_READ_MODE(x) (((x)&1)<<14)
157 #define v_W1_INTERLACE_READ_MODE(x) (((x)&1)<<15)
158 #define v_W2_INTERLACE_READ_MODE(x) (((x)&1)<<16)
159 #define v_W0_YRGB_DEFLICK_MODE(x) (((x)&1)<<17)
160 #define v_W0_CBR_DEFLICK_MODE(x) (((x)&1)<<18)
161 #define v_W1_YRGB_DEFLICK_MODE(x) (((x)&1)<<19)
162 #define v_W1_CBR_DEFLICK_MODE(x) (((x)&1)<<20)
163 #define v_W0_ALPHA_MODE(x) (((x)&1)<<21)
164 #define v_W1_ALPHA_MODE(x) (((x)&1)<<22)
165 #define v_W2_ALPHA_MODE(x) (((x)&1)<<23)
166 #define v_W0_COLOR_SPACE_CONVERSION(x) (((x)&3)<<24)
167 #define v_W1_COLOR_SPACE_CONVERSION(x) (((x)&3)<<26)
168 #define v_W2_COLOR_SPACE_CONVERSION(x) (((x)&1)<<28)
169 #define v_YCRCB_CLIP_EN(x) (((x)&1)<<29)
170 #define v_CBR_FILTER_656(x) (((x)&1)<<30)
173 #define m_BG_COLOR (0xffffff<<0)
174 #define m_BG_B (0xff<<0)
175 #define m_BG_G (0xff<<8)
176 #define m_BG_R (0xff<<16)
177 #define v_BG_COLOR(x) (((x)&0xffffff)<<0)
178 #define v_BG_B(x) (((x)&0xff)<<0)
179 #define v_BG_G(x) (((x)&0xff)<<8)
180 #define v_BG_R(x) (((x)&0xff)<<16)
186 #define m_HWC_BLEND_EN (1<<0)
187 #define m_W2_BLEND_EN (1<<1)
188 #define m_W1_BLEND_EN (1<<2)
189 #define m_W0_BLEND_EN (1<<3)
190 #define m_HWC_BLEND_FACTOR (15<<4)
191 #define m_W2_BLEND_FACTOR (0xff<<8)
192 #define m_W1_BLEND_FACTOR (0xff<<16)
193 #define m_W0_BLEND_FACTOR (0xff<<24)
195 #define v_HWC_BLEND_EN(x) (((x)&1)<<0)
196 #define v_W2_BLEND_EN(x) (((x)&1)<<1)
197 #define v_W1_BLEND_EN(x) (((x)&1)<<2)
198 #define v_W0_BLEND_EN(x) (((x)&1)<<3)
199 #define v_HWC_BLEND_FACTOR(x) (((x)&15)<<4)
200 #define v_W2_BLEND_FACTOR(x) (((x)&0xff)<<8)
201 #define v_W1_BLEND_FACTOR(x) (((x)&0xff)<<16)
202 #define v_W0_BLEND_FACTOR(x) (((x)&0xff)<<24)
205 #define v_HOR_START_INT_STA (1<<0) //status
206 #define v_FRM_START_INT_STA (1<<1)
207 #define v_LINE_FLAG_INT_STA (1<<2)
208 #define v_BUS_ERR_INT_STA (1<<3)
209 #define m_HOR_START_INT_EN (1<<4) //enable
210 #define m_FRM_START_INT_EN (1<<5)
211 #define m_LINE_FLAG_INT_EN (1<<6)
212 #define m_BUS_ERR_INT_EN (1<<7)
213 #define m_HOR_START_INT_CLEAR (1<<8) //auto clear
214 #define m_FRM_START_INT_CLEAR (1<<9)
215 #define m_LINE_FLAG_INT_CLEAR (1<<10)
216 #define m_BUS_ERR_INT_CLEAR (1<<11)
217 #define m_LINE_FLAG_NUM (0xfff<<12)
218 #define v_HOR_START_INT_EN(x) (((x)&1)<<4)
219 #define v_FRM_START_INT_EN(x) (((x)&1)<<5)
220 #define v_LINE_FLAG_INT_EN(x) (((x)&1)<<6)
221 #define v_BUS_ERR_INT_EN(x) (((x)&1)<<7)
222 #define v_HOR_START_INT_CLEAR(x) (((x)&1)<<8)
223 #define v_FRM_START_INT_CLEAR(x) (((x)&1)<<9)
224 #define v_LINE_FLAG_INT_CLEAR(x) (((x)&1)<<10)
225 #define v_BUS_ERR_INT_CLEAR(x) (((x)&1)<<11)
226 #define v_LINE_FLAG_NUM(x) (((x)&0xfff)<<12)
230 #define m_WIN0_VIR (0xfff << 0)
231 #define m_WIN1_VIR (0xfff << 16)
232 //LCDC_WINx_VIR ,x is number of words of win0 virtual width
233 #define v_WIN0_ARGB888_VIRWIDTH(x) (x)
234 #define v_WIN0_RGB888_VIRWIDTH(x) (((x*3)>>2)+((x)%3))
235 #define v_WIN0_RGB565_VIRWIDTH(x) (((x)>>1) + ((x%2)?1:0))
236 #define v_WIN0_YUV_VIRWIDTH(x) (((x)>>2) +((x%4)?1:0))
238 #define v_WIN1_ARGB888_VIRWIDTH(x) (x << 16)
239 #define v_WIN1_RGB888_VIRWIDTH(x) ((((x*3)>>2)+((x)%3)) << 16)
240 #define v_WIN1_RGB565_VIRWIDTH(x) ((((x)>>1) + ((x%2)?1:0)) << 16)
241 #define v_WIN1_YUV_VIRWIDTH(x) ((((x)>>2) +((x%4)?1:0)) << 16 )
244 //LCDC_WIN0_COLOR_KEY_CTRL / LCDC_WIN1_COLOR_KEY_CTRL
245 #define m_KEYCOLOR (0xffffff<<0)
246 #define m_KEYCOLOR_B (0xff<<0)
247 #define m_KEYCOLOR_G (0xff<<8)
248 #define m_KEYCOLOR_R (0xff<<16)
249 #define m_COLORKEY_EN (1<<24)
250 #define v_KEYCOLOR(x) (((x)&0xffffff)<<0)
251 #define v_KEYCOLOR_B(x) (((x)&0xff)<<0)
252 #define v_KEYCOLOR_G(x) (((x)&0xff)<<8)
253 #define v_KEYCOLOR_R(x) (((x)&0xff)<<16)
254 #define v_COLORKEY_EN(x) (((x)&1)<<24)
256 //LCDC_DEFLICKER_SCL_OFFSET
257 #define m_W0_YRGB_VSD_OFFSET (0xff<<0)
258 #define m_W0_YRGB_VSP_OFFSET (0xff<<8)
259 #define m_W1_VSD_OFFSET (0xff<<16)
260 #define m_W1_VSP_OFFSET (0xff<<24)
261 #define v_W0_YRGB_VSD_OFFSET(x) (((x)&0xff)<<0)
262 #define v_W0_YRGB_VSP_OFFSET(x) (((x)&0xff)<<8)
263 #define v_W1_VSD_OFFSET(x) (((x)&0xff)<<16)
264 #define v_W1_VSP_OFFSET(x) (((x)&0xff)<<24)
271 #define m_W0_YRGB_CH_ID (0xF<<0)
272 #define m_W0_CBR_CH_ID (0xF<<4)
273 #define m_W1_YRGB_CH_ID (0xF<<8)
274 #define m_W2_CH_ID (0xF<<12)
275 #define m_HWC_CH_ID (0xF<<16)
276 #define v_W0_YRGB_CH_ID(x) (((x)&0xF)<<0)
277 #define v_W0_CBR_CH_ID(x) (((x)&0xF)<<4)
278 #define v_W1_YRGB_CH_ID(x) (((x)&0xF)<<8)
279 #define v_W2_CH_ID(x) (((x)&0xF)<<12)
280 #define v_HWC_CH_ID(x) (((x)&0xF)<<16)
284 #define m_WORDLO (0xffff<<0)
285 #define m_WORDHI (0xffff<<16)
286 #define v_WORDLO(x) (((x)&0xffff)<<0)
287 #define v_WORDHI(x) (((x)&0xffff)<<16)
290 //LCDC_WINx_SCL_FACTOR_Y/CBCR
291 #define v_X_SCL_FACTOR(x) ((x)<<0)
292 #define v_Y_SCL_FACTOR(x) ((x)<<16)
294 //LCDC_DSP_HTOTAL_HS_END
295 #define v_HSYNC(x) ((x)<<0) //hsync pulse width
296 #define v_HORPRD(x) ((x)<<16) //horizontal period
299 //LCDC_DSP_HACT_ST_END
300 #define v_HAEP(x) ((x)<<0) //horizontal active end point
301 #define v_HASP(x) ((x)<<16) //horizontal active start point
303 //LCDC_DSP_VTOTAL_VS_END
304 #define v_VSYNC(x) ((x)<<0)
305 #define v_VERPRD(x) ((x)<<16)
307 //LCDC_DSP_VACT_ST_END
308 #define v_VAEP(x) ((x)<<0)
309 #define v_VASP(x) ((x)<<16)
313 #define m_ACTWIDTH (0xffff<<0)
314 #define m_ACTHEIGHT (0xffff<<16)
315 #define v_ACTWIDTH(x) (((x)&0xffff)<<0)
316 #define v_ACTHEIGHT(x) (((x)&0xffff)<<16)
318 #define m_VIRST_X (0xffff<<0)
319 #define m_VIRST_Y (0xffff<<16)
320 #define v_VIRST_X(x) (((x)&0xffff)<<0)
321 #define v_VIRST_Y(x) (((x)&0xffff)<<16)
323 #define m_PANELST_X (0x3ff<<0)
324 #define m_PANELST_Y (0x3ff<<16)
325 #define v_PANELST_X(x) (((x)&0x3ff)<<0)
326 #define v_PANELST_Y(x) (((x)&0x3ff)<<16)
328 #define m_PANELWIDTH (0x3ff<<0)
329 #define m_PANELHEIGHT (0x3ff<<16)
330 #define v_PANELWIDTH(x) (((x)&0x3ff)<<0)
331 #define v_PANELHEIGHT(x) (((x)&0x3ff)<<16)
333 #define m_HWC_B (0xff<<0)
334 #define m_HWC_G (0xff<<8)
335 #define m_HWC_R (0xff<<16)
336 #define m_W0_YRGB_HSP_OFFSET (0xff<<24)
337 #define m_W0_YRGB_HSD_OFFSET (0xff<<24)
338 #define v_HWC_B(x) (((x)&0xff)<<0)
339 #define v_HWC_G(x) (((x)&0xff)<<8)
340 #define v_HWC_R(x) (((x)&0xff)<<16)
341 #define v_W0_YRGB_HSP_OFFSET(x) (((x)&0xff)<<24)
342 #define v_W0_YRGB_HSD_OFFSET(x) (((x)&0xff)<<24)
345 #define v_ACT_WIDTH(x) ((x-1)<<0)
346 #define v_ACT_HEIGHT(x) ((x-1)<<16)
349 #define v_DSP_WIDTH(x) ((x-1)<<0)
350 #define v_DSP_HEIGHT(x) ((x-1)<<16)
352 //LCDC_WIN0_DSP_ST //x,y start point of the panel scanning
353 #define v_DSP_STX(x) (x<<0)
354 #define v_DSP_STY(x) (x<<16)
356 //Panel display scanning
357 #define m_PANEL_HSYNC_WIDTH (0x3ff<<0)
358 #define m_PANEL_HORIZONTAL_PERIOD (0x3ff<<16)
359 #define v_PANEL_HSYNC_WIDTH(x) (((x)&0x3ff)<<0)
360 #define v_PANEL_HORIZONTAL_PERIOD(x) (((x)&0x3ff)<<16)
362 #define m_PANEL_END (0x3ff<<0)
363 #define m_PANEL_START (0x3ff<<16)
364 #define v_PANEL_END(x) (((x)&0x3ff)<<0)
365 #define v_PANEL_START(x) (((x)&0x3ff)<<16)
367 #define m_PANEL_VSYNC_WIDTH (0x3ff<<0)
368 #define m_PANEL_VERTICAL_PERIOD (0x3ff<<16)
369 #define v_PANEL_VSYNC_WIDTH(x) (((x)&0x3ff)<<0)
370 #define v_PANEL_VERTICAL_PERIOD(x) (((x)&0x3ff)<<16)
373 #define m_HSCALE_FACTOR (0xffff<<0)
374 #define m_VSCALE_FACTOR (0xffff<<16)
375 #define v_HSCALE_FACTOR(x) (((x)&0xffff)<<0)
376 #define v_VSCALE_FACTOR(x) (((x)&0xffff)<<16)
378 #define m_W0_CBR_HSD_OFFSET (0xff<<0)
379 #define m_W0_CBR_HSP_OFFSET (0xff<<8)
380 #define m_W0_CBR_VSD_OFFSET (0xff<<16)
381 #define m_W0_CBR_VSP_OFFSET (0xff<<24)
382 #define v_W0_CBR_HSD_OFFSET(x) (((x)&0xff)<<0)
383 #define v_W0_CBR_HSP_OFFSET(x) (((x)&0xff)<<8)
384 #define v_W0_CBR_VSD_OFFSET(x) (((x)&0xff)<<16)
385 #define v_W0_CBR_VSP_OFFSET(x) (((x)&0xff)<<24)
389 #define m_SCL_DSP_ZERO (1<<4)
390 #define m_SCL_DEN_INVERT (1<<3)
391 #define m_SCL_SYNC_INVERT (1<<2)
392 #define m_SCL_DCLK_INVERT (1<<1)
393 #define m_SCL_EN (1<<0)
394 #define v_SCL_DSP_ZERO(x) (((x)&1)<<4)
395 #define v_SCL_DEN_INVERT(x) (((x)&1)<<3)
396 #define v_SCL_SYNC_INVERT(x) (((x)&1)<<2)
397 #define v_SCL_DCLK_INVERT(x) (((x)&1)<<1)
398 #define v_SCL_EN(x) (((x)&1)<<0)
401 #define m_SCL_V_FACTOR (0x3fff<<16)
402 #define m_SCL_H_FACTOR (0x3fff<<0)
403 #define v_SCL_V_FACTOR(x) (((x)&0x3fff)<<16)
404 #define v_SCL_H_FACTOR(x) (((x)&0x3fff)<<0)
408 #define m_SCL_DSP_FRAME_VST (0xfff<<16)
409 #define m_SCL_DSP_FRAME_HST (0xfff<<0)
410 #define v_SCL_DSP_FRAME_VST(x) (((x)&0xfff)<<16)
411 #define v_SCL_DSP_FRAME_HST(x) (((x)&0xfff)<<0)
414 #define m_SCL_DSP_HS_END (0xff<<16)
415 #define m_SCL_DSP_HTOTAL (0xfff<<0)
416 #define v_SCL_DSP_HS_END(x) (((x)&0xff)<<16)
417 #define v_SCL_DSP_HTOTAL(x) (((x)&0xfff)<<0)
420 #define m_SCL_DSP_HACT_ST (0x3ff<<16)
421 #define m_SCL_DSP_HACT_END (0xfff<<0)
422 #define v_SCL_DSP_HACT_ST(x) (((x)&0x3ff)<<16)
423 #define v_SCL_DSP_HACT_END(x) (((x)&0xfff)<<0)
426 #define m_SCL_DSP_VS_END (0xff<<16)
427 #define m_SCL_DSP_VTOTAL (0xfff<<0)
428 #define v_SCL_DSP_VS_END(x) (((x)&0xff)<<16)
429 #define v_SCL_DSP_VTOTAL(x) (((x)&0xfff)<<0)
432 #define m_SCL_DSP_VACT_ST (0xff<<16)
433 #define m_SCL_DSP_VACT_END (0xfff<<0)
434 #define v_SCL_DSP_VACT_ST(x) (((x)&0xff)<<16)
435 #define v_SCL_DSP_VACT_END(x) (((x)&0xfff)<<0)
439 #define m_SCL_DSP_HBOR_ST (0x3ff<<16)
440 #define m_SCL_DSP_HBOR_END (0xfff<<0)
441 #define v_SCL_DSP_HBOR_ST(x) (((x)&0x3ff)<<16)
442 #define v_SCL_DSP_HBOR_END(x) (((x)&0xfff)<<0)
446 #define m_SCL_DSP_VBOR_ST (0xff<<16)
447 #define m_SCL_DSP_VBOR_END (0xfff<<0)
448 #define v_SCL_DSP_VBOR_ST(x) (((x)&0xff)<<16)
449 #define v_SCL_DSP_VBOR_END(x) (((x)&0xfff)<<0)
455 #define CalScale(x, y) (((u32)(x)*0x1000)/(y))
456 struct rk2928_lcdc_device{
458 struct rk_lcdc_device_driver driver;
461 LCDC_REG *preg; // LCDC reg base address and backup reg
464 void __iomem *reg_vir_base; // virtual basic address of lcdc register
465 u32 reg_phy_base; // physical basic address of lcdc register
466 u32 len; // physical map length of lcdc register
467 spinlock_t reg_lock; //one time only one process allowed to config the register
468 bool clk_on; //if aclk or hclk is closed ,acess to register is not allowed
469 u8 atv_layer_cnt; //active layer counter,when atv_layer_cnt = 0,disable lcdc
472 struct clk *pd; //lcdc power domain
473 struct clk *hclk; //lcdc AHP clk
474 struct clk *dclk; //lcdc dclk
475 struct clk *aclk; //lcdc share memory frequency
476 struct clk *sclk; //scale clk
477 struct clk *aclk_parent; //lcdc aclk divider frequency source
478 struct clk *aclk_ddr_lcdc; //DDR LCDC AXI clock disable.
479 struct clk *aclk_disp_matrix; //DISPLAY matrix AXI clock disable.
480 struct clk *hclk_cpu_display; //CPU DISPLAY AHB bus clock disable.
481 struct clk *pd_display; // display power domain
487 struct rk2928_lcdc_device lcdc0;
493 volatile u32 y_offset;
494 volatile u32 c_offset;
502 u32 xpos; //size in panel
504 u32 xsize; //start point in panel
506 enum data_format format;
508 wait_queue_head_t wait;
509 struct win_set mirror;
510 struct win_set displ;