drivers/video/rockchip/hdmi/rk_hdmi.h

   1 #ifndef __RK_HDMI_H__
   2 #define __RK_HDMI_H__
   3
   4 #include <linux/kernel.h>
   5 #include <linux/fb.h>
   6 #include <linux/spinlock.h>
   7 #include <linux/mutex.h>
   8 #include <linux/device.h>
   9 #include <linux/workqueue.h>
  10 #include <linux/display-sys.h>
  11 #ifdef CONFIG_SWITCH
  12 #include <linux/switch.h>
  13 #endif
  14 #ifdef CONFIG_HAS_EARLYSUSPEND
  15 #include <linux/earlysuspend.h>
  16 #endif
  17 #include <linux/atomic.h>
  18 #include<linux/rk_screen.h>
  19 #include <linux/rk_fb.h>
  20
  21 /* default HDMI output video mode */
  22 #define HDMI_VIDEO_DEFAULT_MODE                 HDMI_1280x720p_60Hz
  23
  24 #define HDMI_720X480P_60HZ_VIC          2
  25 #define HDMI_720X480I_60HZ_VIC          6
  26 #define HDMI_720X576P_50HZ_VIC          17
  27 #define HDMI_720X576I_50HZ_VIC          21
  28 #define HDMI_1280X720P_50HZ_VIC         19
  29 #define HDMI_1280X720P_60HZ_VIC         4
  30 #define HDMI_1920X1080P_50HZ_VIC        31
  31 #define HDMI_1920X1080I_50HZ_VIC        20
  32 #define HDMI_1920X1080P_60HZ_VIC        16
  33 #define HDMI_1920X1080I_60HZ_VIC        5
  34 #define HDMI_3840X2160P_24HZ_VIC        93
  35 #define HDMI_3840X2160P_25HZ_VIC        94
  36 #define HDMI_3840X2160P_30HZ_VIC        95
  37 #define HDMI_3840X2160P_50HZ_VIC        96
  38 #define HDMI_3840X2160P_60HZ_VIC        97
  39 #define HDMI_4096X2160P_24HZ_VIC        98
  40 #define HDMI_4096X2160P_25HZ_VIC        99
  41 #define HDMI_4096X2160P_30HZ_VIC        100
  42 #define HDMI_4096X2160P_50HZ_VIC        101
  43 #define HDMI_4096X2160P_60HZ_VIC        102
  44
  45 /* HDMI video source */
  46 enum {
  47         HDMI_SOURCE_LCDC0 = 0,
  48         HDMI_SOURCE_LCDC1 = 1
  49 };
  50
  51 enum {
  52         HDMI_SOC_RK3036,
  53         HDMI_SOC_RK312X,
  54         HDMI_SOC_RK3288
  55 };
  56 /*
  57  * If HDMI_ENABLE, system will auto configure output mode according to EDID
  58  * If HDMI_DISABLE, system will output mode according to
  59  * macro HDMI_VIDEO_DEFAULT_MODE
  60  */
  61 #define HDMI_AUTO_CONFIGURE                     HDMI_DISABLE
  62
  63 /* default HDMI output audio mode */
  64 #define HDMI_AUDIO_DEFAULT_CHANNEL              2
  65 #define HDMI_AUDIO_DEFAULT_RATE                 HDMI_AUDIO_FS_44100
  66 #define HDMI_AUDIO_DEFAULT_WORD_LENGTH  HDMI_AUDIO_WORD_LENGTH_16bit
  67
  68 enum {
  69         VIDEO_INPUT_RGB_YCBCR_444 = 0,
  70         VIDEO_INPUT_YCBCR422,
  71         VIDEO_INPUT_YCBCR422_EMBEDDED_SYNC,
  72         VIDEO_INPUT_2X_CLOCK,
  73         VIDEO_INPUT_2X_CLOCK_EMBEDDED_SYNC,
  74         VIDEO_INPUT_RGB444_DDR,
  75         VIDEO_INPUT_YCBCR422_DDR
  76 };
  77
  78 enum {
  79         VIDEO_OUTPUT_RGB444 = 0,
  80         VIDEO_OUTPUT_YCBCR444,
  81         VIDEO_OUTPUT_YCBCR422,
  82         VIDEO_OUTPUT_YCBCR420
  83 };
  84
  85 enum {
  86         VIDEO_INPUT_COLOR_RGB = 0,
  87         VIDEO_INPUT_COLOR_YCBCR444,
  88         VIDEO_INPUT_COLOR_YCBCR422,
  89         VIDEO_INPUT_COLOR_YCBCR420
  90 };
  91 /********************************************************************
  92 **                          ½á¹¹¶¨Òå                                *
  93 ********************************************************************/
  94 /* HDMI video mode code according CEA-861-E */
  95 enum hdmi_video_mode {
  96         HDMI_640x480p_60Hz = 1,
  97         HDMI_720x480p_60Hz_4_3,
  98         HDMI_720x480p_60Hz_16_9,
  99         HDMI_1280x720p_60Hz,
 100         HDMI_1920x1080i_60Hz,           /* 5 */
 101         HDMI_720x480i_60Hz_4_3,
 102         HDMI_720x480i_60Hz_16_9,
 103         HDMI_720x240p_60Hz_4_3,
 104         HDMI_720x240p_60Hz_16_9,
 105         HDMI_2880x480i_60Hz_4_3,        /* 10 */
 106         HDMI_2880x480i_60Hz_16_9,
 107         HDMI_2880x240p_60Hz_4_3,
 108         HDMI_2880x240p_60Hz_16_9,
 109         HDMI_1440x480p_60Hz_4_3,
 110         HDMI_1440x480p_60Hz_16_9,       /* 15 */
 111         HDMI_1920x1080p_60Hz,
 112         HDMI_720x576p_50Hz_4_3,
 113         HDMI_720x576p_50Hz_16_9,
 114         HDMI_1280x720p_50Hz,
 115         HDMI_1920x1080i_50Hz,           /* 20 */
 116         HDMI_720x576i_50Hz_4_3,
 117         HDMI_720x576i_50Hz_16_9,
 118         HDMI_720x288p_50Hz_4_3,
 119         HDMI_720x288p_50Hz_16_9,
 120         HDMI_2880x576i_50Hz_4_3,        /* 25 */
 121         HDMI_2880x576i_50Hz_16_9,
 122         HDMI_2880x288p_50Hz_4_3,
 123         HDMI_2880x288p_50Hz_16_9,
 124         HDMI_1440x576p_50Hz_4_3,
 125         HDMI_1440x576p_50Hz_16_9,       /* 30 */
 126         HDMI_1920x1080p_50Hz,
 127         HDMI_1920x1080p_24Hz,
 128         HDMI_1920x1080p_25Hz,
 129         HDMI_1920x1080p_30Hz,
 130         HDMI_2880x480p_60Hz_4_3,        /* 35 */
 131         HDMI_2880x480p_60Hz_16_9,
 132         HDMI_2880x576p_50Hz_4_3,
 133         HDMI_2880x576p_50Hz_16_9,
 134         HDMI_1920x1080i_50Hz_2, /* V Line 1250 total */
 135         HDMI_1920x1080i_100Hz,          /* 40 */
 136         HDMI_1280x720p_100Hz,
 137         HDMI_720x576p_100Hz_4_3,
 138         HDMI_720x576p_100Hz_16_9,
 139         HDMI_720x576i_100Hz_4_3,
 140         HDMI_720x576i_100Hz_16_9,       /* 45 */
 141         HDMI_1920x1080i_120Hz,
 142         HDMI_1280x720p_120Hz,
 143         HDMI_720x480p_120Hz_4_3,
 144         HDMI_720x480p_120Hz_16_9,
 145         HDMI_720x480i_120Hz_4_3,        /* 50 */
 146         HDMI_720x480i_120Hz_16_9,
 147         HDMI_720x576p_200Hz_4_3,
 148         HDMI_720x576p_200Hz_16_9,
 149         HDMI_720x576i_200Hz_4_3,
 150         HDMI_720x576i_200Hz_16_9,       /* 55 */
 151         HDMI_720x480p_240Hz_4_3,
 152         HDMI_720x480p_240Hz_16_9,
 153         HDMI_720x480i_240Hz_4_3,
 154         HDMI_720x480i_240Hz_16_9,
 155         HDMI_1280x720p_24Hz,            /* 60 */
 156         HDMI_1280x720p_25Hz,
 157         HDMI_1280x720p_30Hz,
 158         HDMI_1920x1080p_120Hz,
 159         HDMI_1920x1080p_100Hz,
 160 };
 161
 162 /* HDMI Video Data Color Mode */
 163 enum {
 164         HDMI_COLOR_RGB = 0,
 165         HDMI_COLOR_YCbCr422,
 166         HDMI_COLOR_YCbCr444
 167 };
 168
 169 /* HDMI Video Color Depth */
 170 enum {
 171         HDMI_COLOR_DEPTH_8BIT = 0x1,
 172         HDMI_COLOR_DEPTH_10BIT = 0x2,
 173         HDMI_COLOR_DEPTH_12BIT = 0x4,
 174         HDMI_COLOR_DEPTH_16BIT = 0x8
 175 };
 176
 177 /* HDMI Audio type */
 178 enum hdmi_audio_type {
 179         HDMI_AUDIO_LPCM = 1,
 180         HDMI_AUDIO_AC3,
 181         HDMI_AUDIO_MPEG1,
 182         HDMI_AUDIO_MP3,
 183         HDMI_AUDIO_MPEG2,
 184         HDMI_AUDIO_AAC_LC,      /* AAC */
 185         HDMI_AUDIO_DTS,
 186         HDMI_AUDIO_ATARC,
 187         HDMI_AUDIO_DSD,         /* One bit Audio */
 188         HDMI_AUDIO_E_AC3,
 189         HDMI_AUDIO_DTS_HD,
 190         HDMI_AUDIO_MLP,
 191         HDMI_AUDIO_DST,
 192         HDMI_AUDIO_WMA_PRO
 193 };
 194
 195 /* I2S Fs */
 196 enum hdmi_audio_fs {
 197         HDMI_AUDIO_FS_32000 = 0x1,
 198         HDMI_AUDIO_FS_44100 = 0x2,
 199         HDMI_AUDIO_FS_48000 = 0x4,
 200         HDMI_AUDIO_FS_88200 = 0x8,
 201         HDMI_AUDIO_FS_96000 = 0x10,
 202         HDMI_AUDIO_FS_176400 = 0x20,
 203         HDMI_AUDIO_FS_192000 = 0x40
 204 };
 205
 206 /* Audio Word Length */
 207 enum hdmi_audio_word_length {
 208         HDMI_AUDIO_WORD_LENGTH_16bit = 0x1,
 209         HDMI_AUDIO_WORD_LENGTH_20bit = 0x2,
 210         HDMI_AUDIO_WORD_LENGTH_24bit = 0x4
 211 };
 212
 213 /* EDID block size */
 214 #define HDMI_EDID_BLOCK_SIZE    128
 215
 216 /* HDMI state machine */
 217 enum hdmi_state {
 218         HDMI_SLEEP = 0,
 219         HDMI_INITIAL,
 220         WAIT_HOTPLUG,
 221         READ_PARSE_EDID,
 222         WAIT_HDMI_ENABLE,
 223         SYSTEM_CONFIG,
 224         CONFIG_VIDEO,
 225         CONFIG_AUDIO,
 226         PLAY_BACK,
 227 };
 228
 229 /* HDMI configuration command */
 230 enum hdmi_change {
 231         HDMI_CONFIG_NONE = 0,
 232         HDMI_CONFIG_VIDEO,
 233         HDMI_CONFIG_AUDIO,
 234         HDMI_CONFIG_COLOR,
 235         HDMI_CONFIG_HDCP,
 236         HDMI_CONFIG_ENABLE,
 237         HDMI_CONFIG_DISABLE,
 238         HDMI_CONFIG_DISPLAY
 239 };
 240
 241 /* HDMI Hotplug status */
 242 enum {
 243         HDMI_HPD_REMOVED = 0,
 244         HDMI_HPD_INSERT,
 245         HDMI_HPD_ACTIVED
 246 };
 247
 248 /* HDMI STATUS */
 249 #define HDMI_DISABLE            0
 250 #define HDMI_ENABLE             1
 251 #define HDMI_UNKOWN             0xFF
 252
 253 /* HDMI Error Code */
 254 enum hdmi_errorcode {
 255         HDMI_ERROR_SUCESS = 0,
 256         HDMI_ERROR_FALSE,
 257         HDMI_ERROR_I2C,
 258         HDMI_ERROR_EDID,
 259 };
 260
 261 /* HDMI audio parameters */
 262 struct hdmi_audio {
 263         u32 type;               /* Audio type */
 264         u32 channel;            /* Audio channel number */
 265         u32 rate;               /* Audio sampling rate */
 266         u32 word_length;        /* Audio data word length */
 267 };
 268
 269 struct hdmi_edid {
 270         unsigned char sink_hdmi;        /* HDMI display device flag */
 271         unsigned char ycbcr444;         /* Display device support YCbCr444 */
 272         unsigned char ycbcr422;         /* Display device support YCbCr422 */
 273         unsigned char deepcolor;        /* bit3:DC_48bit; bit2:DC_36bit;
 274                                          * bit1:DC_30bit; bit0:DC_Y444;
 275                                          */
 276         unsigned char latency_fields_present;
 277         unsigned char i_latency_fields_present;
 278         unsigned char video_latency;
 279         unsigned char audio_latency;
 280         unsigned char interlaced_video_latency;
 281         unsigned char interlaced_audio_latency;
 282         unsigned char video_present;    /* have additional video format
 283                                          * abount 4k and/or 3d
 284                                          */
 285         unsigned char support_3d;       /* 3D format support */
 286         unsigned int maxtmdsclock;      /* max tmds clock freq support */
 287         struct fb_monspecs *specs;      /* Device spec */
 288         struct list_head modelist;      /* Device supported display mode list */
 289         struct hdmi_audio *audio;       /* Device supported audio info */
 290         int audio_num;                  /* Device supported audio type number */
 291         int base_audio_support;         /* Device supported base audio */
 292         unsigned int  cecaddress;                       //CEC physical address
 293 };
 294
 295 /* RK HDMI Video Configure Parameters */
 296 struct hdmi_video_para {
 297         int vic;
 298         int input_mode;                 /* input video data interface */
 299         int input_color;                /* input video color mode */
 300         int output_mode;                /* output hdmi or dvi */
 301         int output_color;               /* output video color mode */
 302         unsigned char format_3d;        /* output 3d format */
 303         unsigned char color_depth;      /* color depth: 8bit; 10bit;
 304                                          * 12bit; 16bit;
 305                                          */
 306         unsigned char pixel_repet;      /* pixel repettion */
 307         unsigned char pixel_pack_phase; /* pixel packing default phase */
 308         unsigned char color_limit_range;        /* quantization range
 309                                                  * 0: full range(0~255)
 310                                                  * 1:limit range(16~235)
 311                                                  */
 312 };
 313
 314 struct rk_hdmi_drvdata  {
 315         u8 soc_type;
 316         u32 reversed;
 317 };
 318
 319 struct hdmi {
 320         struct device *dev;
 321         int id;
 322         int irq;
 323         struct rk_lcdc_driver *lcdc;
 324         struct rk_hdmi_drvdata *data;
 325
 326 #ifdef CONFIG_SWITCH
 327         struct switch_dev switch_hdmi;
 328 #endif
 329
 330         struct workqueue_struct *workqueue;
 331         struct delayed_work delay_work;
 332
 333         spinlock_t irq_lock;
 334         struct mutex enable_mutex;
 335
 336         int wait;
 337         struct completion complete;
 338
 339         int suspend;
 340 #ifdef CONFIG_HAS_EARLYSUSPEND
 341         struct early_suspend early_suspend;
 342 #endif
 343
 344         struct hdmi_edid edid;
 345         int enable;             /* Enable HDMI output or not */
 346         int vic;                /* HDMI output video mode code */
 347         struct hdmi_audio audio;        /* HDMI output audio type */
 348
 349         int pwr_mode;           /* power mode */
 350         int hotplug;            /* hot plug status */
 351         int state;              /* hdmi state machine status */
 352         int autoconfig;         /* if true, auto config hdmi output mode
 353                                  * according to EDID
 354                                  */
 355         int command;            /* HDMI configuration command */
 356         int display;            /* HDMI display status */
 357         int xscale;             /* x direction scale value */
 358         int yscale;             /* y directoon scale value */
 359         int tmdsclk;            /* TDMS Clock frequency */
 360         int pixclock;           /* Pixel Clcok frequency */
 361
 362         struct list_head pwrlist_head;
 363
 364         int (*insert) (struct hdmi *hdmi);
 365         int (*remove) (struct hdmi *hdmi);
 366         void (*control_output) (struct hdmi *hdmi, int enable);
 367         int (*config_video) (struct hdmi *hdmi,
 368                              struct hdmi_video_para *vpara);
 369         int (*config_audio) (struct hdmi *hdmi, struct hdmi_audio *audio);
 370         int (*detect_hotplug) (struct hdmi *hdmi);
 371         /* call back for edid */
 372         int (*read_edid) (struct hdmi *hdmi, int block, unsigned char *buff);
 373         int (*set_vif) (struct hdmi *hdmi, struct rk_screen *screen,
 374                         bool connect);
 375
 376         /* call back for hdcp operation */
 377         void (*hdcp_cb) (void);
 378         void (*hdcp_irq_cb) (int);
 379         int (*hdcp_power_on_cb) (void);
 380         void (*hdcp_power_off_cb) (void);
 381
 382         /*call back for cec operation*/
 383         void (*cec_irq) (void);
 384         void (*cec_set_device_pa) (int);
 385         int (*cec_enumerate) (void);
 386 };
 387
 388 #define hdmi_err(dev, format, arg...)           \
 389         dev_err(dev , format , ## arg)
 390
 391 #ifdef HDMI_DEBUG
 392 #define hdmi_dbg(dev, format, arg...)           \
 393         dev_info(dev , format , ## arg)
 394 #else
 395 #define hdmi_dbg(dev, format, arg...)
 396 #endif
 397
 398 extern int hdmi_drv_register(struct hdmi *hdmi_drv);
 399 extern int hdmi_get_hotplug(void);
 400 extern int hdmi_set_info(struct rk_screen *screen, unsigned int vic);
 401 extern void hdmi_init_lcdc(struct rk_screen *screen,
 402                            struct rk29lcd_info *lcd_info);
 403 extern int hdmi_sys_init(struct hdmi *hdmi_drv);
 404 extern int hdmi_sys_parse_edid(struct hdmi *hdmi_drv);
 405 extern const char *hdmi_get_video_mode_name(unsigned char vic);
 406 extern int hdmi_videomode_to_vic(struct fb_videomode *vmode);
 407 extern const struct fb_videomode *hdmi_vic_to_videomode(int vic);
 408 extern int hdmi_add_videomode(const struct fb_videomode *mode,
 409                               struct list_head *head);
 410 extern struct hdmi_video_timing *hdmi_find_mode(int vic);
 411 extern int hdmi_find_best_mode(struct hdmi *hdmi_drv, int vic);
 412 extern int hdmi_ouputmode_select(struct hdmi *hdmi_drv, int edid_ok);
 413 extern int hdmi_switch_fb(struct hdmi *hdmi_drv, int vic);
 414 extern int hdmi_init_video_para(struct hdmi *hdmi_drv,
 415                                 struct hdmi_video_para *video);
 416 extern void hdmi_work(struct work_struct *work);
 417 extern void hdmi_register_display_sysfs(struct hdmi *hdmi_drv,
 418                                         struct device *parent);
 419 extern void hdmi_unregister_display_sysfs(struct hdmi *hdmi_drv);
 420
 421 int rk_hdmi_parse_dt(struct hdmi *hdmi_drv);
 422 int rk_hdmi_pwr_enable(struct hdmi *dev_drv);
 423 int rk_hdmi_pwr_disable(struct hdmi *dev_drv);
 424
 425 #endif