drivers/video/rockchip/hdmi/rk_hdmi.h

   1 #ifndef __RK_HDMI_H__
   2 #define __RK_HDMI_H__
   3
   4 #include <linux/kernel.h>
   5 #include <linux/fb.h>
   6 #include <linux/spinlock.h>
   7 #include <linux/mutex.h>
   8 #include <linux/device.h>
   9 #include <linux/workqueue.h>
  10 #include <linux/display-sys.h>
  11 #ifdef CONFIG_SWITCH
  12 #include <linux/switch.h>
  13 #endif
  14 #ifdef CONFIG_HAS_EARLYSUSPEND
  15 #include <linux/earlysuspend.h>
  16 #endif
  17 #include <linux/atomic.h>
  18 #include<linux/rk_screen.h>
  19 #include <linux/rk_fb.h>
  20
  21 /* default HDMI output video mode */
  22 #define HDMI_VIDEO_DEFAULT_MODE                 HDMI_1280x720p_60Hz
  23
  24 #define HDMI_720X480P_60HZ_VIC          2
  25 #define HDMI_720X480I_60HZ_VIC          6
  26 #define HDMI_720X576P_50HZ_VIC          17
  27 #define HDMI_720X576I_50HZ_VIC          21
  28 #define HDMI_1280X720P_50HZ_VIC         19
  29 #define HDMI_1280X720P_60HZ_VIC         4
  30 #define HDMI_1920X1080P_50HZ_VIC        31
  31 #define HDMI_1920X1080I_50HZ_VIC        20
  32 #define HDMI_1920X1080P_60HZ_VIC        16
  33 #define HDMI_1920X1080I_60HZ_VIC        5
  34 #define HDMI_3840X2160P_24HZ_VIC        93
  35 #define HDMI_3840X2160P_25HZ_VIC        94
  36 #define HDMI_3840X2160P_30HZ_VIC        95
  37 #define HDMI_3840X2160P_50HZ_VIC        96
  38 #define HDMI_3840X2160P_60HZ_VIC        97
  39 #define HDMI_4096X2160P_24HZ_VIC        98
  40 #define HDMI_4096X2160P_25HZ_VIC        99
  41 #define HDMI_4096X2160P_30HZ_VIC        100
  42 #define HDMI_4096X2160P_50HZ_VIC        101
  43 #define HDMI_4096X2160P_60HZ_VIC        102
  44
  45 /* HDMI video source */
  46 enum {
  47         HDMI_SOURCE_LCDC0 = 0,
  48         HDMI_SOURCE_LCDC1 = 1
  49 };
  50
  51 /*
  52  * If HDMI_ENABLE, system will auto configure output mode according to EDID
  53  * If HDMI_DISABLE, system will output mode according to
  54  * macro HDMI_VIDEO_DEFAULT_MODE
  55  */
  56 #define HDMI_AUTO_CONFIGURE                     HDMI_DISABLE
  57
  58 /* default HDMI output audio mode */
  59 #define HDMI_AUDIO_DEFAULT_CHANNEL              2
  60 #define HDMI_AUDIO_DEFAULT_RATE                 HDMI_AUDIO_FS_44100
  61 #define HDMI_AUDIO_DEFAULT_WORD_LENGTH  HDMI_AUDIO_WORD_LENGTH_16bit
  62
  63 enum {
  64         VIDEO_INPUT_RGB_YCBCR_444 = 0,
  65         VIDEO_INPUT_YCBCR422,
  66         VIDEO_INPUT_YCBCR422_EMBEDDED_SYNC,
  67         VIDEO_INPUT_2X_CLOCK,
  68         VIDEO_INPUT_2X_CLOCK_EMBEDDED_SYNC,
  69         VIDEO_INPUT_RGB444_DDR,
  70         VIDEO_INPUT_YCBCR422_DDR
  71 };
  72
  73 enum {
  74         VIDEO_OUTPUT_RGB444 = 0,
  75         VIDEO_OUTPUT_YCBCR444,
  76         VIDEO_OUTPUT_YCBCR422,
  77         VIDEO_OUTPUT_YCBCR420
  78 };
  79
  80 enum {
  81         VIDEO_INPUT_COLOR_RGB = 0,
  82         VIDEO_INPUT_COLOR_YCBCR444,
  83         VIDEO_INPUT_COLOR_YCBCR422,
  84         VIDEO_INPUT_COLOR_YCBCR420
  85 };
  86 /********************************************************************
  87 **                          ½á¹¹¶¨Òå                                *
  88 ********************************************************************/
  89 /* HDMI video mode code according CEA-861-E */
  90 enum hdmi_video_mode {
  91         HDMI_640x480p_60Hz = 1,
  92         HDMI_720x480p_60Hz_4_3,
  93         HDMI_720x480p_60Hz_16_9,
  94         HDMI_1280x720p_60Hz,
  95         HDMI_1920x1080i_60Hz,           /* 5 */
  96         HDMI_720x480i_60Hz_4_3,
  97         HDMI_720x480i_60Hz_16_9,
  98         HDMI_720x240p_60Hz_4_3,
  99         HDMI_720x240p_60Hz_16_9,
 100         HDMI_2880x480i_60Hz_4_3,        /* 10 */
 101         HDMI_2880x480i_60Hz_16_9,
 102         HDMI_2880x240p_60Hz_4_3,
 103         HDMI_2880x240p_60Hz_16_9,
 104         HDMI_1440x480p_60Hz_4_3,
 105         HDMI_1440x480p_60Hz_16_9,       /* 15 */
 106         HDMI_1920x1080p_60Hz,
 107         HDMI_720x576p_50Hz_4_3,
 108         HDMI_720x576p_50Hz_16_9,
 109         HDMI_1280x720p_50Hz,
 110         HDMI_1920x1080i_50Hz,           /* 20 */
 111         HDMI_720x576i_50Hz_4_3,
 112         HDMI_720x576i_50Hz_16_9,
 113         HDMI_720x288p_50Hz_4_3,
 114         HDMI_720x288p_50Hz_16_9,
 115         HDMI_2880x576i_50Hz_4_3,        /* 25 */
 116         HDMI_2880x576i_50Hz_16_9,
 117         HDMI_2880x288p_50Hz_4_3,
 118         HDMI_2880x288p_50Hz_16_9,
 119         HDMI_1440x576p_50Hz_4_3,
 120         HDMI_1440x576p_50Hz_16_9,       /* 30 */
 121         HDMI_1920x1080p_50Hz,
 122         HDMI_1920x1080p_24Hz,
 123         HDMI_1920x1080p_25Hz,
 124         HDMI_1920x1080p_30Hz,
 125         HDMI_2880x480p_60Hz_4_3,        /* 35 */
 126         HDMI_2880x480p_60Hz_16_9,
 127         HDMI_2880x576p_50Hz_4_3,
 128         HDMI_2880x576p_50Hz_16_9,
 129         HDMI_1920x1080i_50Hz_2, /* V Line 1250 total */
 130         HDMI_1920x1080i_100Hz,          /* 40 */
 131         HDMI_1280x720p_100Hz,
 132         HDMI_720x576p_100Hz_4_3,
 133         HDMI_720x576p_100Hz_16_9,
 134         HDMI_720x576i_100Hz_4_3,
 135         HDMI_720x576i_100Hz_16_9,       /* 45 */
 136         HDMI_1920x1080i_120Hz,
 137         HDMI_1280x720p_120Hz,
 138         HDMI_720x480p_120Hz_4_3,
 139         HDMI_720x480p_120Hz_16_9,
 140         HDMI_720x480i_120Hz_4_3,        /* 50 */
 141         HDMI_720x480i_120Hz_16_9,
 142         HDMI_720x576p_200Hz_4_3,
 143         HDMI_720x576p_200Hz_16_9,
 144         HDMI_720x576i_200Hz_4_3,
 145         HDMI_720x576i_200Hz_16_9,       /* 55 */
 146         HDMI_720x480p_240Hz_4_3,
 147         HDMI_720x480p_240Hz_16_9,
 148         HDMI_720x480i_240Hz_4_3,
 149         HDMI_720x480i_240Hz_16_9,
 150         HDMI_1280x720p_24Hz,            /* 60 */
 151         HDMI_1280x720p_25Hz,
 152         HDMI_1280x720p_30Hz,
 153         HDMI_1920x1080p_120Hz,
 154         HDMI_1920x1080p_100Hz,
 155 };
 156
 157 /* HDMI Video Data Color Mode */
 158 enum {
 159         HDMI_COLOR_RGB = 0,
 160         HDMI_COLOR_YCbCr422,
 161         HDMI_COLOR_YCbCr444
 162 };
 163
 164 /* HDMI Video Color Depth */
 165 enum {
 166         HDMI_COLOR_DEPTH_8BIT = 0x1,
 167         HDMI_COLOR_DEPTH_10BIT = 0x2,
 168         HDMI_COLOR_DEPTH_12BIT = 0x4,
 169         HDMI_COLOR_DEPTH_16BIT = 0x8
 170 };
 171
 172 /* HDMI Audio type */
 173 enum hdmi_audio_type {
 174         HDMI_AUDIO_LPCM = 1,
 175         HDMI_AUDIO_AC3,
 176         HDMI_AUDIO_MPEG1,
 177         HDMI_AUDIO_MP3,
 178         HDMI_AUDIO_MPEG2,
 179         HDMI_AUDIO_AAC_LC,      /* AAC */
 180         HDMI_AUDIO_DTS,
 181         HDMI_AUDIO_ATARC,
 182         HDMI_AUDIO_DSD,         /* One bit Audio */
 183         HDMI_AUDIO_E_AC3,
 184         HDMI_AUDIO_DTS_HD,
 185         HDMI_AUDIO_MLP,
 186         HDMI_AUDIO_DST,
 187         HDMI_AUDIO_WMA_PRO
 188 };
 189
 190 /* I2S Fs */
 191 enum hdmi_audio_fs {
 192         HDMI_AUDIO_FS_32000 = 0x1,
 193         HDMI_AUDIO_FS_44100 = 0x2,
 194         HDMI_AUDIO_FS_48000 = 0x4,
 195         HDMI_AUDIO_FS_88200 = 0x8,
 196         HDMI_AUDIO_FS_96000 = 0x10,
 197         HDMI_AUDIO_FS_176400 = 0x20,
 198         HDMI_AUDIO_FS_192000 = 0x40
 199 };
 200
 201 /* Audio Word Length */
 202 enum hdmi_audio_word_length {
 203         HDMI_AUDIO_WORD_LENGTH_16bit = 0x1,
 204         HDMI_AUDIO_WORD_LENGTH_20bit = 0x2,
 205         HDMI_AUDIO_WORD_LENGTH_24bit = 0x4
 206 };
 207
 208 /* EDID block size */
 209 #define HDMI_EDID_BLOCK_SIZE    128
 210
 211 /* HDMI state machine */
 212 enum hdmi_state {
 213         HDMI_SLEEP = 0,
 214         HDMI_INITIAL,
 215         WAIT_HOTPLUG,
 216         READ_PARSE_EDID,
 217         WAIT_HDMI_ENABLE,
 218         SYSTEM_CONFIG,
 219         CONFIG_VIDEO,
 220         CONFIG_AUDIO,
 221         PLAY_BACK,
 222 };
 223
 224 /* HDMI configuration command */
 225 enum hdmi_change {
 226         HDMI_CONFIG_NONE = 0,
 227         HDMI_CONFIG_VIDEO,
 228         HDMI_CONFIG_AUDIO,
 229         HDMI_CONFIG_COLOR,
 230         HDMI_CONFIG_HDCP,
 231         HDMI_CONFIG_ENABLE,
 232         HDMI_CONFIG_DISABLE,
 233         HDMI_CONFIG_DISPLAY
 234 };
 235
 236 /* HDMI Hotplug status */
 237 enum {
 238         HDMI_HPD_REMOVED = 0,
 239         HDMI_HPD_INSERT,
 240         HDMI_HPD_ACTIVED
 241 };
 242
 243 /* HDMI STATUS */
 244 #define HDMI_DISABLE            0
 245 #define HDMI_ENABLE             1
 246 #define HDMI_UNKOWN             0xFF
 247
 248 /* HDMI Error Code */
 249 enum hdmi_errorcode {
 250         HDMI_ERROR_SUCESS = 0,
 251         HDMI_ERROR_FALSE,
 252         HDMI_ERROR_I2C,
 253         HDMI_ERROR_EDID,
 254 };
 255
 256 /* HDMI audio parameters */
 257 struct hdmi_audio {
 258         u32 type;               /* Audio type */
 259         u32 channel;            /* Audio channel number */
 260         u32 rate;               /* Audio sampling rate */
 261         u32 word_length;        /* Audio data word length */
 262 };
 263
 264 struct hdmi_edid {
 265         unsigned char sink_hdmi;        /* HDMI display device flag */
 266         unsigned char ycbcr444;         /* Display device support YCbCr444 */
 267         unsigned char ycbcr422;         /* Display device support YCbCr422 */
 268         unsigned char deepcolor;        /* bit3:DC_48bit; bit2:DC_36bit;
 269                                          * bit1:DC_30bit; bit0:DC_Y444;
 270                                          */
 271         unsigned char latency_fields_present;
 272         unsigned char i_latency_fields_present;
 273         unsigned char video_latency;
 274         unsigned char audio_latency;
 275         unsigned char interlaced_video_latency;
 276         unsigned char interlaced_audio_latency;
 277         unsigned char video_present;    /* have additional video format
 278                                          * abount 4k and/or 3d
 279                                          */
 280         unsigned char support_3d;       /* 3D format support */
 281         unsigned int maxtmdsclock;      /* max tmds clock freq support */
 282         struct fb_monspecs *specs;      /* Device spec */
 283         struct list_head modelist;      /* Device supported display mode list */
 284         struct hdmi_audio *audio;       /* Device supported audio info */
 285         int audio_num;                  /* Device supported audio type number */
 286         int base_audio_support;         /* Device supported base audio */
 287         unsigned int  cecaddress;                       //CEC physical address
 288 };
 289
 290 /* RK HDMI Video Configure Parameters */
 291 struct hdmi_video_para {
 292         int vic;
 293         int input_mode;                 /* input video data interface */
 294         int input_color;                /* input video color mode */
 295         int output_mode;                /* output hdmi or dvi */
 296         int output_color;               /* output video color mode */
 297         unsigned char format_3d;        /* output 3d format */
 298         unsigned char color_depth;      /* color depth: 8bit; 10bit;
 299                                          * 12bit; 16bit;
 300                                          */
 301         unsigned char pixel_repet;      /* pixel repettion */
 302         unsigned char pixel_pack_phase; /* pixel packing default phase */
 303         unsigned char color_limit_range;        /* quantization range
 304                                                  * 0: full range(0~255)
 305                                                  * 1:limit range(16~235)
 306                                                  */
 307 };
 308
 309 struct hdmi {
 310         struct device *dev;
 311         int id;
 312         int irq;
 313         struct rk_lcdc_driver *lcdc;
 314
 315 #ifdef CONFIG_SWITCH
 316         struct switch_dev switch_hdmi;
 317 #endif
 318
 319         struct workqueue_struct *workqueue;
 320         struct delayed_work delay_work;
 321
 322         spinlock_t irq_lock;
 323         struct mutex enable_mutex;
 324
 325         int wait;
 326         struct completion complete;
 327
 328         int suspend;
 329 #ifdef CONFIG_HAS_EARLYSUSPEND
 330         struct early_suspend early_suspend;
 331 #endif
 332
 333         struct hdmi_edid edid;
 334         int enable;             /* Enable HDMI output or not */
 335         int vic;                /* HDMI output video mode code */
 336         struct hdmi_audio audio;        /* HDMI output audio type */
 337
 338         int pwr_mode;           /* power mode */
 339         int hotplug;            /* hot plug status */
 340         int state;              /* hdmi state machine status */
 341         int autoconfig;         /* if true, auto config hdmi output mode
 342                                  * according to EDID
 343                                  */
 344         int command;            /* HDMI configuration command */
 345         int display;            /* HDMI display status */
 346         int xscale;             /* x direction scale value */
 347         int yscale;             /* y directoon scale value */
 348         int tmdsclk;            /* TDMS Clock frequency */
 349         int pixclock;           /* Pixel Clcok frequency */
 350
 351         struct list_head pwrlist_head;
 352
 353         int (*insert) (struct hdmi *hdmi);
 354         int (*remove) (struct hdmi *hdmi);
 355         void (*control_output) (struct hdmi *hdmi, int enable);
 356         int (*config_video) (struct hdmi *hdmi,
 357                              struct hdmi_video_para *vpara);
 358         int (*config_audio) (struct hdmi *hdmi, struct hdmi_audio *audio);
 359         int (*detect_hotplug) (struct hdmi *hdmi);
 360         /* call back for edid */
 361         int (*read_edid) (struct hdmi *hdmi, int block, unsigned char *buff);
 362         int (*set_vif) (struct hdmi *hdmi, struct rk_screen *screen,
 363                         bool connect);
 364
 365         /* call back for hdcp operation */
 366         void (*hdcp_cb) (void);
 367         void (*hdcp_irq_cb) (int);
 368         int (*hdcp_power_on_cb) (void);
 369         void (*hdcp_power_off_cb) (void);
 370
 371         /*call back for cec operation*/
 372         void (*cec_irq) (void);
 373         void (*cec_set_device_pa) (int);
 374         int (*cec_enumerate) (void);
 375 };
 376
 377 #define hdmi_err(dev, format, arg...)           \
 378         dev_err(dev , format , ## arg)
 379
 380 #ifdef HDMI_DEBUG
 381 #define hdmi_dbg(dev, format, arg...)           \
 382         dev_info(dev , format , ## arg)
 383 #else
 384 #define hdmi_dbg(dev, format, arg...)
 385 #endif
 386
 387 extern int hdmi_drv_register(struct hdmi *hdmi_drv);
 388 extern int hdmi_get_hotplug(void);
 389 extern int hdmi_set_info(struct rk_screen *screen, unsigned int vic);
 390 extern void hdmi_init_lcdc(struct rk_screen *screen,
 391                            struct rk29lcd_info *lcd_info);
 392 extern int hdmi_sys_init(struct hdmi *hdmi_drv);
 393 extern int hdmi_sys_parse_edid(struct hdmi *hdmi_drv);
 394 extern const char *hdmi_get_video_mode_name(unsigned char vic);
 395 extern int hdmi_videomode_to_vic(struct fb_videomode *vmode);
 396 extern const struct fb_videomode *hdmi_vic_to_videomode(int vic);
 397 extern int hdmi_add_videomode(const struct fb_videomode *mode,
 398                               struct list_head *head);
 399 extern struct hdmi_video_timing *hdmi_find_mode(int vic);
 400 extern int hdmi_find_best_mode(struct hdmi *hdmi_drv, int vic);
 401 extern int hdmi_ouputmode_select(struct hdmi *hdmi_drv, int edid_ok);
 402 extern int hdmi_switch_fb(struct hdmi *hdmi_drv, int vic);
 403 extern int hdmi_init_video_para(struct hdmi *hdmi_drv,
 404                                 struct hdmi_video_para *video);
 405 extern void hdmi_work(struct work_struct *work);
 406 extern void hdmi_register_display_sysfs(struct hdmi *hdmi_drv,
 407                                         struct device *parent);
 408 extern void hdmi_unregister_display_sysfs(struct hdmi *hdmi_drv);
 409
 410 int rk_hdmi_parse_dt(struct hdmi *hdmi_drv);
 411 int rk_hdmi_pwr_enable(struct hdmi *dev_drv);
 412 int rk_hdmi_pwr_disable(struct hdmi *dev_drv);
 413
 414 #endif