1 #include "rockchip-hdmi.h"
2 #include "../../edid.h"
7 #define EDBG(format, ...)
11 E_HDMI_EDID_SUCCESS = 0,
16 E_HDMI_EDID_UNKOWNDATA,
20 static int hdmi_edid_checksum(unsigned char *buf)
25 for (i = 0; i < HDMI_EDID_BLOCK_SIZE; i++)
31 return E_HDMI_EDID_SUCCESS;
33 return E_HDMI_EDID_CHECKSUM;
37 @Des Parse Detail Timing Descriptor.
38 @Param buf : pointer to DTD data.
39 @Param pvic: VIC of DTD descripted.
41 static int hdmi_edid_parse_dtd(unsigned char *block, struct fb_videomode *mode)
43 mode->xres = H_ACTIVE;
44 mode->yres = V_ACTIVE;
45 mode->pixclock = PIXEL_CLOCK;
46 /* mode->pixclock /= 1000;
47 mode->pixclock = KHZ2PICOS(mode->pixclock);
48 */ mode->right_margin = H_SYNC_OFFSET;
49 mode->left_margin = (H_ACTIVE + H_BLANKING) -
50 (H_ACTIVE + H_SYNC_OFFSET + H_SYNC_WIDTH);
51 mode->upper_margin = V_BLANKING - V_SYNC_OFFSET -
53 mode->lower_margin = V_SYNC_OFFSET;
54 mode->hsync_len = H_SYNC_WIDTH;
55 mode->vsync_len = V_SYNC_WIDTH;
57 mode->sync |= FB_SYNC_HOR_HIGH_ACT;
59 mode->sync |= FB_SYNC_VERT_HIGH_ACT;
60 mode->refresh = PIXEL_CLOCK/((H_ACTIVE + H_BLANKING) *
61 (V_ACTIVE + V_BLANKING));
64 mode->upper_margin *= 2;
65 mode->lower_margin *= 2;
67 mode->vmode |= FB_VMODE_INTERLACED;
69 mode->flag = FB_MODE_IS_DETAILED;
71 EDBG("<<<<<<<<Detailed Time>>>>>>>>>\n");
72 EDBG("%d KHz Refresh %d Hz",
73 PIXEL_CLOCK/1000, mode->refresh);
74 EDBG("%d %d %d %d ", H_ACTIVE, H_ACTIVE + H_SYNC_OFFSET,
75 H_ACTIVE + H_SYNC_OFFSET + H_SYNC_WIDTH, H_ACTIVE + H_BLANKING);
76 EDBG("%d %d %d %d ", V_ACTIVE, V_ACTIVE + V_SYNC_OFFSET,
77 V_ACTIVE + V_SYNC_OFFSET + V_SYNC_WIDTH, V_ACTIVE + V_BLANKING);
78 EDBG("%sHSync %sVSync\n\n", (HSYNC_POSITIVE) ? "+" : "-",
79 (VSYNC_POSITIVE) ? "+" : "-");
80 return E_HDMI_EDID_SUCCESS;
83 int hdmi_edid_parse_base(unsigned char *buf,
84 int *extend_num, struct hdmi_edid *pedid)
88 if (buf == NULL || extend_num == NULL)
89 return E_HDMI_EDID_PARAM;
91 /* Check first 8 byte to ensure it is an edid base block. */
100 pr_err("[EDID] check header error\n");
101 return E_HDMI_EDID_HEAD;
104 *extend_num = buf[0x7e];
106 EDBG("[EDID] extend block num is %d\n", buf[0x7e]);
110 rc = hdmi_edid_checksum(buf);
111 if (rc != E_HDMI_EDID_SUCCESS) {
112 pr_err("[EDID] base block checksum error\n");
113 return E_HDMI_EDID_CHECKSUM;
116 pedid->specs = kzalloc(sizeof(*pedid->specs), GFP_KERNEL);
117 if (pedid->specs == NULL)
118 return E_HDMI_EDID_NOMEMORY;
120 fb_edid_to_monspecs(buf, pedid->specs);
122 return E_HDMI_EDID_SUCCESS;
125 /* Parse CEA Short Video Descriptor */
126 static int hdmi_edid_get_cea_svd(unsigned char *buf, struct hdmi_edid *pedid)
130 count = buf[0] & 0x1F;
131 for (i = 0; i < count; i++) {
132 EDBG("[CEA] %02x VID %d native %d\n",
133 buf[1 + i], buf[1 + i] & 0x7f, buf[1 + i] >> 7);
134 vic = buf[1 + i] & 0x7f;
135 hdmi_add_vic(vic, &pedid->modelist);
138 struct list_head *pos;
139 struct display_modelist *modelist;
141 list_for_each(pos, &pedid->modelist) {
142 modelist = list_entry(pos, struct display_modelist, list);
143 pr_info("%s vic %d\n", __FUNCTION__, modelist->vic);
148 /* Parse CEA Short Audio Descriptor */
149 static int hdmi_edid_parse_cea_sad(unsigned char *buf, struct hdmi_edid *pedid)
153 count = buf[0] & 0x1F;
154 pedid->audio = kmalloc((count/3)*sizeof(struct hdmi_audio), GFP_KERNEL);
155 if (pedid->audio == NULL)
156 return E_HDMI_EDID_NOMEMORY;
158 pedid->audio_num = count/3;
159 for (i = 0; i < pedid->audio_num; i++) {
160 pedid->audio[i].type = (buf[1 + i*3] >> 3) & 0x0F;
161 pedid->audio[i].channel = (buf[1 + i*3] & 0x07) + 1;
162 pedid->audio[i].rate = buf[1 + i*3 + 1];
163 if (pedid->audio[i].type == HDMI_AUDIO_LPCM)
164 pedid->audio[i].word_length = buf[1 + i*3 + 2];
166 /* pr_info("type %d channel %d rate %d word length %d\n",
167 pedid->audio[i].type, pedid->audio[i].channel,
168 pedid->audio[i].rate, pedid->audio[i].word_length);
170 return E_HDMI_EDID_SUCCESS;
173 static int hdmi_edid_parse_3dinfo(unsigned char *buf, struct list_head *head)
175 int i, j, len = 0, format_3d, vic_mask;
176 unsigned char offset = 2, vic_2d, structure_3d;
177 struct list_head *pos;
178 struct display_modelist *modelist;
181 len = (buf[1] & 0xe0) >> 5;
182 for (i = 0; i < len; i++) {
184 hdmi_add_vic((96 - buf[offset]), head);
191 len += (buf[1] & 0x1F) + 2;
192 if (((buf[0] & 0x60) == 0x40) || ((buf[0] & 0x60) == 0x20)) {
193 format_3d = buf[offset++] << 8;
194 format_3d |= buf[offset++];
195 if ((buf[0] & 0x60) == 0x20) {
198 vic_mask = buf[offset++] << 8;
199 vic_mask |= buf[offset++];
206 for (i = 0; i < 16; i++) {
207 if (vic_mask & (1 << i)) {
209 for (pos = (head)->next; pos != (head);
213 list_entry(pos, struct display_modelist, list);
214 modelist->format_3d = format_3d;
220 while (offset < len) {
221 vic_2d = (buf[offset] & 0xF0) >> 4;
222 structure_3d = (buf[offset++] & 0x0F);
224 for (pos = (head)->next; pos != (head);
229 list_entry(pos, struct display_modelist, list);
230 modelist->format_3d |=
232 if (structure_3d & 0x08)
233 modelist->detail_3d =
234 (buf[offset++] & 0xF0) >> 4;
239 /* mandatory formats */
240 for (pos = (head)->next; pos != (head); pos = pos->next) {
241 modelist = list_entry(pos,
242 struct display_modelist,
244 if (modelist->vic == HDMI_1920X1080P_24HZ ||
245 modelist->vic == HDMI_1280X720P_60HZ ||
246 modelist->vic == HDMI_1280X720P_50HZ) {
247 modelist->format_3d |=
248 (1 << HDMI_3D_FRAME_PACKING) |
249 (1 << HDMI_3D_TOP_BOOTOM);
250 } else if (modelist->vic == HDMI_1920X1080I_60HZ ||
251 modelist->vic == HDMI_1920X1080I_50HZ) {
252 modelist->format_3d |=
253 (1 << HDMI_3D_SIDE_BY_SIDE_HALF);
260 static int hdmi_edmi_parse_vsdb(unsigned char *buf, struct hdmi_edid *pedid,
261 int cur_offset, int IEEEOUI)
263 int count, buf_offset;
265 count = buf[cur_offset] & 0x1F;
268 pedid->sink_hdmi = 1;
269 pedid->cecaddress = buf[cur_offset + 5];
270 pedid->cecaddress |= buf[cur_offset + 4] << 8;
271 EDBG("[CEA] CEC Physical addres is 0x%08x.\n",
274 pedid->deepcolor = (buf[cur_offset + 6] >> 3) & 0x0F;
276 pedid->maxtmdsclock = buf[cur_offset + 7] * 5000000;
277 EDBG("[CEA] maxtmdsclock is %d.\n",
278 pedid->maxtmdsclock);
281 pedid->fields_present = buf[cur_offset + 8];
282 EDBG("[CEA] fields_present is 0x%02x.\n",
283 pedid->fields_present);
285 buf_offset = cur_offset + 9;
286 if (pedid->fields_present & 0x80) {
287 pedid->video_latency = buf[buf_offset++];
288 pedid->audio_latency = buf[buf_offset++];
290 if (pedid->fields_present & 0x40) {
291 pedid->interlaced_video_latency = buf[buf_offset++];
292 pedid->interlaced_audio_latency = buf[buf_offset++];
294 if (pedid->fields_present & 0x20) {
295 hdmi_edid_parse_3dinfo(buf + buf_offset,
300 pedid->sink_hdmi = 1;
302 pedid->hf_vsdb_version = buf[cur_offset + 4];
303 switch (pedid->hf_vsdb_version) {
304 case 1:/*compliant with HDMI Specification 2.0*/
306 pedid->maxtmdsclock =
307 buf[cur_offset + 5] * 5000000;
308 EDBG("[CEA] maxtmdsclock is %d.\n",
309 pedid->maxtmdsclock);
312 pedid->scdc_present = buf[cur_offset+6] >> 7;
314 (buf[cur_offset+6]&0x40) >> 6;
315 pedid->lte_340mcsc_scramble =
316 (buf[cur_offset+6]&0x08) >> 3;
317 pedid->independent_view =
318 (buf[cur_offset+6]&0x04) >> 2;
320 (buf[cur_offset+6]&0x02) >> 1;
321 pedid->osd_disparity_3d =
322 buf[cur_offset+6] & 0x01;
325 pedid->deepcolor = buf[cur_offset+7]&0x7;
326 EDBG("[CEA] deepcolor is %d.\n",
331 pr_info("hf_vsdb_version = %d\n",
332 pedid->hf_vsdb_version);
337 pr_info("IEEOUT = 0x%x\n", IEEEOUI);
343 static void hdmi_edid_parse_yuv420cmdb(unsigned char *buf, int count,
344 struct list_head *head)
346 struct list_head *pos;
347 struct display_modelist *modelist;
348 int i, j, yuv420_mask, vic;
350 for (i = 0; i < count - 1; i++) {
351 EDBG("vic which support yuv420 mode is %x\n", buf[i]);
352 yuv420_mask |= buf[i] << (8 * i);
354 for (i = 0; i < 32; i++) {
355 if (yuv420_mask & (1 << i)) {
357 for (pos = head->next; pos != (head); pos = pos->next) {
360 list_entry(pos, struct display_modelist, list);
361 vic = modelist->vic |
363 hdmi_add_vic(vic, head);
371 /* Parse CEA 861 Serial Extension. */
372 static int hdmi_edid_parse_extensions_cea(unsigned char *buf,
373 struct hdmi_edid *pedid)
375 unsigned int ddc_offset, native_dtd_num, cur_offset = 4;
376 unsigned int tag, IEEEOUI = 0, count, i;
377 /* unsigned int underscan_support, baseaudio_support; */
380 return E_HDMI_EDID_PARAM;
382 /* Check ces extension version */
384 pr_err("[CEA] error version.\n");
385 return E_HDMI_EDID_VERSION;
389 /* underscan_support = (buf[3] >> 7) & 0x01;
390 */ pedid->baseaudio_support = (buf[3] >> 6) & 0x01;
391 pedid->ycbcr444 = (buf[3] >> 5) & 0x01;
392 pedid->ycbcr422 = (buf[3] >> 4) & 0x01;
393 native_dtd_num = buf[3] & 0x0F;
394 /* EDBG("[CEA] ddc_offset %d underscan_support %d
395 baseaudio_support %d yuv_support %d
396 native_dtd_num %d\n",
397 ddc_offset, underscan_support, baseaudio_support,
398 yuv_support, native_dtd_num);
399 */ /* Parse data block */
400 while (cur_offset < ddc_offset) {
401 tag = buf[cur_offset] >> 5;
402 count = buf[cur_offset] & 0x1F;
404 case 0x02: /* Video Data Block */
405 EDBG("[CEA] Video Data Block.\n");
406 hdmi_edid_get_cea_svd(buf + cur_offset, pedid);
408 case 0x01: /* Audio Data Block */
409 EDBG("[CEA] Audio Data Block.\n");
410 hdmi_edid_parse_cea_sad(buf + cur_offset, pedid);
412 case 0x04: /* Speaker Allocation Data Block */
413 EDBG("[CEA] Speaker Allocatio Data Block.\n");
415 case 0x03: /* Vendor Specific Data Block */
416 EDBG("[CEA] Vendor Specific Data Block.\n");
418 IEEEOUI = buf[cur_offset + 3];
420 IEEEOUI += buf[cur_offset + 2];
422 IEEEOUI += buf[cur_offset + 1];
423 EDBG("[CEA] IEEEOUI is 0x%08x.\n", IEEEOUI);
425 hdmi_edmi_parse_vsdb(buf, pedid,
426 cur_offset, IEEEOUI);
428 case 0x05: /* VESA DTC Data Block */
429 EDBG("[CEA] VESA DTC Data Block.\n");
431 case 0x07: /* Use Extended Tag */
432 EDBG("[CEA] Use Extended Tag Data Block %02x.\n",
433 buf[cur_offset + 1]);
434 switch (buf[cur_offset + 1]) {
436 EDBG("[CEA] Video Capability Data Block\n");
437 EDBG("value is %02x\n", buf[cur_offset + 2]);
440 EDBG("[CEA] Colorimetry Data Block\n");
441 EDBG("value is %02x\n", buf[cur_offset + 2]);
444 EDBG("[CEA] YCBCR 4:2:0 Video Data Block\n");
445 for (i = 0; i < count - 1; i++) {
447 buf[cur_offset + 2 + i]);
449 IEEEOUI = buf[cur_offset + 2 + i] |
451 hdmi_add_vic(IEEEOUI,
456 EDBG("[CEA] YCBCR 4:2:0 Capability Map Data\n");
457 hdmi_edid_parse_yuv420cmdb(&buf[cur_offset+2],
465 pr_err("[CEA] unkowned data block tag.\n");
468 cur_offset += (buf[cur_offset] & 0x1F) + 1;
473 struct fb_videomode *vmode =
474 kmalloc(sizeof(struct fb_videomode), GFP_KERNEL);
477 return E_HDMI_EDID_SUCCESS;
478 while (ddc_offset < HDMI_EDID_BLOCK_SIZE - 2) {
479 if (!buf[ddc_offset] && !buf[ddc_offset + 1])
481 memset(vmode, 0, sizeof(struct fb_videomode));
482 hdmi_edid_parse_dtd(buf + ddc_offset, vmode);
483 hdmi_add_vic(hdmi_videomode_to_vic(vmode), &pedid->modelist);
489 return E_HDMI_EDID_SUCCESS;
492 int hdmi_edid_parse_extensions(unsigned char *buf, struct hdmi_edid *pedid)
496 if (buf == NULL || pedid == NULL)
497 return E_HDMI_EDID_PARAM;
500 rc = hdmi_edid_checksum(buf);
501 if (rc != E_HDMI_EDID_SUCCESS) {
502 pr_err("[EDID] extensions block checksum error\n");
503 return E_HDMI_EDID_CHECKSUM;
508 EDBG("[EDID-EXTEND] Iextensions block map.\n");
511 EDBG("[EDID-EXTEND] CEA 861 Series Extension.\n");
512 hdmi_edid_parse_extensions_cea(buf, pedid);
515 EDBG("[EDID-EXTEND] Video Timing Block Extension.\n");
518 EDBG("[EDID-EXTEND] Display Information Extension.\n");
521 EDBG("[EDID-EXTEND] Localized String Extension.\n");
524 EDBG("[EDID-EXTEND] Digital Packet Video Link Extension.\n");
527 pr_err("[EDID-EXTEND] Unkowned Extension.\n");
528 return E_HDMI_EDID_UNKOWNDATA;
531 return E_HDMI_EDID_SUCCESS;