drivers/video/rockchip/hdmi/rockchip-hdmiv2/rockchip_hdmiv2_hw.c

   1 #include <linux/clk.h>
   2 #include <linux/delay.h>
   3 #include <linux/interrupt.h>
   4 #include <linux/rockchip/cru.h>
   5 #include <linux/rockchip/grf.h>
   6 #include <linux/rockchip/iomap.h>
   7 #include "rockchip_hdmiv2.h"
   8 #include "rockchip_hdmiv2_hw.h"
   9
  10 static const struct phy_mpll_config_tab PHY_MPLL_TABLE[] = {
  11 /*      tmdsclk = (pixclk / ref_cntrl ) * (fbdiv2 * fbdiv1) / nctrl / tmdsmhl
  12  *      opmode: 0:HDMI1.4       1:HDMI2.0
  13  *
  14  *      |pixclock|      tmdsclock|pixrepet|colordepth|prepdiv|tmdsmhl|opmode|
  15  *              fbdiv2|fbdiv1|ref_cntrl|nctrl|propctrl|intctrl|gmpctrl|
  16  */
  17         {27000000,      27000000,       0,      8,      0,      0,      0,
  18                 2,      3,      0,      3,      3,      0,      0},
  19         {27000000,      33750000,       0,      10,     1,      0,      0,
  20                 5,      1,      0,      3,      3,      0,      0},
  21         {27000000,      40500000,       0,      12,     2,      0,      0,
  22                 3,      3,      0,      3,      3,      0,      0},
  23         {27000000,      54000000,       0,      16,     3,      0,      0,
  24                 2,      3,      0,      2,      5,      0,      1},
  25         {59400000,      59400000,       0,      8,      0,      0,      0,
  26                 1,      3,      0,      2,      5,      0,      1},
  27         {59400000,      74250000,       0,      10,     1,      0,      0,
  28                 5,      0,      0,      2,      5,      0,      1},
  29         {59400000,      89100000,       0,      12,     2,      0,      0,
  30                 2,      2,      0,      2,      5,      0,      1},
  31         {59400000,      118800000,      0,      16,     3,      0,      0,
  32                 1,      3,      0,      1,      7,      0,      2},
  33         {65000000,      65000000,       0,      8,      0,      0,      0,
  34                 1,      3,      0,      2,      5,      0,      1},
  35         {74250000,      74250000,       0,      8,      0,      0,      0,
  36                 4,      3,      3,      2,      7,      0,      3},
  37         {74250000,      92812500,       0,      10,     1,      0,      0,
  38                 5,      0,      1,      1,      7,      0,      2},
  39         {74250000,      111375000,      0,      12,     2,      0,      0,
  40                 1,      2,      0,      1,      7,      0,      2},
  41         {74250000,      148500000,      0,      16,     3,      0,      0,
  42                 1,      3,      0,      1,      7,      0,      2},
  43         {83500000,      83500000,       0,      8,      0,      0,      0,
  44                 1,      3,      0,      2,      5,      0,      1},
  45         {85500000,      85500000,       0,      8,      0,      0,      0,
  46                 1,      3,      0,      2,      5,      0,      1},
  47         {106500000,     106500000,      0,      8,      0,      0,      0,
  48                 1,      1,      0,      1,      7,      0,      2},
  49         {108000000,     108000000,      0,      8,      0,      0,      0,
  50                 1,      1,      0,      1,      7,      0,      2},
  51         {146250000,     146250000,      0,      8,      0,      0,      0,
  52                 1,      1,      0,      1,      7,      0,      2},
  53         {148500000,     74250000,       0,      8,      0,      0,      0,
  54                 1,      1,      1,      1,      0,      0,      3},
  55         {148500000,     148500000,      0,      8,      0,      0,      0,
  56                 1,      1,      0,      1,      0,      0,      3},
  57         {148500000,     185625000,      0,      10,     1,      0,      0,
  58                 5,      0,      3,      0,      7,      0,      3},
  59         {148500000,     222750000,      0,      12,     2,      0,      0,
  60                 1,      2,      1,      0,      7,      0,      3},
  61         {148500000,     297000000,      0,      16,     3,      0,      0,
  62                 1,      1,      0,      0,      7,      0,      3},
  63         {297000000,     148500000,      0,      8,      0,      0,      0,
  64                 1,      0,      1,      0,      0,      0,      3},
  65         {297000000,     297000000,      0,      8,      0,      0,      0,
  66                 1,      0,      0,      0,      0,      0,      3},
  67         {297000000,     371250000,      0,      10,     1,      3,      1,
  68                 5,      1,      3,      1,      7,      0,      3},
  69         {297000000,     445500000,      0,      12,     2,      3,      1,
  70                 1,      2,      0,      1,      7,      0,      3},
  71         {297000000,     594000000,      0,      16,     3,      3,      1,
  72                 1,      3,      1,      0,      0,      0,      3},
  73         {594000000,     297000000,      0,      8,      0,      0,      0,
  74                 1,      0,      1,      0,      0,      0,      3},
  75         {594000000,     371250000,      0,      10,     1,      3,      1,
  76                 5,      0,      3,      0,      7,      0,      3},
  77         {594000000,     445500000,      0,      12,     2,      3,      1,
  78                 1,      2,      1,      1,      7,      0,      3},
  79         {594000000,     594000000,      0,      16,     3,      3,      1,
  80                 1,      3,      3,      0,      0,      0,      3},
  81         {594000000,     594000000,      0,      8,      0,      3,      1,
  82                 1,      3,      3,      0,      0,      0,      3},
  83 };
  84
  85 static const struct ext_pll_config_tab EXT_PLL_TABLE[] = {
  86         {27000000,      27000000,       8,      1,      90,     3,      2,
  87                 2,      10,     3,      3,      4,      0,      1,      40,
  88                 8},
  89         {27000000,      33750000,       10,     1,      90,     1,      3,
  90                 3,      10,     3,      3,      4,      0,      1,      40,
  91                 8},
  92         {59400000,      59400000,       8,      1,      99,     3,      2,
  93                 2,      1,      3,      3,      4,      0,      1,      40,
  94                 8},
  95         {59400000,      74250000,       10,     1,      99,     1,      2,
  96                 2,      1,      3,      3,      4,      0,      1,      40,
  97                 8},
  98         {74250000,      74250000,       8,      1,      99,     1,      2,
  99                 2,      1,      2,      3,      4,      0,      1,      40,
 100                 8},
 101         {74250000,      92812500,       10,     4,      495,    1,      2,
 102                 2,      1,      3,      3,      4,      0,      2,      40,
 103                 4},
 104         {148500000,     148500000,      8,      1,      99,     1,      1,
 105                 1,      1,      2,      2,      2,      0,      2,      40,
 106                 4},
 107         {148500000,     185625000,      10,     4,      495,    0,      2,
 108                 2,      1,      3,      2,      2,      0,      4,      40,
 109                 2},
 110         {297000000,     297000000,      8,      1,      99,     0,      1,
 111                 1,      1,      0,      2,      2,      0,      4,      40,
 112                 2},
 113         {297000000,     371250000,      10,     4,      495,    1,      2,
 114                 0,      1,      3,      1,      1,      0,      8,      40,
 115                 1},
 116         {594000000,     297000000,      8,      1,      99,     0,      1,
 117                 1,      1,      0,      2,      1,      0,      4,      40,
 118                 2},
 119         {594000000,     371250000,      10,     4,      495,    1,      2,
 120                 0,      1,      3,      1,      1,      1,      8,      40,
 121                 1},
 122         {594000000,     594000000,      8,      1,      99,     0,      2,
 123                 0,      1,      0,      1,      1,      0,      8,      40,
 124                 1},
 125 };
 126
 127 /* ddc i2c master reset */
 128 static void rockchip_hdmiv2_i2cm_reset(struct hdmi_dev *hdmi_dev)
 129 {
 130         hdmi_msk_reg(hdmi_dev, I2CM_SOFTRSTZ,
 131                      m_I2CM_SOFTRST, v_I2CM_SOFTRST(0));
 132         usleep_range(90, 100);
 133 }
 134
 135 /*set read/write offset,set read/write mode*/
 136 static void rockchip_hdmiv2_i2cm_write_request(struct hdmi_dev *hdmi_dev,
 137                                                u8 offset, u8 data)
 138 {
 139         hdmi_writel(hdmi_dev, I2CM_ADDRESS, offset);
 140         hdmi_writel(hdmi_dev, I2CM_DATAO, data);
 141         hdmi_msk_reg(hdmi_dev, I2CM_OPERATION, m_I2CM_WR, v_I2CM_WR(1));
 142 }
 143
 144 static void rockchip_hdmiv2_i2cm_read_request(struct hdmi_dev *hdmi_dev,
 145                                               u8 offset)
 146 {
 147         hdmi_writel(hdmi_dev, I2CM_ADDRESS, offset);
 148         hdmi_msk_reg(hdmi_dev, I2CM_OPERATION, m_I2CM_RD, v_I2CM_RD(1));
 149 }
 150
 151 static void rockchip_hdmiv2_i2cm_write_data(struct hdmi_dev *hdmi_dev,
 152                                             u8 data, u8 offset)
 153 {
 154         u8 interrupt;
 155         int trytime = 2;
 156         int i = 20;
 157
 158         while (trytime-- > 0) {
 159                 rockchip_hdmiv2_i2cm_write_request(hdmi_dev, offset, data);
 160                 while (i--) {
 161                         usleep_range(900, 1000);
 162                         interrupt = hdmi_readl(hdmi_dev, IH_I2CM_STAT0);
 163                         if (interrupt)
 164                                 hdmi_writel(hdmi_dev,
 165                                             IH_I2CM_STAT0, interrupt);
 166
 167                         if (interrupt & (m_SCDC_READREQ |
 168                                          m_I2CM_DONE | m_I2CM_ERROR))
 169                                 break;
 170                 }
 171
 172                 if (interrupt & m_I2CM_DONE) {
 173                         dev_dbg(hdmi_dev->hdmi->dev,
 174                                 "[%s] write offset %02x data %02x success\n",
 175                                 __func__, offset, data);
 176                         trytime = 0;
 177                 } else if ((interrupt & m_I2CM_ERROR) || (i == -1)) {
 178                         dev_err(hdmi_dev->hdmi->dev,
 179                                 "[%s] write data error\n", __func__);
 180                         rockchip_hdmiv2_i2cm_reset(hdmi_dev);
 181                 }
 182         }
 183 }
 184
 185 static int rockchip_hdmiv2_i2cm_read_data(struct hdmi_dev *hdmi_dev, u8 offset)
 186 {
 187         u8 interrupt, val;
 188         int trytime = 2;
 189         int i = 20;
 190
 191         while (trytime-- > 0) {
 192                 rockchip_hdmiv2_i2cm_read_request(hdmi_dev, offset);
 193                 while (i--) {
 194                         usleep_range(900, 1000);
 195                         interrupt = hdmi_readl(hdmi_dev, IH_I2CM_STAT0);
 196                         if (interrupt)
 197                                 hdmi_writel(hdmi_dev, IH_I2CM_STAT0, interrupt);
 198
 199                         if (interrupt & (m_SCDC_READREQ |
 200                                 m_I2CM_DONE | m_I2CM_ERROR))
 201                                 break;
 202                 }
 203
 204                 if (interrupt & m_I2CM_DONE) {
 205                         val = hdmi_readl(hdmi_dev, I2CM_DATAI);
 206                         trytime = 0;
 207                 } else if ((interrupt & m_I2CM_ERROR) || (i == -1)) {
 208                         pr_err("[%s] read data error\n", __func__);
 209                         rockchip_hdmiv2_i2cm_reset(hdmi_dev);
 210                 }
 211         }
 212         return val;
 213 }
 214
 215 static void rockchip_hdmiv2_i2cm_mask_int(struct hdmi_dev *hdmi_dev, int mask)
 216 {
 217         if (!mask) {
 218                 hdmi_msk_reg(hdmi_dev, I2CM_INT,
 219                              m_I2CM_DONE_MASK, v_I2CM_DONE_MASK(0));
 220                 hdmi_msk_reg(hdmi_dev, I2CM_CTLINT,
 221                              m_I2CM_NACK_MASK | m_I2CM_ARB_MASK,
 222                              v_I2CM_NACK_MASK(0) | v_I2CM_ARB_MASK(0));
 223         } else {
 224                 hdmi_msk_reg(hdmi_dev, I2CM_INT,
 225                              m_I2CM_DONE_MASK, v_I2CM_DONE_MASK(1));
 226                 hdmi_msk_reg(hdmi_dev, I2CM_CTLINT,
 227                              m_I2CM_NACK_MASK | m_I2CM_ARB_MASK,
 228                              v_I2CM_NACK_MASK(1) | v_I2CM_ARB_MASK(1));
 229         }
 230 }
 231
 232 #define I2C_DIV_FACTOR 1000000
 233 static u16 i2c_count(u16 sfrclock, u16 sclmintime)
 234 {
 235         unsigned long tmp_scl_period = 0;
 236
 237         if (((sfrclock * sclmintime) % I2C_DIV_FACTOR) != 0)
 238                 tmp_scl_period = (unsigned long)((sfrclock * sclmintime) +
 239                                 (I2C_DIV_FACTOR - ((sfrclock * sclmintime) %
 240                                 I2C_DIV_FACTOR))) / I2C_DIV_FACTOR;
 241         else
 242                 tmp_scl_period = (unsigned long)(sfrclock * sclmintime) /
 243                                 I2C_DIV_FACTOR;
 244
 245         return (u16)(tmp_scl_period);
 246 }
 247
 248 #define EDID_I2C_MIN_SS_SCL_HIGH_TIME   9625
 249 #define EDID_I2C_MIN_SS_SCL_LOW_TIME    10000
 250
 251 static void rockchip_hdmiv2_i2cm_clk_init(struct hdmi_dev *hdmi_dev)
 252 {
 253         int value;
 254
 255         /* Set DDC I2C CLK which devided from DDC_CLK. */
 256         value = i2c_count(24000, EDID_I2C_MIN_SS_SCL_HIGH_TIME);
 257         hdmi_writel(hdmi_dev, I2CM_SS_SCL_HCNT_0_ADDR,
 258                     value & 0xff);
 259         hdmi_writel(hdmi_dev, I2CM_SS_SCL_HCNT_1_ADDR,
 260                     (value >> 8) & 0xff);
 261         value = i2c_count(24000, EDID_I2C_MIN_SS_SCL_LOW_TIME);
 262         hdmi_writel(hdmi_dev, I2CM_SS_SCL_LCNT_0_ADDR,
 263                     value & 0xff);
 264         hdmi_writel(hdmi_dev, I2CM_SS_SCL_LCNT_1_ADDR,
 265                     (value >> 8) & 0xff);
 266         hdmi_msk_reg(hdmi_dev, I2CM_DIV, m_I2CM_FAST_STD_MODE,
 267                      v_I2CM_FAST_STD_MODE(STANDARD_MODE));
 268 }
 269
 270 static int rockchip_hdmiv2_scdc_get_sink_version(struct hdmi_dev *hdmi_dev)
 271 {
 272         return rockchip_hdmiv2_i2cm_read_data(hdmi_dev, SCDC_SINK_VER);
 273 }
 274
 275 static void rockchip_hdmiv2_scdc_set_source_version(struct hdmi_dev *hdmi_dev,
 276                                                     u8 version)
 277 {
 278         rockchip_hdmiv2_i2cm_write_data(hdmi_dev, version, SCDC_SOURCE_VER);
 279 }
 280
 281
 282 static void rockchip_hdmiv2_scdc_read_request(struct hdmi_dev *hdmi_dev,
 283                                               int enable)
 284 {
 285         hdmi_msk_reg(hdmi_dev, I2CM_SCDC_READ_UPDATE,
 286                      m_I2CM_READ_REQ_EN, v_I2CM_READ_REQ_EN(enable));
 287         rockchip_hdmiv2_i2cm_write_data(hdmi_dev, enable, SCDC_CONFIG_0);
 288 }
 289
 290 #ifdef HDMI_20_SCDC
 291 static void rockchip_hdmiv2_scdc_update_read(struct hdmi_dev *hdmi_dev)
 292 {
 293         hdmi_msk_reg(hdmi_dev, I2CM_SCDC_READ_UPDATE,
 294                      m_I2CM_READ_UPDATE, v_I2CM_READ_UPDATE(1));
 295 }
 296
 297
 298 static int rockchip_hdmiv2_scdc_get_scambling_status(struct hdmi_dev *hdmi_dev)
 299 {
 300         int val;
 301
 302         val = rockchip_hdmiv2_i2cm_read_data(hdmi_dev, SCDC_SCRAMBLER_STAT);
 303         return val;
 304 }
 305
 306 static void rockchip_hdmiv2_scdc_enable_polling(struct hdmi_dev *hdmi_dev,
 307                                                 int enable)
 308 {
 309         rockchip_hdmiv2_scdc_read_request(hdmi_dev, enable);
 310         hdmi_msk_reg(hdmi_dev, I2CM_SCDC_READ_UPDATE,
 311                      m_I2CM_UPRD_VSYNC_EN, v_I2CM_UPRD_VSYNC_EN(enable));
 312 }
 313
 314 static int rockchip_hdmiv2_scdc_get_status_reg0(struct hdmi_dev *hdmi_dev)
 315 {
 316         rockchip_hdmiv2_scdc_read_request(hdmi_dev, 1);
 317         rockchip_hdmiv2_scdc_update_read(hdmi_dev);
 318         return hdmi_readl(hdmi_dev, I2CM_SCDC_UPDATE0);
 319 }
 320
 321 static int rockchip_hdmiv2_scdc_get_status_reg1(struct hdmi_dev *hdmi_dev)
 322 {
 323         rockchip_hdmiv2_scdc_read_request(hdmi_dev, 1);
 324         rockchip_hdmiv2_scdc_update_read(hdmi_dev);
 325         return hdmi_readl(hdmi_dev, I2CM_SCDC_UPDATE1);
 326 }
 327 #endif
 328
 329 static void rockchip_hdmiv2_scdc_init(struct hdmi_dev *hdmi_dev)
 330 {
 331         rockchip_hdmiv2_i2cm_reset(hdmi_dev);
 332         rockchip_hdmiv2_i2cm_mask_int(hdmi_dev, 1);
 333         rockchip_hdmiv2_i2cm_clk_init(hdmi_dev);
 334         /* set scdc i2c addr */
 335         hdmi_writel(hdmi_dev, I2CM_SLAVE, DDC_I2C_SCDC_ADDR);
 336         rockchip_hdmiv2_i2cm_mask_int(hdmi_dev, 0);/*enable interrupt*/
 337 }
 338
 339 static void rockchip_hdmiv2_scdc_set_tmds_rate(struct hdmi_dev *hdmi_dev)
 340 {
 341         int stat;
 342
 343         mutex_lock(&hdmi_dev->ddc_lock);
 344         rockchip_hdmiv2_scdc_init(hdmi_dev);
 345         stat = rockchip_hdmiv2_i2cm_read_data(hdmi_dev,
 346                                               SCDC_TMDS_CONFIG);
 347         if (hdmi_dev->tmdsclk > 340000000)
 348                 stat |= 2;
 349         else
 350                 stat &= 0x1;
 351         rockchip_hdmiv2_i2cm_write_data(hdmi_dev,
 352                                         stat, SCDC_TMDS_CONFIG);
 353         mutex_unlock(&hdmi_dev->ddc_lock);
 354 }
 355
 356 static int rockchip_hdmiv2_scrambling_enable(struct hdmi_dev *hdmi_dev,
 357                                              int enable)
 358 {
 359         HDMIDBG("%s enable %d\n", __func__, enable);
 360         if (enable == 1) {
 361                 /* Write on Rx the bit Scrambling_Enable, register 0x20 */
 362                 rockchip_hdmiv2_i2cm_write_data(hdmi_dev, 1, SCDC_TMDS_CONFIG);
 363                 /* TMDS software reset request */
 364                 hdmi_msk_reg(hdmi_dev, MC_SWRSTZREQ,
 365                              m_TMDS_SWRST, v_TMDS_SWRST(0));
 366                 /* Enable/Disable Scrambling */
 367                 hdmi_msk_reg(hdmi_dev, FC_SCRAMBLER_CTRL,
 368                              m_FC_SCRAMBLE_EN, v_FC_SCRAMBLE_EN(1));
 369         } else {
 370                 /* Enable/Disable Scrambling */
 371                 hdmi_msk_reg(hdmi_dev, FC_SCRAMBLER_CTRL,
 372                              m_FC_SCRAMBLE_EN, v_FC_SCRAMBLE_EN(0));
 373                 /* TMDS software reset request */
 374                 hdmi_msk_reg(hdmi_dev, MC_SWRSTZREQ,
 375                              m_TMDS_SWRST, v_TMDS_SWRST(0));
 376                 /* Write on Rx the bit Scrambling_Enable, register 0x20 */
 377                 rockchip_hdmiv2_i2cm_write_data(hdmi_dev, 0, SCDC_TMDS_CONFIG);
 378         }
 379         return 0;
 380 }
 381
 382 static const struct ext_pll_config_tab *get_phy_ext_tab(
 383                 unsigned int pixclock, unsigned int tmdsclk,
 384                 char colordepth)
 385 {
 386         int i;
 387
 388         if (pixclock == 0)
 389                 return NULL;
 390         HDMIDBG("%s pixClock %u tmdsclk %u colorDepth %d\n",
 391                 __func__, pixclock, tmdsclk, colordepth);
 392         for (i = 0; i < ARRAY_SIZE(EXT_PLL_TABLE); i++) {
 393                 if ((EXT_PLL_TABLE[i].pix_clock == pixclock) &&
 394                     (EXT_PLL_TABLE[i].tmdsclock == tmdsclk) &&
 395                     (EXT_PLL_TABLE[i].color_depth == colordepth))
 396                         return &EXT_PLL_TABLE[i];
 397         }
 398         return NULL;
 399 }
 400
 401 static const struct phy_mpll_config_tab *get_phy_mpll_tab(
 402                 unsigned int pixclock, unsigned int tmdsclk,
 403                 char pixrepet, char colordepth)
 404 {
 405         int i;
 406
 407         if (pixclock == 0)
 408                 return NULL;
 409         HDMIDBG("%s pixClock %u tmdsclk %u pixRepet %d colorDepth %d\n",
 410                 __func__, pixclock, tmdsclk, pixrepet, colordepth);
 411         for (i = 0; i < ARRAY_SIZE(PHY_MPLL_TABLE); i++) {
 412                 if ((PHY_MPLL_TABLE[i].pix_clock == pixclock) &&
 413                     (PHY_MPLL_TABLE[i].tmdsclock == tmdsclk) &&
 414                     (PHY_MPLL_TABLE[i].pix_repet == pixrepet) &&
 415                     (PHY_MPLL_TABLE[i].color_depth == colordepth))
 416                         return &PHY_MPLL_TABLE[i];
 417         }
 418         return NULL;
 419 }
 420
 421 static void rockchip_hdmiv2_powerdown(struct hdmi_dev *hdmi_dev)
 422 {
 423         hdmi_msk_reg(hdmi_dev, PHY_MASK, m_PHY_LOCK, v_PHY_LOCK(1));
 424         if (hdmi_dev->soctype != HDMI_SOC_RK322X) {
 425                 hdmi_msk_reg(hdmi_dev, PHY_CONF0,
 426                              m_PDDQ_SIG | m_TXPWRON_SIG |
 427                              m_ENHPD_RXSENSE_SIG | m_SVSRET_SIG,
 428                              v_PDDQ_SIG(1) | v_TXPWRON_SIG(0) |
 429                              v_ENHPD_RXSENSE_SIG(1)) | v_SVSRET_SIG(0);
 430         } else {
 431                 hdmi_msk_reg(hdmi_dev, PHY_CONF0,
 432                              m_TXPWRON_SIG | m_ENHPD_RXSENSE_SIG,
 433                              v_TXPWRON_SIG(0) | v_ENHPD_RXSENSE_SIG(0));
 434                 regmap_write(hdmi_dev->grf_base,
 435                              RK322X_GRF_SOC_CON2,
 436                              RK322X_PLL_PDATA_DEN);
 437         }
 438         hdmi_writel(hdmi_dev, MC_CLKDIS, 0x7f);
 439 }
 440
 441 int rockchip_hdmiv2_write_phy(struct hdmi_dev *hdmi_dev,
 442                               int reg_addr, int val)
 443 {
 444         int trytime = 2, i = 0, op_status = 0;
 445
 446         if (hdmi_dev->phybase) {
 447                 writel_relaxed(val, hdmi_dev->phybase + (reg_addr) * 0x04);
 448                 return 0;
 449         }
 450         while (trytime--) {
 451                 hdmi_writel(hdmi_dev, PHY_I2CM_ADDRESS, reg_addr);
 452                 hdmi_writel(hdmi_dev, PHY_I2CM_DATAO_1, (val >> 8) & 0xff);
 453                 hdmi_writel(hdmi_dev, PHY_I2CM_DATAO_0, val & 0xff);
 454                 hdmi_writel(hdmi_dev, PHY_I2CM_OPERATION, m_PHY_I2CM_WRITE);
 455
 456                 i = 20;
 457                 while (i--) {
 458                         usleep_range(900, 1000);
 459                         op_status = hdmi_readl(hdmi_dev, IH_I2CMPHY_STAT0);
 460                         if (op_status)
 461                                 hdmi_writel(hdmi_dev,
 462                                             IH_I2CMPHY_STAT0,
 463                                             op_status);
 464
 465                         if (op_status & (m_I2CMPHY_DONE | m_I2CMPHY_ERR))
 466                                 break;
 467                 }
 468
 469                 if (!(op_status & m_I2CMPHY_DONE))
 470                         dev_err(hdmi_dev->hdmi->dev,
 471                                 "[%s] operation error,trytime=%d\n",
 472                                 __func__, trytime);
 473                 else
 474                         return 0;
 475                 msleep(100);
 476         }
 477
 478         return -1;
 479 }
 480
 481 int rockchip_hdmiv2_read_phy(struct hdmi_dev *hdmi_dev,
 482                              int reg_addr)
 483 {
 484         int trytime = 2, i = 0, op_status = 0;
 485         int val = 0;
 486
 487         if (hdmi_dev->phybase)
 488                 return readl_relaxed(hdmi_dev->phybase + (reg_addr) * 0x04);
 489
 490         while (trytime--) {
 491                 hdmi_writel(hdmi_dev, PHY_I2CM_ADDRESS, reg_addr);
 492                 hdmi_writel(hdmi_dev, PHY_I2CM_DATAI_1, 0x00);
 493                 hdmi_writel(hdmi_dev, PHY_I2CM_DATAI_0, 0x00);
 494                 hdmi_writel(hdmi_dev, PHY_I2CM_OPERATION, m_PHY_I2CM_READ);
 495
 496                 i = 20;
 497                 while (i--) {
 498                         usleep_range(900, 1000);
 499                         op_status = hdmi_readl(hdmi_dev, IH_I2CMPHY_STAT0);
 500                         if (op_status)
 501                                 hdmi_writel(hdmi_dev, IH_I2CMPHY_STAT0,
 502                                             op_status);
 503
 504                         if (op_status & (m_I2CMPHY_DONE | m_I2CMPHY_ERR))
 505                                 break;
 506                 }
 507
 508                 if (!(op_status & m_I2CMPHY_DONE)) {
 509                         pr_err("[%s] operation error,trytime=%d\n",
 510                                __func__, trytime);
 511                 } else {
 512                         val = hdmi_readl(hdmi_dev, PHY_I2CM_DATAI_1);
 513                         val = (val & 0xff) << 8;
 514                         val += (hdmi_readl(hdmi_dev, PHY_I2CM_DATAI_0) & 0xff);
 515                         pr_debug("phy_reg0x%02x: 0x%04x",
 516                                  reg_addr, val);
 517                         return val;
 518                 }
 519                 msleep(100);
 520         }
 521
 522         return -1;
 523 }
 524
 525 #define PHY_TIMEOUT     10000
 526
 527 static int ext_phy_config(struct hdmi_dev *hdmi_dev)
 528 {
 529         int stat = 0, i = 0, temp;
 530         const struct ext_pll_config_tab *phy_ext = NULL;
 531
 532         if (hdmi_dev->grf_base)
 533                 regmap_write(hdmi_dev->grf_base,
 534                              RK322X_GRF_SOC_CON2,
 535                              RK322X_PLL_POWER_DOWN |
 536                              RK322X_PLL_PDATA_DEN);
 537         if (hdmi_dev->tmdsclk_ratio_change &&
 538             hdmi_dev->hdmi->edid.scdc_present == 1)
 539                 rockchip_hdmiv2_scdc_set_tmds_rate(hdmi_dev);
 540
 541         /* config the required PHY I2C register */
 542         phy_ext = get_phy_ext_tab(hdmi_dev->pixelclk,
 543                                   hdmi_dev->tmdsclk,
 544                                   hdmi_dev->colordepth);
 545         if (phy_ext) {
 546                 stat = ((phy_ext->pll_nf >> 1) & EXT_PHY_PLL_FB_BIT8_MASK) |
 547                        ((phy_ext->vco_div_5 & 1) << 5) |
 548                        (phy_ext->pll_nd & EXT_PHY_PLL_PRE_DIVIDER_MASK);
 549                 rockchip_hdmiv2_write_phy(hdmi_dev,
 550                                           EXT_PHY_PLL_PRE_DIVIDER, stat);
 551                 stat = phy_ext->pll_nf & 0xff;
 552                 rockchip_hdmiv2_write_phy(hdmi_dev,
 553                                           EXT_PHY_PLL_FB_DIVIDER, stat);
 554                 stat = (phy_ext->pclk_divider_a & EXT_PHY_PCLK_DIVIDERA_MASK) |
 555                        ((phy_ext->pclk_divider_b & 3) << 5);
 556                 rockchip_hdmiv2_write_phy(hdmi_dev,
 557                                           EXT_PHY_PCLK_DIVIDER1, stat);
 558                 stat = (phy_ext->pclk_divider_d & EXT_PHY_PCLK_DIVIDERD_MASK) |
 559                        ((phy_ext->pclk_divider_c & 3) << 5);
 560                 rockchip_hdmiv2_write_phy(hdmi_dev,
 561                                           EXT_PHY_PCLK_DIVIDER2, stat);
 562                 stat = ((phy_ext->tmsd_divider_c & 3) << 4) |
 563                        ((phy_ext->tmsd_divider_a & 3) << 2) |
 564                        (phy_ext->tmsd_divider_b & 3);
 565                 rockchip_hdmiv2_write_phy(hdmi_dev,
 566                                           EXT_PHY_TMDSCLK_DIVIDER, stat);
 567                 rockchip_hdmiv2_write_phy(hdmi_dev,
 568                                           EXT_PHY_PPLL_FB_DIVIDER,
 569                                           phy_ext->ppll_nf);
 570
 571                 if (phy_ext->ppll_no == 1) {
 572                         rockchip_hdmiv2_write_phy(hdmi_dev,
 573                                                   EXT_PHY_PPLL_POST_DIVIDER,
 574                                                   0);
 575                         stat = 0x20 | phy_ext->ppll_nd;
 576                         rockchip_hdmiv2_write_phy(hdmi_dev,
 577                                                   EXT_PHY_PPLL_PRE_DIVIDER,
 578                                                   stat);
 579                 } else {
 580                         stat = ((phy_ext->ppll_no / 2) - 1) << 4;
 581                         rockchip_hdmiv2_write_phy(hdmi_dev,
 582                                                   EXT_PHY_PPLL_POST_DIVIDER,
 583                                                   stat);
 584                         stat = 0xe0 | phy_ext->ppll_nd;
 585                         rockchip_hdmiv2_write_phy(hdmi_dev,
 586                                                   EXT_PHY_PPLL_PRE_DIVIDER,
 587                                                   stat);
 588                 }
 589         } else {
 590                 pr_err("%s no supported phy configuration.\n", __func__);
 591                 return -1;
 592         }
 593
 594         if (hdmi_dev->phy_table) {
 595                 for (i = 0; i < hdmi_dev->phy_table_size; i++) {
 596                         temp = hdmi_dev->phy_table[i].maxfreq;
 597                         if (hdmi_dev->tmdsclk <= temp)
 598                                 break;
 599                 }
 600         }
 601
 602         if (i != hdmi_dev->phy_table_size) {
 603                 if (hdmi_dev->phy_table[i].slopeboost) {
 604                         rockchip_hdmiv2_write_phy(hdmi_dev,
 605                                                   EXT_PHY_SIGNAL_CTRL, 0xff);
 606                         temp = hdmi_dev->phy_table[i].slopeboost - 1;
 607                         stat = ((temp & 3) << 6) | ((temp & 3) << 4) |
 608                                ((temp & 3) << 2) | (temp & 3);
 609                         rockchip_hdmiv2_write_phy(hdmi_dev,
 610                                                   EXT_PHY_SLOPEBOOST, stat);
 611                 } else {
 612                         rockchip_hdmiv2_write_phy(hdmi_dev,
 613                                                   EXT_PHY_SIGNAL_CTRL, 0x0f);
 614                 }
 615                 stat = ((hdmi_dev->phy_table[i].pre_emphasis & 3) << 4) |
 616                        ((hdmi_dev->phy_table[i].pre_emphasis & 3) << 2) |
 617                        (hdmi_dev->phy_table[i].pre_emphasis & 3);
 618                 rockchip_hdmiv2_write_phy(hdmi_dev,
 619                                           EXT_PHY_PREEMPHASIS, stat);
 620                 stat = ((hdmi_dev->phy_table[i].clk_level & 0xf) << 4) |
 621                        (hdmi_dev->phy_table[i].data2_level & 0xf);
 622                 rockchip_hdmiv2_write_phy(hdmi_dev,
 623                                           EXT_PHY_LEVEL1, stat);
 624                 stat = ((hdmi_dev->phy_table[i].data1_level & 0xf) << 4) |
 625                        (hdmi_dev->phy_table[i].data0_level & 0xf);
 626                 rockchip_hdmiv2_write_phy(hdmi_dev,
 627                                           EXT_PHY_LEVEL2, stat);
 628         } else {
 629                 rockchip_hdmiv2_write_phy(hdmi_dev,
 630                                           EXT_PHY_SIGNAL_CTRL, 0x0f);
 631         }
 632         rockchip_hdmiv2_write_phy(hdmi_dev, 0xf3, 0x22);
 633
 634         stat = clk_get_rate(hdmi_dev->pclk_phy) / 100000;
 635         rockchip_hdmiv2_write_phy(hdmi_dev, EXT_PHY_TERM_CAL,
 636                                   ((stat >> 8) & 0xff) | 0x80);
 637         rockchip_hdmiv2_write_phy(hdmi_dev, EXT_PHY_TERM_CAL_DIV_L,
 638                                   stat & 0xff);
 639         if (hdmi_dev->tmdsclk > 340000000)
 640                 stat = EXT_PHY_AUTO_R100_OHMS;
 641         else if (hdmi_dev->tmdsclk > 200000000)
 642                 stat = EXT_PHY_AUTO_R50_OHMS;
 643         else
 644                 stat = EXT_PHY_AUTO_ROPEN_CIRCUIT;
 645         rockchip_hdmiv2_write_phy(hdmi_dev, EXT_PHY_TERM_RESIS_AUTO,
 646                                   stat | 0x20);
 647         rockchip_hdmiv2_write_phy(hdmi_dev, EXT_PHY_TERM_CAL,
 648                                   (stat >> 8) & 0xff);
 649         if (hdmi_dev->tmdsclk > 200000000)
 650                 stat = 0;
 651         else
 652                 stat = 0x11;
 653         rockchip_hdmiv2_write_phy(hdmi_dev, EXT_PHY_PLL_BW, stat);
 654         rockchip_hdmiv2_write_phy(hdmi_dev, EXT_PHY_PPLL_BW, 0x27);
 655         if (hdmi_dev->grf_base)
 656                 regmap_write(hdmi_dev->grf_base,
 657                              RK322X_GRF_SOC_CON2,
 658                              RK322X_PLL_POWER_UP);
 659         if (hdmi_dev->tmdsclk_ratio_change)
 660                 msleep(100);
 661         else
 662                 usleep_range(900, 1000);
 663         hdmi_msk_reg(hdmi_dev, PHY_CONF0,
 664                      m_TXPWRON_SIG, v_TXPWRON_SIG(1));
 665         i = 0;
 666         while (i++ < PHY_TIMEOUT) {
 667                 if ((i % 10) == 0) {
 668                         temp = EXT_PHY_PPLL_POST_DIVIDER;
 669                         stat = rockchip_hdmiv2_read_phy(hdmi_dev, temp);
 670                         if (stat & EXT_PHY_PPLL_LOCK_STATUS_MASK)
 671                                 break;
 672                         usleep_range(1000, 2000);
 673                 }
 674         }
 675         if ((stat & EXT_PHY_PPLL_LOCK_STATUS_MASK) == 0) {
 676                 stat = hdmi_readl(hdmi_dev, MC_LOCKONCLOCK);
 677                 dev_err(hdmi_dev->hdmi->dev,
 678                         "PHY PLL not locked: PCLK_ON=%d,TMDSCLK_ON=%d\n",
 679                         (stat & m_PCLK_ON) >> 6, (stat & m_TMDSCLK_ON) >> 5);
 680                 return -1;
 681         }
 682
 683         if (hdmi_dev->grf_base)
 684                 regmap_write(hdmi_dev->grf_base,
 685                              RK322X_GRF_SOC_CON2,
 686                              RK322X_PLL_PDATA_EN);
 687
 688         return 0;
 689 }
 690
 691 static int rockchip_hdmiv2_config_phy(struct hdmi_dev *hdmi_dev)
 692 {
 693         int stat = 0, i = 0;
 694         const struct phy_mpll_config_tab *phy_mpll = NULL;
 695
 696         if (hdmi_dev->soctype == HDMI_SOC_RK322X)
 697                 return ext_phy_config(hdmi_dev);
 698
 699         hdmi_msk_reg(hdmi_dev, PHY_I2CM_DIV,
 700                      m_PHY_I2CM_FAST_STD, v_PHY_I2CM_FAST_STD(0));
 701         hdmi_msk_reg(hdmi_dev, PHY_MASK, m_PHY_LOCK, v_PHY_LOCK(1));
 702         /* power off PHY */
 703         hdmi_msk_reg(hdmi_dev, PHY_CONF0,
 704                      m_PDDQ_SIG | m_TXPWRON_SIG | m_SVSRET_SIG,
 705                      v_PDDQ_SIG(1) | v_TXPWRON_SIG(0) | v_SVSRET_SIG(1));
 706
 707         if (hdmi_dev->tmdsclk_ratio_change &&
 708             hdmi_dev->hdmi->edid.scdc_present == 1)
 709                 rockchip_hdmiv2_scdc_set_tmds_rate(hdmi_dev);
 710
 711         /* reset PHY */
 712         hdmi_writel(hdmi_dev, MC_PHYRSTZ, v_PHY_RSTZ(1));
 713         usleep_range(1000, 2000);
 714         hdmi_writel(hdmi_dev, MC_PHYRSTZ, v_PHY_RSTZ(0));
 715
 716         /* Set slave address as PHY GEN2 address */
 717         hdmi_writel(hdmi_dev, PHY_I2CM_SLAVE, PHY_GEN2_ADDR);
 718
 719         /* config the required PHY I2C register */
 720         phy_mpll = get_phy_mpll_tab(hdmi_dev->pixelclk,
 721                                     hdmi_dev->tmdsclk,
 722                                     hdmi_dev->pixelrepeat - 1,
 723                                     hdmi_dev->colordepth);
 724         if (phy_mpll) {
 725                 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_OPMODE_PLLCFG,
 726                                           v_PREP_DIV(phy_mpll->prep_div) |
 727                                           v_TMDS_CNTRL(
 728                                           phy_mpll->tmdsmhl_cntrl) |
 729                                           v_OPMODE(phy_mpll->opmode) |
 730                                           v_FBDIV2_CNTRL(
 731                                           phy_mpll->fbdiv2_cntrl) |
 732                                           v_FBDIV1_CNTRL(
 733                                           phy_mpll->fbdiv1_cntrl) |
 734                                           v_REF_CNTRL(phy_mpll->ref_cntrl) |
 735                                           v_MPLL_N_CNTRL(phy_mpll->n_cntrl));
 736                 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_PLLCURRCTRL,
 737                                           v_MPLL_PROP_CNTRL(
 738                                           phy_mpll->prop_cntrl) |
 739                                           v_MPLL_INT_CNTRL(
 740                                           phy_mpll->int_cntrl));
 741                 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_PLLGMPCTRL,
 742                                           v_MPLL_GMP_CNTRL(
 743                                           phy_mpll->gmp_cntrl));
 744         }
 745
 746         if (hdmi_dev->phy_table) {
 747                 for (i = 0; i < hdmi_dev->phy_table_size; i++)
 748                         if (hdmi_dev->tmdsclk <= hdmi_dev->phy_table[i].maxfreq)
 749                                 break;
 750         }
 751         if (i == hdmi_dev->phy_table_size) {
 752                 pr_info("%s use default phy settings\n", __func__);
 753                 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_CLKSYMCTRL,
 754                                           v_OVERRIDE(1) | v_SLOPEBOOST(0) |
 755                                           v_TX_SYMON(1) | v_CLK_SYMON(1) |
 756                                           v_PREEMPHASIS(0));
 757                 if (hdmi_dev->tmdsclk > 340000000)
 758                         rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_VLEVCTRL,
 759                                                   v_SUP_TXLVL(9) |
 760                                                   v_SUP_CLKLVL(17));
 761                 else if (hdmi_dev->tmdsclk > 165000000)
 762                         rockchip_hdmiv2_write_phy(hdmi_dev,
 763                                                   PHYTX_VLEVCTRL,
 764                                                   v_SUP_TXLVL(14) |
 765                                                   v_SUP_CLKLVL(17));
 766                 else
 767                         rockchip_hdmiv2_write_phy(hdmi_dev,
 768                                                   PHYTX_VLEVCTRL,
 769                                                   v_SUP_TXLVL(18) |
 770                                                   v_SUP_CLKLVL(17));
 771         } else {
 772                 stat = v_OVERRIDE(1) | v_TX_SYMON(1) | v_CLK_SYMON(1) |
 773                        v_PREEMPHASIS(hdmi_dev->phy_table[i].pre_emphasis) |
 774                        v_SLOPEBOOST(hdmi_dev->phy_table[i].slopeboost);
 775                 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_CLKSYMCTRL, stat);
 776
 777                 stat = v_SUP_CLKLVL(hdmi_dev->phy_table[i].clk_level) |
 778                        v_SUP_TXLVL(hdmi_dev->phy_table[i].data0_level);
 779                 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_VLEVCTRL, stat);
 780         }
 781
 782         if (hdmi_dev->tmdsclk > 340000000)
 783                 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_TERM_RESIS,
 784                                           v_TX_TERM(R50_OHMS));
 785         else
 786                 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_TERM_RESIS,
 787                                           v_TX_TERM(R100_OHMS));
 788         /* rockchip_hdmiv2_write_phy(hdmi_dev, 0x05, 0x8000); */
 789         if (hdmi_dev->tmdsclk_ratio_change)
 790                 msleep(100);
 791         /* power on PHY */
 792         hdmi_writel(hdmi_dev, PHY_CONF0, 0x2e);
 793
 794         /* check if the PHY PLL is locked */
 795
 796         i = 0;
 797         while (i++ < PHY_TIMEOUT) {
 798                 if ((i % 10) == 0) {
 799                         stat = hdmi_readl(hdmi_dev, PHY_STAT0);
 800                         if (stat & m_PHY_LOCK)
 801                                 break;
 802                         usleep_range(1000, 2000);
 803                 }
 804         }
 805         if ((stat & m_PHY_LOCK) == 0) {
 806                 stat = hdmi_readl(hdmi_dev, MC_LOCKONCLOCK);
 807                 dev_err(hdmi_dev->hdmi->dev,
 808                         "PHY PLL not locked: PCLK_ON=%d,TMDSCLK_ON=%d\n",
 809                         (stat & m_PCLK_ON) >> 6, (stat & m_TMDSCLK_ON) >> 5);
 810                 return -1;
 811         }
 812         hdmi_msk_reg(hdmi_dev, PHY_MASK, m_PHY_LOCK, v_PHY_LOCK(0));
 813         return 0;
 814 }
 815
 816 static int rockchip_hdmiv2_video_framecomposer(struct hdmi *hdmi_drv,
 817                                                struct hdmi_video *vpara)
 818 {
 819         struct hdmi_dev *hdmi_dev = hdmi_drv->property->priv;
 820         int value, vsync_pol, hsync_pol, de_pol;
 821         struct hdmi_video_timing *timing = NULL;
 822         struct fb_videomode *mode = NULL;
 823         u32 sink_version, tmdsclk;
 824
 825         vsync_pol = hdmi_drv->lcdc->cur_screen->pin_vsync;
 826         hsync_pol = hdmi_drv->lcdc->cur_screen->pin_hsync;
 827         de_pol = (hdmi_drv->lcdc->cur_screen->pin_den == 0) ? 1 : 0;
 828
 829         hdmi_msk_reg(hdmi_dev, A_VIDPOLCFG,
 830                      m_DATAEN_POL | m_VSYNC_POL | m_HSYNC_POL,
 831                      v_DATAEN_POL(de_pol) |
 832                      v_VSYNC_POL(vsync_pol) |
 833                      v_HSYNC_POL(hsync_pol));
 834
 835         timing = (struct hdmi_video_timing *)hdmi_vic2timing(vpara->vic);
 836         if (timing == NULL) {
 837                 dev_err(hdmi_drv->dev,
 838                         "[%s] not found vic %d\n", __func__, vpara->vic);
 839                 return -ENOENT;
 840         }
 841         mode = &(timing->mode);
 842         if (vpara->color_input == HDMI_COLOR_YCBCR420)
 843                 tmdsclk = mode->pixclock / 2;
 844         else if (vpara->format_3d == HDMI_3D_FRAME_PACKING)
 845                 tmdsclk = 2 * mode->pixclock;
 846         else
 847                 tmdsclk = mode->pixclock;
 848         if (vpara->color_output != HDMI_COLOR_YCBCR422) {
 849                 switch (vpara->color_output_depth) {
 850                 case 10:
 851                         tmdsclk += tmdsclk / 4;
 852                         break;
 853                 case 12:
 854                         tmdsclk += tmdsclk / 2;
 855                         break;
 856                 case 16:
 857                         tmdsclk += tmdsclk;
 858                         break;
 859                 case 8:
 860                 default:
 861                         break;
 862                 }
 863         } else if (vpara->color_output_depth > 12) {
 864                 /* YCbCr422 mode only support up to 12bit */
 865                 vpara->color_output_depth = 12;
 866         }
 867         if ((tmdsclk > 594000000) ||
 868             (tmdsclk > 340000000 &&
 869              tmdsclk > hdmi_drv->edid.maxtmdsclock)) {
 870                 pr_warn("out of max tmds clock, limit to 8bit\n");
 871                 vpara->color_output_depth = 8;
 872                 if (vpara->color_input == HDMI_COLOR_YCBCR420)
 873                         tmdsclk = mode->pixclock / 2;
 874                 else if (vpara->format_3d != HDMI_3D_FRAME_PACKING)
 875                         tmdsclk = mode->pixclock;
 876                 else
 877                         return -1;
 878         }
 879
 880         if ((tmdsclk > 340000000) ||
 881             (tmdsclk < 340000000 && hdmi_dev->tmdsclk > 340000000))
 882                 hdmi_dev->tmdsclk_ratio_change = true;
 883         else
 884                 hdmi_dev->tmdsclk_ratio_change = false;
 885
 886         hdmi_dev->tmdsclk = tmdsclk;
 887         if (vpara->format_3d == HDMI_3D_FRAME_PACKING)
 888                 hdmi_dev->pixelclk = 2 * mode->pixclock;
 889         else
 890                 hdmi_dev->pixelclk = mode->pixclock;
 891         hdmi_dev->pixelrepeat = timing->pixelrepeat;
 892         /* hdmi_dev->colordepth is used for find pll config.
 893          * For YCbCr422, tmdsclk is same on all color depth.
 894          */
 895         if (vpara->color_output == HDMI_COLOR_YCBCR422)
 896                 hdmi_dev->colordepth = 8;
 897         else
 898                 hdmi_dev->colordepth = vpara->color_output_depth;
 899         pr_info("pixel clk is %lu tmds clk is %u\n",
 900                 hdmi_dev->pixelclk, hdmi_dev->tmdsclk);
 901         /* Start/stop HDCP keepout window generation */
 902         hdmi_msk_reg(hdmi_dev, FC_INVIDCONF,
 903                      m_FC_HDCP_KEEPOUT, v_FC_HDCP_KEEPOUT(1));
 904         if (hdmi_drv->edid.scdc_present == 1 && !hdmi_drv->uboot) {
 905                 if (tmdsclk > 340000000 ||
 906                     hdmi_drv->edid.lte_340mcsc_scramble) {
 907                         /* used for HDMI 2.0 TX */
 908                         mutex_lock(&hdmi_dev->ddc_lock);
 909                         rockchip_hdmiv2_scdc_init(hdmi_dev);
 910                         sink_version =
 911                         rockchip_hdmiv2_scdc_get_sink_version(hdmi_dev);
 912                         pr_info("sink scdc version is %d\n", sink_version);
 913                         sink_version = hdmi_drv->edid.hf_vsdb_version;
 914                         rockchip_hdmiv2_scdc_set_source_version(hdmi_dev,
 915                                                                 sink_version);
 916                         if (hdmi_drv->edid.rr_capable == 1)
 917                                 rockchip_hdmiv2_scdc_read_request(hdmi_dev, 1);
 918                         rockchip_hdmiv2_scrambling_enable(hdmi_dev, 1);
 919                         mutex_unlock(&hdmi_dev->ddc_lock);
 920                 } else {
 921                         mutex_lock(&hdmi_dev->ddc_lock);
 922                         rockchip_hdmiv2_scdc_init(hdmi_dev);
 923                         rockchip_hdmiv2_scrambling_enable(hdmi_dev, 0);
 924                         mutex_unlock(&hdmi_dev->ddc_lock);
 925                 }
 926         } else {
 927                 hdmi_msk_reg(hdmi_dev, FC_SCRAMBLER_CTRL,
 928                              m_FC_SCRAMBLE_EN, v_FC_SCRAMBLE_EN(0));
 929         }
 930
 931         hdmi_msk_reg(hdmi_dev, FC_INVIDCONF,
 932                      m_FC_VSYNC_POL | m_FC_HSYNC_POL | m_FC_DE_POL |
 933                      m_FC_HDMI_DVI | m_FC_INTERLACE_MODE,
 934                      v_FC_VSYNC_POL(vsync_pol) | v_FC_HSYNC_POL(hsync_pol) |
 935                      v_FC_DE_POL(de_pol) | v_FC_HDMI_DVI(vpara->sink_hdmi) |
 936                      v_FC_INTERLACE_MODE(mode->vmode));
 937         if ((mode->vmode & FB_VMODE_INTERLACED) &&
 938             vpara->format_3d != HDMI_3D_FRAME_PACKING)
 939                 hdmi_msk_reg(hdmi_dev, FC_INVIDCONF,
 940                              m_FC_VBLANK, v_FC_VBLANK(1));
 941         else
 942                 hdmi_msk_reg(hdmi_dev, FC_INVIDCONF,
 943                              m_FC_VBLANK, v_FC_VBLANK(0));
 944
 945         value = mode->xres;
 946         if (vpara->color_input == HDMI_COLOR_YCBCR420)
 947                 value = value / 2;
 948         hdmi_writel(hdmi_dev, FC_INHACTIV1, v_FC_HACTIVE1(value >> 8));
 949         hdmi_writel(hdmi_dev, FC_INHACTIV0, (value & 0xff));
 950
 951         if (vpara->format_3d == HDMI_3D_FRAME_PACKING) {
 952                 if (mode->vmode == 0)
 953                         value = 2 * mode->yres +
 954                                 mode->upper_margin +
 955                                 mode->lower_margin +
 956                                 mode->vsync_len;
 957                 else
 958                         value = 2 * mode->yres +
 959                                 3 * (mode->upper_margin +
 960                                      mode->lower_margin +
 961                                      mode->vsync_len) + 2;
 962         } else {
 963                 value = mode->yres;
 964         }
 965         hdmi_writel(hdmi_dev, FC_INVACTIV1, v_FC_VACTIVE1(value >> 8));
 966         hdmi_writel(hdmi_dev, FC_INVACTIV0, (value & 0xff));
 967
 968         value = mode->hsync_len + mode->left_margin + mode->right_margin;
 969         if (vpara->color_input == HDMI_COLOR_YCBCR420)
 970                 value = value / 2;
 971         hdmi_writel(hdmi_dev, FC_INHBLANK1, v_FC_HBLANK1(value >> 8));
 972         hdmi_writel(hdmi_dev, FC_INHBLANK0, (value & 0xff));
 973
 974         value = mode->vsync_len + mode->upper_margin + mode->lower_margin;
 975         hdmi_writel(hdmi_dev, FC_INVBLANK, (value & 0xff));
 976
 977         value = mode->right_margin;
 978         if (vpara->color_input == HDMI_COLOR_YCBCR420)
 979                 value = value / 2;
 980         hdmi_writel(hdmi_dev, FC_HSYNCINDELAY1, v_FC_HSYNCINDEAY1(value >> 8));
 981         hdmi_writel(hdmi_dev, FC_HSYNCINDELAY0, (value & 0xff));
 982
 983         value = mode->lower_margin;
 984         hdmi_writel(hdmi_dev, FC_VSYNCINDELAY, (value & 0xff));
 985
 986         value = mode->hsync_len;
 987         if (vpara->color_input == HDMI_COLOR_YCBCR420)
 988                 value = value / 2;
 989         hdmi_writel(hdmi_dev, FC_HSYNCINWIDTH1, v_FC_HSYNCWIDTH1(value >> 8));
 990         hdmi_writel(hdmi_dev, FC_HSYNCINWIDTH0, (value & 0xff));
 991
 992         value = mode->vsync_len;
 993         hdmi_writel(hdmi_dev, FC_VSYNCINWIDTH, (value & 0xff));
 994
 995         /* Set the control period minimum duration (min. of 12 pixel
 996          * clock cycles, refer to HDMI 1.4b specification)
 997          */
 998         hdmi_writel(hdmi_dev, FC_CTRLDUR, 12);
 999         hdmi_writel(hdmi_dev, FC_EXCTRLDUR, 32);
1000
1001         /* spacing < 256^2 * config / tmdsClock, spacing <= 50ms
1002          * worst case: tmdsClock == 25MHz => config <= 19
1003          */
1004         hdmi_writel(hdmi_dev, FC_EXCTRLSPAC,
1005                     (hdmi_dev->tmdsclk/1000) * 50 / (256 * 512));
1006 #if 0
1007         if (!hdmi_drv->uboot)
1008                 hdmi_msk_reg(hdmi_dev, MC_SWRSTZREQ,
1009                              m_TMDS_SWRST, v_TMDS_SWRST(0));
1010
1011         /*Set PreambleFilter*/
1012         for (i = 0; i < 3; i++) {
1013                 value = (i + 1) * 11;
1014                 if (i == 0)             /*channel 0*/
1015                         hdmi_writel(hdmi_dev, FC_CH0PREAM, value);
1016                 else if (i == 1)        /*channel 1*/
1017                         hdmi_writel(hdmi_dev, FC_CH1PREAM, value & 0x3f);
1018                 else if (i == 2)        /*channel 2*/
1019                         hdmi_writel(hdmi_dev, FC_CH2PREAM, value & 0x3f);
1020         }
1021 #endif
1022
1023         hdmi_writel(hdmi_dev, FC_PRCONF,
1024                     v_FC_PR_FACTOR(timing->pixelrepeat) |
1025                     v_FC_PR_FACTOR_OUT(timing->pixelrepeat - 1));
1026
1027         return 0;
1028 }
1029
1030 static int rockchip_hdmiv2_video_packetizer(struct hdmi_dev *hdmi_dev,
1031                                             struct hdmi_video *vpara)
1032 {
1033         unsigned char color_depth = COLOR_DEPTH_24BIT_DEFAULT;
1034         unsigned char output_select = 0;
1035         unsigned char remap_size = 0;
1036
1037         if (vpara->color_output == HDMI_COLOR_YCBCR422) {
1038                 switch (vpara->color_output_depth) {
1039                 case 8:
1040                         remap_size = YCC422_16BIT;
1041                         break;
1042                 case 10:
1043                         remap_size = YCC422_20BIT;
1044                         break;
1045                 case 12:
1046                         remap_size = YCC422_24BIT;
1047                         break;
1048                 default:
1049                         remap_size = YCC422_16BIT;
1050                         break;
1051                 }
1052
1053                 output_select = OUT_FROM_YCC422_REMAP;
1054                 /*Config remap size for the different color Depth*/
1055                 hdmi_msk_reg(hdmi_dev, VP_REMAP,
1056                              m_YCC422_SIZE, v_YCC422_SIZE(remap_size));
1057         } else {
1058                 switch (vpara->color_output_depth) {
1059                 case 10:
1060                         color_depth = COLOR_DEPTH_30BIT;
1061                         output_select = OUT_FROM_PIXEL_PACKING;
1062                         break;
1063                 case 12:
1064                         color_depth = COLOR_DEPTH_36BIT;
1065                         output_select = OUT_FROM_PIXEL_PACKING;
1066                         break;
1067                 case 16:
1068                         color_depth = COLOR_DEPTH_48BIT;
1069                         output_select = OUT_FROM_PIXEL_PACKING;
1070                         break;
1071                 case 8:
1072                 default:
1073                         color_depth = COLOR_DEPTH_24BIT_DEFAULT;
1074                         output_select = OUT_FROM_8BIT_BYPASS;
1075                         break;
1076                 }
1077         }
1078         /*Config Color Depth*/
1079         hdmi_msk_reg(hdmi_dev, VP_PR_CD,
1080                      m_COLOR_DEPTH, v_COLOR_DEPTH(color_depth));
1081         /*Config pixel repettion*/
1082         hdmi_msk_reg(hdmi_dev, VP_PR_CD, m_DESIRED_PR_FACTOR,
1083                      v_DESIRED_PR_FACTOR(hdmi_dev->pixelrepeat - 1));
1084         if (hdmi_dev->pixelrepeat > 1)
1085                 hdmi_msk_reg(hdmi_dev, VP_CONF,
1086                              m_PIXEL_REPET_EN | m_BYPASS_SEL,
1087                              v_PIXEL_REPET_EN(1) | v_BYPASS_SEL(0));
1088         else
1089                 hdmi_msk_reg(hdmi_dev, VP_CONF,
1090                              m_PIXEL_REPET_EN | m_BYPASS_SEL,
1091                              v_PIXEL_REPET_EN(0) | v_BYPASS_SEL(1));
1092
1093         /*config output select*/
1094         if (output_select == OUT_FROM_PIXEL_PACKING) { /* pixel packing */
1095                 hdmi_msk_reg(hdmi_dev, VP_CONF,
1096                              m_BYPASS_EN | m_PIXEL_PACK_EN |
1097                              m_YCC422_EN | m_OUTPUT_SEL,
1098                              v_BYPASS_EN(0) | v_PIXEL_PACK_EN(1) |
1099                              v_YCC422_EN(0) | v_OUTPUT_SEL(output_select));
1100         } else if (output_select == OUT_FROM_YCC422_REMAP) { /* YCC422 */
1101                 hdmi_msk_reg(hdmi_dev, VP_CONF,
1102                              m_BYPASS_EN | m_PIXEL_PACK_EN |
1103                              m_YCC422_EN | m_OUTPUT_SEL,
1104                              v_BYPASS_EN(0) | v_PIXEL_PACK_EN(0) |
1105                              v_YCC422_EN(1) | v_OUTPUT_SEL(output_select));
1106         } else if (output_select == OUT_FROM_8BIT_BYPASS ||
1107                    output_select == 3) { /* bypass */
1108                 hdmi_msk_reg(hdmi_dev, VP_CONF,
1109                              m_BYPASS_EN | m_PIXEL_PACK_EN |
1110                              m_YCC422_EN | m_OUTPUT_SEL,
1111                              v_BYPASS_EN(1) | v_PIXEL_PACK_EN(0) |
1112                              v_YCC422_EN(0) | v_OUTPUT_SEL(output_select));
1113         }
1114
1115 #if defined(HDMI_VIDEO_STUFFING)
1116         /* YCC422 and pixel packing stuffing*/
1117         hdmi_msk_reg(hdmi_dev, VP_STUFF, m_PR_STUFFING, v_PR_STUFFING(1));
1118         hdmi_msk_reg(hdmi_dev, VP_STUFF,
1119                      m_YCC422_STUFFING | m_PP_STUFFING,
1120                      v_YCC422_STUFFING(1) | v_PP_STUFFING(1));
1121 #endif
1122         return 0;
1123 }
1124
1125 static int rockchip_hdmiv2_video_sampler(struct hdmi_dev *hdmi_dev,
1126                                          struct hdmi_video *vpara)
1127 {
1128         int map_code = 0;
1129
1130         if (vpara->color_input == HDMI_COLOR_YCBCR422) {
1131                 /* YCC422 mapping is discontinued - only map 1 is supported */
1132                 switch (vpara->color_output_depth) {
1133                 case 8:
1134                         map_code = VIDEO_YCBCR422_8BIT;
1135                         break;
1136                 case 10:
1137                         map_code = VIDEO_YCBCR422_10BIT;
1138                         break;
1139                 case 12:
1140                         map_code = VIDEO_YCBCR422_12BIT;
1141                         break;
1142                 default:
1143                         map_code = VIDEO_YCBCR422_8BIT;
1144                         break;
1145                 }
1146         } else if (vpara->color_input == HDMI_COLOR_YCBCR420 ||
1147                    vpara->color_input == HDMI_COLOR_YCBCR444) {
1148                 switch (vpara->color_output_depth) {
1149                 case 10:
1150                         map_code = VIDEO_YCBCR444_10BIT;
1151                         break;
1152                 case 12:
1153                         map_code = VIDEO_YCBCR444_12BIT;
1154                         break;
1155                 case 16:
1156                         map_code = VIDEO_YCBCR444_16BIT;
1157                         break;
1158                 case 8:
1159                 default:
1160                         map_code = VIDEO_YCBCR444_8BIT;
1161                         break;
1162                 }
1163         } else {
1164                 switch (vpara->color_output_depth) {
1165                 case 10:
1166                         map_code = VIDEO_RGB444_10BIT;
1167                         break;
1168                 case 12:
1169                         map_code = VIDEO_RGB444_12BIT;
1170                         break;
1171                 case 16:
1172                         map_code = VIDEO_RGB444_16BIT;
1173                         break;
1174                 case 8:
1175                 default:
1176                         map_code = VIDEO_RGB444_8BIT;
1177                         break;
1178                 }
1179                 map_code += (vpara->color_input == HDMI_COLOR_YCBCR444) ?
1180                             8 : 0;
1181         }
1182
1183         /* Set Data enable signal from external
1184          * and set video sample input mapping
1185          */
1186         hdmi_msk_reg(hdmi_dev, TX_INVID0,
1187                      m_INTERNAL_DE_GEN | m_VIDEO_MAPPING,
1188                      v_INTERNAL_DE_GEN(0) | v_VIDEO_MAPPING(map_code));
1189
1190 #if defined(HDMI_VIDEO_STUFFING)
1191         hdmi_writel(hdmi_dev, TX_GYDATA0, 0x00);
1192         hdmi_writel(hdmi_dev, TX_GYDATA1, 0x00);
1193         hdmi_msk_reg(hdmi_dev, TX_INSTUFFING,
1194                      m_GYDATA_STUFF, v_GYDATA_STUFF(1));
1195         hdmi_writel(hdmi_dev, TX_RCRDATA0, 0x00);
1196         hdmi_writel(hdmi_dev, TX_RCRDATA1, 0x00);
1197         hdmi_msk_reg(hdmi_dev, TX_INSTUFFING,
1198                      m_RCRDATA_STUFF, v_RCRDATA_STUFF(1));
1199         hdmi_writel(hdmi_dev, TX_BCBDATA0, 0x00);
1200         hdmi_writel(hdmi_dev, TX_BCBDATA1, 0x00);
1201         hdmi_msk_reg(hdmi_dev, TX_INSTUFFING,
1202                      m_BCBDATA_STUFF, v_BCBDATA_STUFF(1));
1203 #endif
1204         return 0;
1205 }
1206
1207 static const char coeff_csc[][24] = {
1208                 /*   G          R           B           Bias
1209                  *   A1    |    A2     |    A3     |    A4    |
1210                  *   B1    |    B2     |    B3     |    B4    |
1211                  *   C1    |    C2     |    C3     |    C4    |
1212                  */
1213         {       /* CSC_RGB_0_255_TO_RGB_16_235_8BIT */
1214                 0x36, 0xf7, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,         /*G*/
1215                 0x00, 0x00, 0x36, 0xf7, 0x00, 0x00, 0x00, 0x40,         /*R*/
1216                 0x00, 0x00, 0x00, 0x00, 0x36, 0xf7, 0x00, 0x40,         /*B*/
1217         },
1218         {       /* CSC_RGB_0_255_TO_RGB_16_235_10BIT */
1219                 0x36, 0xf7, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,         /*G*/
1220                 0x00, 0x00, 0x36, 0xf7, 0x00, 0x00, 0x01, 0x00,         /*R*/
1221                 0x00, 0x00, 0x00, 0x00, 0x36, 0xf7, 0x01, 0x00,         /*B*/
1222         },
1223         {       /* CSC_RGB_0_255_TO_ITU601_16_235_8BIT */
1224                 0x20, 0x40, 0x10, 0x80, 0x06, 0x40, 0x00, 0x40,         /*Y*/
1225                 0xe8, 0x80, 0x1c, 0x00, 0xfb, 0x80, 0x02, 0x00,         /*Cr*/
1226                 0xed, 0x80, 0xf6, 0x80, 0x1c, 0x00, 0x02, 0x00,         /*Cb*/
1227         },
1228         {       /* CSC_RGB_0_255_TO_ITU601_16_235_10BIT */
1229                 0x20, 0x40, 0x10, 0x80, 0x06, 0x40, 0x01, 0x00,         /*Y*/
1230                 0xe8, 0x80, 0x1c, 0x00, 0xfb, 0x80, 0x08, 0x00,         /*Cr*/
1231                 0xed, 0x80, 0xf6, 0x80, 0x1c, 0x00, 0x08, 0x00,         /*Cb*/
1232         },
1233         {       /* CSC_RGB_0_255_TO_ITU709_16_235_8BIT */
1234                 0x27, 0x40, 0x0b, 0xc0, 0x04, 0x00, 0x00, 0x40,         /*Y*/
1235                 0xe6, 0x80, 0x1c, 0x00, 0xfd, 0x80, 0x02, 0x00,         /*Cr*/
1236                 0xea, 0x40, 0xf9, 0x80, 0x1c, 0x00, 0x02, 0x00,         /*Cb*/
1237         },
1238         {       /* CSC_RGB_0_255_TO_ITU709_16_235_10BIT */
1239                 0x27, 0x40, 0x0b, 0xc0, 0x04, 0x00, 0x01, 0x00,         /*Y*/
1240                 0xe6, 0x80, 0x1c, 0x00, 0xfd, 0x80, 0x08, 0x00,         /*Cr*/
1241                 0xea, 0x40, 0xf9, 0x80, 0x1c, 0x00, 0x08, 0x00,         /*Cb*/
1242         },
1243                 /* Y            Cr          Cb          Bias */
1244         {       /* CSC_ITU601_16_235_TO_RGB_0_255_8BIT */
1245                 0x20, 0x00, 0x69, 0x26, 0x74, 0xfd, 0x01, 0x0e,         /*G*/
1246                 0x20, 0x00, 0x2c, 0xdd, 0x00, 0x00, 0x7e, 0x9a,         /*R*/
1247                 0x20, 0x00, 0x00, 0x00, 0x38, 0xb4, 0x7e, 0x3b,         /*B*/
1248         },
1249         {       /* CSC_ITU709_16_235_TO_RGB_0_255_8BIT */
1250                 0x20, 0x00, 0x71, 0x06, 0x7a, 0x02, 0x00, 0xa7,         /*G*/
1251                 0x20, 0x00, 0x32, 0x64, 0x00, 0x00, 0x7e, 0x6d,         /*R*/
1252                 0x20, 0x00, 0x00, 0x00, 0x3b, 0x61, 0x7e, 0x25,         /*B*/
1253         },
1254 };
1255
1256 static int rockchip_hdmiv2_video_csc(struct hdmi_dev *hdmi_dev,
1257                                      struct hdmi_video *vpara)
1258 {
1259         int i, mode, interpolation, decimation, csc_scale;
1260         const char *coeff = NULL;
1261         unsigned char color_depth = 0;
1262
1263         if (vpara->color_input == vpara->color_output) {
1264                 hdmi_msk_reg(hdmi_dev, MC_FLOWCTRL,
1265                              m_FEED_THROUGH_OFF, v_FEED_THROUGH_OFF(0));
1266                 return 0;
1267         }
1268
1269         if (vpara->color_input == HDMI_COLOR_YCBCR422 &&
1270             vpara->color_output != HDMI_COLOR_YCBCR422 &&
1271             vpara->color_output != HDMI_COLOR_YCBCR420) {
1272                 interpolation = 1;
1273                 hdmi_msk_reg(hdmi_dev, CSC_CFG,
1274                              m_CSC_INTPMODE, v_CSC_INTPMODE(interpolation));
1275         }
1276
1277         if ((vpara->color_input == HDMI_COLOR_RGB_0_255 ||
1278              vpara->color_input == HDMI_COLOR_YCBCR444) &&
1279              vpara->color_output == HDMI_COLOR_YCBCR422) {
1280                 decimation = 1;
1281                 hdmi_msk_reg(hdmi_dev, CSC_CFG,
1282                              m_CSC_DECIMODE, v_CSC_DECIMODE(decimation));
1283         }
1284
1285         switch (vpara->vic) {
1286         case HDMI_720X480I_60HZ_4_3:
1287         case HDMI_720X576I_50HZ_4_3:
1288         case HDMI_720X480P_60HZ_4_3:
1289         case HDMI_720X576P_50HZ_4_3:
1290         case HDMI_720X480I_60HZ_16_9:
1291         case HDMI_720X576I_50HZ_16_9:
1292         case HDMI_720X480P_60HZ_16_9:
1293         case HDMI_720X576P_50HZ_16_9:
1294                 if (vpara->color_input == HDMI_COLOR_RGB_0_255 &&
1295                     vpara->color_output >= HDMI_COLOR_YCBCR444) {
1296                         mode = CSC_RGB_0_255_TO_ITU601_16_235_8BIT;
1297                         csc_scale = 0;
1298                 } else if (vpara->color_input >= HDMI_COLOR_YCBCR444 &&
1299                            vpara->color_output == HDMI_COLOR_RGB_0_255) {
1300                         mode = CSC_ITU601_16_235_TO_RGB_0_255_8BIT;
1301                         csc_scale = 1;
1302                 }
1303                 break;
1304         default:
1305                 if (vpara->color_input == HDMI_COLOR_RGB_0_255 &&
1306                     vpara->color_output >= HDMI_COLOR_YCBCR444) {
1307                         mode = CSC_RGB_0_255_TO_ITU709_16_235_8BIT;
1308                         csc_scale = 0;
1309                 } else if (vpara->color_input >= HDMI_COLOR_YCBCR444 &&
1310                            vpara->color_output == HDMI_COLOR_RGB_0_255) {
1311                         mode = CSC_ITU709_16_235_TO_RGB_0_255_8BIT;
1312                         csc_scale = 1;
1313                 }
1314                 break;
1315         }
1316
1317         if ((vpara->color_input == HDMI_COLOR_RGB_0_255) &&
1318             (vpara->color_output == HDMI_COLOR_RGB_16_235)) {
1319                 mode = CSC_RGB_0_255_TO_RGB_16_235_8BIT;
1320                 csc_scale = 0;
1321         }
1322
1323         switch (vpara->color_output_depth) {
1324         case 10:
1325                 color_depth = COLOR_DEPTH_30BIT;
1326                 mode += 1;
1327                 break;
1328         case 12:
1329                 color_depth = COLOR_DEPTH_36BIT;
1330                 mode += 2;
1331                 break;
1332         case 16:
1333                 color_depth = COLOR_DEPTH_48BIT;
1334                 mode += 3;
1335                 break;
1336         case 8:
1337         default:
1338                 color_depth = COLOR_DEPTH_24BIT;
1339                 break;
1340         }
1341
1342         coeff = coeff_csc[mode];
1343         for (i = 0; i < 24; i++)
1344                 hdmi_writel(hdmi_dev, CSC_COEF_A1_MSB + i, coeff[i]);
1345
1346         hdmi_msk_reg(hdmi_dev, CSC_SCALE,
1347                      m_CSC_SCALE, v_CSC_SCALE(csc_scale));
1348         /*config CSC_COLOR_DEPTH*/
1349         hdmi_msk_reg(hdmi_dev, CSC_SCALE,
1350                      m_CSC_COLOR_DEPTH, v_CSC_COLOR_DEPTH(color_depth));
1351
1352         /* enable CSC */
1353         hdmi_msk_reg(hdmi_dev, MC_FLOWCTRL,
1354                      m_FEED_THROUGH_OFF, v_FEED_THROUGH_OFF(1));
1355
1356         return 0;
1357 }
1358
1359
1360 static int hdmi_dev_detect_hotplug(struct hdmi *hdmi)
1361 {
1362         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1363         u32 value;
1364
1365         value = hdmi_readl(hdmi_dev, PHY_STAT0);
1366         HDMIDBG("[%s] reg%x value %02x\n", __func__, PHY_STAT0, value);
1367         if (value & m_PHY_HPD)
1368                 return HDMI_HPD_ACTIVED;
1369
1370         return HDMI_HPD_REMOVED;
1371 }
1372
1373 static int hdmi_dev_read_edid(struct hdmi *hdmi, int block, unsigned char *buff)
1374 {
1375         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1376         int i = 0, n = 0, index = 0, ret = -1, trytime = 5;
1377         int offset = (block % 2) * 0x80;
1378         int interrupt = 0;
1379
1380         HDMIDBG("[%s] block %d\n", __func__, block);
1381
1382         rockchip_hdmiv2_i2cm_reset(hdmi_dev);
1383
1384         /* Set DDC I2C CLK which devided from DDC_CLK to 100KHz. */
1385         rockchip_hdmiv2_i2cm_clk_init(hdmi_dev);
1386
1387         /* Enable I2C interrupt for reading edid */
1388         rockchip_hdmiv2_i2cm_mask_int(hdmi_dev, 0);
1389
1390         hdmi_writel(hdmi_dev, I2CM_SLAVE, DDC_I2C_EDID_ADDR);
1391         hdmi_writel(hdmi_dev, I2CM_SEGADDR, DDC_I2C_SEG_ADDR);
1392         hdmi_writel(hdmi_dev, I2CM_SEGPTR, block / 2);
1393         for (n = 0; n < HDMI_EDID_BLOCK_SIZE / 8; n++) {
1394                 for (trytime = 0; trytime < 5; trytime++) {
1395                         hdmi_writel(hdmi_dev, I2CM_ADDRESS, offset + 8 * n);
1396                         /* enable extend sequential read operation */
1397                         if (block == 0)
1398                                 hdmi_msk_reg(hdmi_dev, I2CM_OPERATION,
1399                                              m_I2CM_RD8, v_I2CM_RD8(1));
1400                         else
1401                                 hdmi_msk_reg(hdmi_dev, I2CM_OPERATION,
1402                                              m_I2CM_RD8_EXT,
1403                                              v_I2CM_RD8_EXT(1));
1404
1405                         i = 20;
1406                         while (i--) {
1407                                 usleep_range(900, 1000);
1408                                 interrupt = hdmi_readl(hdmi_dev,
1409                                                        IH_I2CM_STAT0);
1410                                 if (interrupt)
1411                                         hdmi_writel(hdmi_dev,
1412                                                     IH_I2CM_STAT0, interrupt);
1413
1414                                 if (interrupt &
1415                                     (m_SCDC_READREQ | m_I2CM_DONE |
1416                                      m_I2CM_ERROR))
1417                                         break;
1418                         }
1419
1420                         if (interrupt & m_I2CM_DONE) {
1421                                 for (index = 0; index < 8; index++)
1422                                         buff[8 * n + index] =
1423                                                 hdmi_readl(hdmi_dev,
1424                                                            I2CM_READ_BUFF0 +
1425                                                            index);
1426
1427                                 if (n == HDMI_EDID_BLOCK_SIZE / 8 - 1) {
1428                                         ret = 0;
1429                                         goto exit;
1430                                 }
1431                                 break;
1432                         } else if ((interrupt & m_I2CM_ERROR) || (i == -1)) {
1433                                 dev_err(hdmi->dev,
1434                                         "[%s] edid read %d error\n",
1435                                         __func__, offset + 8 * n);
1436                         }
1437                 }
1438                 if (trytime == 5) {
1439                         dev_err(hdmi->dev,
1440                                 "[%s] edid read error\n", __func__);
1441                         break;
1442                 }
1443         }
1444
1445 exit:
1446         /* Disable I2C interrupt */
1447         rockchip_hdmiv2_i2cm_mask_int(hdmi_dev, 1);
1448         return ret;
1449 }
1450
1451 static void hdmi_dev_config_avi(struct hdmi_dev *hdmi_dev,
1452                                 struct hdmi_video *vpara)
1453 {
1454         unsigned char colorimetry, ext_colorimetry, aspect_ratio, y1y0;
1455         unsigned char rgb_quan_range = AVI_QUANTIZATION_RANGE_DEFAULT;
1456
1457         hdmi_msk_reg(hdmi_dev, FC_DATAUTO3, m_AVI_AUTO, v_AVI_AUTO(0));
1458         hdmi_msk_reg(hdmi_dev, IH_FC_STAT1,
1459                      m_AVI_INFOFRAME, v_AVI_INFOFRAME(1));
1460         /* Set AVI infoFrame Data byte1 */
1461         if (vpara->color_output == HDMI_COLOR_YCBCR444)
1462                 y1y0 = AVI_COLOR_MODE_YCBCR444;
1463         else if (vpara->color_output == HDMI_COLOR_YCBCR422)
1464                 y1y0 = AVI_COLOR_MODE_YCBCR422;
1465         else if (vpara->color_output == HDMI_COLOR_YCBCR420)
1466                 y1y0 = AVI_COLOR_MODE_YCBCR420;
1467         else
1468                 y1y0 = AVI_COLOR_MODE_RGB;
1469
1470         hdmi_msk_reg(hdmi_dev, FC_AVICONF0,
1471                      m_FC_ACTIV_FORMAT | m_FC_RGC_YCC,
1472                      v_FC_RGC_YCC(y1y0) | v_FC_ACTIV_FORMAT(1));
1473
1474         /* Set AVI infoFrame Data byte2 */
1475         switch (vpara->vic) {
1476         case HDMI_720X480I_60HZ_4_3:
1477         case HDMI_720X576I_50HZ_4_3:
1478         case HDMI_720X480P_60HZ_4_3:
1479         case HDMI_720X576P_50HZ_4_3:
1480                 aspect_ratio = AVI_CODED_FRAME_ASPECT_4_3;
1481                 if (vpara->colorimetry == HDMI_COLORIMETRY_NO_DATA)
1482                         colorimetry = AVI_COLORIMETRY_SMPTE_170M;
1483                 break;
1484         case HDMI_720X480I_60HZ_16_9:
1485         case HDMI_720X576I_50HZ_16_9:
1486         case HDMI_720X480P_60HZ_16_9:
1487         case HDMI_720X576P_50HZ_16_9:
1488                 aspect_ratio = AVI_CODED_FRAME_ASPECT_16_9;
1489                 if (vpara->colorimetry == HDMI_COLORIMETRY_NO_DATA)
1490                         colorimetry = AVI_COLORIMETRY_SMPTE_170M;
1491                 break;
1492         default:
1493                 aspect_ratio = AVI_CODED_FRAME_ASPECT_16_9;
1494                 if (vpara->colorimetry == HDMI_COLORIMETRY_NO_DATA)
1495                         colorimetry = AVI_COLORIMETRY_ITU709;
1496         }
1497
1498         if (vpara->colorimetry > HDMI_COLORIMETRY_ITU709) {
1499                 colorimetry = AVI_COLORIMETRY_EXTENDED;
1500                 ext_colorimetry = vpara->colorimetry;
1501         } else if (vpara->color_output == HDMI_COLOR_RGB_16_235 ||
1502                  vpara->color_output == HDMI_COLOR_RGB_0_255) {
1503                 colorimetry = AVI_COLORIMETRY_NO_DATA;
1504                 ext_colorimetry = 0;
1505         } else if (vpara->colorimetry != HDMI_COLORIMETRY_NO_DATA) {
1506                 colorimetry = vpara->colorimetry;
1507         }
1508
1509         hdmi_writel(hdmi_dev, FC_AVICONF1,
1510                     v_FC_COLORIMETRY(colorimetry) |
1511                     v_FC_PIC_ASPEC_RATIO(aspect_ratio) |
1512                     v_FC_ACT_ASPEC_RATIO(ACTIVE_ASPECT_RATE_DEFAULT));
1513
1514         /* Set AVI infoFrame Data byte3 */
1515         hdmi_msk_reg(hdmi_dev, FC_AVICONF2,
1516                      m_FC_EXT_COLORIMETRY | m_FC_QUAN_RANGE,
1517                      v_FC_EXT_COLORIMETRY(ext_colorimetry) |
1518                      v_FC_QUAN_RANGE(rgb_quan_range));
1519
1520         /* Set AVI infoFrame Data byte4 */
1521         if ((vpara->vic > 92 && vpara->vic < 96) ||
1522             (vpara->vic == 98) ||
1523             (vpara->vic & HDMI_VIDEO_DMT))
1524                 hdmi_writel(hdmi_dev, FC_AVIVID, 0);
1525         else
1526                 hdmi_writel(hdmi_dev, FC_AVIVID, vpara->vic & 0xff);
1527         /* Set AVI infoFrame Data byte5 */
1528         hdmi_msk_reg(hdmi_dev, FC_AVICONF3, m_FC_YQ | m_FC_CN,
1529                      v_FC_YQ(YQ_LIMITED_RANGE) | v_FC_CN(CN_GRAPHICS));
1530         hdmi_msk_reg(hdmi_dev, FC_DATAUTO3, m_AVI_AUTO, v_AVI_AUTO(1));
1531 }
1532
1533 static int hdmi_dev_config_vsi(struct hdmi *hdmi,
1534                                unsigned char vic_3d, unsigned char format)
1535 {
1536         int i = 0, id = 0x000c03;
1537         unsigned char data[3] = {0};
1538
1539         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1540
1541         HDMIDBG("[%s] vic %d format %d.\n", __func__, vic_3d, format);
1542
1543         hdmi_msk_reg(hdmi_dev, FC_DATAUTO0, m_VSD_AUTO, v_VSD_AUTO(0));
1544         hdmi_writel(hdmi_dev, FC_VSDIEEEID2, id & 0xff);
1545         hdmi_writel(hdmi_dev, FC_VSDIEEEID1, (id >> 8) & 0xff);
1546         hdmi_writel(hdmi_dev, FC_VSDIEEEID0, (id >> 16) & 0xff);
1547
1548         data[0] = format << 5;  /* PB4 --HDMI_Video_Format */
1549         switch (format) {
1550         case HDMI_VIDEO_FORMAT_4KX2K:
1551                 data[1] = vic_3d;       /* PB5--HDMI_VIC */
1552                 data[2] = 0;
1553                 break;
1554         case HDMI_VIDEO_FORMAT_3D:
1555                 data[1] = vic_3d << 4;  /* PB5--3D_Structure field */
1556                 data[2] = 0;            /* PB6--3D_Ext_Data field */
1557                 break;
1558         default:
1559                 data[1] = 0;
1560                 data[2] = 0;
1561                 break;
1562         }
1563
1564         for (i = 0; i < 3; i++)
1565                 hdmi_writel(hdmi_dev, FC_VSDPAYLOAD0 + i, data[i]);
1566         hdmi_writel(hdmi_dev, FC_VSDSIZE, 0x6);
1567
1568         hdmi_writel(hdmi_dev, FC_DATAUTO1, 0);
1569         hdmi_writel(hdmi_dev, FC_DATAUTO2, 0x11);
1570         hdmi_msk_reg(hdmi_dev, FC_DATAUTO0, m_VSD_AUTO, v_VSD_AUTO(1));
1571         return 0;
1572 }
1573
1574 static int hdmi_dev_config_spd(struct hdmi *hdmi, const char *vendor,
1575                                const char *product, char deviceinfo)
1576 {
1577         struct hdmi_dev *hdmi_dev;
1578         int i, len;
1579
1580         if (!hdmi || !vendor || !product)
1581                 return -1;
1582         hdmi_dev = hdmi->property->priv;
1583
1584         hdmi_msk_reg(hdmi_dev, FC_DATAUTO0, m_SPD_AUTO, v_SPD_AUTO(0));
1585         len = strlen(vendor);
1586         for (i = 0; i < 8; i++) {
1587                 if (i < len)
1588                         hdmi_writel(hdmi_dev, FC_SPDVENDORNAME0 + i,
1589                                     vendor[i]);
1590                 else
1591                         hdmi_writel(hdmi_dev, FC_SPDVENDORNAME0 + i,
1592                                     0);
1593         }
1594         len = strlen(product);
1595         for (i = 0; i < 16; i++) {
1596                 if (i < len)
1597                         hdmi_writel(hdmi_dev, FC_SPDPRODUCTNAME0 + i,
1598                                     product[i]);
1599                 else
1600                         hdmi_writel(hdmi_dev, FC_SPDPRODUCTNAME0 + i,
1601                                     0);
1602         }
1603         hdmi_writel(hdmi_dev, FC_SPDDEVICEINF, deviceinfo);
1604         hdmi_msk_reg(hdmi_dev, FC_DATAUTO0, m_SPD_AUTO, v_SPD_AUTO(1));
1605         return 0;
1606 }
1607
1608 static int hdmi_dev_config_video(struct hdmi *hdmi, struct hdmi_video *vpara)
1609 {
1610         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1611
1612         HDMIDBG("%s vic %d 3dformat %d color mode %d color depth %d\n",
1613                 __func__, vpara->vic, vpara->format_3d,
1614                 vpara->color_output, vpara->color_output_depth);
1615
1616         if (hdmi_dev->soctype == HDMI_SOC_RK3288)
1617                 vpara->color_input = HDMI_COLOR_RGB_0_255;
1618
1619         if (!hdmi->uboot) {
1620                 /* befor configure video, we power off phy */
1621                 if (hdmi_dev->soctype != HDMI_SOC_RK322X) {
1622                         hdmi_msk_reg(hdmi_dev, PHY_CONF0,
1623                                      m_PDDQ_SIG | m_TXPWRON_SIG,
1624                                      v_PDDQ_SIG(1) | v_TXPWRON_SIG(0));
1625                 } else {
1626                         hdmi_msk_reg(hdmi_dev, PHY_CONF0,
1627                                      m_ENHPD_RXSENSE_SIG,
1628                                      v_ENHPD_RXSENSE_SIG(1));
1629                         regmap_write(hdmi_dev->grf_base,
1630                                      RK322X_GRF_SOC_CON2,
1631                                      RK322X_PLL_POWER_DOWN);
1632                 }
1633                 /* force output blue */
1634                 if (vpara->color_output == HDMI_COLOR_RGB_0_255) {
1635                         hdmi_writel(hdmi_dev, FC_DBGTMDS2, 0x00);       /*R*/
1636                         hdmi_writel(hdmi_dev, FC_DBGTMDS1, 0x00);       /*G*/
1637                         hdmi_writel(hdmi_dev, FC_DBGTMDS0, 0x00);       /*B*/
1638                 } else if (vpara->color_output == HDMI_COLOR_RGB_16_235) {
1639                         hdmi_writel(hdmi_dev, FC_DBGTMDS2, 0x10);       /*R*/
1640                         hdmi_writel(hdmi_dev, FC_DBGTMDS1, 0x10);       /*G*/
1641                         hdmi_writel(hdmi_dev, FC_DBGTMDS0, 0x10);       /*B*/
1642                 } else {
1643                         hdmi_writel(hdmi_dev, FC_DBGTMDS2, 0x80);       /*Cr*/
1644                         hdmi_writel(hdmi_dev, FC_DBGTMDS1, 0x10);       /*Y*/
1645                         hdmi_writel(hdmi_dev, FC_DBGTMDS0, 0x80);       /*Cb*/
1646                 }
1647                 hdmi_msk_reg(hdmi_dev, FC_DBGFORCE,
1648                              m_FC_FORCEVIDEO, v_FC_FORCEVIDEO(1));
1649                 hdmi_writel(hdmi_dev, MC_CLKDIS, m_HDCPCLK_DISABLE);
1650         }
1651
1652         if (rockchip_hdmiv2_video_framecomposer(hdmi, vpara) < 0)
1653                 return -1;
1654
1655         if (rockchip_hdmiv2_video_packetizer(hdmi_dev, vpara) < 0)
1656                 return -1;
1657         /* Color space convert */
1658         if (rockchip_hdmiv2_video_csc(hdmi_dev, vpara) < 0)
1659                 return -1;
1660         if (rockchip_hdmiv2_video_sampler(hdmi_dev, vpara) < 0)
1661                 return -1;
1662
1663         if (vpara->sink_hdmi == OUTPUT_HDMI) {
1664                 hdmi_dev_config_avi(hdmi_dev, vpara);
1665                 hdmi_dev_config_spd(hdmi, hdmi_dev->vendor_name,
1666                                     hdmi_dev->product_name,
1667                                     hdmi_dev->deviceinfo);
1668                 if (vpara->format_3d != HDMI_3D_NONE) {
1669                         hdmi_dev_config_vsi(hdmi,
1670                                             vpara->format_3d,
1671                                             HDMI_VIDEO_FORMAT_3D);
1672                 } else if ((vpara->vic > 92 && vpara->vic < 96) ||
1673                          (vpara->vic == 98)) {
1674                         vpara->vic = (vpara->vic == 98) ?
1675                                      4 : (96 - vpara->vic);
1676                         hdmi_dev_config_vsi(hdmi,
1677                                             vpara->vic,
1678                                             HDMI_VIDEO_FORMAT_4KX2K);
1679                 } else {
1680                         hdmi_dev_config_vsi(hdmi,
1681                                             vpara->vic,
1682                                             HDMI_VIDEO_FORMAT_NORMAL);
1683                 }
1684                 dev_info(hdmi->dev, "[%s] sucess output HDMI.\n", __func__);
1685         } else {
1686                 dev_info(hdmi->dev, "[%s] sucess output DVI.\n", __func__);
1687         }
1688
1689         if (!hdmi->uboot)
1690                 rockchip_hdmiv2_config_phy(hdmi_dev);
1691         else
1692                 hdmi_msk_reg(hdmi_dev, PHY_MASK, m_PHY_LOCK, v_PHY_LOCK(0));
1693         return 0;
1694 }
1695
1696 static void hdmi_dev_config_aai(struct hdmi_dev *hdmi_dev,
1697                                 struct hdmi_audio *audio)
1698 {
1699         /* Refer to CEA861-E Audio infoFrame
1700          * Set both Audio Channel Count and Audio Coding
1701          * Type Refer to Stream Head for HDMI
1702          */
1703         hdmi_msk_reg(hdmi_dev, FC_AUDICONF0,
1704                      m_FC_CHN_CNT | m_FC_CODING_TYEP,
1705                      v_FC_CHN_CNT(audio->channel-1) | v_FC_CODING_TYEP(0));
1706
1707         /* Set both Audio Sample Size and Sample Frequency
1708          * Refer to Stream Head for HDMI
1709          */
1710         hdmi_msk_reg(hdmi_dev, FC_AUDICONF1,
1711                      m_FC_SAMPLE_SIZE | m_FC_SAMPLE_FREQ,
1712                      v_FC_SAMPLE_SIZE(0) | v_FC_SAMPLE_FREQ(0));
1713
1714         /* Set Channel Allocation */
1715         hdmi_writel(hdmi_dev, FC_AUDICONF2, 0x00);
1716
1717         /* Set LFEPBLDOWN-MIX INH and LSV */
1718         hdmi_writel(hdmi_dev, FC_AUDICONF3, 0x00);
1719 }
1720
1721 static int hdmi_dev_config_audio(struct hdmi *hdmi, struct hdmi_audio *audio)
1722 {
1723         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1724         int word_length = 0, channel = 0, mclk_fs;
1725         unsigned int N = 0, CTS = 0;
1726         int rate = 0;
1727
1728         HDMIDBG("%s\n", __func__);
1729
1730         if (audio->channel < 3)
1731                 channel = I2S_CHANNEL_1_2;
1732         else if (audio->channel < 5)
1733                 channel = I2S_CHANNEL_3_4;
1734         else if (audio->channel < 7)
1735                 channel = I2S_CHANNEL_5_6;
1736         else
1737                 channel = I2S_CHANNEL_7_8;
1738
1739         switch (audio->rate) {
1740         case HDMI_AUDIO_FS_32000:
1741                 mclk_fs = FS_128;
1742                 rate = AUDIO_32K;
1743                 if (hdmi_dev->tmdsclk >= 594000000)
1744                         N = N_32K_HIGHCLK;
1745                 else if (hdmi_dev->tmdsclk >= 297000000)
1746                         N = N_32K_MIDCLK;
1747                 else
1748                         N = N_32K_LOWCLK;
1749                 /*div a num to avoid the value is exceed 2^32(int)*/
1750                 CTS = CALC_CTS(N, hdmi_dev->tmdsclk/1000, 32);
1751                 break;
1752         case HDMI_AUDIO_FS_44100:
1753                 mclk_fs = FS_128;
1754                 rate = AUDIO_441K;
1755                 if (hdmi_dev->tmdsclk >= 594000000)
1756                         N = N_441K_HIGHCLK;
1757                 else if (hdmi_dev->tmdsclk >= 297000000)
1758                         N = N_441K_MIDCLK;
1759                 else
1760                         N = N_441K_LOWCLK;
1761
1762                 CTS = CALC_CTS(N, hdmi_dev->tmdsclk/100, 441);
1763                 break;
1764         case HDMI_AUDIO_FS_48000:
1765                 mclk_fs = FS_128;
1766                 rate = AUDIO_48K;
1767                 if (hdmi_dev->tmdsclk >= 594000000)     /*FS_153.6*/
1768                         N = N_48K_HIGHCLK;
1769                 else if (hdmi_dev->tmdsclk >= 297000000)
1770                         N = N_48K_MIDCLK;
1771                 else
1772                         N = N_48K_LOWCLK;
1773
1774                 CTS = CALC_CTS(N, hdmi_dev->tmdsclk/1000, 48);
1775                 break;
1776         case HDMI_AUDIO_FS_88200:
1777                 mclk_fs = FS_128;
1778                 rate = AUDIO_882K;
1779                 if (hdmi_dev->tmdsclk >= 594000000)
1780                         N = N_882K_HIGHCLK;
1781                 else if (hdmi_dev->tmdsclk >= 297000000)
1782                         N = N_882K_MIDCLK;
1783                 else
1784                         N = N_882K_LOWCLK;
1785
1786                 CTS = CALC_CTS(N, hdmi_dev->tmdsclk/100, 882);
1787                 break;
1788         case HDMI_AUDIO_FS_96000:
1789                 mclk_fs = FS_128;
1790                 rate = AUDIO_96K;
1791                 if (hdmi_dev->tmdsclk >= 594000000)     /*FS_153.6*/
1792                         N = N_96K_HIGHCLK;
1793                 else if (hdmi_dev->tmdsclk >= 297000000)
1794                         N = N_96K_MIDCLK;
1795                 else
1796                         N = N_96K_LOWCLK;
1797
1798                 CTS = CALC_CTS(N, hdmi_dev->tmdsclk/1000, 96);
1799                 break;
1800         case HDMI_AUDIO_FS_176400:
1801                 mclk_fs = FS_128;
1802                 rate = AUDIO_1764K;
1803                 if (hdmi_dev->tmdsclk >= 594000000)
1804                         N = N_1764K_HIGHCLK;
1805                 else if (hdmi_dev->tmdsclk >= 297000000)
1806                         N = N_1764K_MIDCLK;
1807                 else
1808                         N = N_1764K_LOWCLK;
1809
1810                 CTS = CALC_CTS(N, hdmi_dev->tmdsclk/100, 1764);
1811                 break;
1812         case HDMI_AUDIO_FS_192000:
1813                 mclk_fs = FS_128;
1814                 rate = AUDIO_192K;
1815                 if (hdmi_dev->tmdsclk >= 594000000)     /*FS_153.6*/
1816                         N = N_192K_HIGHCLK;
1817                 else if (hdmi_dev->tmdsclk >= 297000000)
1818                         N = N_192K_MIDCLK;
1819                 else
1820                         N = N_192K_LOWCLK;
1821
1822                 CTS = CALC_CTS(N, hdmi_dev->tmdsclk/1000, 192);
1823                 break;
1824         default:
1825                 dev_err(hdmi_dev->hdmi->dev,
1826                         "[%s] not support such sample rate %d\n",
1827                         __func__, audio->rate);
1828                 return -ENOENT;
1829         }
1830
1831         switch (audio->word_length) {
1832         case HDMI_AUDIO_WORD_LENGTH_16bit:
1833                 word_length = I2S_16BIT_SAMPLE;
1834                 break;
1835         case HDMI_AUDIO_WORD_LENGTH_20bit:
1836                 word_length = I2S_20BIT_SAMPLE;
1837                 break;
1838         case HDMI_AUDIO_WORD_LENGTH_24bit:
1839                 word_length = I2S_24BIT_SAMPLE;
1840                 break;
1841         default:
1842                 word_length = I2S_16BIT_SAMPLE;
1843         }
1844
1845         HDMIDBG("rate = %d, tmdsclk = %u, N = %d, CTS = %d\n",
1846                 audio->rate, hdmi_dev->tmdsclk, N, CTS);
1847         /* more than 2 channels => layout 1 else layout 0 */
1848         hdmi_msk_reg(hdmi_dev, FC_AUDSCONF,
1849                      m_AUD_PACK_LAYOUT,
1850                      v_AUD_PACK_LAYOUT((audio->channel > 2) ? 1 : 0));
1851
1852         if (hdmi_dev->audiosrc == HDMI_AUDIO_SRC_SPDIF) {
1853                 mclk_fs = FS_128;
1854                 hdmi_msk_reg(hdmi_dev, AUD_CONF0,
1855                              m_I2S_SEL, v_I2S_SEL(AUDIO_SPDIF_GPA));
1856                 hdmi_msk_reg(hdmi_dev, AUD_SPDIF1,
1857                              m_SET_NLPCM | m_SPDIF_WIDTH,
1858                              v_SET_NLPCM(PCM_LINEAR) |
1859                              v_SPDIF_WIDTH(word_length));
1860                 /*Mask fifo empty and full int and reset fifo*/
1861                 hdmi_msk_reg(hdmi_dev, AUD_SPDIFINT,
1862                              m_FIFO_EMPTY_MASK | m_FIFO_FULL_MASK,
1863                              v_FIFO_EMPTY_MASK(1) | v_FIFO_FULL_MASK(1));
1864                 hdmi_msk_reg(hdmi_dev, AUD_SPDIF0,
1865                              m_SW_SAUD_FIFO_RST, v_SW_SAUD_FIFO_RST(1));
1866         } else {
1867                 /*Mask fifo empty and full int and reset fifo*/
1868                 hdmi_msk_reg(hdmi_dev, AUD_INT,
1869                              m_FIFO_EMPTY_MASK | m_FIFO_FULL_MASK,
1870                              v_FIFO_EMPTY_MASK(1) | v_FIFO_FULL_MASK(1));
1871                 hdmi_msk_reg(hdmi_dev, AUD_CONF0,
1872                              m_SW_AUD_FIFO_RST, v_SW_AUD_FIFO_RST(1));
1873                 hdmi_writel(hdmi_dev, MC_SWRSTZREQ, 0xF7);
1874                 hdmi_writel(hdmi_dev, AUD_CONF2, 0x0);
1875                 usleep_range(90, 100);
1876                 if (channel == I2S_CHANNEL_7_8) {
1877                         HDMIDBG("hbr mode.\n");
1878                         hdmi_writel(hdmi_dev, AUD_CONF2, 0x1);
1879                         word_length = I2S_24BIT_SAMPLE;
1880                 } else if ((audio->rate == HDMI_AUDIO_FS_48000) ||
1881                            (audio->rate == HDMI_AUDIO_FS_192000)) {
1882                         HDMIDBG("nlpcm mode.\n");
1883                         hdmi_writel(hdmi_dev, AUD_CONF2, 0x2);
1884                         word_length = I2S_24BIT_SAMPLE;
1885                 } else {
1886                         hdmi_writel(hdmi_dev, AUD_CONF2, 0x0);
1887                 }
1888                 hdmi_msk_reg(hdmi_dev, AUD_CONF0,
1889                              m_I2S_SEL | m_I2S_IN_EN,
1890                              v_I2S_SEL(AUDIO_I2S) | v_I2S_IN_EN(channel));
1891                 hdmi_writel(hdmi_dev, AUD_CONF1,
1892                             v_I2S_MODE(I2S_STANDARD_MODE) |
1893                             v_I2S_WIDTH(word_length));
1894         }
1895
1896         hdmi_msk_reg(hdmi_dev, AUD_INPUTCLKFS,
1897                      m_LFS_FACTOR, v_LFS_FACTOR(mclk_fs));
1898
1899         /*Set N value*/
1900         hdmi_msk_reg(hdmi_dev, AUD_N3, m_NCTS_ATOMIC_WR, v_NCTS_ATOMIC_WR(1));
1901         /*Set CTS by manual*/
1902         hdmi_msk_reg(hdmi_dev, AUD_CTS3,
1903                      m_N_SHIFT | m_CTS_MANUAL | m_AUD_CTS3,
1904                      v_N_SHIFT(N_SHIFT_1) |
1905                      v_CTS_MANUAL(1) |
1906                      v_AUD_CTS3(CTS >> 16));
1907         hdmi_writel(hdmi_dev, AUD_CTS2, (CTS >> 8) & 0xff);
1908         hdmi_writel(hdmi_dev, AUD_CTS1, CTS & 0xff);
1909
1910         hdmi_msk_reg(hdmi_dev, AUD_N3, m_AUD_N3, v_AUD_N3(N >> 16));
1911         hdmi_writel(hdmi_dev, AUD_N2, (N >> 8) & 0xff);
1912         hdmi_writel(hdmi_dev, AUD_N1, N & 0xff);
1913
1914         /* set channel status register */
1915         hdmi_msk_reg(hdmi_dev, FC_AUDSCHNLS7,
1916                      m_AUDIO_SAMPLE_RATE, v_AUDIO_SAMPLE_RATE(rate));
1917         hdmi_writel(hdmi_dev, FC_AUDSCHNLS8, ((~rate) << 4) | 0x2);
1918
1919         hdmi_msk_reg(hdmi_dev, AUD_CONF0,
1920                      m_SW_AUD_FIFO_RST, v_SW_AUD_FIFO_RST(1));
1921
1922         hdmi_dev_config_aai(hdmi_dev, audio);
1923
1924         return 0;
1925 }
1926
1927 static int hdmi_dev_control_output(struct hdmi *hdmi, int enable)
1928 {
1929         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1930         struct hdmi_video vpara;
1931
1932         HDMIDBG("[%s] %d\n", __func__, enable);
1933         if (enable == HDMI_AV_UNMUTE) {
1934                 hdmi_writel(hdmi_dev, FC_DBGFORCE, 0x00);
1935                 if (hdmi->edid.sink_hdmi == OUTPUT_HDMI)
1936                         hdmi_msk_reg(hdmi_dev, FC_GCP,
1937                                      m_FC_SET_AVMUTE | m_FC_CLR_AVMUTE,
1938                                      v_FC_SET_AVMUTE(0) | v_FC_CLR_AVMUTE(1));
1939         } else {
1940                 if (enable & HDMI_VIDEO_MUTE) {
1941                         hdmi_msk_reg(hdmi_dev, FC_DBGFORCE,
1942                                      m_FC_FORCEVIDEO, v_FC_FORCEVIDEO(1));
1943                         if (hdmi->edid.sink_hdmi == OUTPUT_HDMI) {
1944                                 hdmi_msk_reg(hdmi_dev, FC_GCP,
1945                                              m_FC_SET_AVMUTE |
1946                                              m_FC_CLR_AVMUTE,
1947                                              v_FC_SET_AVMUTE(1) |
1948                                              v_FC_CLR_AVMUTE(0));
1949                                 vpara.vic = hdmi->vic;
1950                                 vpara.color_output = HDMI_COLOR_RGB_0_255;
1951                                 hdmi_dev_config_avi(hdmi_dev, &vpara);
1952                                 while ((!hdmi_readl(hdmi_dev, IH_FC_STAT1)) &
1953                                        m_AVI_INFOFRAME) {
1954                                         usleep_range(900, 1000);
1955                                 }
1956                         }
1957                 }
1958 /*              if (enable & HDMI_AUDIO_MUTE) {
1959  *                      hdmi_msk_reg(hdmi_dev, FC_AUDSCONF,
1960  *                                   m_AUD_PACK_SAMPFIT,
1961  *                                   v_AUD_PACK_SAMPFIT(0x0F));
1962  *              }
1963  */
1964                 if (enable == (HDMI_VIDEO_MUTE | HDMI_AUDIO_MUTE)) {
1965                         if (hdmi->ops->hdcp_power_off_cb)
1966                                 hdmi->ops->hdcp_power_off_cb(hdmi);
1967                         rockchip_hdmiv2_powerdown(hdmi_dev);
1968                 }
1969         }
1970         return 0;
1971 }
1972
1973 static int hdmi_dev_insert(struct hdmi *hdmi)
1974 {
1975         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1976
1977         HDMIDBG("%s\n", __func__);
1978         if (!hdmi->uboot)
1979                 hdmi_writel(hdmi_dev, MC_CLKDIS, m_HDCPCLK_DISABLE);
1980         return HDMI_ERROR_SUCESS;
1981 }
1982
1983 static int hdmi_dev_remove(struct hdmi *hdmi)
1984 {
1985         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1986
1987         HDMIDBG("%s\n", __func__);
1988         if (hdmi->ops->hdcp_power_off_cb)
1989                 hdmi->ops->hdcp_power_off_cb(hdmi);
1990         rockchip_hdmiv2_powerdown(hdmi_dev);
1991         hdmi_dev->tmdsclk = 0;
1992         return HDMI_ERROR_SUCESS;
1993 }
1994
1995 static int hdmi_dev_enable(struct hdmi *hdmi)
1996 {
1997         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1998
1999         HDMIDBG("%s\n", __func__);
2000         if (!hdmi_dev->enable) {
2001                 hdmi_writel(hdmi_dev, IH_MUTE, 0x00);
2002                 hdmi_dev->enable = 1;
2003         }
2004         hdmi_submit_work(hdmi, HDMI_HPD_CHANGE, 10, 0);
2005         return 0;
2006 }
2007
2008 static int hdmi_dev_disable(struct hdmi *hdmi)
2009 {
2010         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
2011
2012         HDMIDBG("%s\n", __func__);
2013         if (hdmi_dev->enable) {
2014                 hdmi_dev->enable = 0;
2015                 hdmi_writel(hdmi_dev, IH_MUTE, 0x1);
2016         }
2017         return 0;
2018 }
2019
2020 void rockchip_hdmiv2_dev_init_ops(struct hdmi_ops *ops)
2021 {
2022         if (ops) {
2023                 ops->enable     = hdmi_dev_enable;
2024                 ops->disable    = hdmi_dev_disable;
2025                 ops->getstatus  = hdmi_dev_detect_hotplug;
2026                 ops->insert     = hdmi_dev_insert;
2027                 ops->remove     = hdmi_dev_remove;
2028                 ops->getedid    = hdmi_dev_read_edid;
2029                 ops->setvideo   = hdmi_dev_config_video;
2030                 ops->setaudio   = hdmi_dev_config_audio;
2031                 ops->setmute    = hdmi_dev_control_output;
2032                 ops->setvsi     = hdmi_dev_config_vsi;
2033         }
2034 }
2035
2036 void rockchip_hdmiv2_dev_initial(struct hdmi_dev *hdmi_dev)
2037 {
2038         struct hdmi *hdmi = hdmi_dev->hdmi;
2039
2040         if (!hdmi->uboot) {
2041                 pr_info("reset hdmi\n");
2042                 if (hdmi_dev->soctype == HDMI_SOC_RK3288) {
2043                         rk3288_cru_set_soft_reset(RK3288_SOFT_RST_HDMI, true);
2044                         usleep_range(10, 20);
2045                         rk3288_cru_set_soft_reset(RK3288_SOFT_RST_HDMI, false);
2046                 } else {
2047                         if (hdmi_dev->soctype == HDMI_SOC_RK322X) {
2048                                 regmap_write(hdmi_dev->grf_base,
2049                                              RK322X_GRF_SOC_CON2,
2050                                              RK322X_DDC_MASK_EN);
2051                                 regmap_write(hdmi_dev->grf_base,
2052                                              RK322X_GRF_SOC_CON6,
2053                                              RK322X_IO_3V_DOMAIN);
2054                         }
2055                         reset_control_assert(hdmi_dev->reset);
2056                         usleep_range(10, 20);
2057                         reset_control_deassert(hdmi_dev->reset);
2058                 }
2059                 rockchip_hdmiv2_powerdown(hdmi_dev);
2060         } else {
2061                 hdmi->hotplug = hdmi_dev_detect_hotplug(hdmi);
2062                 if (hdmi->hotplug != HDMI_HPD_ACTIVED)
2063                         hdmi->uboot = 0;
2064         }
2065         /*mute unnecessary interrrupt, only enable hpd*/
2066         hdmi_writel(hdmi_dev, IH_MUTE_FC_STAT0, 0xff);
2067         hdmi_writel(hdmi_dev, IH_MUTE_FC_STAT1, 0xff);
2068         hdmi_writel(hdmi_dev, IH_MUTE_FC_STAT2, 0xff);
2069         hdmi_writel(hdmi_dev, IH_MUTE_AS_STAT0, 0xff);
2070         hdmi_writel(hdmi_dev, IH_MUTE_PHY_STAT0, 0xfc);
2071         hdmi_writel(hdmi_dev, IH_MUTE_I2CM_STAT0, 0xff);
2072         hdmi_writel(hdmi_dev, IH_MUTE_CEC_STAT0, 0xff);
2073         hdmi_writel(hdmi_dev, IH_MUTE_VP_STAT0, 0xff);
2074         hdmi_writel(hdmi_dev, IH_MUTE_I2CMPHY_STAT0, 0xff);
2075         hdmi_writel(hdmi_dev, IH_MUTE_AHBDMAAUD_STAT0, 0xff);
2076
2077         /* disable hdcp interrup */
2078         hdmi_writel(hdmi_dev, A_APIINTMSK, 0xff);
2079         hdmi_writel(hdmi_dev, PHY_MASK, 0xf1);
2080
2081         if (hdmi->property->feature & SUPPORT_CEC)
2082                 rockchip_hdmiv2_cec_init(hdmi);
2083         if (hdmi->property->feature & SUPPORT_HDCP)
2084                 rockchip_hdmiv2_hdcp_init(hdmi);
2085 }
2086
2087 irqreturn_t rockchip_hdmiv2_dev_irq(int irq, void *priv)
2088 {
2089         struct hdmi_dev *hdmi_dev = priv;
2090         struct hdmi *hdmi = hdmi_dev->hdmi;
2091         char phy_pol = hdmi_readl(hdmi_dev, PHY_POL0);
2092         char phy_status = hdmi_readl(hdmi_dev, PHY_STAT0);
2093         char phy_int0 = hdmi_readl(hdmi_dev, PHY_INI0);
2094         /*read interrupt*/
2095         char fc_stat0 = hdmi_readl(hdmi_dev, IH_FC_STAT0);
2096         char fc_stat1 = hdmi_readl(hdmi_dev, IH_FC_STAT1);
2097         char fc_stat2 = hdmi_readl(hdmi_dev, IH_FC_STAT2);
2098         char aud_int = hdmi_readl(hdmi_dev, IH_AS_SATA0);
2099         char phy_int = hdmi_readl(hdmi_dev, IH_PHY_STAT0);
2100         char vp_stat0 = hdmi_readl(hdmi_dev, IH_VP_STAT0);
2101         char cec_int = hdmi_readl(hdmi_dev, IH_CEC_STAT0);
2102         char hdcp_int = hdmi_readl(hdmi_dev, A_APIINTSTAT);
2103         char hdcp2_int = hdmi_readl(hdmi_dev, HDCP2REG_STAT);
2104
2105         /*clear interrupt*/
2106         hdmi_writel(hdmi_dev, IH_FC_STAT0, fc_stat0);
2107         hdmi_writel(hdmi_dev, IH_FC_STAT1, fc_stat1);
2108         hdmi_writel(hdmi_dev, IH_FC_STAT2, fc_stat2);
2109         hdmi_writel(hdmi_dev, IH_VP_STAT0, vp_stat0);
2110
2111         if (phy_int0 || phy_int) {
2112                 if ((phy_int0 & m_PHY_LOCK) &&
2113                     (phy_pol & m_PHY_LOCK) == 0) {
2114                         pr_info("hdmi phy pll unlock\n");
2115                         hdmi_submit_work(hdmi, HDMI_SET_VIDEO, 0, 0);
2116                 }
2117                 phy_pol = (phy_int0 & (~phy_status)) | ((~phy_int0) & phy_pol);
2118                 hdmi_writel(hdmi_dev, PHY_POL0, phy_pol);
2119                 hdmi_writel(hdmi_dev, IH_PHY_STAT0, phy_int);
2120                 if ((phy_int & m_HPD) || ((phy_int & 0x3c) == 0x3c))
2121                         hdmi_submit_work(hdmi, HDMI_HPD_CHANGE, 20, 0);
2122         }
2123
2124         /* Audio error */
2125         if (aud_int) {
2126                 hdmi_writel(hdmi_dev, IH_AS_SATA0, aud_int);
2127                 hdmi_msk_reg(hdmi_dev, AUD_CONF0,
2128                              m_SW_AUD_FIFO_RST, v_SW_AUD_FIFO_RST(1));
2129                 hdmi_writel(hdmi_dev, MC_SWRSTZREQ, 0xF7);
2130         }
2131         /* CEC */
2132         if (cec_int) {
2133                 hdmi_writel(hdmi_dev, IH_CEC_STAT0, cec_int);
2134                 if (hdmi_dev->hdmi->property->feature & SUPPORT_CEC)
2135                         rockchip_hdmiv2_cec_isr(hdmi_dev, cec_int);
2136         }
2137         /* HDCP */
2138         if (hdcp_int) {
2139                 hdmi_writel(hdmi_dev, A_APIINTCLR, hdcp_int);
2140                 rockchip_hdmiv2_hdcp_isr(hdmi_dev, hdcp_int);
2141         }
2142
2143         /* HDCP2 */
2144         if (hdcp2_int) {
2145                 hdmi_writel(hdmi_dev, HDCP2REG_STAT, hdcp2_int);
2146                 pr_info("hdcp2_int is 0x%02x\n", hdcp2_int);
2147                 if ((hdcp2_int & m_HDCP2_AUTH_FAIL ||
2148                      hdcp2_int & m_HDCP2_AUTH_LOST) &&
2149                     hdmi_dev->hdcp2_start) {
2150                         pr_info("hdcp2 failed or lost\n");
2151                         hdmi_dev->hdcp2_start();
2152                 }
2153         }
2154         return IRQ_HANDLED;
2155 }