drivers/video/rockchip/hdmi/rockchip-hdmiv2/rockchip_hdmiv2_hw.c

   1 #include <linux/delay.h>
   2 #include <linux/interrupt.h>
   3 #include <linux/rockchip/grf.h>
   4 #include <linux/rockchip/iomap.h>
   5 #include "rockchip_hdmiv2.h"
   6 #include "rockchip_hdmiv2_hw.h"
   7
   8 static const struct phy_mpll_config_tab PHY_MPLL_TABLE[] = {
   9         /*tmdsclk = (pixclk / ref_cntrl ) * (fbdiv2 * fbdiv1) / nctrl / tmdsmhl
  10           opmode: 0:HDMI1.4     1:HDMI2.0
  11         */
  12 /*      |pixclock|      tmdsclock|pixrepet|colordepth|prepdiv|tmdsmhl|opmode|
  13                 fbdiv2|fbdiv1|ref_cntrl|nctrl|propctrl|intctrl|gmpctrl| */
  14         {27000000,      27000000,       0,      8,      0,      0,      0,
  15                 2,      3,      0,      3,      3,      0,      0},
  16         {27000000,      33750000,       0,      10,     1,      0,      0,
  17                 5,      1,      0,      3,      3,      0,      0},
  18         {27000000,      40500000,       0,      12,     2,      0,      0,
  19                 3,      3,      0,      3,      3,      0,      0},
  20         {27000000,      54000000,       0,      16,     3,      0,      0,
  21                 2,      3,      0,      2,      5,      0,      1},
  22 /*      {74250000,      74250000,       0,      8,      0,      0,      0,
  23         1,      3,      0,      2,      5,      0,      1}, */
  24         {74250000,      74250000,       0,      8,      0,      0,      0,
  25                 4,      3,      3,      2,      7,      0,      3},
  26         {74250000,      92812500,       0,      10,     1,      0,      0,
  27                 5,      0,      1,      1,      7,      0,      2},
  28         {74250000,      111375000,      0,      12,     2,      0,      0,
  29                 1,      2,      0,      1,      7,      0,      2},
  30         {74250000,      148500000,      0,      16,     3,      0,      0,
  31                 1,      3,      0,      1,      7,      0,      2},
  32         {148500000,     74250000,       0,      8,      0,      0,      0,
  33                 1,      1,      1,      1,      0,      0,      3},
  34         {148500000,     148500000,      0,      8,      0,      0,      0,
  35                 1,      1,      0,      1,      0,      0,      3},
  36         {148500000,     185625000,      0,      10,     1,      0,      0,
  37                 5,      0,      3,      0,      7,      0,      3},
  38         {148500000,     222750000,      0,      12,     2,      0,      0,
  39                 1,      2,      1,      0,      7,      0,      3},
  40         {148500000,     297000000,      0,      16,     3,      0,      0,
  41                 1,      1,      0,      0,      7,      0,      3},
  42         {297000000,     148500000,      0,      8,      0,      0,      0,
  43                 1,      0,      1,      0,      0,      0,      3},
  44         {297000000,     297000000,      0,      8,      0,      0,      0,
  45                 1,      0,      0,      0,      0,      0,      3},
  46         {297000000,     371250000,      0,      10,     1,      3,      1,
  47                 5,      1,      3,      1,      7,      0,      3},
  48         {297000000,     445500000,      0,      12,     2,      3,      1,
  49                 1,      2,      0,      1,      7,      0,      3},
  50         {297000000,     594000000,      0,      16,     3,      3,      1,
  51                 1,      3,      1,      0,      0,      0,      3},
  52 /*      {594000000,     297000000,      0,      8,      0,      0,      0,
  53                 1,      3,      3,      1,      0,      0,      3},*/
  54         {594000000,     297000000,      0,      8,      0,      0,      0,
  55                 1,      0,      1,      0,      0,      0,      3},
  56         {594000000,     371250000,      0,      10,     1,      3,      1,
  57                 5,      0,      3,      0,      7,      0,      3},
  58         {594000000,     445500000,      0,      12,     2,      3,      1,
  59                 1,      2,      1,      1,      7,      0,      3},
  60         {594000000,     594000000,      0,      16,     3,      3,      1,
  61                 1,      3,      3,      0,      0,      0,      3},
  62         {594000000,     594000000,      0,      8,      0,      3,      1,
  63                 1,      3,      3,      0,      0,      0,      3},
  64 };
  65 /* ddc i2c master reset */
  66 static void rockchip_hdmiv2_i2cm_reset(struct hdmi_dev *hdmi_dev)
  67 {
  68         hdmi_msk_reg(hdmi_dev, I2CM_SOFTRSTZ,
  69                      m_I2CM_SOFTRST, v_I2CM_SOFTRST(0));
  70         usleep_range(90, 100);
  71 }
  72
  73 /*set read/write offset,set read/write mode*/
  74 static void rockchip_hdmiv2_i2cm_write_request(struct hdmi_dev *hdmi_dev,
  75                                                u8 offset, u8 data)
  76 {
  77         hdmi_writel(hdmi_dev, I2CM_ADDRESS, offset);
  78         hdmi_writel(hdmi_dev, I2CM_DATAO, data);
  79         hdmi_msk_reg(hdmi_dev, I2CM_OPERATION, m_I2CM_WR, v_I2CM_WR(1));
  80 }
  81
  82 static void rockchip_hdmiv2_i2cm_read_request(struct hdmi_dev *hdmi_dev,
  83                                               u8 offset)
  84 {
  85         hdmi_writel(hdmi_dev, I2CM_ADDRESS, offset);
  86         hdmi_msk_reg(hdmi_dev, I2CM_OPERATION, m_I2CM_RD, v_I2CM_RD(1));
  87 }
  88
  89 static void rockchip_hdmiv2_i2cm_write_data(struct hdmi_dev *hdmi_dev,
  90                                             u8 data, u8 offset)
  91 {
  92         u8 interrupt;
  93         int trytime = 2;
  94         int i = 20;
  95
  96         while (trytime-- > 0) {
  97                 rockchip_hdmiv2_i2cm_write_request(hdmi_dev, offset, data);
  98                 while (i--) {
  99                         usleep_range(900, 1000);
 100                         interrupt = hdmi_readl(hdmi_dev, IH_I2CM_STAT0);
 101                         if (interrupt)
 102                                 hdmi_writel(hdmi_dev,
 103                                             IH_I2CM_STAT0, interrupt);
 104
 105                         if (interrupt & (m_SCDC_READREQ |
 106                                          m_I2CM_DONE | m_I2CM_ERROR))
 107                                 break;
 108                 }
 109
 110                 if (interrupt & m_I2CM_DONE) {
 111                         dev_dbg(hdmi_dev->hdmi->dev,
 112                                 "[%s] write offset %02x data %02x success\n",
 113                                 __func__, offset, data);
 114                         trytime = 0;
 115                 } else if ((interrupt & m_I2CM_ERROR) || (i == -1)) {
 116                         dev_err(hdmi_dev->hdmi->dev,
 117                                 "[%s] write data error\n", __func__);
 118                         rockchip_hdmiv2_i2cm_reset(hdmi_dev);
 119                 }
 120         }
 121 }
 122
 123 static int rockchip_hdmiv2_i2cm_read_data(struct hdmi_dev *hdmi_dev, u8 offset)
 124 {
 125         u8 interrupt, val;
 126         int trytime = 2;
 127         int i = 20;
 128
 129         while (trytime-- > 0) {
 130                 rockchip_hdmiv2_i2cm_read_request(hdmi_dev, offset);
 131                 while (i--) {
 132                         usleep_range(900, 1000);
 133                         interrupt = hdmi_readl(hdmi_dev, IH_I2CM_STAT0);
 134                         if (interrupt)
 135                                 hdmi_writel(hdmi_dev, IH_I2CM_STAT0, interrupt);
 136
 137                         if (interrupt & (m_SCDC_READREQ |
 138                                 m_I2CM_DONE | m_I2CM_ERROR))
 139                                 break;
 140                 }
 141
 142                 if (interrupt & m_I2CM_DONE) {
 143                         val = hdmi_readl(hdmi_dev, I2CM_DATAI);
 144                         trytime = 0;
 145                 } else if ((interrupt & m_I2CM_ERROR) || (i == -1)) {
 146                         pr_err("[%s] read data error\n", __func__);
 147                         rockchip_hdmiv2_i2cm_reset(hdmi_dev);
 148                 }
 149         }
 150         return val;
 151 }
 152
 153 static void rockchip_hdmiv2_i2cm_mask_int(struct hdmi_dev *hdmi_dev, int mask)
 154 {
 155         if (0 == mask) {
 156                 hdmi_msk_reg(hdmi_dev, I2CM_INT,
 157                              m_I2CM_DONE_MASK, v_I2CM_DONE_MASK(0));
 158                 hdmi_msk_reg(hdmi_dev, I2CM_CTLINT,
 159                              m_I2CM_NACK_MASK | m_I2CM_ARB_MASK,
 160                              v_I2CM_NACK_MASK(0) | v_I2CM_ARB_MASK(0));
 161         } else {
 162                 hdmi_msk_reg(hdmi_dev, I2CM_INT,
 163                              m_I2CM_DONE_MASK, v_I2CM_DONE_MASK(1));
 164                 hdmi_msk_reg(hdmi_dev, I2CM_CTLINT,
 165                              m_I2CM_NACK_MASK | m_I2CM_ARB_MASK,
 166                              v_I2CM_NACK_MASK(1) | v_I2CM_ARB_MASK(1));
 167         }
 168 }
 169
 170 #define I2C_DIV_FACTOR 100000
 171 static u16 i2c_count(u16 sfrclock, u16 sclmintime)
 172 {
 173         unsigned long tmp_scl_period = 0;
 174
 175         if (((sfrclock * sclmintime) % I2C_DIV_FACTOR) != 0)
 176                 tmp_scl_period = (unsigned long)((sfrclock * sclmintime) +
 177                                 (I2C_DIV_FACTOR - ((sfrclock * sclmintime) %
 178                                 I2C_DIV_FACTOR))) / I2C_DIV_FACTOR;
 179         else
 180                 tmp_scl_period = (unsigned long)(sfrclock * sclmintime) /
 181                                 I2C_DIV_FACTOR;
 182
 183         return (u16)(tmp_scl_period);
 184 }
 185
 186 #define EDID_I2C_MIN_SS_SCL_HIGH_TIME   50000
 187 #define EDID_I2C_MIN_SS_SCL_LOW_TIME    50000
 188
 189 static void rockchip_hdmiv2_i2cm_clk_init(struct hdmi_dev *hdmi_dev)
 190 {
 191         /* Set DDC I2C CLK which devided from DDC_CLK. */
 192         hdmi_writel(hdmi_dev, I2CM_SS_SCL_HCNT_0_ADDR,
 193                     i2c_count(24000, EDID_I2C_MIN_SS_SCL_HIGH_TIME));
 194         hdmi_writel(hdmi_dev, I2CM_SS_SCL_LCNT_0_ADDR,
 195                     i2c_count(24000, EDID_I2C_MIN_SS_SCL_LOW_TIME));
 196         hdmi_msk_reg(hdmi_dev, I2CM_DIV, m_I2CM_FAST_STD_MODE,
 197                      v_I2CM_FAST_STD_MODE(STANDARD_MODE));
 198 }
 199
 200 static int rockchip_hdmiv2_scdc_get_sink_version(struct hdmi_dev *hdmi_dev)
 201 {
 202         return rockchip_hdmiv2_i2cm_read_data(hdmi_dev, SCDC_SINK_VER);
 203 }
 204
 205 static void rockchip_hdmiv2_scdc_set_source_version(struct hdmi_dev *hdmi_dev,
 206                                                     u8 version)
 207 {
 208         rockchip_hdmiv2_i2cm_write_data(hdmi_dev, version, SCDC_SOURCE_VER);
 209 }
 210
 211
 212 static void rockchip_hdmiv2_scdc_read_request(struct hdmi_dev *hdmi_dev,
 213                                               int enable)
 214 {
 215         hdmi_msk_reg(hdmi_dev, I2CM_SCDC_READ_UPDATE,
 216                      m_I2CM_READ_REQ_EN, v_I2CM_READ_REQ_EN(enable));
 217         rockchip_hdmiv2_i2cm_write_data(hdmi_dev, enable, SCDC_CONFIG_0);
 218 }
 219
 220 #ifdef HDMI_20_SCDC
 221 static void rockchip_hdmiv2_scdc_update_read(struct hdmi_dev *hdmi_dev)
 222 {
 223         hdmi_msk_reg(hdmi_dev, I2CM_SCDC_READ_UPDATE,
 224                      m_I2CM_READ_UPDATE, v_I2CM_READ_UPDATE(1));
 225 }
 226
 227
 228 static int rockchip_hdmiv2_scdc_get_scambling_status(struct hdmi_dev *hdmi_dev)
 229 {
 230         int val;
 231
 232         val = rockchip_hdmiv2_i2cm_read_data(hdmi_dev, SCDC_SCRAMBLER_STAT);
 233         return val;
 234 }
 235
 236 static void rockchip_hdmiv2_scdc_enable_polling(struct hdmi_dev *hdmi_dev,
 237                                                 int enable)
 238 {
 239         rockchip_hdmiv2_scdc_read_request(hdmi_dev, enable);
 240         hdmi_msk_reg(hdmi_dev, I2CM_SCDC_READ_UPDATE,
 241                      m_I2CM_UPRD_VSYNC_EN, v_I2CM_UPRD_VSYNC_EN(enable));
 242 }
 243
 244 static int rockchip_hdmiv2_scdc_get_status_reg0(struct hdmi_dev *hdmi_dev)
 245 {
 246         rockchip_hdmiv2_scdc_read_request(hdmi_dev, 1);
 247         rockchip_hdmiv2_scdc_update_read(hdmi_dev);
 248         return hdmi_readl(hdmi_dev, I2CM_SCDC_UPDATE0);
 249 }
 250
 251 static int rockchip_hdmiv2_scdc_get_status_reg1(struct hdmi_dev *hdmi_dev)
 252 {
 253         rockchip_hdmiv2_scdc_read_request(hdmi_dev, 1);
 254         rockchip_hdmiv2_scdc_update_read(hdmi_dev);
 255         return hdmi_readl(hdmi_dev, I2CM_SCDC_UPDATE1);
 256 }
 257 #endif
 258
 259 static void rockchip_hdmiv2_scdc_init(struct hdmi_dev *hdmi_dev)
 260 {
 261         rockchip_hdmiv2_i2cm_reset(hdmi_dev);
 262         rockchip_hdmiv2_i2cm_mask_int(hdmi_dev, 1);
 263         rockchip_hdmiv2_i2cm_clk_init(hdmi_dev);
 264         /* set scdc i2c addr */
 265         hdmi_writel(hdmi_dev, I2CM_SLAVE, DDC_I2C_SCDC_ADDR);
 266         rockchip_hdmiv2_i2cm_mask_int(hdmi_dev, 0);/*enable interrupt*/
 267 }
 268
 269
 270 static int rockchip_hdmiv2_scrambling_enable(struct hdmi_dev *hdmi_dev,
 271                                              int enable)
 272 {
 273         HDMIDBG("%s enable %d\n", __func__, enable);
 274         if (1 == enable) {
 275                 /* Write on Rx the bit Scrambling_Enable, register 0x20 */
 276                 rockchip_hdmiv2_i2cm_write_data(hdmi_dev, 1, SCDC_TMDS_CONFIG);
 277                 /* TMDS software reset request */
 278                 hdmi_msk_reg(hdmi_dev, MC_SWRSTZREQ,
 279                              m_TMDS_SWRST, v_TMDS_SWRST(0));
 280                 /* Enable/Disable Scrambling */
 281                 hdmi_msk_reg(hdmi_dev, FC_SCRAMBLER_CTRL,
 282                              m_FC_SCRAMBLE_EN, v_FC_SCRAMBLE_EN(1));
 283         } else {
 284                 /* Enable/Disable Scrambling */
 285                 hdmi_msk_reg(hdmi_dev, FC_SCRAMBLER_CTRL,
 286                              m_FC_SCRAMBLE_EN, v_FC_SCRAMBLE_EN(0));
 287                 /* TMDS software reset request */
 288                 hdmi_msk_reg(hdmi_dev, MC_SWRSTZREQ,
 289                              m_TMDS_SWRST, v_TMDS_SWRST(0));
 290                 /* Write on Rx the bit Scrambling_Enable, register 0x20 */
 291                 rockchip_hdmiv2_i2cm_write_data(hdmi_dev, 0, SCDC_TMDS_CONFIG);
 292         }
 293         return 0;
 294 }
 295
 296
 297
 298 static const struct phy_mpll_config_tab *get_phy_mpll_tab(
 299                 unsigned int pixclock, unsigned int tmdsclk,
 300                 char pixrepet, char colordepth)
 301 {
 302         int i;
 303
 304         if (pixclock == 0)
 305                 return NULL;
 306         HDMIDBG("%s pixClock %u pixRepet %d colorDepth %d\n",
 307                 __func__, pixclock, pixrepet, colordepth);
 308         for (i = 0; i < ARRAY_SIZE(PHY_MPLL_TABLE); i++) {
 309                 if ((PHY_MPLL_TABLE[i].pix_clock == pixclock) &&
 310                     (PHY_MPLL_TABLE[i].tmdsclock == tmdsclk) &&
 311                     (PHY_MPLL_TABLE[i].pix_repet == pixrepet) &&
 312                     (PHY_MPLL_TABLE[i].color_depth == colordepth))
 313                         return &PHY_MPLL_TABLE[i];
 314         }
 315         return NULL;
 316 }
 317
 318 static void rockchip_hdmiv2_powerdown(struct hdmi_dev *hdmi_dev)
 319 {
 320         hdmi_msk_reg(hdmi_dev, PHY_CONF0,
 321                      m_PDDQ_SIG | m_TXPWRON_SIG |
 322                      m_ENHPD_RXSENSE_SIG | m_SVSRET_SIG,
 323                      v_PDDQ_SIG(1) | v_TXPWRON_SIG(0) |
 324                      v_ENHPD_RXSENSE_SIG(1)) | v_SVSRET_SIG(0);
 325         hdmi_writel(hdmi_dev, MC_CLKDIS, 0x7f);
 326 }
 327
 328 int rockchip_hdmiv2_write_phy(struct hdmi_dev *hdmi_dev,
 329                               int reg_addr, int val)
 330 {
 331         int trytime = 2, i = 0, op_status = 0;
 332
 333         while (trytime--) {
 334                 hdmi_writel(hdmi_dev, PHY_I2CM_ADDRESS, reg_addr);
 335                 hdmi_writel(hdmi_dev, PHY_I2CM_DATAO_1, (val >> 8) & 0xff);
 336                 hdmi_writel(hdmi_dev, PHY_I2CM_DATAO_0, val & 0xff);
 337                 hdmi_writel(hdmi_dev, PHY_I2CM_OPERATION, m_PHY_I2CM_WRITE);
 338
 339                 i = 20;
 340                 while (i--) {
 341                         usleep_range(900, 1000);
 342                         op_status = hdmi_readl(hdmi_dev, IH_I2CMPHY_STAT0);
 343                         if (op_status)
 344                                 hdmi_writel(hdmi_dev,
 345                                             IH_I2CMPHY_STAT0,
 346                                             op_status);
 347
 348                         if (op_status & (m_I2CMPHY_DONE | m_I2CMPHY_ERR))
 349                                 break;
 350                 }
 351
 352                 if (op_status & m_I2CMPHY_DONE)
 353                         return 0;
 354                 else
 355                         dev_err(hdmi_dev->hdmi->dev,
 356                                 "[%s] operation error,trytime=%d\n",
 357                                 __func__, trytime);
 358                 msleep(100);
 359         }
 360
 361         return -1;
 362 }
 363
 364 int rockchip_hdmiv2_read_phy(struct hdmi_dev *hdmi_dev,
 365                              int reg_addr)
 366 {
 367         int trytime = 2, i = 0, op_status = 0;
 368         int val = 0;
 369
 370         while (trytime--) {
 371                 hdmi_writel(hdmi_dev, PHY_I2CM_ADDRESS, reg_addr);
 372                 hdmi_writel(hdmi_dev, PHY_I2CM_DATAI_1, 0x00);
 373                 hdmi_writel(hdmi_dev, PHY_I2CM_DATAI_0, 0x00);
 374                 hdmi_writel(hdmi_dev, PHY_I2CM_OPERATION, m_PHY_I2CM_READ);
 375
 376                 i = 20;
 377                 while (i--) {
 378                         usleep_range(900, 1000);
 379                         op_status = hdmi_readl(hdmi_dev, IH_I2CMPHY_STAT0);
 380                         if (op_status)
 381                                 hdmi_writel(hdmi_dev, IH_I2CMPHY_STAT0,
 382                                             op_status);
 383
 384                         if (op_status & (m_I2CMPHY_DONE | m_I2CMPHY_ERR))
 385                                 break;
 386                 }
 387
 388                 if (op_status & m_I2CMPHY_DONE) {
 389                         val = hdmi_readl(hdmi_dev, PHY_I2CM_DATAI_1);
 390                         val = (val & 0xff) << 8;
 391                         val += (hdmi_readl(hdmi_dev, PHY_I2CM_DATAI_0) & 0xff);
 392                         pr_debug("phy_reg0x%02x: 0x%04x",
 393                                  reg_addr, val);
 394                         return val;
 395                 } else {
 396                         pr_err("[%s] operation error,trytime=%d\n",
 397                                __func__, trytime);
 398                 }
 399                 msleep(100);
 400         }
 401
 402         return -1;
 403 }
 404
 405 static int rockchip_hdmiv2_config_phy(struct hdmi_dev *hdmi_dev)
 406 {
 407         int stat = 0, i = 0;
 408         const struct phy_mpll_config_tab *phy_mpll = NULL;
 409
 410         hdmi_msk_reg(hdmi_dev, PHY_I2CM_DIV,
 411                      m_PHY_I2CM_FAST_STD, v_PHY_I2CM_FAST_STD(0));
 412         /* power off PHY */
 413         /* hdmi_writel(hdmi_dev, PHY_CONF0, 0x1e); */
 414         hdmi_msk_reg(hdmi_dev, PHY_CONF0,
 415                      m_PDDQ_SIG | m_TXPWRON_SIG | m_SVSRET_SIG,
 416                      v_PDDQ_SIG(1) | v_TXPWRON_SIG(0) | v_SVSRET_SIG(1));
 417
 418         if (hdmi_dev->tmdsclk_ratio_change &&
 419             hdmi_dev->hdmi->edid.scdc_present == 1) {
 420                 mutex_lock(&hdmi_dev->ddc_lock);
 421                 rockchip_hdmiv2_scdc_init(hdmi_dev);
 422                 stat = rockchip_hdmiv2_i2cm_read_data(hdmi_dev,
 423                                                       SCDC_TMDS_CONFIG);
 424                 if (hdmi_dev->tmdsclk > 340000000)
 425                         stat |= 2;
 426                 else
 427                         stat &= 0x1;
 428                 rockchip_hdmiv2_i2cm_write_data(hdmi_dev,
 429                                                 stat, SCDC_TMDS_CONFIG);
 430                 mutex_unlock(&hdmi_dev->ddc_lock);
 431         }
 432         /* reset PHY */
 433         hdmi_writel(hdmi_dev, MC_PHYRSTZ, v_PHY_RSTZ(1));
 434         usleep_range(1000, 2000);
 435         hdmi_writel(hdmi_dev, MC_PHYRSTZ, v_PHY_RSTZ(0));
 436
 437         /* Set slave address as PHY GEN2 address */
 438         hdmi_writel(hdmi_dev, PHY_I2CM_SLAVE, PHY_GEN2_ADDR);
 439
 440         /* config the required PHY I2C register */
 441         phy_mpll = get_phy_mpll_tab(hdmi_dev->pixelclk,
 442                                     hdmi_dev->tmdsclk,
 443                                     hdmi_dev->pixelrepeat - 1,
 444                                     hdmi_dev->colordepth);
 445         if (phy_mpll) {
 446                 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_OPMODE_PLLCFG,
 447                                           v_PREP_DIV(phy_mpll->prep_div) |
 448                                           v_TMDS_CNTRL(
 449                                           phy_mpll->tmdsmhl_cntrl) |
 450                                           v_OPMODE(phy_mpll->opmode) |
 451                                           v_FBDIV2_CNTRL(
 452                                           phy_mpll->fbdiv2_cntrl) |
 453                                           v_FBDIV1_CNTRL(
 454                                           phy_mpll->fbdiv1_cntrl) |
 455                                           v_REF_CNTRL(phy_mpll->ref_cntrl) |
 456                                           v_MPLL_N_CNTRL(phy_mpll->n_cntrl));
 457                 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_PLLCURRCTRL,
 458                                           v_MPLL_PROP_CNTRL(
 459                                           phy_mpll->prop_cntrl) |
 460                                           v_MPLL_INT_CNTRL(
 461                                           phy_mpll->int_cntrl));
 462                 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_PLLGMPCTRL,
 463                                           v_MPLL_GMP_CNTRL(
 464                                           phy_mpll->gmp_cntrl));
 465         }
 466
 467         rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_CLKSYMCTRL,
 468                                   v_OVERRIDE(1) | v_SLOPEBOOST(0) |
 469                                   v_TX_SYMON(1) | v_TX_TRAON(0) |
 470                                   v_TX_TRBON(0) | v_CLK_SYMON(1));
 471         if (hdmi_dev->tmdsclk > 340000000) {
 472                 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_TERM_RESIS,
 473                                           v_TX_TERM(R50_OHMS));
 474                 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_VLEVCTRL,
 475                                           v_SUP_TXLVL(9) |
 476                                           v_SUP_CLKLVL(17));
 477         } else {
 478                 rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_TERM_RESIS,
 479                                           v_TX_TERM(R100_OHMS));
 480                 if (hdmi_dev->tmdsclk > 165000000)
 481                         rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_VLEVCTRL,
 482                                                   v_SUP_TXLVL(14) |
 483                                                   v_SUP_CLKLVL(17));
 484                 else
 485                         rockchip_hdmiv2_write_phy(hdmi_dev, PHYTX_VLEVCTRL,
 486                                                   v_SUP_TXLVL(18) |
 487                                                   v_SUP_CLKLVL(17));
 488         }
 489         /* rockchip_hdmiv2_write_phy(hdmi_dev, 0x05, 0x8000); */
 490         if (hdmi_dev->tmdsclk_ratio_change)
 491                 msleep(100);
 492         /* power on PHY */
 493         hdmi_writel(hdmi_dev, PHY_CONF0, 0x2e);
 494         /*
 495         hdmi_msk_reg(hdmi_dev, PHY_CONF0,
 496                      m_PDDQ_SIG | m_TXPWRON_SIG | m_ENHPD_RXSENSE_SIG,
 497                      v_PDDQ_SIG(0) | v_TXPWRON_SIG(1) |
 498                      v_ENHPD_RXSENSE_SIG(1));
 499         */
 500         /* check if the PHY PLL is locked */
 501         #define PHY_TIMEOUT     10000
 502         while (i++ < PHY_TIMEOUT) {
 503                 if ((i % 10) == 0) {
 504                         stat = hdmi_readl(hdmi_dev, PHY_STAT0);
 505                         if (stat & m_PHY_LOCK)
 506                                 break;
 507                         usleep_range(1000, 2000);
 508                 }
 509         }
 510         if ((stat & m_PHY_LOCK) == 0) {
 511                 stat = hdmi_readl(hdmi_dev, MC_LOCKONCLOCK);
 512                 dev_err(hdmi_dev->hdmi->dev,
 513                         "PHY PLL not locked: PCLK_ON=%d,TMDSCLK_ON=%d\n",
 514                         (stat & m_PCLK_ON) >> 6, (stat & m_TMDSCLK_ON) >> 5);
 515                 return -1;
 516         }
 517
 518         return 0;
 519 }
 520
 521 static int rockchip_hdmiv2_video_framecomposer(struct hdmi *hdmi_drv,
 522                                                struct hdmi_video *vpara)
 523 {
 524         struct hdmi_dev *hdmi_dev = hdmi_drv->property->priv;
 525         int value, vsync_pol, hsync_pol, de_pol;
 526         struct hdmi_video_timing *timing = NULL;
 527         struct fb_videomode *mode = NULL;
 528         u32 sink_version, tmdsclk;
 529
 530         vsync_pol = hdmi_drv->lcdc->cur_screen->pin_vsync;
 531         hsync_pol = hdmi_drv->lcdc->cur_screen->pin_hsync;
 532         de_pol = (hdmi_drv->lcdc->cur_screen->pin_den == 0) ? 1 : 0;
 533
 534         hdmi_msk_reg(hdmi_dev, A_VIDPOLCFG,
 535                      m_DATAEN_POL | m_VSYNC_POL | m_HSYNC_POL,
 536                      v_DATAEN_POL(de_pol) |
 537                      v_VSYNC_POL(vsync_pol) |
 538                      v_HSYNC_POL(hsync_pol));
 539
 540         timing = (struct hdmi_video_timing *)hdmi_vic2timing(vpara->vic);
 541         if (timing == NULL) {
 542                 dev_err(hdmi_drv->dev,
 543                         "[%s] not found vic %d\n", __func__, vpara->vic);
 544                 return -ENOENT;
 545         }
 546         mode = &(timing->mode);
 547         if (vpara->color_input == HDMI_COLOR_YCBCR420)
 548                 tmdsclk = mode->pixclock / 2;
 549         else
 550                 tmdsclk = mode->pixclock;
 551         switch (vpara->color_output_depth) {
 552         case 10:
 553                 tmdsclk += tmdsclk / 4;
 554                 break;
 555         case 12:
 556                 tmdsclk += tmdsclk / 2;
 557                 break;
 558         case 16:
 559                 tmdsclk += tmdsclk;
 560                 break;
 561         case 8:
 562         default:
 563                 break;
 564         }
 565
 566         if (tmdsclk > 594000000) {
 567                 vpara->color_output_depth = 8;
 568                 tmdsclk = mode->pixclock;
 569         }
 570         pr_info("pixel clk is %u tmds clk is %u\n", mode->pixclock, tmdsclk);
 571         if ((tmdsclk > 340000000 && hdmi_dev->tmdsclk < 340000000) ||
 572             (tmdsclk < 340000000 && hdmi_dev->tmdsclk > 340000000))
 573                 hdmi_dev->tmdsclk_ratio_change = true;
 574         else
 575                 hdmi_dev->tmdsclk_ratio_change = false;
 576
 577         hdmi_dev->tmdsclk = tmdsclk;
 578         hdmi_dev->pixelclk = mode->pixclock;
 579         hdmi_dev->pixelrepeat = timing->pixelrepeat;
 580         hdmi_dev->colordepth = vpara->color_output_depth;
 581
 582         /* Start/stop HDCP keepout window generation */
 583         hdmi_msk_reg(hdmi_dev, FC_INVIDCONF,
 584                      m_FC_HDCP_KEEPOUT, v_FC_HDCP_KEEPOUT(1));
 585         if (hdmi_drv->edid.scdc_present == 1) {
 586                 if (tmdsclk > 340000000) {/* used for HDMI 2.0 TX */
 587                         mutex_lock(&hdmi_dev->ddc_lock);
 588                         rockchip_hdmiv2_scdc_init(hdmi_dev);
 589                         sink_version =
 590                         rockchip_hdmiv2_scdc_get_sink_version(hdmi_dev);
 591                         pr_info("sink scdc version is %d\n", sink_version);
 592                         sink_version = hdmi_drv->edid.hf_vsdb_version;
 593                         rockchip_hdmiv2_scdc_set_source_version(hdmi_dev,
 594                                                                 sink_version);
 595                         if (hdmi_drv->edid.rr_capable == 1)
 596                                 rockchip_hdmiv2_scdc_read_request(hdmi_dev, 1);
 597                         rockchip_hdmiv2_scrambling_enable(hdmi_dev, 1);
 598                         mutex_unlock(&hdmi_dev->ddc_lock);
 599                 } else {
 600                         mutex_lock(&hdmi_dev->ddc_lock);
 601                         rockchip_hdmiv2_scdc_init(hdmi_dev);
 602                         rockchip_hdmiv2_scrambling_enable(hdmi_dev, 0);
 603                         mutex_unlock(&hdmi_dev->ddc_lock);
 604                 }
 605         }
 606
 607         hdmi_msk_reg(hdmi_dev, FC_INVIDCONF,
 608                      m_FC_VSYNC_POL | m_FC_HSYNC_POL | m_FC_DE_POL |
 609                      m_FC_HDMI_DVI | m_FC_INTERLACE_MODE,
 610                      v_FC_VSYNC_POL(vsync_pol) | v_FC_HSYNC_POL(hsync_pol) |
 611                      v_FC_DE_POL(de_pol) | v_FC_HDMI_DVI(vpara->sink_hdmi) |
 612                      v_FC_INTERLACE_MODE(mode->vmode));
 613         if (mode->vmode == FB_VMODE_INTERLACED)
 614                 hdmi_msk_reg(hdmi_dev, FC_INVIDCONF,
 615                              m_FC_VBLANK, v_FC_VBLANK(1));
 616         else
 617                 hdmi_msk_reg(hdmi_dev, FC_INVIDCONF,
 618                              m_FC_VBLANK, v_FC_VBLANK(0));
 619
 620         value = mode->xres;
 621         if (vpara->color_input == HDMI_COLOR_YCBCR420)
 622                 value = value / 2;
 623         hdmi_writel(hdmi_dev, FC_INHACTIV1, v_FC_HACTIVE1(value >> 8));
 624         hdmi_writel(hdmi_dev, FC_INHACTIV0, (value & 0xff));
 625
 626         value = mode->yres;
 627         hdmi_writel(hdmi_dev, FC_INVACTIV1, v_FC_VACTIVE1(value >> 8));
 628         hdmi_writel(hdmi_dev, FC_INVACTIV0, (value & 0xff));
 629
 630         value = mode->hsync_len + mode->left_margin + mode->right_margin;
 631         if (vpara->color_input == HDMI_COLOR_YCBCR420)
 632                 value = value / 2;
 633         hdmi_writel(hdmi_dev, FC_INHBLANK1, v_FC_HBLANK1(value >> 8));
 634         hdmi_writel(hdmi_dev, FC_INHBLANK0, (value & 0xff));
 635
 636         value = mode->vsync_len + mode->upper_margin + mode->lower_margin;
 637         hdmi_writel(hdmi_dev, FC_INVBLANK, (value & 0xff));
 638
 639         value = mode->right_margin;
 640         if (vpara->color_input == HDMI_COLOR_YCBCR420)
 641                 value = value / 2;
 642         hdmi_writel(hdmi_dev, FC_HSYNCINDELAY1, v_FC_HSYNCINDEAY1(value >> 8));
 643         hdmi_writel(hdmi_dev, FC_HSYNCINDELAY0, (value & 0xff));
 644
 645         value = mode->lower_margin;
 646         hdmi_writel(hdmi_dev, FC_VSYNCINDELAY, (value & 0xff));
 647
 648         value = mode->hsync_len;
 649         if (vpara->color_input == HDMI_COLOR_YCBCR420)
 650                 value = value / 2;
 651         hdmi_writel(hdmi_dev, FC_HSYNCINWIDTH1, v_FC_HSYNCWIDTH1(value >> 8));
 652         hdmi_writel(hdmi_dev, FC_HSYNCINWIDTH0, (value & 0xff));
 653
 654         value = mode->vsync_len;
 655         hdmi_writel(hdmi_dev, FC_VSYNCINWIDTH, (value & 0xff));
 656
 657         /*Set the control period minimum duration
 658          (min. of 12 pixel clock cycles, refer to HDMI 1.4b specification)*/
 659         hdmi_writel(hdmi_dev, FC_CTRLDUR, 12);
 660         hdmi_writel(hdmi_dev, FC_EXCTRLDUR, 32);
 661
 662         /* spacing < 256^2 * config / tmdsClock, spacing <= 50ms
 663          * worst case: tmdsClock == 25MHz => config <= 19
 664          */
 665         hdmi_writel(hdmi_dev, FC_EXCTRLSPAC,
 666                     (hdmi_dev->tmdsclk/1000) * 50 / (256 * 512));
 667
 668 #if 0
 669         /*Set PreambleFilter*/
 670         for (i = 0; i < 3; i++) {
 671                 value = (i + 1) * 11;
 672                 if (i == 0)             /*channel 0*/
 673                         hdmi_writel(hdmi_dev, FC_CH0PREAM, value);
 674                 else if (i == 1)        /*channel 1*/
 675                         hdmi_writel(hdmi_dev, FC_CH1PREAM, value & 0x3f);
 676                 else if (i == 2)        /*channel 2*/
 677                         hdmi_writel(hdmi_dev, FC_CH2PREAM, value & 0x3f);
 678         }
 679 #endif
 680
 681         hdmi_writel(hdmi_dev, FC_PRCONF, v_FC_PR_FACTOR(timing->pixelrepeat));
 682
 683         return 0;
 684 }
 685
 686 static int rockchip_hdmiv2_video_packetizer(struct hdmi_dev *hdmi_dev,
 687                                             struct hdmi_video *vpara)
 688 {
 689         unsigned char color_depth = 0;
 690         unsigned char output_select = 0;
 691         unsigned char remap_size = 0;
 692
 693         if (vpara->color_output == HDMI_COLOR_YCBCR422) {
 694                 switch (vpara->color_output_depth) {
 695                 case 8:
 696                         remap_size = YCC422_16BIT;
 697                         break;
 698                 case 10:
 699                         remap_size = YCC422_20BIT;
 700                         break;
 701                 case 12:
 702                         remap_size = YCC422_24BIT;
 703                         break;
 704                 default:
 705                         remap_size = YCC422_16BIT;
 706                         break;
 707                 }
 708
 709                 output_select = OUT_FROM_YCC422_REMAP;
 710                 /*Config remap size for the different color Depth*/
 711                 hdmi_msk_reg(hdmi_dev, VP_REMAP,
 712                              m_YCC422_SIZE, v_YCC422_SIZE(remap_size));
 713         } else {
 714                 switch (vpara->color_output_depth) {
 715                 case 10:
 716                         color_depth = COLOR_DEPTH_30BIT;
 717                         output_select = OUT_FROM_PIXEL_PACKING;
 718                         break;
 719                 case 12:
 720                         color_depth = COLOR_DEPTH_36BIT;
 721                         output_select = OUT_FROM_PIXEL_PACKING;
 722                         break;
 723                 case 16:
 724                         color_depth = COLOR_DEPTH_48BIT;
 725                         output_select = OUT_FROM_PIXEL_PACKING;
 726                         break;
 727                 case 8:
 728                 default:
 729                         color_depth = COLOR_DEPTH_24BIT_DEFAULT;
 730                         output_select = OUT_FROM_8BIT_BYPASS;
 731                         break;
 732                 }
 733
 734                 /*Config Color Depth*/
 735                 hdmi_msk_reg(hdmi_dev, VP_PR_CD,
 736                              m_COLOR_DEPTH, v_COLOR_DEPTH(color_depth));
 737         }
 738
 739         /*Config pixel repettion*/
 740         hdmi_msk_reg(hdmi_dev, VP_PR_CD, m_DESIRED_PR_FACTOR,
 741                      v_DESIRED_PR_FACTOR(hdmi_dev->pixelrepeat - 1));
 742         if (hdmi_dev->pixelrepeat > 1)
 743                 hdmi_msk_reg(hdmi_dev, VP_CONF,
 744                              m_PIXEL_REPET_EN | m_BYPASS_SEL,
 745                              v_PIXEL_REPET_EN(1) | v_BYPASS_SEL(0));
 746         else
 747                 hdmi_msk_reg(hdmi_dev, VP_CONF,
 748                              m_PIXEL_REPET_EN | m_BYPASS_SEL,
 749                              v_PIXEL_REPET_EN(0) | v_BYPASS_SEL(1));
 750
 751         /*config output select*/
 752         if (output_select == OUT_FROM_PIXEL_PACKING) { /* pixel packing */
 753                 hdmi_msk_reg(hdmi_dev, VP_CONF,
 754                              m_BYPASS_EN | m_PIXEL_PACK_EN |
 755                              m_YCC422_EN | m_OUTPUT_SEL,
 756                              v_BYPASS_EN(0) | v_PIXEL_PACK_EN(1) |
 757                              v_YCC422_EN(0) | v_OUTPUT_SEL(output_select));
 758         } else if (output_select == OUT_FROM_YCC422_REMAP) { /* YCC422 */
 759                 hdmi_msk_reg(hdmi_dev, VP_CONF,
 760                              m_BYPASS_EN | m_PIXEL_PACK_EN |
 761                              m_YCC422_EN | m_OUTPUT_SEL,
 762                              v_BYPASS_EN(0) | v_PIXEL_PACK_EN(0) |
 763                              v_YCC422_EN(1) | v_OUTPUT_SEL(output_select));
 764         } else if (output_select == OUT_FROM_8BIT_BYPASS ||
 765                    output_select == 3) { /* bypass */
 766                 hdmi_msk_reg(hdmi_dev, VP_CONF,
 767                              m_BYPASS_EN | m_PIXEL_PACK_EN |
 768                              m_YCC422_EN | m_OUTPUT_SEL,
 769                              v_BYPASS_EN(1) | v_PIXEL_PACK_EN(0) |
 770                              v_YCC422_EN(0) | v_OUTPUT_SEL(output_select));
 771         }
 772
 773 #if defined(HDMI_VIDEO_STUFFING)
 774         /* YCC422 and pixel packing stuffing*/
 775         hdmi_msk_reg(hdmi_dev, VP_STUFF, m_PR_STUFFING, v_PR_STUFFING(1));
 776         hdmi_msk_reg(hdmi_dev, VP_STUFF,
 777                      m_YCC422_STUFFING | m_PP_STUFFING,
 778                      v_YCC422_STUFFING(1) | v_PP_STUFFING(1));
 779 #endif
 780         return 0;
 781 }
 782
 783 static int rockchip_hdmiv2_video_sampler(struct hdmi_dev *hdmi_dev,
 784                                          struct hdmi_video *vpara)
 785 {
 786         int map_code = 0;
 787
 788         if (vpara->color_input == HDMI_COLOR_YCBCR422) {
 789                 /* YCC422 mapping is discontinued - only map 1 is supported */
 790                 switch (vpara->color_output_depth) {
 791                 case 8:
 792                         map_code = VIDEO_YCBCR422_8BIT;
 793                         break;
 794                 case 10:
 795                         map_code = VIDEO_YCBCR422_10BIT;
 796                         break;
 797                 case 12:
 798                         map_code = VIDEO_YCBCR422_12BIT;
 799                         break;
 800                 default:
 801                         map_code = VIDEO_YCBCR422_8BIT;
 802                         break;
 803                 }
 804         } else if (vpara->color_input == HDMI_COLOR_YCBCR420 ||
 805                    vpara->color_input == HDMI_COLOR_YCBCR444) {
 806                 switch (vpara->color_output_depth) {
 807                 case 10:
 808                         map_code = VIDEO_YCBCR444_10BIT;
 809                         break;
 810                 case 12:
 811                         map_code = VIDEO_YCBCR444_12BIT;
 812                         break;
 813                 case 16:
 814                         map_code = VIDEO_YCBCR444_16BIT;
 815                         break;
 816                 case 8:
 817                 default:
 818                         map_code = VIDEO_YCBCR444_8BIT;
 819                         break;
 820                 }
 821         } else {
 822                 switch (vpara->color_output_depth) {
 823                 case 10:
 824                         map_code = VIDEO_RGB444_10BIT;
 825                         break;
 826                 case 12:
 827                         map_code = VIDEO_RGB444_12BIT;
 828                         break;
 829                 case 16:
 830                         map_code = VIDEO_RGB444_16BIT;
 831                         break;
 832                 case 8:
 833                 default:
 834                         map_code = VIDEO_RGB444_8BIT;
 835                         break;
 836                 }
 837                 map_code += (vpara->color_input == HDMI_COLOR_YCBCR444) ?
 838                             8 : 0;
 839         }
 840
 841         /* Set Data enable signal from external
 842            and set video sample input mapping */
 843         hdmi_msk_reg(hdmi_dev, TX_INVID0,
 844                      m_INTERNAL_DE_GEN | m_VIDEO_MAPPING,
 845                      v_INTERNAL_DE_GEN(0) | v_VIDEO_MAPPING(map_code));
 846
 847 #if defined(HDMI_VIDEO_STUFFING)
 848         hdmi_writel(hdmi_dev, TX_GYDATA0, 0x00);
 849         hdmi_writel(hdmi_dev, TX_GYDATA1, 0x00);
 850         hdmi_msk_reg(hdmi_dev, TX_INSTUFFING,
 851                      m_GYDATA_STUFF, v_GYDATA_STUFF(1));
 852         hdmi_writel(hdmi_dev, TX_RCRDATA0, 0x00);
 853         hdmi_writel(hdmi_dev, TX_RCRDATA1, 0x00);
 854         hdmi_msk_reg(hdmi_dev, TX_INSTUFFING,
 855                      m_RCRDATA_STUFF, v_RCRDATA_STUFF(1));
 856         hdmi_writel(hdmi_dev, TX_BCBDATA0, 0x00);
 857         hdmi_writel(hdmi_dev, TX_BCBDATA1, 0x00);
 858         hdmi_msk_reg(hdmi_dev, TX_INSTUFFING,
 859                      m_BCBDATA_STUFF, v_BCBDATA_STUFF(1));
 860 #endif
 861         return 0;
 862 }
 863
 864 static const char coeff_csc[][24] = {
 865                 /*   G          R           B           Bias
 866                      A1    |    A2     |    A3     |    A4    |
 867                      B1    |    B2     |    B3     |    B4    |
 868                      C1    |    C2     |    C3     |    C4    | */
 869         {       /* CSC_RGB_0_255_TO_RGB_16_235_8BIT */
 870                 0x36, 0xf7, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40,         /*G*/
 871                 0x00, 0x00, 0x36, 0xf7, 0x00, 0x00, 0x00, 0x40,         /*R*/
 872                 0x00, 0x00, 0x00, 0x00, 0x36, 0xf7, 0x00, 0x40,         /*B*/
 873         },
 874         {       /* CSC_RGB_0_255_TO_RGB_16_235_10BIT */
 875                 0x36, 0xf7, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,         /*G*/
 876                 0x00, 0x00, 0x36, 0xf7, 0x00, 0x00, 0x01, 0x00,         /*R*/
 877                 0x00, 0x00, 0x00, 0x00, 0x36, 0xf7, 0x01, 0x00,         /*B*/
 878         },
 879         {       /* CSC_RGB_0_255_TO_ITU601_16_235_8BIT */
 880                 0x20, 0x40, 0x10, 0x80, 0x06, 0x40, 0x00, 0x40,         /*Y*/
 881                 0xe8, 0x80, 0x1c, 0x00, 0xfb, 0x80, 0x02, 0x00,         /*Cr*/
 882                 0xed, 0x80, 0xf6, 0x80, 0x1c, 0x00, 0x02, 0x00,         /*Cb*/
 883         },
 884         {       /* CSC_RGB_0_255_TO_ITU601_16_235_10BIT */
 885                 0x20, 0x40, 0x10, 0x80, 0x06, 0x40, 0x01, 0x00,         /*Y*/
 886                 0xe8, 0x80, 0x1c, 0x00, 0xfb, 0x80, 0x08, 0x00,         /*Cr*/
 887                 0xed, 0x80, 0xf6, 0x80, 0x1c, 0x00, 0x08, 0x00,         /*Cb*/
 888         },
 889         {       /* CSC_RGB_0_255_TO_ITU709_16_235_8BIT */
 890                 0x27, 0x40, 0x0b, 0xc0, 0x04, 0x00, 0x00, 0x40,         /*Y*/
 891                 0xe6, 0x80, 0x1c, 0x00, 0xfd, 0x80, 0x02, 0x00,         /*Cr*/
 892                 0xea, 0x40, 0xf9, 0x80, 0x1c, 0x00, 0x02, 0x00,         /*Cb*/
 893         },
 894         {       /* CSC_RGB_0_255_TO_ITU709_16_235_10BIT */
 895                 0x27, 0x40, 0x0b, 0xc0, 0x04, 0x00, 0x01, 0x00,         /*Y*/
 896                 0xe6, 0x80, 0x1c, 0x00, 0xfd, 0x80, 0x08, 0x00,         /*Cr*/
 897                 0xea, 0x40, 0xf9, 0x80, 0x1c, 0x00, 0x08, 0x00,         /*Cb*/
 898         },
 899                 /* Y            Cr          Cb          Bias */
 900         {       /* CSC_ITU601_16_235_TO_RGB_0_255_8BIT */
 901                 0x20, 0x00, 0x69, 0x26, 0x74, 0xfd, 0x01, 0x0e,         /*G*/
 902                 0x20, 0x00, 0x2c, 0xdd, 0x00, 0x00, 0x7e, 0x9a,         /*R*/
 903                 0x20, 0x00, 0x00, 0x00, 0x38, 0xb4, 0x7e, 0x3b,         /*B*/
 904         },
 905         {       /* CSC_ITU709_16_235_TO_RGB_0_255_8BIT */
 906                 0x20, 0x00, 0x71, 0x06, 0x7a, 0x02, 0x00, 0xa7,         /*G*/
 907                 0x20, 0x00, 0x32, 0x64, 0x00, 0x00, 0x7e, 0x6d,         /*R*/
 908                 0x20, 0x00, 0x00, 0x00, 0x3b, 0x61, 0x7e, 0x25,         /*B*/
 909         },
 910 };
 911
 912 static int rockchip_hdmiv2_video_csc(struct hdmi_dev *hdmi_dev,
 913                                      struct hdmi_video *vpara)
 914 {
 915         int i, mode, interpolation, decimation, csc_scale;
 916         const char *coeff = NULL;
 917         unsigned char color_depth = 0;
 918
 919         if (vpara->color_input == vpara->color_output) {
 920                 hdmi_msk_reg(hdmi_dev, MC_FLOWCTRL,
 921                              m_FEED_THROUGH_OFF, v_FEED_THROUGH_OFF(0));
 922                 return 0;
 923         }
 924
 925         if (vpara->color_input == HDMI_COLOR_YCBCR422 &&
 926             vpara->color_output != HDMI_COLOR_YCBCR422 &&
 927             vpara->color_output != HDMI_COLOR_YCBCR420) {
 928                 interpolation = 1;
 929                 hdmi_msk_reg(hdmi_dev, CSC_CFG,
 930                              m_CSC_INTPMODE, v_CSC_INTPMODE(interpolation));
 931         }
 932
 933         if ((vpara->color_input == HDMI_COLOR_RGB_0_255 ||
 934              vpara->color_input == HDMI_COLOR_YCBCR444) &&
 935              vpara->color_output == HDMI_COLOR_YCBCR422) {
 936                 decimation = 1;
 937                 hdmi_msk_reg(hdmi_dev, CSC_CFG,
 938                              m_CSC_DECIMODE, v_CSC_DECIMODE(decimation));
 939         }
 940
 941         switch (vpara->vic) {
 942         case HDMI_720X480I_60HZ_4_3:
 943         case HDMI_720X576I_50HZ_4_3:
 944         case HDMI_720X480P_60HZ_4_3:
 945         case HDMI_720X576P_50HZ_4_3:
 946         case HDMI_720X480I_60HZ_16_9:
 947         case HDMI_720X576I_50HZ_16_9:
 948         case HDMI_720X480P_60HZ_16_9:
 949         case HDMI_720X576P_50HZ_16_9:
 950                 if (vpara->color_input == HDMI_COLOR_RGB_0_255 &&
 951                     vpara->color_output >= HDMI_COLOR_YCBCR444) {
 952                         mode = CSC_RGB_0_255_TO_ITU601_16_235_8BIT;
 953                         csc_scale = 0;
 954                 } else if (vpara->color_input >= HDMI_COLOR_YCBCR444 &&
 955                            vpara->color_output == HDMI_COLOR_RGB_0_255) {
 956                         mode = CSC_ITU601_16_235_TO_RGB_0_255_8BIT;
 957                         csc_scale = 1;
 958                 }
 959                 break;
 960         default:
 961                 if (vpara->color_input == HDMI_COLOR_RGB_0_255 &&
 962                     vpara->color_output >= HDMI_COLOR_YCBCR444) {
 963                         mode = CSC_RGB_0_255_TO_ITU709_16_235_8BIT;
 964                         csc_scale = 0;
 965                 } else if (vpara->color_input >= HDMI_COLOR_YCBCR444 &&
 966                            vpara->color_output == HDMI_COLOR_RGB_0_255) {
 967                         mode = CSC_ITU709_16_235_TO_RGB_0_255_8BIT;
 968                         csc_scale = 1;
 969                 }
 970                 break;
 971         }
 972
 973         if ((vpara->color_input == HDMI_COLOR_RGB_0_255) &&
 974             (vpara->color_output == HDMI_COLOR_RGB_16_235)) {
 975                 mode = CSC_RGB_0_255_TO_RGB_16_235_8BIT;
 976                 csc_scale = 0;
 977         }
 978
 979         switch (vpara->color_output_depth) {
 980         case 10:
 981                 color_depth = COLOR_DEPTH_30BIT;
 982                 mode += 1;
 983                 break;
 984         case 12:
 985                 color_depth = COLOR_DEPTH_36BIT;
 986                 mode += 2;
 987                 break;
 988         case 16:
 989                 color_depth = COLOR_DEPTH_48BIT;
 990                 mode += 3;
 991                 break;
 992         case 8:
 993         default:
 994                 color_depth = COLOR_DEPTH_24BIT;
 995                 break;
 996         }
 997
 998         coeff = coeff_csc[mode];
 999         for (i = 0; i < 24; i++)
1000                 hdmi_writel(hdmi_dev, CSC_COEF_A1_MSB + i, coeff[i]);
1001
1002         hdmi_msk_reg(hdmi_dev, CSC_SCALE,
1003                      m_CSC_SCALE, v_CSC_SCALE(csc_scale));
1004         /*config CSC_COLOR_DEPTH*/
1005         hdmi_msk_reg(hdmi_dev, CSC_SCALE,
1006                      m_CSC_COLOR_DEPTH, v_CSC_COLOR_DEPTH(color_depth));
1007
1008         /* enable CSC */
1009         hdmi_msk_reg(hdmi_dev, MC_FLOWCTRL,
1010                      m_FEED_THROUGH_OFF, v_FEED_THROUGH_OFF(1));
1011
1012         return 0;
1013 }
1014
1015
1016 static int hdmi_dev_detect_hotplug(struct hdmi *hdmi)
1017 {
1018         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1019         u32 value = hdmi_readl(hdmi_dev, PHY_STAT0);
1020
1021         HDMIDBG("[%s] reg%x value %02x\n", __func__, PHY_STAT0, value);
1022
1023         if (value & m_PHY_HPD)
1024                 return HDMI_HPD_ACTIVED;
1025         else
1026                 return HDMI_HPD_REMOVED;
1027 }
1028
1029 static int hdmi_dev_read_edid(struct hdmi *hdmi, int block, unsigned char *buff)
1030 {
1031         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1032         int i = 0, n = 0, index = 0, ret = -1, trytime = 5;
1033         int offset = (block % 2) * 0x80;
1034         int interrupt = 0;
1035
1036         HDMIDBG("[%s] block %d\n", __func__, block);
1037
1038         rockchip_hdmiv2_i2cm_reset(hdmi_dev);
1039
1040         /* Set DDC I2C CLK which devided from DDC_CLK to 100KHz. */
1041         rockchip_hdmiv2_i2cm_clk_init(hdmi_dev);
1042
1043         /* Enable I2C interrupt for reading edid */
1044         rockchip_hdmiv2_i2cm_mask_int(hdmi_dev, 0);
1045
1046         hdmi_writel(hdmi_dev, I2CM_SLAVE, DDC_I2C_EDID_ADDR);
1047         hdmi_writel(hdmi_dev, I2CM_SEGADDR, DDC_I2C_SEG_ADDR);
1048         hdmi_writel(hdmi_dev, I2CM_SEGPTR, block / 2);
1049         for (n = 0; n < HDMI_EDID_BLOCK_SIZE / 8; n++) {
1050                 for (trytime = 0; trytime < 5; trytime++) {
1051                         hdmi_writel(hdmi_dev, I2CM_ADDRESS, offset + 8 * n);
1052                         /* enable extend sequential read operation */
1053                         if (block == 0)
1054                                 hdmi_msk_reg(hdmi_dev, I2CM_OPERATION,
1055                                              m_I2CM_RD8, v_I2CM_RD8(1));
1056                         else
1057                                 hdmi_msk_reg(hdmi_dev, I2CM_OPERATION,
1058                                              m_I2CM_RD8_EXT,
1059                                              v_I2CM_RD8_EXT(1));
1060
1061                         i = 20;
1062                         while (i--) {
1063                                 usleep_range(900, 1000);
1064                                 interrupt = hdmi_readl(hdmi_dev,
1065                                                        IH_I2CM_STAT0);
1066                                 if (interrupt)
1067                                         hdmi_writel(hdmi_dev,
1068                                                     IH_I2CM_STAT0, interrupt);
1069
1070                                 if (interrupt &
1071                                     (m_SCDC_READREQ | m_I2CM_DONE |
1072                                      m_I2CM_ERROR))
1073                                         break;
1074                         }
1075
1076                         if (interrupt & m_I2CM_DONE) {
1077                                 for (index = 0; index < 8; index++)
1078                                         buff[8 * n + index] =
1079                                                 hdmi_readl(hdmi_dev,
1080                                                            I2CM_READ_BUFF0 +
1081                                                            index);
1082
1083                                 if (n == HDMI_EDID_BLOCK_SIZE / 8 - 1) {
1084                                         ret = 0;
1085                                         goto exit;
1086                                 }
1087                                 break;
1088                         } else if ((interrupt & m_I2CM_ERROR) || (i == -1)) {
1089                                 dev_err(hdmi->dev,
1090                                         "[%s] edid read %d error\n",
1091                                         __func__, offset + 8 * n);
1092                         }
1093                 }
1094                 if (trytime == 5) {
1095                         dev_err(hdmi->dev,
1096                                 "[%s] edid read error\n", __func__);
1097                         break;
1098                 }
1099         }
1100
1101 exit:
1102         /* Disable I2C interrupt */
1103         rockchip_hdmiv2_i2cm_mask_int(hdmi_dev, 1);
1104         return ret;
1105 }
1106
1107 static void hdmi_dev_config_avi(struct hdmi_dev *hdmi_dev,
1108                                 struct hdmi_video *vpara)
1109 {
1110         unsigned char colorimetry, ext_colorimetry, aspect_ratio, y1y0;
1111         unsigned char rgb_quan_range = AVI_QUANTIZATION_RANGE_DEFAULT;
1112
1113         /* Set AVI infoFrame Data byte1 */
1114         if (vpara->color_output == HDMI_COLOR_YCBCR444)
1115                 y1y0 = AVI_COLOR_MODE_YCBCR444;
1116         else if (vpara->color_output == HDMI_COLOR_YCBCR422)
1117                 y1y0 = AVI_COLOR_MODE_YCBCR422;
1118         else if (vpara->color_output == HDMI_COLOR_YCBCR420)
1119                 y1y0 = AVI_COLOR_MODE_YCBCR420;
1120         else
1121                 y1y0 = AVI_COLOR_MODE_RGB;
1122
1123         hdmi_msk_reg(hdmi_dev, FC_AVICONF0,
1124                      m_FC_ACTIV_FORMAT | m_FC_RGC_YCC,
1125                      v_FC_RGC_YCC(y1y0) | v_FC_ACTIV_FORMAT(1));
1126
1127         /* Set AVI infoFrame Data byte2 */
1128         switch (vpara->vic) {
1129         case HDMI_720X480I_60HZ_4_3:
1130         case HDMI_720X576I_50HZ_4_3:
1131         case HDMI_720X480P_60HZ_4_3:
1132         case HDMI_720X576P_50HZ_4_3:
1133                 aspect_ratio = AVI_CODED_FRAME_ASPECT_4_3;
1134                 if (vpara->colorimetry == HDMI_COLORIMETRY_NO_DATA)
1135                         colorimetry = AVI_COLORIMETRY_SMPTE_170M;
1136                 break;
1137         case HDMI_720X480I_60HZ_16_9:
1138         case HDMI_720X576I_50HZ_16_9:
1139         case HDMI_720X480P_60HZ_16_9:
1140         case HDMI_720X576P_50HZ_16_9:
1141                 aspect_ratio = AVI_CODED_FRAME_ASPECT_16_9;
1142                 if (vpara->colorimetry == HDMI_COLORIMETRY_NO_DATA)
1143                         colorimetry = AVI_COLORIMETRY_SMPTE_170M;
1144                 break;
1145         default:
1146                 aspect_ratio = AVI_CODED_FRAME_ASPECT_16_9;
1147                 if (vpara->colorimetry == HDMI_COLORIMETRY_NO_DATA)
1148                         colorimetry = AVI_COLORIMETRY_ITU709;
1149         }
1150
1151         if (vpara->colorimetry > HDMI_COLORIMETRY_ITU709) {
1152                 colorimetry = AVI_COLORIMETRY_EXTENDED;
1153                 ext_colorimetry = vpara->colorimetry;
1154         } else if (vpara->color_output == HDMI_COLOR_RGB_16_235 ||
1155                  vpara->color_output == HDMI_COLOR_RGB_0_255) {
1156                 colorimetry = AVI_COLORIMETRY_NO_DATA;
1157                 ext_colorimetry = 0;
1158         } else if (vpara->colorimetry != HDMI_COLORIMETRY_NO_DATA) {
1159                 colorimetry = vpara->colorimetry;
1160         }
1161
1162         hdmi_writel(hdmi_dev, FC_AVICONF1,
1163                     v_FC_COLORIMETRY(colorimetry) |
1164                     v_FC_PIC_ASPEC_RATIO(aspect_ratio) |
1165                     v_FC_ACT_ASPEC_RATIO(ACTIVE_ASPECT_RATE_DEFAULT));
1166
1167         /* Set AVI infoFrame Data byte3 */
1168         hdmi_msk_reg(hdmi_dev, FC_AVICONF2,
1169                      m_FC_EXT_COLORIMETRY | m_FC_QUAN_RANGE,
1170                      v_FC_EXT_COLORIMETRY(ext_colorimetry) |
1171                      v_FC_QUAN_RANGE(rgb_quan_range));
1172
1173         /* Set AVI infoFrame Data byte4 */
1174         if ((vpara->vic > 92 && vpara->vic < 96) || (vpara->vic == 98))
1175                 hdmi_writel(hdmi_dev, FC_AVIVID, 0);
1176         else
1177                 hdmi_writel(hdmi_dev, FC_AVIVID, vpara->vic & 0xff);
1178         /* Set AVI infoFrame Data byte5 */
1179         hdmi_msk_reg(hdmi_dev, FC_AVICONF3, m_FC_YQ | m_FC_CN,
1180                      v_FC_YQ(YQ_LIMITED_RANGE) | v_FC_CN(CN_GRAPHICS));
1181 }
1182
1183 static int hdmi_dev_config_vsi(struct hdmi *hdmi,
1184                                unsigned char vic_3d, unsigned char format)
1185 {
1186         int i = 0, id = 0x000c03;
1187         unsigned char data[3] = {0};
1188
1189         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1190
1191         HDMIDBG("[%s] vic %d format %d.\n", __func__, vic_3d, format);
1192
1193         hdmi_msk_reg(hdmi_dev, FC_DATAUTO0, m_VSD_AUTO, v_VSD_AUTO(0));
1194         hdmi_writel(hdmi_dev, FC_VSDIEEEID2, id & 0xff);
1195         hdmi_writel(hdmi_dev, FC_VSDIEEEID1, (id >> 8) & 0xff);
1196         hdmi_writel(hdmi_dev, FC_VSDIEEEID0, (id >> 16) & 0xff);
1197
1198         data[0] = format << 5;  /* PB4 --HDMI_Video_Format */
1199         switch (format) {
1200         case HDMI_VIDEO_FORMAT_4KX2K:
1201                 data[1] = vic_3d;       /* PB5--HDMI_VIC */
1202                 data[2] = 0;
1203                 break;
1204         case HDMI_VIDEO_FORMAT_3D:
1205                 data[1] = vic_3d << 4;  /* PB5--3D_Structure field */
1206                 data[2] = 0;            /* PB6--3D_Ext_Data field */
1207                 break;
1208         default:
1209                 data[1] = 0;
1210                 data[2] = 0;
1211                 break;
1212         }
1213
1214         for (i = 0; i < 3; i++)
1215                 hdmi_writel(hdmi_dev, FC_VSDPAYLOAD0 + i, data[i]);
1216         hdmi_writel(hdmi_dev, FC_VSDSIZE, 0x6);
1217 /*      if (auto_send) { */
1218         hdmi_writel(hdmi_dev, FC_DATAUTO1, 0);
1219         hdmi_writel(hdmi_dev, FC_DATAUTO2, 0x11);
1220         hdmi_msk_reg(hdmi_dev, FC_DATAUTO0, m_VSD_AUTO, v_VSD_AUTO(1));
1221 /*      }
1222         else {
1223                 hdmi_msk_reg(hdmi_dev, FC_DATMAN, m_VSD_MAN, v_VSD_MAN(1));
1224         }
1225 */
1226         return 0;
1227 }
1228
1229 static int hdmi_dev_config_video(struct hdmi *hdmi, struct hdmi_video *vpara)
1230 {
1231         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1232
1233         HDMIDBG("%s vic %d 3dformat %d color mode %d color depth %d\n",
1234                 __func__, vpara->vic, vpara->format_3d,
1235                 vpara->color_output, vpara->color_output_depth);
1236
1237         if (hdmi_dev->soctype == HDMI_SOC_RK3288)
1238                 vpara->color_input = HDMI_COLOR_RGB_0_255;
1239
1240         if (!hdmi->uboot) {
1241                 /* befor configure video, we power off phy */
1242                 hdmi_msk_reg(hdmi_dev, PHY_CONF0,
1243                              m_PDDQ_SIG | m_TXPWRON_SIG,
1244                              v_PDDQ_SIG(1) | v_TXPWRON_SIG(0));
1245
1246                 /* force output blue */
1247                 if (vpara->color_output == HDMI_COLOR_RGB_0_255) {
1248                         hdmi_writel(hdmi_dev, FC_DBGTMDS2, 0x00);       /*R*/
1249                         hdmi_writel(hdmi_dev, FC_DBGTMDS1, 0x00);       /*G*/
1250                         hdmi_writel(hdmi_dev, FC_DBGTMDS0, 0x00);       /*B*/
1251                 } else if (vpara->color_output == HDMI_COLOR_RGB_16_235) {
1252                         hdmi_writel(hdmi_dev, FC_DBGTMDS2, 0x10);       /*R*/
1253                         hdmi_writel(hdmi_dev, FC_DBGTMDS1, 0x10);       /*G*/
1254                         hdmi_writel(hdmi_dev, FC_DBGTMDS0, 0x10);       /*B*/
1255                 } else {
1256                         hdmi_writel(hdmi_dev, FC_DBGTMDS2, 0x80);       /*R*/
1257                         hdmi_writel(hdmi_dev, FC_DBGTMDS1, 0x10);       /*G*/
1258                         hdmi_writel(hdmi_dev, FC_DBGTMDS0, 0x80);       /*B*/
1259                 }
1260                 hdmi_msk_reg(hdmi_dev, FC_DBGFORCE,
1261                              m_FC_FORCEVIDEO, v_FC_FORCEVIDEO(1));
1262                 hdmi_writel(hdmi_dev, MC_CLKDIS, m_HDCPCLK_DISABLE);
1263         }
1264
1265         if (rockchip_hdmiv2_video_framecomposer(hdmi, vpara) < 0)
1266                 return -1;
1267
1268         if (rockchip_hdmiv2_video_packetizer(hdmi_dev, vpara) < 0)
1269                 return -1;
1270         /* Color space convert */
1271         if (rockchip_hdmiv2_video_csc(hdmi_dev, vpara) < 0)
1272                 return -1;
1273         if (rockchip_hdmiv2_video_sampler(hdmi_dev, vpara) < 0)
1274                 return -1;
1275
1276         if (vpara->sink_hdmi == OUTPUT_HDMI) {
1277                 hdmi_dev_config_avi(hdmi_dev, vpara);
1278                 if (vpara->format_3d != HDMI_3D_NONE) {
1279                         hdmi_dev_config_vsi(hdmi,
1280                                             vpara->format_3d,
1281                                             HDMI_VIDEO_FORMAT_3D);
1282                 } else if ((vpara->vic > 92 && vpara->vic < 96) ||
1283                          (vpara->vic == 98)) {
1284                         vpara->vic = (vpara->vic == 98) ?
1285                                      4 : (96 - vpara->vic);
1286                         hdmi_dev_config_vsi(hdmi,
1287                                             vpara->vic,
1288                                             HDMI_VIDEO_FORMAT_4KX2K);
1289                 } else {
1290                         hdmi_dev_config_vsi(hdmi,
1291                                             vpara->vic,
1292                                             HDMI_VIDEO_FORMAT_NORMAL);
1293                 }
1294                 dev_info(hdmi->dev, "[%s] sucess output HDMI.\n", __func__);
1295         } else {
1296                 dev_info(hdmi->dev, "[%s] sucess output DVI.\n", __func__);
1297         }
1298
1299         if (!hdmi->uboot)
1300                 rockchip_hdmiv2_config_phy(hdmi_dev);
1301         return 0;
1302 }
1303
1304 static void hdmi_dev_config_aai(struct hdmi_dev *hdmi_dev,
1305                                 struct hdmi_audio *audio)
1306 {
1307         /*Refer to CEA861-E Audio infoFrame*/
1308         /*Set both Audio Channel Count and Audio Coding
1309           Type Refer to Stream Head for HDMI*/
1310         hdmi_msk_reg(hdmi_dev, FC_AUDICONF0,
1311                      m_FC_CHN_CNT | m_FC_CODING_TYEP,
1312                      v_FC_CHN_CNT(audio->channel-1) | v_FC_CODING_TYEP(0));
1313
1314         /*Set both Audio Sample Size and Sample Frequency
1315           Refer to Stream Head for HDMI*/
1316         hdmi_msk_reg(hdmi_dev, FC_AUDICONF1,
1317                      m_FC_SAMPLE_SIZE | m_FC_SAMPLE_FREQ,
1318                      v_FC_SAMPLE_SIZE(0) | v_FC_SAMPLE_FREQ(0));
1319
1320         /*Set Channel Allocation*/
1321         hdmi_writel(hdmi_dev, FC_AUDICONF2, 0x00);
1322
1323         /*Set LFEPBL¡¢DOWN-MIX INH and LSV*/
1324         hdmi_writel(hdmi_dev, FC_AUDICONF3, 0x00);
1325 }
1326
1327 static int hdmi_dev_config_audio(struct hdmi *hdmi, struct hdmi_audio *audio)
1328 {
1329         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1330         int word_length = 0, channel = 0, mclk_fs;
1331         unsigned int N = 0, CTS = 0;
1332         int rate = 0;
1333
1334         HDMIDBG("%s\n", __func__);
1335
1336         if (audio->channel < 3)
1337                 channel = I2S_CHANNEL_1_2;
1338         else if (audio->channel < 5)
1339                 channel = I2S_CHANNEL_3_4;
1340         else if (audio->channel < 7)
1341                 channel = I2S_CHANNEL_5_6;
1342         else
1343                 channel = I2S_CHANNEL_7_8;
1344
1345         switch (audio->rate) {
1346         case HDMI_AUDIO_FS_32000:
1347                 mclk_fs = FS_128;
1348                 rate = AUDIO_32K;
1349                 if (hdmi_dev->tmdsclk >= 594000000)
1350                         N = N_32K_HIGHCLK;
1351                 else if (hdmi_dev->tmdsclk >= 297000000)
1352                         N = N_32K_MIDCLK;
1353                 else
1354                         N = N_32K_LOWCLK;
1355                 /*div a num to avoid the value is exceed 2^32(int)*/
1356                 CTS = CALC_CTS(N, hdmi_dev->tmdsclk/1000, 32);
1357                 break;
1358         case HDMI_AUDIO_FS_44100:
1359                 mclk_fs = FS_128;
1360                 rate = AUDIO_441K;
1361                 if (hdmi_dev->tmdsclk >= 594000000)
1362                         N = N_441K_HIGHCLK;
1363                 else if (hdmi_dev->tmdsclk >= 297000000)
1364                         N = N_441K_MIDCLK;
1365                 else
1366                         N = N_441K_LOWCLK;
1367
1368                 CTS = CALC_CTS(N, hdmi_dev->tmdsclk/100, 441);
1369                 break;
1370         case HDMI_AUDIO_FS_48000:
1371                 mclk_fs = FS_128;
1372                 rate = AUDIO_48K;
1373                 if (hdmi_dev->tmdsclk >= 594000000)     /*FS_153.6*/
1374                         N = N_48K_HIGHCLK;
1375                 else if (hdmi_dev->tmdsclk >= 297000000)
1376                         N = N_48K_MIDCLK;
1377                 else
1378                         N = N_48K_LOWCLK;
1379
1380                 CTS = CALC_CTS(N, hdmi_dev->tmdsclk/1000, 48);
1381                 break;
1382         case HDMI_AUDIO_FS_88200:
1383                 mclk_fs = FS_128;
1384                 rate = AUDIO_882K;
1385                 if (hdmi_dev->tmdsclk >= 594000000)
1386                         N = N_882K_HIGHCLK;
1387                 else if (hdmi_dev->tmdsclk >= 297000000)
1388                         N = N_882K_MIDCLK;
1389                 else
1390                         N = N_882K_LOWCLK;
1391
1392                 CTS = CALC_CTS(N, hdmi_dev->tmdsclk/100, 882);
1393                 break;
1394         case HDMI_AUDIO_FS_96000:
1395                 mclk_fs = FS_128;
1396                 rate = AUDIO_96K;
1397                 if (hdmi_dev->tmdsclk >= 594000000)     /*FS_153.6*/
1398                         N = N_96K_HIGHCLK;
1399                 else if (hdmi_dev->tmdsclk >= 297000000)
1400                         N = N_96K_MIDCLK;
1401                 else
1402                         N = N_96K_LOWCLK;
1403
1404                 CTS = CALC_CTS(N, hdmi_dev->tmdsclk/1000, 96);
1405                 break;
1406         case HDMI_AUDIO_FS_176400:
1407                 mclk_fs = FS_128;
1408                 rate = AUDIO_1764K;
1409                 if (hdmi_dev->tmdsclk >= 594000000)
1410                         N = N_1764K_HIGHCLK;
1411                 else if (hdmi_dev->tmdsclk >= 297000000)
1412                         N = N_1764K_MIDCLK;
1413                 else
1414                         N = N_1764K_LOWCLK;
1415
1416                 CTS = CALC_CTS(N, hdmi_dev->tmdsclk/100, 1764);
1417                 break;
1418         case HDMI_AUDIO_FS_192000:
1419                 mclk_fs = FS_128;
1420                 rate = AUDIO_192K;
1421                 if (hdmi_dev->tmdsclk >= 594000000)     /*FS_153.6*/
1422                         N = N_192K_HIGHCLK;
1423                 else if (hdmi_dev->tmdsclk >= 297000000)
1424                         N = N_192K_MIDCLK;
1425                 else
1426                         N = N_192K_LOWCLK;
1427
1428                 CTS = CALC_CTS(N, hdmi_dev->tmdsclk/1000, 192);
1429                 break;
1430         default:
1431                 dev_err(hdmi_dev->hdmi->dev,
1432                         "[%s] not support such sample rate %d\n",
1433                         __func__, audio->rate);
1434                 return -ENOENT;
1435         }
1436
1437         switch (audio->word_length) {
1438         case HDMI_AUDIO_WORD_LENGTH_16bit:
1439                 word_length = I2S_16BIT_SAMPLE;
1440                 break;
1441         case HDMI_AUDIO_WORD_LENGTH_20bit:
1442                 word_length = I2S_20BIT_SAMPLE;
1443                 break;
1444         case HDMI_AUDIO_WORD_LENGTH_24bit:
1445                 word_length = I2S_24BIT_SAMPLE;
1446                 break;
1447         default:
1448                 word_length = I2S_16BIT_SAMPLE;
1449         }
1450
1451         HDMIDBG("rate = %d, tmdsclk = %u, N = %d, CTS = %d\n",
1452                 audio->rate, hdmi_dev->tmdsclk, N, CTS);
1453         /* more than 2 channels => layout 1 else layout 0 */
1454         hdmi_msk_reg(hdmi_dev, FC_AUDSCONF,
1455                      m_AUD_PACK_LAYOUT,
1456                      v_AUD_PACK_LAYOUT((audio->channel > 2) ? 1 : 0));
1457
1458         if (hdmi_dev->audiosrc == HDMI_AUDIO_SRC_SPDIF) {
1459                 mclk_fs = FS_128;
1460                 hdmi_msk_reg(hdmi_dev, AUD_CONF0,
1461                              m_I2S_SEL, v_I2S_SEL(AUDIO_SPDIF_GPA));
1462                 hdmi_msk_reg(hdmi_dev, AUD_SPDIF1,
1463                              m_SET_NLPCM | m_SPDIF_WIDTH,
1464                              v_SET_NLPCM(PCM_LINEAR) |
1465                              v_SPDIF_WIDTH(word_length));
1466                 /*Mask fifo empty and full int and reset fifo*/
1467                 hdmi_msk_reg(hdmi_dev, AUD_SPDIFINT,
1468                              m_FIFO_EMPTY_MASK | m_FIFO_FULL_MASK,
1469                              v_FIFO_EMPTY_MASK(1) | v_FIFO_FULL_MASK(1));
1470                 hdmi_msk_reg(hdmi_dev, AUD_SPDIF0,
1471                              m_SW_SAUD_FIFO_RST, v_SW_SAUD_FIFO_RST(1));
1472         } else {
1473                 /*Mask fifo empty and full int and reset fifo*/
1474                 hdmi_msk_reg(hdmi_dev, AUD_INT,
1475                              m_FIFO_EMPTY_MASK | m_FIFO_FULL_MASK,
1476                              v_FIFO_EMPTY_MASK(1) | v_FIFO_FULL_MASK(1));
1477                 hdmi_msk_reg(hdmi_dev, AUD_CONF0,
1478                              m_SW_AUD_FIFO_RST, v_SW_AUD_FIFO_RST(1));
1479                 hdmi_writel(hdmi_dev, MC_SWRSTZREQ, 0xF7);
1480                 hdmi_writel(hdmi_dev, AUD_CONF2, 0x0);
1481                 usleep_range(90, 100);
1482                 if (I2S_CHANNEL_7_8 == channel) {
1483                         HDMIDBG("hbr mode.\n");
1484                         hdmi_writel(hdmi_dev, AUD_CONF2, 0x1);
1485                         word_length = I2S_24BIT_SAMPLE;
1486                 } else if ((HDMI_AUDIO_FS_48000 == audio->rate) ||
1487                            (HDMI_AUDIO_FS_192000 == audio->rate)) {
1488                         HDMIDBG("nlpcm mode.\n");
1489                         hdmi_writel(hdmi_dev, AUD_CONF2, 0x2);
1490                         word_length = I2S_24BIT_SAMPLE;
1491                 } else {
1492                         hdmi_writel(hdmi_dev, AUD_CONF2, 0x0);
1493                 }
1494                 hdmi_msk_reg(hdmi_dev, AUD_CONF0,
1495                              m_I2S_SEL | m_I2S_IN_EN,
1496                              v_I2S_SEL(AUDIO_I2S) | v_I2S_IN_EN(channel));
1497                 hdmi_writel(hdmi_dev, AUD_CONF1,
1498                             v_I2S_MODE(I2S_STANDARD_MODE) |
1499                             v_I2S_WIDTH(word_length));
1500         }
1501
1502         hdmi_msk_reg(hdmi_dev, AUD_INPUTCLKFS,
1503                      m_LFS_FACTOR, v_LFS_FACTOR(mclk_fs));
1504
1505         /*Set N value*/
1506         hdmi_msk_reg(hdmi_dev, AUD_N3, m_NCTS_ATOMIC_WR, v_NCTS_ATOMIC_WR(1));
1507         /*Set CTS by manual*/
1508         hdmi_msk_reg(hdmi_dev, AUD_CTS3,
1509                      m_N_SHIFT | m_CTS_MANUAL | m_AUD_CTS3,
1510                      v_N_SHIFT(N_SHIFT_1) |
1511                      v_CTS_MANUAL(1) |
1512                      v_AUD_CTS3(CTS >> 16));
1513         hdmi_writel(hdmi_dev, AUD_CTS2, (CTS >> 8) & 0xff);
1514         hdmi_writel(hdmi_dev, AUD_CTS1, CTS & 0xff);
1515
1516         hdmi_msk_reg(hdmi_dev, AUD_N3, m_AUD_N3, v_AUD_N3(N >> 16));
1517         hdmi_writel(hdmi_dev, AUD_N2, (N >> 8) & 0xff);
1518         hdmi_writel(hdmi_dev, AUD_N1, N & 0xff);
1519
1520         /* set channel status register */
1521         hdmi_msk_reg(hdmi_dev, FC_AUDSCHNLS7,
1522                      m_AUDIO_SAMPLE_RATE, v_AUDIO_SAMPLE_RATE(rate));
1523         hdmi_writel(hdmi_dev, FC_AUDSCHNLS8, ((~rate) << 4) | 0x2);
1524
1525         hdmi_msk_reg(hdmi_dev, AUD_CONF0,
1526                      m_SW_AUD_FIFO_RST, v_SW_AUD_FIFO_RST(1));
1527
1528         hdmi_dev_config_aai(hdmi_dev, audio);
1529
1530         return 0;
1531 }
1532
1533 static int hdmi_dev_control_output(struct hdmi *hdmi, int enable)
1534 {
1535         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1536         struct hdmi_video vpara;
1537
1538         HDMIDBG("[%s] %d\n", __func__, enable);
1539         if (enable == HDMI_AV_UNMUTE) {
1540                 hdmi_writel(hdmi_dev, FC_DBGFORCE, 0x00);
1541                 if (hdmi->edid.sink_hdmi == OUTPUT_HDMI)
1542                         hdmi_msk_reg(hdmi_dev, FC_GCP,
1543                                      m_FC_SET_AVMUTE | m_FC_CLR_AVMUTE,
1544                                      v_FC_SET_AVMUTE(0) | v_FC_CLR_AVMUTE(1));
1545         } else {
1546                 if (enable & HDMI_VIDEO_MUTE) {
1547                         hdmi_msk_reg(hdmi_dev, FC_DBGFORCE,
1548                                      m_FC_FORCEVIDEO, v_FC_FORCEVIDEO(1));
1549                         if (hdmi->edid.sink_hdmi == OUTPUT_HDMI) {
1550                                 hdmi_msk_reg(hdmi_dev, FC_GCP,
1551                                              m_FC_SET_AVMUTE |
1552                                              m_FC_CLR_AVMUTE,
1553                                              v_FC_SET_AVMUTE(1) |
1554                                              v_FC_CLR_AVMUTE(0));
1555                                 vpara.vic = hdmi->vic;
1556                                 vpara.color_output = HDMI_COLOR_RGB_0_255;
1557                                 hdmi_dev_config_avi(hdmi_dev, &vpara);
1558                         }
1559                 }
1560 /*              if (enable & HDMI_AUDIO_MUTE) {
1561                         hdmi_msk_reg(hdmi_dev, FC_AUDSCONF,
1562                                      m_AUD_PACK_SAMPFIT,
1563                                      v_AUD_PACK_SAMPFIT(0x0F));
1564                 }
1565 */              if (enable == (HDMI_VIDEO_MUTE | HDMI_AUDIO_MUTE)) {
1566                         msleep(100);
1567                         if (hdmi->ops->hdcp_power_off_cb)
1568                                 hdmi->ops->hdcp_power_off_cb(hdmi);
1569                         rockchip_hdmiv2_powerdown(hdmi_dev);
1570                         hdmi_dev->tmdsclk = 0;
1571 /*
1572                         hdmi_msk_reg(hdmi_dev, PHY_CONF0,
1573                                      m_PDDQ_SIG | m_TXPWRON_SIG,
1574                                      v_PDDQ_SIG(1) | v_TXPWRON_SIG(0));
1575                         hdmi_writel(hdmi_dev, MC_CLKDIS, 0x7f);
1576 */              }
1577         }
1578         return 0;
1579 }
1580
1581 static int hdmi_dev_insert(struct hdmi *hdmi)
1582 {
1583         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1584
1585         HDMIDBG("%s\n", __func__);
1586         if (!hdmi->uboot)
1587                 hdmi_writel(hdmi_dev, MC_CLKDIS, m_HDCPCLK_DISABLE);
1588         return HDMI_ERROR_SUCESS;
1589 }
1590
1591 static int hdmi_dev_remove(struct hdmi *hdmi)
1592 {
1593         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1594
1595         HDMIDBG("%s\n", __func__);
1596         if (hdmi->ops->hdcp_power_off_cb)
1597                 hdmi->ops->hdcp_power_off_cb(hdmi);
1598         rockchip_hdmiv2_powerdown(hdmi_dev);
1599         hdmi_dev->tmdsclk = 0;
1600         return HDMI_ERROR_SUCESS;
1601 }
1602
1603 static int hdmi_dev_enable(struct hdmi *hdmi)
1604 {
1605         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1606
1607         HDMIDBG("%s\n", __func__);
1608         if (!hdmi_dev->enable) {
1609                 hdmi_writel(hdmi_dev, IH_MUTE, 0x00);
1610                 hdmi_dev->enable = 1;
1611         }
1612         hdmi_submit_work(hdmi, HDMI_HPD_CHANGE, 10, 0);
1613         return 0;
1614 }
1615
1616 static int hdmi_dev_disable(struct hdmi *hdmi)
1617 {
1618         struct hdmi_dev *hdmi_dev = hdmi->property->priv;
1619
1620         HDMIDBG("%s\n", __func__);
1621         if (hdmi_dev->enable) {
1622                 hdmi_dev->enable = 0;
1623                 hdmi_writel(hdmi_dev, IH_MUTE, 0x1);
1624         }
1625         return 0;
1626 }
1627
1628 void rockchip_hdmiv2_dev_init_ops(struct hdmi_ops *ops)
1629 {
1630         if (ops) {
1631                 ops->enable     = hdmi_dev_enable;
1632                 ops->disable    = hdmi_dev_disable;
1633                 ops->getstatus  = hdmi_dev_detect_hotplug;
1634                 ops->insert     = hdmi_dev_insert;
1635                 ops->remove     = hdmi_dev_remove;
1636                 ops->getedid    = hdmi_dev_read_edid;
1637                 ops->setvideo   = hdmi_dev_config_video;
1638                 ops->setaudio   = hdmi_dev_config_audio;
1639                 ops->setmute    = hdmi_dev_control_output;
1640                 ops->setvsi     = hdmi_dev_config_vsi;
1641         }
1642 }
1643
1644 void rockchip_hdmiv2_dev_initial(struct hdmi_dev *hdmi_dev)
1645 {
1646         struct hdmi *hdmi = hdmi_dev->hdmi;
1647
1648         if (!hdmi->uboot) {
1649                 /* reset hdmi */
1650                 if (hdmi_dev->soctype == HDMI_SOC_RK3288) {
1651                         writel_relaxed((1 << 9) | (1 << 25),
1652                                        RK_CRU_VIRT + 0x01d4);
1653                         udelay(1);
1654                         writel_relaxed((0 << 9) | (1 << 25),
1655                                        RK_CRU_VIRT + 0x01d4);
1656                 } else if (hdmi_dev->soctype == HDMI_SOC_RK3368) {
1657                         pr_info("reset hdmi\n");
1658                         regmap_write(hdmi_dev->grf_base, 0x031c,
1659                                      (1 << 9) | (1 << 25));
1660                         udelay(5);
1661                         regmap_write(hdmi_dev->grf_base, 0x031c,
1662                                      (0 << 9) | (1 << 25));
1663                 }
1664                 rockchip_hdmiv2_powerdown(hdmi_dev);
1665         }
1666         /*mute unnecessary interrrupt, only enable hpd*/
1667         hdmi_writel(hdmi_dev, IH_MUTE_FC_STAT0, 0xff);
1668         hdmi_writel(hdmi_dev, IH_MUTE_FC_STAT1, 0xff);
1669         hdmi_writel(hdmi_dev, IH_MUTE_FC_STAT2, 0xff);
1670         hdmi_writel(hdmi_dev, IH_MUTE_AS_STAT0, 0xff);
1671         hdmi_writel(hdmi_dev, IH_MUTE_PHY_STAT0, 0xfe);
1672         hdmi_writel(hdmi_dev, IH_MUTE_I2CM_STAT0, 0xff);
1673         hdmi_writel(hdmi_dev, IH_MUTE_CEC_STAT0, 0xff);
1674         hdmi_writel(hdmi_dev, IH_MUTE_VP_STAT0, 0xff);
1675         hdmi_writel(hdmi_dev, IH_MUTE_I2CMPHY_STAT0, 0xff);
1676         hdmi_writel(hdmi_dev, IH_MUTE_AHBDMAAUD_STAT0, 0xff);
1677
1678         /* disable hdcp interrup */
1679         hdmi_writel(hdmi_dev, A_APIINTMSK, 0xff);
1680         hdmi_writel(hdmi_dev, PHY_MASK, 0xf1);
1681
1682         if (hdmi->property->feature & SUPPORT_CEC)
1683                 rockchip_hdmiv2_cec_init(hdmi);
1684         if (hdmi->property->feature & SUPPORT_HDCP)
1685                 rockchip_hdmiv2_hdcp_init(hdmi);
1686 }
1687
1688 irqreturn_t rockchip_hdmiv2_dev_irq(int irq, void *priv)
1689 {
1690         struct hdmi_dev *hdmi_dev = priv;
1691         struct hdmi *hdmi = hdmi_dev->hdmi;
1692         char phy_pol = hdmi_readl(hdmi_dev, PHY_POL0);
1693         char phy_status = hdmi_readl(hdmi_dev, PHY_STAT0);
1694         char phy_int0 = hdmi_readl(hdmi_dev, PHY_INI0);
1695         /*read interrupt*/
1696         char fc_stat0 = hdmi_readl(hdmi_dev, IH_FC_STAT0);
1697         char fc_stat1 = hdmi_readl(hdmi_dev, IH_FC_STAT1);
1698         char fc_stat2 = hdmi_readl(hdmi_dev, IH_FC_STAT2);
1699         char aud_int = hdmi_readl(hdmi_dev, IH_AS_SATA0);
1700         char phy_int = hdmi_readl(hdmi_dev, IH_PHY_STAT0);
1701         char vp_stat0 = hdmi_readl(hdmi_dev, IH_VP_STAT0);
1702         char cec_int = hdmi_readl(hdmi_dev, IH_CEC_STAT0);
1703         char hdcp_int = hdmi_readl(hdmi_dev, A_APIINTSTAT);
1704         char hdcp2_int = hdmi_readl(hdmi_dev, HDCP2REG_STAT);
1705
1706         /*clear interrupt*/
1707         hdmi_writel(hdmi_dev, IH_FC_STAT0, fc_stat0);
1708         hdmi_writel(hdmi_dev, IH_FC_STAT1, fc_stat1);
1709         hdmi_writel(hdmi_dev, IH_FC_STAT2, fc_stat2);
1710         hdmi_writel(hdmi_dev, IH_VP_STAT0, vp_stat0);
1711
1712         if (phy_int0 || phy_int) {
1713                 phy_pol = (phy_int0 & (~phy_status)) | ((~phy_int0) & phy_pol);
1714                 hdmi_writel(hdmi_dev, PHY_POL0, phy_pol);
1715                 hdmi_writel(hdmi_dev, IH_PHY_STAT0, phy_int);
1716                 if ((phy_int & m_HPD) || ((phy_int & 0x3c) == 0x3c))
1717                         hdmi_submit_work(hdmi, HDMI_HPD_CHANGE, 20, 0);
1718         }
1719
1720         /* Audio error */
1721         if (aud_int) {
1722                 hdmi_writel(hdmi_dev, IH_AS_SATA0, aud_int);
1723                 hdmi_msk_reg(hdmi_dev, AUD_CONF0,
1724                              m_SW_AUD_FIFO_RST, v_SW_AUD_FIFO_RST(1));
1725                 hdmi_writel(hdmi_dev, MC_SWRSTZREQ, 0xF7);
1726         }
1727         /* CEC */
1728         if (cec_int) {
1729                 hdmi_writel(hdmi_dev, IH_CEC_STAT0, cec_int);
1730                 rockchip_hdmiv2_cec_isr(hdmi_dev, cec_int);
1731         }
1732         /* HDCP */
1733         if (hdcp_int) {
1734                 hdmi_writel(hdmi_dev, A_APIINTCLR, hdcp_int);
1735                 rockchip_hdmiv2_hdcp_isr(hdmi_dev, hdcp_int);
1736         }
1737
1738         /* HDCP2 */
1739         if (hdcp2_int) {
1740                 hdmi_writel(hdmi_dev, HDCP2REG_STAT, hdcp2_int);
1741                 pr_info("hdcp2_int is 0x%02x\n", hdcp2_int);
1742                 if ((hdcp2_int & m_HDCP2_AUTH_FAIL ||
1743                      hdcp2_int & m_HDCP2_AUTH_LOST) &&
1744                     hdmi_dev->hdcp2_start) {
1745                         pr_info("hdcp2 failed or lost\n");
1746                         hdmi_dev->hdcp2_start();
1747                 }
1748         }
1749         return IRQ_HANDLED;
1750 }