3 #include "hw_iep_config_addr.h"
\r
7 //#include "typedef.h"
\r
10 uint32_t reserved0 : 1;
\r
11 uint32_t scl_sts : 1;
\r
12 uint32_t dil_sts : 1;
\r
13 uint32_t reserved1 : 1;
\r
14 uint32_t wyuv_sts : 1;
\r
15 uint32_t ryuv_sts : 1;
\r
16 uint32_t wrgb_sts : 1;
\r
17 uint32_t rrgb_sts : 1;
\r
18 uint32_t voi_sts : 1;
\r
21 #if defined(CONFIG_IEP_MMU)
\r
22 struct iep_mmu_status {
\r
23 uint32_t paging_enabled : 1;
\r
24 uint32_t page_fault_active : 1;
\r
25 uint32_t stall_active : 1;
\r
27 uint32_t replay_buffer_empty : 1;
\r
28 uint32_t page_fault_is_write : 1;
\r
29 uint32_t page_fault_bus_id : 5;
\r
32 struct iep_mmu_int_status {
\r
33 uint32_t page_fault : 1;
\r
34 uint32_t read_bus_error : 1;
\r
43 MMU_PAGE_FAULT_DONE,
\r
48 //Öмä±äÁ¿£¬¼Ä´æÆ÷ÅäÖõØÖ·
\r
49 #define rIEP_CONFIG0 (IEP_BASE+IEP_CONFIG0)
\r
50 #define rIEP_CONFIG1 (IEP_BASE+IEP_CONFIG1)
\r
52 #define rIEP_STATUS (IEP_BASE+IEP_STATUS)
\r
53 #define rIEP_INT (IEP_BASE+IEP_INT)
\r
54 #define rIEP_FRM_START (IEP_BASE+IEP_FRM_START)
\r
55 #define rIEP_SOFT_RST (IEP_BASE+IEP_SOFT_RST)
\r
56 #define rIEP_CONF_DONE (IEP_BASE+IEP_CONF_DONE)
\r
58 #define rIEP_VIR_IMG_WIDTH (IEP_BASE+IEP_VIR_IMG_WIDTH)
\r
60 #define rIEP_IMG_SCL_FCT (IEP_BASE+IEP_IMG_SCL_FCT)
\r
62 #define rIEP_SRC_IMG_SIZE (IEP_BASE+IEP_SRC_IMG_SIZE)
\r
63 #define rIEP_DST_IMG_SIZE (IEP_BASE+IEP_DST_IMG_SIZE)
\r
65 #define rIEP_DST_IMG_WIDTH_TILE0 (IEP_BASE+IEP_DST_IMG_WIDTH_TILE0)
\r
66 #define rIEP_DST_IMG_WIDTH_TILE1 (IEP_BASE+IEP_DST_IMG_WIDTH_TILE1)
\r
67 #define rIEP_DST_IMG_WIDTH_TILE2 (IEP_BASE+IEP_DST_IMG_WIDTH_TILE2)
\r
68 #define rIEP_DST_IMG_WIDTH_TILE3 (IEP_BASE+IEP_DST_IMG_WIDTH_TILE3)
\r
70 #define rIEP_ENH_YUV_CNFG_0 (IEP_BASE+IEP_ENH_YUV_CNFG_0)
\r
71 #define rIEP_ENH_YUV_CNFG_1 (IEP_BASE+IEP_ENH_YUV_CNFG_1)
\r
72 #define rIEP_ENH_YUV_CNFG_2 (IEP_BASE+IEP_ENH_YUV_CNFG_2)
\r
73 #define rIEP_ENH_RGB_CNFG (IEP_BASE+IEP_ENH_RGB_CNFG)
\r
74 #define rIEP_ENH_C_COE (IEP_BASE+IEP_ENH_C_COE)
\r
76 #define rIEP_SRC_ADDR_YRGB (IEP_BASE+IEP_SRC_ADDR_YRGB)
\r
77 #define rIEP_SRC_ADDR_CBCR (IEP_BASE+IEP_SRC_ADDR_CBCR)
\r
78 #define rIEP_SRC_ADDR_CR (IEP_BASE+IEP_SRC_ADDR_CR)
\r
79 #define rIEP_SRC_ADDR_Y1 (IEP_BASE+IEP_SRC_ADDR_Y1)
\r
80 #define rIEP_SRC_ADDR_CBCR1 (IEP_BASE+IEP_SRC_ADDR_CBCR1)
\r
81 #define rIEP_SRC_ADDR_CR1 (IEP_BASE+IEP_SRC_ADDR_CR1)
\r
82 #define rIEP_SRC_ADDR_Y_ITEMP (IEP_BASE+IEP_SRC_ADDR_Y_ITEMP)
\r
83 #define rIEP_SRC_ADDR_CBCR_ITEMP (IEP_BASE+IEP_SRC_ADDR_CBCR_ITEMP)
\r
84 #define rIEP_SRC_ADDR_CR_ITEMP (IEP_BASE+IEP_SRC_ADDR_CR_ITEMP)
\r
85 #define rIEP_SRC_ADDR_Y_FTEMP (IEP_BASE+IEP_SRC_ADDR_Y_FTEMP)
\r
86 #define rIEP_SRC_ADDR_CBCR_FTEMP (IEP_BASE+IEP_SRC_ADDR_CBCR_FTEMP)
\r
87 #define rIEP_SRC_ADDR_CR_FTEMP (IEP_BASE+IEP_SRC_ADDR_CR_FTEMP)
\r
89 #define rIEP_DST_ADDR_YRGB (IEP_BASE+IEP_DST_ADDR_YRGB)
\r
90 #define rIEP_DST_ADDR_CBCR (IEP_BASE+IEP_DST_ADDR_CBCR)
\r
91 #define rIEP_DST_ADDR_CR (IEP_BASE+IEP_DST_ADDR_CR)
\r
92 #define rIEP_DST_ADDR_Y1 (IEP_BASE+IEP_DST_ADDR_Y1)
\r
93 #define rIEP_DST_ADDR_CBCR1 (IEP_BASE+IEP_DST_ADDR_CBCR1)
\r
94 #define rIEP_DST_ADDR_CR1 (IEP_BASE+IEP_DST_ADDR_CR1)
\r
95 #define rIEP_DST_ADDR_Y_ITEMP (IEP_BASE+IEP_DST_ADDR_Y_ITEMP)
\r
96 #define rIEP_DST_ADDR_CBCR_ITEMP (IEP_BASE+IEP_DST_ADDR_CBCR_ITEMP)
\r
97 #define rIEP_DST_ADDR_CR_ITEMP (IEP_BASE+IEP_DST_ADDR_CR_ITEMP)
\r
98 #define rIEP_DST_ADDR_Y_FTEMP (IEP_BASE+IEP_DST_ADDR_Y_FTEMP)
\r
99 #define rIEP_DST_ADDR_CBCR_FTEMP (IEP_BASE+IEP_DST_ADDR_CBCR_FTEMP)
\r
100 #define rIEP_DST_ADDR_CR_FTEMP (IEP_BASE+IEP_DST_ADDR_CR_FTEMP)
\r
102 #define rIEP_DIL_MTN_TAB0 (IEP_BASE+IEP_DIL_MTN_TAB0)
\r
103 #define rIEP_DIL_MTN_TAB1 (IEP_BASE+IEP_DIL_MTN_TAB1)
\r
104 #define rIEP_DIL_MTN_TAB2 (IEP_BASE+IEP_DIL_MTN_TAB2)
\r
105 #define rIEP_DIL_MTN_TAB3 (IEP_BASE+IEP_DIL_MTN_TAB3)
\r
106 #define rIEP_DIL_MTN_TAB4 (IEP_BASE+IEP_DIL_MTN_TAB4)
\r
107 #define rIEP_DIL_MTN_TAB5 (IEP_BASE+IEP_DIL_MTN_TAB5)
\r
108 #define rIEP_DIL_MTN_TAB6 (IEP_BASE+IEP_DIL_MTN_TAB6)
\r
109 #define rIEP_DIL_MTN_TAB7 (IEP_BASE+IEP_DIL_MTN_TAB7)
\r
111 #define rIEP_ENH_CG_TAB (IEP_BASE+IEP_ENH_CG_TAB)
\r
113 #define rIEP_YUV_DNS_CRCT_TEMP (IEP_BASE+IEP_YUV_DNS_CRCT_TEMP)
\r
114 #define rIEP_YUV_DNS_CRCT_SPAT (IEP_BASE+IEP_YUV_DNS_CRCT_SPAT)
\r
116 #define rIEP_ENH_DDE_COE0 (IEP_BASE+IEP_ENH_DDE_COE0)
\r
117 #define rIEP_ENH_DDE_COE1 (IEP_BASE+IEP_ENH_DDE_COE1)
\r
119 #define RAW_rIEP_CONFIG0 (IEP_BASE+RAW_IEP_CONFIG0)
\r
120 #define RAW_rIEP_CONFIG1 (IEP_BASE+RAW_IEP_CONFIG1)
\r
121 #define RAW_rIEP_VIR_IMG_WIDTH (IEP_BASE+RAW_IEP_VIR_IMG_WIDTH)
\r
123 #define RAW_rIEP_IMG_SCL_FCT (IEP_BASE+RAW_IEP_IMG_SCL_FCT)
\r
125 #define RAW_rIEP_SRC_IMG_SIZE (IEP_BASE+RAW_IEP_SRC_IMG_SIZE)
\r
126 #define RAW_rIEP_DST_IMG_SIZE (IEP_BASE+RAW_IEP_DST_IMG_SIZE)
\r
128 #define RAW_rIEP_ENH_YUV_CNFG_0 (IEP_BASE+RAW_IEP_ENH_YUV_CNFG_0)
\r
129 #define RAW_rIEP_ENH_YUV_CNFG_1 (IEP_BASE+RAW_IEP_ENH_YUV_CNFG_1)
\r
130 #define RAW_rIEP_ENH_YUV_CNFG_2 (IEP_BASE+RAW_IEP_ENH_YUV_CNFG_2)
\r
131 #define RAW_rIEP_ENH_RGB_CNFG (IEP_BASE+RAW_IEP_ENH_RGB_CNFG)
\r
133 #define rIEP_CG_TAB_ADDR (IEP_BASE+0x0100)
\r
135 #if defined(CONFIG_IEP_MMU)
\r
136 #define rIEP_MMU_BASE 0x0800
\r
137 #define rIEP_MMU_DTE_ADDR (IEP_MMU_BASE+0x00)
\r
138 #define rIEP_MMU_STATUS (IEP_MMU_BASE+0x04)
\r
139 #define rIEP_MMU_CMD (IEP_MMU_BASE+0x08)
\r
140 #define rIEP_MMU_PAGE_FAULT_ADDR (IEP_MMU_BASE+0x0c)
\r
141 #define rIEP_MMU_ZAP_ONE_LINE (IEP_MMU_BASE+0x10)
\r
142 #define rIEP_MMU_INT_RAWSTAT (IEP_MMU_BASE+0x14)
\r
143 #define rIEP_MMU_INT_CLEAR (IEP_MMU_BASE+0x18)
\r
144 #define rIEP_MMU_INT_MASK (IEP_MMU_BASE+0x1c)
\r
145 #define rIEP_MMU_INT_STATUS (IEP_MMU_BASE+0x20)
\r
146 #define rIEP_MMU_AUTO_GATING (IEP_MMU_BASE+0x24)
\r
149 /*-----------------------------------------------------------------
\r
150 //reg bit operation definition
\r
151 -----------------------------------------------------------------*/
\r
152 /*-----------------------------------------------------------------
\r
153 //MaskRegBits32(addr, y, z),get z£¬Öмä±äÁ¿¡£
\r
154 -----------------------------------------------------------------*/
\r
156 #define IEP_REGB_V_REVERSE_DISP_Z(x) (((x)&0x1 ) << 31 )
\r
157 #define IEP_REGB_H_REVERSE_DISP_Z(x) (((x)&0x1 ) << 30 )
\r
158 #define IEP_REGB_SCL_EN_Z(x) (((x)&0x1 ) << 28 )
\r
159 #define IEP_REGB_SCL_SEL_Z(x) (((x)&0x3 ) << 26 )
\r
160 #define IEP_REGB_SCL_UP_COE_SEL_Z(x) (((x)&0x3 ) << 24 )
\r
161 #define IEP_REGB_DIL_EI_SEL_Z(x) (((x)&0x1 ) << 23 )
\r
162 #define IEP_REGB_DIL_EI_RADIUS_Z(x) (((x)&0x3 ) << 21 )
\r
163 #define IEP_REGB_CON_GAM_ORDER_Z(x) (((x)&0x1 ) << 20 )
\r
164 #define IEP_REGB_RGB_ENH_SEL_Z(x) (((x)&0x3 ) << 18 )
\r
165 #define IEP_REGB_RGB_CON_GAM_EN_Z(x) (((x)&0x1 ) << 17 )
\r
166 #define IEP_REGB_RGB_COLOR_ENH_EN_Z(x) (((x)&0x1 ) << 16 )
\r
167 #define IEP_REGB_DIL_EI_SMOOTH_Z(x) (((x)&0x1 ) << 15 )
\r
168 #define IEP_REGB_YUV_ENH_EN_Z(x) (((x)&0x1 ) << 14 )
\r
169 #define IEP_REGB_YUV_DNS_EN_Z(x) (((x)&0x1 ) << 13 )
\r
170 #define IEP_REGB_DIL_EI_MODE_Z(x) (((x)&0x1 ) << 12 )
\r
171 #define IEP_REGB_DIL_HF_EN_Z(x) (((x)&0x1 ) << 11 )
\r
172 #define IEP_REGB_DIL_MODE_Z(x) (((x)&0x7 ) << 8 )
\r
173 #define IEP_REGB_DIL_HF_FCT_Z(x) (((x)&0x7F) << 1 )
\r
174 #define IEP_REGB_LCDC_PATH_EN_Z(x) (((x)&0x1 ) << 0 )
\r
177 #define IEP_REGB_GLB_ALPHA_Z(x) (((x)&0xff) << 24 )
\r
178 #define IEP_REGB_RGB2YUV_INPUT_CLIP_Z(x) (((x)&0x1 ) << 23 )
\r
179 #define IEP_REGB_YUV2RGB_INPUT_CLIP_Z(x) (((x)&0x1 ) << 22 )
\r
180 #define IEP_REGB_RGB_TO_YUV_EN_Z(x) (((x)&0x1 ) << 21 )
\r
181 #define IEP_REGB_YUV_TO_RGB_EN_Z(x) (((x)&0x1 ) << 20 )
\r
182 #define IEP_REGB_RGB2YUV_COE_SEL_Z(x) (((x)&0x3 ) << 18 )
\r
183 #define IEP_REGB_YUV2RGB_COE_SEL_Z(x) (((x)&0x3 ) << 16 )
\r
184 #define IEP_REGB_DITHER_DOWN_EN_Z(x) (((x)&0x1 ) << 15 )
\r
185 #define IEP_REGB_DITHER_UP_EN_Z(x) (((x)&0x1 ) << 14 )
\r
186 #define IEP_REGB_DST_YUV_SWAP_Z(x) (((x)&0x3 ) << 12 )
\r
187 #define IEP_REGB_DST_RGB_SWAP_Z(x) (((x)&0x3 ) << 10 )
\r
188 #define IEP_REGB_DST_FMT_Z(x) (((x)&0x3 ) << 8 )
\r
189 #define IEP_REGB_SRC_YUV_SWAP_Z(x) (((x)&0x3 ) << 4 )
\r
190 #define IEP_REGB_SRC_RGB_SWAP_Z(x) (((x)&0x3 ) << 2 )
\r
191 #define IEP_REGB_SRC_FMT_Z(x) (((x)&0x3 ) << 0 )
\r
194 #define IEP_REGB_FRAME_END_INT_CLR_Z(x) (((x)&0x1 ) << 16 )
\r
195 #define IEP_REGB_FRAME_END_INT_EN_Z(x) (((x)&0x1 ) << 8 )
\r
198 #define IEP_REGB_FRM_START_Z(x) (((x)&0x01 ) << 0 )
\r
201 #define IEP_REGB_SOFT_RST_Z(x) (((x)&0x01 ) << 0 )
\r
203 //iep_vir_img_width
\r
204 #define IEP_REGB_DST_VIR_LINE_WIDTH_Z(x) (((x)&0xffff) << 16 )
\r
205 #define IEP_REGB_SRC_VIR_LINE_WIDTH_Z(x) (((x)&0xffff) << 0 )
\r
208 #define IEP_REGB_SCL_VRT_FCT_Z(x) (((x)&0xffff) << 16 )
\r
209 #define IEP_REGB_SCL_HRZ_FCT_Z(x) (((x)&0xffff) << 0 )
\r
212 #define IEP_REGB_SRC_IMG_HEIGHT_Z(x) (((x)&0x1fff) << 16 )
\r
213 #define IEP_REGB_SRC_IMG_WIDTH_Z(x) (((x)&0x1fff) << 0 )
\r
215 #define IEP_REGB_DST_IMG_HEIGHT_Z(x) (((x)&0x1fff) << 16 )
\r
216 #define IEP_REGB_DST_IMG_WIDTH_Z(x) (((x)&0x1fff) << 0 )
\r
218 //dst_img_width_tile0/1/2/3
\r
219 #define IEP_REGB_DST_IMG_WIDTH_TILE0_Z(x) (((x)&0x3ff ) << 0 )
\r
220 #define IEP_REGB_DST_IMG_WIDTH_TILE1_Z(x) (((x)&0x3ff ) << 0 )
\r
221 #define IEP_REGB_DST_IMG_WIDTH_TILE2_Z(x) (((x)&0x3ff ) << 0 )
\r
222 #define IEP_REGB_DST_IMG_WIDTH_TILE3_Z(x) (((x)&0x3ff ) << 0 )
\r
224 //iep_enh_yuv_cnfg0
\r
225 #define IEP_REGB_SAT_CON_Z(x) (((x)&0x1ff ) << 16 )
\r
226 #define IEP_REGB_CONTRAST_Z(x) (((x)&0xff ) << 8 )
\r
227 #define IEP_REGB_BRIGHTNESS_Z(x) (((x)&0x3f ) << 0 )
\r
228 //iep_enh_yuv_cnfg1
\r
229 #define IEP_REGB_COS_HUE_Z(x) (((x)&0xff ) << 8 )
\r
230 #define IEP_REGB_SIN_HUE_Z(x) (((x)&0xff ) << 0 )
\r
231 //iep_enh_yuv_cnfg2
\r
232 #define IEP_REGB_VIDEO_MODE_Z(x) (((x)&0x3 ) << 24 )
\r
233 #define IEP_REGB_COLOR_BAR_V_Z(x) (((x)&0xff ) << 16 )
\r
234 #define IEP_REGB_COLOR_BAR_U_Z(x) (((x)&0xff ) << 8 )
\r
235 #define IEP_REGB_COLOR_BAR_Y_Z(x) (((x)&0xff ) << 0 )
\r
237 #define IEP_REGB_ENH_THRESHOLD_Z(x) (((x)&0xff ) << 16 )
\r
238 #define IEP_REGB_ENH_ALPHA_Z(x) (((x)&0x3f ) << 8 )
\r
239 #define IEP_REGB_ENH_RADIUS_Z(x) (((x)&0x3 ) << 0 )
\r
241 #define IEP_REGB_ENH_C_COE_Z(x) (((x)&0x7f ) << 0 )
\r
243 #define IEP_REGB_DIL_MTN_TAB0_0_Z(x) (((x)&0x7f ) << 0 )
\r
244 #define IEP_REGB_DIL_MTN_TAB0_1_Z(x) (((x)&0x7f ) << 8 )
\r
245 #define IEP_REGB_DIL_MTN_TAB0_2_Z(x) (((x)&0x7f ) << 16 )
\r
246 #define IEP_REGB_DIL_MTN_TAB0_3_Z(x) (((x)&0x7f ) << 24 )
\r
248 #define IEP_REGB_DIL_MTN_TAB1_0_Z(x) (((x)&0x7f ) << 0 )
\r
249 #define IEP_REGB_DIL_MTN_TAB1_1_Z(x) (((x)&0x7f ) << 8 )
\r
250 #define IEP_REGB_DIL_MTN_TAB1_2_Z(x) (((x)&0x7f ) << 16 )
\r
251 #define IEP_REGB_DIL_MTN_TAB1_3_Z(x) (((x)&0x7f ) << 24 )
\r
253 #define IEP_REGB_DIL_MTN_TAB2_0_Z(x) (((x)&0x7f ) << 0 )
\r
254 #define IEP_REGB_DIL_MTN_TAB2_1_Z(x) (((x)&0x7f ) << 8 )
\r
255 #define IEP_REGB_DIL_MTN_TAB2_2_Z(x) (((x)&0x7f ) << 16 )
\r
256 #define IEP_REGB_DIL_MTN_TAB2_3_Z(x) (((x)&0x7f ) << 24 )
\r
258 #define IEP_REGB_DIL_MTN_TAB3_0_Z(x) (((x)&0x7f ) << 0 )
\r
259 #define IEP_REGB_DIL_MTN_TAB3_1_Z(x) (((x)&0x7f ) << 8 )
\r
260 #define IEP_REGB_DIL_MTN_TAB3_2_Z(x) (((x)&0x7f ) << 16 )
\r
261 #define IEP_REGB_DIL_MTN_TAB3_3_Z(x) (((x)&0x7f ) << 24 )
\r
263 #define IEP_REGB_DIL_MTN_TAB4_0_Z(x) (((x)&0x7f ) << 0 )
\r
264 #define IEP_REGB_DIL_MTN_TAB4_1_Z(x) (((x)&0x7f ) << 8 )
\r
265 #define IEP_REGB_DIL_MTN_TAB4_2_Z(x) (((x)&0x7f ) << 16 )
\r
266 #define IEP_REGB_DIL_MTN_TAB4_3_Z(x) (((x)&0x7f ) << 24 )
\r
268 #define IEP_REGB_DIL_MTN_TAB5_0_Z(x) (((x)&0x7f ) << 0 )
\r
269 #define IEP_REGB_DIL_MTN_TAB5_1_Z(x) (((x)&0x7f ) << 8 )
\r
270 #define IEP_REGB_DIL_MTN_TAB5_2_Z(x) (((x)&0x7f ) << 16 )
\r
271 #define IEP_REGB_DIL_MTN_TAB5_3_Z(x) (((x)&0x7f ) << 24 )
\r
273 #define IEP_REGB_DIL_MTN_TAB6_0_Z(x) (((x)&0x7f ) << 0 )
\r
274 #define IEP_REGB_DIL_MTN_TAB6_1_Z(x) (((x)&0x7f ) << 8 )
\r
275 #define IEP_REGB_DIL_MTN_TAB6_2_Z(x) (((x)&0x7f ) << 16 )
\r
276 #define IEP_REGB_DIL_MTN_TAB6_3_Z(x) (((x)&0x7f ) << 24 )
\r
278 #define IEP_REGB_DIL_MTN_TAB7_0_Z(x) (((x)&0x7f ) << 0 )
\r
279 #define IEP_REGB_DIL_MTN_TAB7_1_Z(x) (((x)&0x7f ) << 8 )
\r
280 #define IEP_REGB_DIL_MTN_TAB7_2_Z(x) (((x)&0x7f ) << 16 )
\r
281 #define IEP_REGB_DIL_MTN_TAB7_3_Z(x) (((x)&0x7f ) << 24 )
\r
283 #if defined(CONFIG_IEP_MMU)
\r
285 #define IEP_REGB_MMU_STATUS_PAGING_ENABLE_Z(x) (((x)&0x01) << 0)
\r
286 #define IEP_REGB_MMU_STATUS_PAGE_FAULT_ACTIVE_Z(x) (((x)&0x01) << 1)
\r
287 #define IEP_REGB_MMU_STATUS_STALL_ACTIVE_Z(x) (((x)&0x01) << 2)
\r
288 #define IEP_REGB_MMU_STATUS_IDLE_Z(x) (((x)&0x01) << 3)
\r
289 #define IEP_REGB_MMU_STATUS_REPLAY_BUFFER_EMPTY_Z(x) (((x)&0x01) << 4)
\r
290 #define IEP_REGB_MMU_STATUS_PAGE_FAULT_IS_WRITE_Z(x) (((x)&0x01) << 5)
\r
291 #define IEP_REGB_MMU_STATUS_PAGE_FAULT_BUS_ID_Z(x) (((x)&0x1F) << 6)
\r
293 #define IEP_REGB_MMU_CMD_Z(x) (((x)&0x07) << 0)
\r
295 #define IEP_REGB_MMU_ZAP_ONE_LINE_Z(x) (((x)&0x01) << 0)
\r
297 #define IEP_REGB_MMU_INT_RAWSTAT_PAGE_FAULT_Z(x) (((x)&0x01) << 0)
\r
298 #define IEP_REGB_MMU_INT_RAWSTAT_READ_BUS_ERROR_Z(x) (((x)&0x01) << 1)
\r
300 #define IEP_REGB_MMU_INT_CLEAR_PAGE_FAULT_CLEAR_Z(x) (((x)&0x01) << 0)
\r
301 #define IEP_REGB_MMU_INT_CLEAR_READ_BUS_ERROR_CLEAR_Z(x) (((x)&0x01) << 1)
\r
303 #define IEP_REGB_MMU_INT_MASK_PAGE_FAULT_INT_EN_Z(x) (((x)&0x01) << 0)
\r
304 #define IEP_REGB_MMU_INT_MASK_READ_BUS_ERROR_INT_EN_Z(x) (((x)&0x01) << 1)
\r
306 #define IEP_REGB_MMU_INT_STATUS_PAGE_FAULT_Z(x) (((x)&0x01) << 0)
\r
307 #define IEP_REGB_MMU_INT_STATUS_READ_BUS_ERROR_Z(x) (((x)&0x01) << 1)
\r
309 #define IEP_REGB_MMU_AUTO_GATING_Z(x) (((x)&0x01) << 0)
\r
312 /*-----------------------------------------------------------------
\r
313 //MaskRegBits32(addr, y, z),get y£¬Öмä±äÁ¿
\r
314 -----------------------------------------------------------------*/
\r
316 #define IEP_REGB_V_REVERSE_DISP_Y (0x1 << 31 )
\r
317 #define IEP_REGB_H_REVERSE_DISP_Y (0x1 << 30 )
\r
318 #define IEP_REGB_SCL_EN_Y (0x1 << 28 )
\r
319 #define IEP_REGB_SCL_SEL_Y (0x3 << 26 )
\r
320 #define IEP_REGB_SCL_UP_COE_SEL_Y (0x3 << 24 )
\r
321 #define IEP_REGB_DIL_EI_SEL_Y (0x1 << 23 )
\r
322 #define IEP_REGB_DIL_EI_RADIUS_Y (0x3 << 21 )
\r
323 #define IEP_REGB_CON_GAM_ORDER_Y (0x1 << 20 )
\r
324 #define IEP_REGB_RGB_ENH_SEL_Y (0x3 << 18 )
\r
325 #define IEP_REGB_RGB_CON_GAM_EN_Y (0x1 << 17 )
\r
326 #define IEP_REGB_RGB_COLOR_ENH_EN_Y (0x1 << 16 )
\r
327 #define IEP_REGB_DIL_EI_SMOOTH_Y (0x1 << 15 )
\r
328 #define IEP_REGB_YUV_ENH_EN_Y (0x1 << 14 )
\r
329 #define IEP_REGB_YUV_DNS_EN_Y (0x1 << 13 )
\r
330 #define IEP_REGB_DIL_EI_MODE_Y (0x1 << 12 )
\r
331 #define IEP_REGB_DIL_HF_EN_Y (0x1 << 11 )
\r
332 #define IEP_REGB_DIL_MODE_Y (0x7 << 8 )
\r
333 #define IEP_REGB_DIL_HF_FCT_Y (0x7F << 1 )
\r
334 #define IEP_REGB_LCDC_PATH_EN_Y (0x1 << 0 )
\r
337 #define IEP_REGB_GLB_ALPHA_Y (0xff << 24 )
\r
338 #define IEP_REGB_RGB2YUV_INPUT_CLIP_Y (0x1 << 23 )
\r
339 #define IEP_REGB_YUV2RGB_INPUT_CLIP_Y (0x1 << 22 )
\r
340 #define IEP_REGB_RGB_TO_YUV_EN_Y (0x1 << 21 )
\r
341 #define IEP_REGB_YUV_TO_RGB_EN_Y (0x1 << 20 )
\r
342 #define IEP_REGB_RGB2YUV_COE_SEL_Y (0x3 << 18 )
\r
343 #define IEP_REGB_YUV2RGB_COE_SEL_Y (0x3 << 16 )
\r
344 #define IEP_REGB_DITHER_DOWN_EN_Y (0x1 << 15 )
\r
345 #define IEP_REGB_DITHER_UP_EN_Y (0x1 << 14 )
\r
346 #define IEP_REGB_DST_YUV_SWAP_Y (0x3 << 12 )
\r
347 #define IEP_REGB_DST_RGB_SWAP_Y (0x3 << 10 )
\r
348 #define IEP_REGB_DST_FMT_Y (0x3 << 8 )
\r
349 #define IEP_REGB_SRC_YUV_SWAP_Y (0x3 << 4 )
\r
350 #define IEP_REGB_SRC_RGB_SWAP_Y (0x3 << 2 )
\r
351 #define IEP_REGB_SRC_FMT_Y (0x3 << 0 )
\r
354 #define IEP_REGB_FRAME_END_INT_CLR_Y (0x1 << 16 )
\r
355 #define IEP_REGB_FRAME_END_INT_EN_Y (0x1 << 8 )
\r
358 #define IEP_REGB_FRM_START_Y (0x1 << 0 )
\r
361 #define IEP_REGB_SOFT_RST_Y (0x1 << 0 )
\r
363 //iep_vir_img_width
\r
364 #define IEP_REGB_DST_VIR_LINE_WIDTH_Y (0xffff << 16 )
\r
365 #define IEP_REGB_SRC_VIR_LINE_WIDTH_Y (0xffff << 0 )
\r
368 #define IEP_REGB_SCL_VRT_FCT_Y (0xffff << 16 )
\r
369 #define IEP_REGB_SCL_HRZ_FCT_Y (0xffff << 0 )
\r
372 #define IEP_REGB_SRC_IMG_HEIGHT_Y (0x1fff << 16 )
\r
373 #define IEP_REGB_SRC_IMG_WIDTH_Y (0x1fff << 0 )
\r
375 #define IEP_REGB_DST_IMG_HEIGHT_Y (0x1fff << 16 )
\r
376 #define IEP_REGB_DST_IMG_WIDTH_Y (0x1fff << 0 )
\r
378 //dst_img_width_tile0/1/2/3
\r
379 #define IEP_REGB_DST_IMG_WIDTH_TILE0_Y (0x3ff << 0 )
\r
380 #define IEP_REGB_DST_IMG_WIDTH_TILE1_Y (0x3ff << 0 )
\r
381 #define IEP_REGB_DST_IMG_WIDTH_TILE2_Y (0x3ff << 0 )
\r
382 #define IEP_REGB_DST_IMG_WIDTH_TILE3_Y (0x3ff << 0 )
\r
384 //iep_enh_yuv_cnfg0
\r
385 #define IEP_REGB_SAT_CON_Y (0x1ff << 16)
\r
386 #define IEP_REGB_CONTRAST_Y (0xff << 8 )
\r
387 #define IEP_REGB_BRIGHTNESS_Y (0x3f << 0 )
\r
388 //iep_enh_yuv_cnfg1
\r
389 #define IEP_REGB_COS_HUE_Y (0xff << 8 )
\r
390 #define IEP_REGB_SIN_HUE_Y (0xff << 0 )
\r
391 //iep_enh_yuv_cnfg2
\r
392 #define IEP_REGB_VIDEO_MODE_Y (0x3 << 24)
\r
393 #define IEP_REGB_COLOR_BAR_V_Y (0xff << 16)
\r
394 #define IEP_REGB_COLOR_BAR_U_Y (0xff << 8 )
\r
395 #define IEP_REGB_COLOR_BAR_Y_Y (0xff << 0 )
\r
397 #define IEP_REGB_ENH_THRESHOLD_Y (0xff << 16)
\r
398 #define IEP_REGB_ENH_ALPHA_Y (0x3f << 8 )
\r
399 #define IEP_REGB_ENH_RADIUS_Y (0x3 << 0 )
\r
401 #define IEP_REGB_ENH_C_COE_Y (0x7f << 0 )
\r
403 #define IEP_REGB_DIL_MTN_TAB0_0_Y (0x7f << 0 )
\r
404 #define IEP_REGB_DIL_MTN_TAB0_1_Y (0x7f << 8 )
\r
405 #define IEP_REGB_DIL_MTN_TAB0_2_Y (0x7f << 16 )
\r
406 #define IEP_REGB_DIL_MTN_TAB0_3_Y (0x7f << 24 )
\r
408 #define IEP_REGB_DIL_MTN_TAB1_0_Y (0x7f << 0 )
\r
409 #define IEP_REGB_DIL_MTN_TAB1_1_Y (0x7f << 8 )
\r
410 #define IEP_REGB_DIL_MTN_TAB1_2_Y (0x7f << 16 )
\r
411 #define IEP_REGB_DIL_MTN_TAB1_3_Y (0x7f << 24 )
\r
413 #define IEP_REGB_DIL_MTN_TAB2_0_Y (0x7f << 0 )
\r
414 #define IEP_REGB_DIL_MTN_TAB2_1_Y (0x7f << 8 )
\r
415 #define IEP_REGB_DIL_MTN_TAB2_2_Y (0x7f << 16 )
\r
416 #define IEP_REGB_DIL_MTN_TAB2_3_Y (0x7f << 24 )
\r
418 #define IEP_REGB_DIL_MTN_TAB3_0_Y (0x7f << 0 )
\r
419 #define IEP_REGB_DIL_MTN_TAB3_1_Y (0x7f << 8 )
\r
420 #define IEP_REGB_DIL_MTN_TAB3_2_Y (0x7f << 16 )
\r
421 #define IEP_REGB_DIL_MTN_TAB3_3_Y (0x7f << 24 )
\r
423 #define IEP_REGB_DIL_MTN_TAB4_0_Y (0x7f << 0 )
\r
424 #define IEP_REGB_DIL_MTN_TAB4_1_Y (0x7f << 8 )
\r
425 #define IEP_REGB_DIL_MTN_TAB4_2_Y (0x7f << 16 )
\r
426 #define IEP_REGB_DIL_MTN_TAB4_3_Y (0x7f << 24 )
\r
428 #define IEP_REGB_DIL_MTN_TAB5_0_Y (0x7f << 0 )
\r
429 #define IEP_REGB_DIL_MTN_TAB5_1_Y (0x7f << 8 )
\r
430 #define IEP_REGB_DIL_MTN_TAB5_2_Y (0x7f << 16 )
\r
431 #define IEP_REGB_DIL_MTN_TAB5_3_Y (0x7f << 24 )
\r
433 #define IEP_REGB_DIL_MTN_TAB6_0_Y (0x7f << 0 )
\r
434 #define IEP_REGB_DIL_MTN_TAB6_1_Y (0x7f << 8 )
\r
435 #define IEP_REGB_DIL_MTN_TAB6_2_Y (0x7f << 16 )
\r
436 #define IEP_REGB_DIL_MTN_TAB6_3_Y (0x7f << 24 )
\r
438 #define IEP_REGB_DIL_MTN_TAB7_0_Y (0x7f << 0 )
\r
439 #define IEP_REGB_DIL_MTN_TAB7_1_Y (0x7f << 8 )
\r
440 #define IEP_REGB_DIL_MTN_TAB7_2_Y (0x7f << 16 )
\r
441 #define IEP_REGB_DIL_MTN_TAB7_3_Y (0x7f << 24 )
\r
443 #if defined(CONFIG_IEP_MMU)
\r
445 #define IEP_REGB_MMU_STATUS_PAGING_ENABLE_Y (0x01 << 0)
\r
446 #define IEP_REGB_MMU_STATUS_PAGE_FAULT_ACTIVE_Y (0x01 << 1)
\r
447 #define IEP_REGB_MMU_STATUS_STALL_ACTIVE_Y (0x01 << 2)
\r
448 #define IEP_REGB_MMU_STATUS_IDLE_Y (0x01 << 3)
\r
449 #define IEP_REGB_MMU_STATUS_REPLAY_BUFFER_EMPTY_Y (0x01 << 4)
\r
450 #define IEP_REGB_MMU_STATUS_PAGE_FAULT_IS_WRITE_Y (0x01 << 5)
\r
451 #define IEP_REGB_MMU_STATUS_PAGE_FAULT_BUS_ID_Y (0x1F << 6)
\r
453 #define IEP_REGB_MMU_CMD_Y (0x07 << 0)
\r
455 #define IEP_REGB_MMU_ZAP_ONE_LINE_Y (0x01 << 0)
\r
457 #define IEP_REGB_MMU_INT_RAWSTAT_PAGE_FAULT_Y (0x01 << 0)
\r
458 #define IEP_REGB_MMU_INT_RAWSTAT_READ_BUS_ERROR_Y (0x01 << 1)
\r
460 #define IEP_REGB_MMU_INT_CLEAR_PAGE_FAULT_CLEAR_Y (0x01 << 0)
\r
461 #define IEP_REGB_MMU_INT_CLEAR_READ_BUS_ERROR_CLEAR_Y (0x01 << 1)
\r
463 #define IEP_REGB_MMU_INT_MASK_PAGE_FAULT_INT_EN_Y (0x01 << 0)
\r
464 #define IEP_REGB_MMU_INT_MASK_READ_BUS_ERROR_INT_EN_Y (0x01 << 1)
\r
466 #define IEP_REGB_MMU_INT_STATUS_PAGE_FAULT_Y (0x01 << 0)
\r
467 #define IEP_REGB_MMU_INT_STATUS_READ_BUS_ERROR_Y (0x01 << 1)
\r
469 #define IEP_REGB_MMU_AUTO_GATING_Y (0x01 << 0)
\r
472 #define IEP_REGB_MMU_STATUS_PAGING_ENABLE_F (0)
\r
473 #define IEP_REGB_MMU_STATUS_PAGE_FAULT_ACTIVE_F (1)
\r
474 #define IEP_REGB_MMU_STATUS_STALL_ACTIVE_F (2)
\r
475 #define IEP_REGB_MMU_STATUS_IDLE_F (3)
\r
476 #define IEP_REGB_MMU_STATUS_REPLAY_BUFFER_EMPTY_F (4)
\r
477 #define IEP_REGB_MMU_STATUS_PAGE_FAULT_IS_WRITE_F (5)
\r
478 #define IEP_REGB_MMU_STATUS_PAGE_FAULT_BUS_ID_F (6)
\r
481 /*-----------------------------------------------------------------
\r
482 //MaskRegBits32(addr, y, z),¼Ä´æÆ÷ÅäÖÃ
\r
483 -----------------------------------------------------------------*/
\r
485 #define IEP_REGB_V_REVERSE_DISP(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_V_REVERSE_DISP_Y,IEP_REGB_V_REVERSE_DISP_Z(x))
\r
486 #define IEP_REGB_H_REVERSE_DISP(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_H_REVERSE_DISP_Y,IEP_REGB_H_REVERSE_DISP_Z(x))
\r
487 #define IEP_REGB_SCL_EN(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_SCL_EN_Y,IEP_REGB_SCL_EN_Z(x))
\r
488 #define IEP_REGB_SCL_SEL(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_SCL_SEL_Y,IEP_REGB_SCL_SEL_Z(x))
\r
489 #define IEP_REGB_SCL_UP_COE_SEL(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_SCL_UP_COE_SEL_Y,IEP_REGB_SCL_UP_COE_SEL_Z(x))
\r
490 #define IEP_REGB_DIL_EI_SEL(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_DIL_EI_SEL_Y,IEP_REGB_DIL_EI_SEL_Z(x))
\r
491 #define IEP_REGB_DIL_EI_RADIUS(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_DIL_EI_RADIUS_Y,IEP_REGB_DIL_EI_RADIUS_Z(x))
\r
492 #define IEP_REGB_CON_GAM_ORDER(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_CON_GAM_ORDER_Y,IEP_REGB_CON_GAM_ORDER_Z(x))
\r
493 #define IEP_REGB_RGB_ENH_SEL(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_RGB_ENH_SEL_Y,IEP_REGB_RGB_ENH_SEL_Z(x))
\r
494 #define IEP_REGB_RGB_CON_GAM_EN(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_RGB_CON_GAM_EN_Y,IEP_REGB_RGB_CON_GAM_EN_Z(x))
\r
495 #define IEP_REGB_RGB_COLOR_ENH_EN(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_RGB_COLOR_ENH_EN_Y,IEP_REGB_RGB_COLOR_ENH_EN_Z(x))
\r
496 #define IEP_REGB_DIL_EI_SMOOTH(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_DIL_EI_SMOOTH_Y,IEP_REGB_DIL_EI_SMOOTH_Z(x))
\r
497 #define IEP_REGB_YUV_ENH_EN(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_YUV_ENH_EN_Y,IEP_REGB_YUV_ENH_EN_Z(x))
\r
498 #define IEP_REGB_YUV_DNS_EN(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_YUV_DNS_EN_Y,IEP_REGB_YUV_DNS_EN_Z(x))
\r
499 #define IEP_REGB_DIL_EI_MODE(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_DIL_EI_MODE_Y,IEP_REGB_DIL_EI_MODE_Z(x))
\r
500 #define IEP_REGB_DIL_HF_EN(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_DIL_HF_EN_Y,IEP_REGB_DIL_HF_EN_Z(x))
\r
501 #define IEP_REGB_DIL_MODE(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_DIL_MODE_Y,IEP_REGB_DIL_MODE_Z(x))
\r
502 #define IEP_REGB_DIL_HF_FCT(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_DIL_HF_FCT_Y,IEP_REGB_DIL_HF_FCT_Z(x))
\r
503 #define IEP_REGB_LCDC_PATH_EN(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_LCDC_PATH_EN_Y,IEP_REGB_LCDC_PATH_EN_Z(x))
\r
506 #define IEP_REGB_GLB_ALPHA(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_GLB_ALPHA_Y,IEP_REGB_GLB_ALPHA_Z(x))
\r
507 #define IEP_REGB_RGB2YUV_INPUT_CLIP(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_RGB2YUV_INPUT_CLIP_Y,IEP_REGB_RGB2YUV_INPUT_CLIP_Z(x))
\r
508 #define IEP_REGB_YUV2RGB_INPUT_CLIP(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_YUV2RGB_INPUT_CLIP_Y,IEP_REGB_YUV2RGB_INPUT_CLIP_Z(x))
\r
509 #define IEP_REGB_RGB_TO_YUV_EN(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_RGB_TO_YUV_EN_Y,IEP_REGB_RGB_TO_YUV_EN_Z(x))
\r
510 #define IEP_REGB_YUV_TO_RGB_EN(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_YUV_TO_RGB_EN_Y,IEP_REGB_YUV_TO_RGB_EN_Z(x))
\r
511 #define IEP_REGB_RGB2YUV_COE_SEL(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_RGB2YUV_COE_SEL_Y,IEP_REGB_RGB2YUV_COE_SEL_Z(x))
\r
512 #define IEP_REGB_YUV2RGB_COE_SEL(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_YUV2RGB_COE_SEL_Y,IEP_REGB_YUV2RGB_COE_SEL_Z(x))
\r
513 #define IEP_REGB_DITHER_DOWN_EN(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_DITHER_DOWN_EN_Y,IEP_REGB_DITHER_DOWN_EN_Z(x))
\r
514 #define IEP_REGB_DITHER_UP_EN(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_DITHER_UP_EN_Y,IEP_REGB_DITHER_UP_EN_Z(x))
\r
515 #define IEP_REGB_DST_YUV_SWAP(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_DST_YUV_SWAP_Y,IEP_REGB_DST_YUV_SWAP_Z(x))
\r
516 #define IEP_REGB_DST_RGB_SWAP(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_DST_RGB_SWAP_Y,IEP_REGB_DST_RGB_SWAP_Z(x))
\r
517 #define IEP_REGB_DST_FMT(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_DST_FMT_Y,IEP_REGB_DST_FMT_Z(x))
\r
518 #define IEP_REGB_SRC_YUV_SWAP(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_SRC_YUV_SWAP_Y,IEP_REGB_SRC_YUV_SWAP_Z(x))
\r
519 #define IEP_REGB_SRC_RGB_SWAP(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_SRC_RGB_SWAP_Y,IEP_REGB_SRC_RGB_SWAP_Z(x))
\r
520 #define IEP_REGB_SRC_FMT(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_SRC_FMT_Y,IEP_REGB_SRC_FMT_Z(x))
\r
523 #define IEP_REGB_FRAME_END_INT_CLR(base, x) MaskRegBits32(base, rIEP_INT,IEP_REGB_FRAME_END_INT_CLR_Y,IEP_REGB_FRAME_END_INT_CLR_Z(x))
\r
524 #define IEP_REGB_FRAME_END_INT_EN(base, x) MaskRegBits32(base, rIEP_INT,IEP_REGB_FRAME_END_INT_EN_Y,IEP_REGB_FRAME_END_INT_EN_Z(x))
\r
527 #define IEP_REGB_FRM_START(base, x) WriteReg32(base, rIEP_FRM_START,x)
\r
530 #define IEP_REGB_SOFT_RST(base, x) WriteReg32(base, rIEP_SOFT_RST,x)
\r
532 //iep_vir_img_width
\r
533 #define IEP_REGB_DST_VIR_LINE_WIDTH(base, x) ConfRegBits32(base, RAW_rIEP_VIR_IMG_WIDTH,rIEP_VIR_IMG_WIDTH,IEP_REGB_DST_VIR_LINE_WIDTH_Y,IEP_REGB_DST_VIR_LINE_WIDTH_Z(x))
\r
534 #define IEP_REGB_SRC_VIR_LINE_WIDTH(base, x) ConfRegBits32(base, RAW_rIEP_VIR_IMG_WIDTH,rIEP_VIR_IMG_WIDTH,IEP_REGB_SRC_VIR_LINE_WIDTH_Y,IEP_REGB_SRC_VIR_LINE_WIDTH_Z(x))
\r
537 #define IEP_REGB_SCL_VRT_FCT(base, x) ConfRegBits32(base, RAW_rIEP_IMG_SCL_FCT,rIEP_IMG_SCL_FCT,IEP_REGB_SCL_VRT_FCT_Y,IEP_REGB_SCL_VRT_FCT_Z(x))
\r
538 #define IEP_REGB_SCL_HRZ_FCT(base, x) ConfRegBits32(base, RAW_rIEP_IMG_SCL_FCT,rIEP_IMG_SCL_FCT,IEP_REGB_SCL_HRZ_FCT_Y,IEP_REGB_SCL_HRZ_FCT_Z(x))
\r
541 #define IEP_REGB_SRC_IMG_HEIGHT(base, x) ConfRegBits32(base, RAW_rIEP_SRC_IMG_SIZE,rIEP_SRC_IMG_SIZE,IEP_REGB_SRC_IMG_HEIGHT_Y,IEP_REGB_SRC_IMG_HEIGHT_Z(x))
\r
542 #define IEP_REGB_SRC_IMG_WIDTH(base, x) ConfRegBits32(base, RAW_rIEP_SRC_IMG_SIZE,rIEP_SRC_IMG_SIZE,IEP_REGB_SRC_IMG_WIDTH_Y,IEP_REGB_SRC_IMG_WIDTH_Z(x))
\r
544 #define IEP_REGB_DST_IMG_HEIGHT(base, x) ConfRegBits32(base, RAW_rIEP_DST_IMG_SIZE,rIEP_DST_IMG_SIZE,IEP_REGB_DST_IMG_HEIGHT_Y,IEP_REGB_DST_IMG_HEIGHT_Z(x))
\r
545 #define IEP_REGB_DST_IMG_WIDTH(base, x) ConfRegBits32(base, RAW_rIEP_DST_IMG_SIZE,rIEP_DST_IMG_SIZE,IEP_REGB_DST_IMG_WIDTH_Y,IEP_REGB_DST_IMG_WIDTH_Z(x))
\r
547 //dst_img_width_tile0/1/2/3
\r
548 #define IEP_REGB_DST_IMG_WIDTH_TILE0(base, x) WriteReg32(base, rIEP_DST_IMG_WIDTH_TILE0,x)
\r
549 #define IEP_REGB_DST_IMG_WIDTH_TILE1(base, x) WriteReg32(base, rIEP_DST_IMG_WIDTH_TILE1,x)
\r
550 #define IEP_REGB_DST_IMG_WIDTH_TILE2(base, x) WriteReg32(base, rIEP_DST_IMG_WIDTH_TILE2,x)
\r
551 #define IEP_REGB_DST_IMG_WIDTH_TILE3(base, x) WriteReg32(base, rIEP_DST_IMG_WIDTH_TILE3,x)
\r
553 //iep_enh_yuv_cnfg0
\r
554 #define IEP_REGB_SAT_CON(base, x) ConfRegBits32(base, RAW_rIEP_ENH_YUV_CNFG_0,rIEP_ENH_YUV_CNFG_0,IEP_REGB_SAT_CON_Y,IEP_REGB_SAT_CON_Z(x))
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555 #define IEP_REGB_CONTRAST(base, x) ConfRegBits32(base, RAW_rIEP_ENH_YUV_CNFG_0,rIEP_ENH_YUV_CNFG_0,IEP_REGB_CONTRAST_Y,IEP_REGB_CONTRAST_Z(x))
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556 #define IEP_REGB_BRIGHTNESS(base, x) ConfRegBits32(base, RAW_rIEP_ENH_YUV_CNFG_0,rIEP_ENH_YUV_CNFG_0,IEP_REGB_BRIGHTNESS_Y,IEP_REGB_BRIGHTNESS_Z(x))
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557 //iep_enh_yuv_cnfg1
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558 #define IEP_REGB_COS_HUE(base, x) ConfRegBits32(base, RAW_rIEP_ENH_YUV_CNFG_1,rIEP_ENH_YUV_CNFG_1,IEP_REGB_COS_HUE_Y,IEP_REGB_COS_HUE_Z(x))
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559 #define IEP_REGB_SIN_HUE(base, x) ConfRegBits32(base, RAW_rIEP_ENH_YUV_CNFG_1,rIEP_ENH_YUV_CNFG_1,IEP_REGB_SIN_HUE_Y,IEP_REGB_SIN_HUE_Z(x))
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560 //iep_enh_yuv_cnfg2
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561 #define IEP_REGB_VIDEO_MODE(base, x) ConfRegBits32(base, RAW_rIEP_ENH_YUV_CNFG_2,rIEP_ENH_YUV_CNFG_2,IEP_REGB_VIDEO_MODE_Y,IEP_REGB_VIDEO_MODE_Z(x))
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562 #define IEP_REGB_COLOR_BAR_V(base, x) ConfRegBits32(base, RAW_rIEP_ENH_YUV_CNFG_2,rIEP_ENH_YUV_CNFG_2,IEP_REGB_COLOR_BAR_V_Y,IEP_REGB_COLOR_BAR_V_Z(x))
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563 #define IEP_REGB_COLOR_BAR_U(base, x) ConfRegBits32(base, RAW_rIEP_ENH_YUV_CNFG_2,rIEP_ENH_YUV_CNFG_2,IEP_REGB_COLOR_BAR_U_Y,IEP_REGB_COLOR_BAR_U_Z(x))
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564 #define IEP_REGB_COLOR_BAR_Y(base, x) ConfRegBits32(base, RAW_rIEP_ENH_YUV_CNFG_2,rIEP_ENH_YUV_CNFG_2,IEP_REGB_COLOR_BAR_Y_Y,IEP_REGB_COLOR_BAR_Y_Z(x))
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566 #define IEP_REGB_ENH_THRESHOLD(base, x) ConfRegBits32(base, RAW_rIEP_ENH_RGB_CNFG,rIEP_ENH_RGB_CNFG,IEP_REGB_ENH_THRESHOLD_Y,IEP_REGB_ENH_THRESHOLD_Z(x))
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567 #define IEP_REGB_ENH_ALPHA(base, x) ConfRegBits32(base, RAW_rIEP_ENH_RGB_CNFG,rIEP_ENH_RGB_CNFG,IEP_REGB_ENH_ALPHA_Y,IEP_REGB_ENH_ALPHA_Z(x))
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568 #define IEP_REGB_ENH_RADIUS(base, x) ConfRegBits32(base, RAW_rIEP_ENH_RGB_CNFG,rIEP_ENH_RGB_CNFG,IEP_REGB_ENH_RADIUS_Y,IEP_REGB_ENH_RADIUS_Z(x))
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570 #define IEP_REGB_ENH_C_COE(base, x) WriteReg32(base, rIEP_ENH_C_COE,x)
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572 #define IEP_REGB_SRC_ADDR_YRGB(base, x) WriteReg32(base, rIEP_SRC_ADDR_YRGB, x)
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573 #define IEP_REGB_SRC_ADDR_CBCR(base, x) WriteReg32(base, rIEP_SRC_ADDR_CBCR, x)
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574 #define IEP_REGB_SRC_ADDR_CR(base, x) WriteReg32(base, rIEP_SRC_ADDR_CR, x)
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575 #define IEP_REGB_SRC_ADDR_Y1(base, x) WriteReg32(base, rIEP_SRC_ADDR_Y1, x)
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576 #define IEP_REGB_SRC_ADDR_CBCR1(base, x) WriteReg32(base, rIEP_SRC_ADDR_CBCR1, x)
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577 #define IEP_REGB_SRC_ADDR_CR1(base, x) WriteReg32(base, rIEP_SRC_ADDR_CR1, x)
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578 #define IEP_REGB_SRC_ADDR_Y_ITEMP(base, x) WriteReg32(base, rIEP_SRC_ADDR_Y_ITEMP, x)
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579 #define IEP_REGB_SRC_ADDR_CBCR_ITEMP(base, x) WriteReg32(base, rIEP_SRC_ADDR_CBCR_ITEMP, x)
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580 #define IEP_REGB_SRC_ADDR_CR_ITEMP(base, x) WriteReg32(base, rIEP_SRC_ADDR_CR_ITEMP, x)
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581 #define IEP_REGB_SRC_ADDR_Y_FTEMP(base, x) WriteReg32(base, rIEP_SRC_ADDR_Y_FTEMP, x)
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582 #define IEP_REGB_SRC_ADDR_CBCR_FTEMP(base, x) WriteReg32(base, rIEP_SRC_ADDR_CBCR_FTEMP, x)
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583 #define IEP_REGB_SRC_ADDR_CR_FTEMP(base, x) WriteReg32(base, rIEP_SRC_ADDR_CR_FTEMP, x)
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585 #define IEP_REGB_DST_ADDR_YRGB(base, x) WriteReg32(base, rIEP_DST_ADDR_YRGB,x)
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586 #define IEP_REGB_DST_ADDR_CBCR(base, x) WriteReg32(base, rIEP_DST_ADDR_CBCR, x)
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587 #define IEP_REGB_DST_ADDR_CR(base, x) WriteReg32(base, rIEP_DST_ADDR_CR, x)
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588 #define IEP_REGB_DST_ADDR_Y1(base, x) WriteReg32(base, rIEP_DST_ADDR_Y1, x)
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589 #define IEP_REGB_DST_ADDR_CBCR1(base, x) WriteReg32(base, rIEP_DST_ADDR_CBCR1, x)
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590 #define IEP_REGB_DST_ADDR_CR1(base, x) WriteReg32(base, rIEP_DST_ADDR_CR1, x)
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591 #define IEP_REGB_DST_ADDR_Y_ITEMP(base, x) WriteReg32(base, rIEP_DST_ADDR_Y_ITEMP, x)
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592 #define IEP_REGB_DST_ADDR_CBCR_ITEMP(base, x) WriteReg32(base, rIEP_DST_ADDR_CBCR_ITEMP, x)
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593 #define IEP_REGB_DST_ADDR_CR_ITEMP(base, x) WriteReg32(base, rIEP_DST_ADDR_CR_ITEMP, x)
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594 #define IEP_REGB_DST_ADDR_Y_FTEMP(base, x) WriteReg32(base, rIEP_DST_ADDR_Y_FTEMP, x)
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595 #define IEP_REGB_DST_ADDR_CBCR_FTEMP(base, x) WriteReg32(base, rIEP_DST_ADDR_CBCR_FTEMP, x)
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596 #define IEP_REGB_DST_ADDR_CR_FTEMP(base, x) WriteReg32(base, rIEP_DST_ADDR_CR_FTEMP, x)
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599 #define IEP_REGB_DIL_MTN_TAB0(base, x) WriteReg32(base, rIEP_DIL_MTN_TAB0,x)
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600 #define IEP_REGB_DIL_MTN_TAB1(base, x) WriteReg32(base, rIEP_DIL_MTN_TAB1,x)
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601 #define IEP_REGB_DIL_MTN_TAB2(base, x) WriteReg32(base, rIEP_DIL_MTN_TAB2,x)
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602 #define IEP_REGB_DIL_MTN_TAB3(base, x) WriteReg32(base, rIEP_DIL_MTN_TAB3,x)
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603 #define IEP_REGB_DIL_MTN_TAB4(base, x) WriteReg32(base, rIEP_DIL_MTN_TAB4,x)
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604 #define IEP_REGB_DIL_MTN_TAB5(base, x) WriteReg32(base, rIEP_DIL_MTN_TAB5,x)
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605 #define IEP_REGB_DIL_MTN_TAB6(base, x) WriteReg32(base, rIEP_DIL_MTN_TAB6,x)
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606 #define IEP_REGB_DIL_MTN_TAB7(base, x) WriteReg32(base, rIEP_DIL_MTN_TAB7,x)
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608 #define IEP_REGB_STATUS(base) ReadReg32(base, rIEP_STATUS)
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610 #if defined(CONFIG_IEP_MMU)
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612 #define IEP_REGB_MMU_DTE_ADDR(base, x) WriteReg32(base, rIEP_MMU_DTE_ADDR, x)
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613 #define IEP_REGB_MMU_STATUS(base) ReadReg32(base, rIEP_MMU_STATUS)
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615 #define IEP_REGB_MMU_CMD(base, x) MaskRegBits32(base, rIEP_MMU_CMD, IEP_REGB_MMU_CMD_Y, IEP_REGB_MMU_CMD_Z(x))
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617 #define IEP_REGB_MMU_PAGE_FAULT_ADDR(base) ReadReg32(base, rIEP_MMU_PAGE_FAULT_ADDR)
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619 #define IEP_REGB_MMU_ZAP_ONE_LINE(base, x) MaskRegBits32(base, rIEP_MMU_ZAP_ONE_LINE, \
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620 IEP_REGB_MMU_ZAP_ONE_LINE_Y, \
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621 IEP_REGB_MMU_ZAP_ONE_LINE_Z(x))
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623 #define IEP_REGB_MMU_INT_RAWSTAT(base) ReadReg32(base, rIEP_MMU_INT_RAWSTAT)
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625 #define IEP_REGB_MMU_INT_CLEAR_PAGE_FAULT_CLEAR(base, x) MaskRegBits32(base, rIEP_MMU_INT_CLEAR, \
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626 IEP_REGB_MMU_INT_CLEAR_PAGE_FAULT_CLEAR_Y, \
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627 IEP_REGB_MMU_INT_CLEAR_PAGE_FAULT_CLEAR_Z(x))
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628 #define IEP_REGB_MMU_INT_CLEAR_READ_BUS_ERROR_CLEAR(base, x) MaskRegBits32(base, rIEP_MMU_INT_CLEAR, \
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629 IEP_REGB_MMU_INT_CLEAR_READ_BUS_ERROR_CLEAR_Y, \
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630 IEP_REGB_MMU_INT_CLEAR_READ_BUS_ERROR_CLEAR_Z(x))
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632 #define IEP_REGB_MMU_INT_MASK_PAGE_FAULT_INT_EN(base, x) MaskRegBits32(base, rIEP_MMU_INT_MASK, \
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633 IEP_REGB_MMU_INT_MASK_PAGE_FAULT_INT_EN_Y, \
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634 IEP_REGB_MMU_INT_MASK_PAGE_FAULT_INT_EN_Z(x))
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635 #define IEP_REGB_MMU_INT_MASK_READ_BUS_ERROR_INT_EN(base, x) MaskRegBits32(base, rIEP_MMU_INT_MASK, \
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636 IEP_REGB_MMU_INT_MASK_READ_BUS_ERROR_INT_EN_Y, \
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637 IEP_REGB_MMU_INT_MASK_PAGE_FAULT_INT_EN_Z(x))
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639 #define IEP_REGB_MMU_INT_STATUS(base) ReadReg32(base, rIEP_MMU_INT_STATUS)
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641 #define IEP_REGB_MMU_AUTO_GATING(base, x) MaskRegBits32(base, rIEP_MMU_AUTO_GATING, \
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642 IEP_REGB_MMU_AUTO_GATING_Y, \
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643 IEP_REGB_MMU_AUTO_GATING_Z(x))
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647 void iep_config_lcdc_path(IEP_MSG *iep_msg);
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649 /// system control, directly operating the device registers.
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650 /// parameter @base need to be set to device base address.
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651 void iep_soft_rst(void *base);
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652 void iep_config_done(void *base);
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653 void iep_config_frm_start(void *base);
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654 int iep_probe_int(void *base);
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655 void iep_config_frame_end_int_clr(void *base);
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656 void iep_config_frame_end_int_en(void *base);
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657 struct iep_status iep_get_status(void *base);
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658 #if defined(CONFIG_IEP_MMU)
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659 struct iep_mmu_int_status iep_probe_mmu_int_status(void *base);
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660 void iep_config_mmu_page_fault_int_en(void *base, bool en);
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661 void iep_config_mmu_page_fault_int_clr(void *base);
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662 void iep_config_mmu_read_bus_error_int_clr(void *base);
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663 uint32_t iep_probe_mmu_page_fault_addr(void *base);
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664 void iep_config_mmu_cmd(void *base, enum iep_mmu_cmd cmd);
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665 void iep_config_mmu_dte_addr(void *base, uint32_t addr);
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667 int iep_get_deinterlace_mode(void *base);
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668 void iep_set_deinterlace_mode(int mode, void *base);
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669 void iep_switch_input_address(void *base);
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671 /// generating a series of iep registers copy to the session private buffer
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672 void iep_config(iep_session *session, IEP_MSG *iep_msg);
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674 //#define IEP_PRINT_INFO
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projects / firefly-linux-kernel-4.4.55.git / blob