3 #include "hw_iep_config_addr.h"
8 uint32_t reserved0 : 1;
11 uint32_t reserved1 : 1;
12 uint32_t wyuv_sts : 1;
13 uint32_t ryuv_sts : 1;
14 uint32_t wrgb_sts : 1;
15 uint32_t rrgb_sts : 1;
19 #define rIEP_CONFIG0 (IEP_BASE+IEP_CONFIG0)
20 #define rIEP_CONFIG1 (IEP_BASE+IEP_CONFIG1)
22 #define rIEP_STATUS (IEP_BASE+IEP_STATUS)
23 #define rIEP_INT (IEP_BASE+IEP_INT)
24 #define rIEP_FRM_START (IEP_BASE+IEP_FRM_START)
25 #define rIEP_SOFT_RST (IEP_BASE+IEP_SOFT_RST)
26 #define rIEP_CONF_DONE (IEP_BASE+IEP_CONF_DONE)
28 #define rIEP_VIR_IMG_WIDTH (IEP_BASE+IEP_VIR_IMG_WIDTH)
30 #define rIEP_IMG_SCL_FCT (IEP_BASE+IEP_IMG_SCL_FCT)
32 #define rIEP_SRC_IMG_SIZE (IEP_BASE+IEP_SRC_IMG_SIZE)
33 #define rIEP_DST_IMG_SIZE (IEP_BASE+IEP_DST_IMG_SIZE)
35 #define rIEP_DST_IMG_WIDTH_TILE0 (IEP_BASE+IEP_DST_IMG_WIDTH_TILE0)
36 #define rIEP_DST_IMG_WIDTH_TILE1 (IEP_BASE+IEP_DST_IMG_WIDTH_TILE1)
37 #define rIEP_DST_IMG_WIDTH_TILE2 (IEP_BASE+IEP_DST_IMG_WIDTH_TILE2)
38 #define rIEP_DST_IMG_WIDTH_TILE3 (IEP_BASE+IEP_DST_IMG_WIDTH_TILE3)
40 #define rIEP_ENH_YUV_CNFG_0 (IEP_BASE+IEP_ENH_YUV_CNFG_0)
41 #define rIEP_ENH_YUV_CNFG_1 (IEP_BASE+IEP_ENH_YUV_CNFG_1)
42 #define rIEP_ENH_YUV_CNFG_2 (IEP_BASE+IEP_ENH_YUV_CNFG_2)
43 #define rIEP_ENH_RGB_CNFG (IEP_BASE+IEP_ENH_RGB_CNFG)
44 #define rIEP_ENH_C_COE (IEP_BASE+IEP_ENH_C_COE)
46 #define rIEP_SRC_ADDR_YRGB (IEP_BASE+IEP_SRC_ADDR_YRGB)
47 #define rIEP_SRC_ADDR_CBCR (IEP_BASE+IEP_SRC_ADDR_CBCR)
48 #define rIEP_SRC_ADDR_CR (IEP_BASE+IEP_SRC_ADDR_CR)
49 #define rIEP_SRC_ADDR_Y1 (IEP_BASE+IEP_SRC_ADDR_Y1)
50 #define rIEP_SRC_ADDR_CBCR1 (IEP_BASE+IEP_SRC_ADDR_CBCR1)
51 #define rIEP_SRC_ADDR_CR1 (IEP_BASE+IEP_SRC_ADDR_CR1)
52 #define rIEP_SRC_ADDR_Y_ITEMP (IEP_BASE+IEP_SRC_ADDR_Y_ITEMP)
53 #define rIEP_SRC_ADDR_CBCR_ITEMP (IEP_BASE+IEP_SRC_ADDR_CBCR_ITEMP)
54 #define rIEP_SRC_ADDR_CR_ITEMP (IEP_BASE+IEP_SRC_ADDR_CR_ITEMP)
55 #define rIEP_SRC_ADDR_Y_FTEMP (IEP_BASE+IEP_SRC_ADDR_Y_FTEMP)
56 #define rIEP_SRC_ADDR_CBCR_FTEMP (IEP_BASE+IEP_SRC_ADDR_CBCR_FTEMP)
57 #define rIEP_SRC_ADDR_CR_FTEMP (IEP_BASE+IEP_SRC_ADDR_CR_FTEMP)
59 #define rIEP_DST_ADDR_YRGB (IEP_BASE+IEP_DST_ADDR_YRGB)
60 #define rIEP_DST_ADDR_CBCR (IEP_BASE+IEP_DST_ADDR_CBCR)
61 #define rIEP_DST_ADDR_CR (IEP_BASE+IEP_DST_ADDR_CR)
62 #define rIEP_DST_ADDR_Y1 (IEP_BASE+IEP_DST_ADDR_Y1)
63 #define rIEP_DST_ADDR_CBCR1 (IEP_BASE+IEP_DST_ADDR_CBCR1)
64 #define rIEP_DST_ADDR_CR1 (IEP_BASE+IEP_DST_ADDR_CR1)
65 #define rIEP_DST_ADDR_Y_ITEMP (IEP_BASE+IEP_DST_ADDR_Y_ITEMP)
66 #define rIEP_DST_ADDR_CBCR_ITEMP (IEP_BASE+IEP_DST_ADDR_CBCR_ITEMP)
67 #define rIEP_DST_ADDR_CR_ITEMP (IEP_BASE+IEP_DST_ADDR_CR_ITEMP)
68 #define rIEP_DST_ADDR_Y_FTEMP (IEP_BASE+IEP_DST_ADDR_Y_FTEMP)
69 #define rIEP_DST_ADDR_CBCR_FTEMP (IEP_BASE+IEP_DST_ADDR_CBCR_FTEMP)
70 #define rIEP_DST_ADDR_CR_FTEMP (IEP_BASE+IEP_DST_ADDR_CR_FTEMP)
72 #define rIEP_DIL_MTN_TAB0 (IEP_BASE+IEP_DIL_MTN_TAB0)
73 #define rIEP_DIL_MTN_TAB1 (IEP_BASE+IEP_DIL_MTN_TAB1)
74 #define rIEP_DIL_MTN_TAB2 (IEP_BASE+IEP_DIL_MTN_TAB2)
75 #define rIEP_DIL_MTN_TAB3 (IEP_BASE+IEP_DIL_MTN_TAB3)
76 #define rIEP_DIL_MTN_TAB4 (IEP_BASE+IEP_DIL_MTN_TAB4)
77 #define rIEP_DIL_MTN_TAB5 (IEP_BASE+IEP_DIL_MTN_TAB5)
78 #define rIEP_DIL_MTN_TAB6 (IEP_BASE+IEP_DIL_MTN_TAB6)
79 #define rIEP_DIL_MTN_TAB7 (IEP_BASE+IEP_DIL_MTN_TAB7)
81 #define rIEP_ENH_CG_TAB (IEP_BASE+IEP_ENH_CG_TAB)
83 #define rIEP_YUV_DNS_CRCT_TEMP (IEP_BASE+IEP_YUV_DNS_CRCT_TEMP)
84 #define rIEP_YUV_DNS_CRCT_SPAT (IEP_BASE+IEP_YUV_DNS_CRCT_SPAT)
86 #define rIEP_ENH_DDE_COE0 (IEP_BASE+IEP_ENH_DDE_COE0)
87 #define rIEP_ENH_DDE_COE1 (IEP_BASE+IEP_ENH_DDE_COE1)
89 #define RAW_rIEP_CONFIG0 (IEP_BASE+RAW_IEP_CONFIG0)
90 #define RAW_rIEP_CONFIG1 (IEP_BASE+RAW_IEP_CONFIG1)
91 #define RAW_rIEP_VIR_IMG_WIDTH (IEP_BASE+RAW_IEP_VIR_IMG_WIDTH)
93 #define RAW_rIEP_IMG_SCL_FCT (IEP_BASE+RAW_IEP_IMG_SCL_FCT)
95 #define RAW_rIEP_SRC_IMG_SIZE (IEP_BASE+RAW_IEP_SRC_IMG_SIZE)
96 #define RAW_rIEP_DST_IMG_SIZE (IEP_BASE+RAW_IEP_DST_IMG_SIZE)
98 #define RAW_rIEP_ENH_YUV_CNFG_0 (IEP_BASE+RAW_IEP_ENH_YUV_CNFG_0)
99 #define RAW_rIEP_ENH_YUV_CNFG_1 (IEP_BASE+RAW_IEP_ENH_YUV_CNFG_1)
100 #define RAW_rIEP_ENH_YUV_CNFG_2 (IEP_BASE+RAW_IEP_ENH_YUV_CNFG_2)
101 #define RAW_rIEP_ENH_RGB_CNFG (IEP_BASE+RAW_IEP_ENH_RGB_CNFG)
103 #define rIEP_CG_TAB_ADDR (IEP_BASE+0x0100)
105 /*-----------------------------------------------------------------
106 //reg bit operation definition
107 -----------------------------------------------------------------*/
109 #define IEP_REGB_V_REVERSE_DISP_Z(x) (((x)&0x1 ) << 31 )
110 #define IEP_REGB_H_REVERSE_DISP_Z(x) (((x)&0x1 ) << 30 )
111 #define IEP_REGB_SCL_EN_Z(x) (((x)&0x1 ) << 28 )
112 #define IEP_REGB_SCL_SEL_Z(x) (((x)&0x3 ) << 26 )
113 #define IEP_REGB_SCL_UP_COE_SEL_Z(x) (((x)&0x3 ) << 24 )
114 #define IEP_REGB_DIL_EI_SEL_Z(x) (((x)&0x1 ) << 23 )
115 #define IEP_REGB_DIL_EI_RADIUS_Z(x) (((x)&0x3 ) << 21 )
116 #define IEP_REGB_CON_GAM_ORDER_Z(x) (((x)&0x1 ) << 20 )
117 #define IEP_REGB_RGB_ENH_SEL_Z(x) (((x)&0x3 ) << 18 )
118 #define IEP_REGB_RGB_CON_GAM_EN_Z(x) (((x)&0x1 ) << 17 )
119 #define IEP_REGB_RGB_COLOR_ENH_EN_Z(x) (((x)&0x1 ) << 16 )
120 #define IEP_REGB_DIL_EI_SMOOTH_Z(x) (((x)&0x1 ) << 15 )
121 #define IEP_REGB_YUV_ENH_EN_Z(x) (((x)&0x1 ) << 14 )
122 #define IEP_REGB_YUV_DNS_EN_Z(x) (((x)&0x1 ) << 13 )
123 #define IEP_REGB_DIL_EI_MODE_Z(x) (((x)&0x1 ) << 12 )
124 #define IEP_REGB_DIL_HF_EN_Z(x) (((x)&0x1 ) << 11 )
125 #define IEP_REGB_DIL_MODE_Z(x) (((x)&0x7 ) << 8 )
126 #define IEP_REGB_DIL_HF_FCT_Z(x) (((x)&0x7F) << 1 )
127 #define IEP_REGB_LCDC_PATH_EN_Z(x) (((x)&0x1 ) << 0 )
130 #define IEP_REGB_GLB_ALPHA_Z(x) (((x)&0xff) << 24 )
131 #define IEP_REGB_RGB2YUV_INPUT_CLIP_Z(x) (((x)&0x1 ) << 23 )
132 #define IEP_REGB_YUV2RGB_INPUT_CLIP_Z(x) (((x)&0x1 ) << 22 )
133 #define IEP_REGB_RGB_TO_YUV_EN_Z(x) (((x)&0x1 ) << 21 )
134 #define IEP_REGB_YUV_TO_RGB_EN_Z(x) (((x)&0x1 ) << 20 )
135 #define IEP_REGB_RGB2YUV_COE_SEL_Z(x) (((x)&0x3 ) << 18 )
136 #define IEP_REGB_YUV2RGB_COE_SEL_Z(x) (((x)&0x3 ) << 16 )
137 #define IEP_REGB_DITHER_DOWN_EN_Z(x) (((x)&0x1 ) << 15 )
138 #define IEP_REGB_DITHER_UP_EN_Z(x) (((x)&0x1 ) << 14 )
139 #define IEP_REGB_DST_YUV_SWAP_Z(x) (((x)&0x3 ) << 12 )
140 #define IEP_REGB_DST_RGB_SWAP_Z(x) (((x)&0x3 ) << 10 )
141 #define IEP_REGB_DST_FMT_Z(x) (((x)&0x3 ) << 8 )
142 #define IEP_REGB_SRC_YUV_SWAP_Z(x) (((x)&0x3 ) << 4 )
143 #define IEP_REGB_SRC_RGB_SWAP_Z(x) (((x)&0x3 ) << 2 )
144 #define IEP_REGB_SRC_FMT_Z(x) (((x)&0x3 ) << 0 )
147 #define IEP_REGB_FRAME_END_INT_CLR_Z(x) (((x)&0x1 ) << 16 )
148 #define IEP_REGB_FRAME_END_INT_EN_Z(x) (((x)&0x1 ) << 8 )
151 #define IEP_REGB_FRM_START_Z(x) (((x)&0x01 ) << 0 )
154 #define IEP_REGB_SOFT_RST_Z(x) (((x)&0x01 ) << 0 )
156 /*iep_vir_img_width*/
157 #define IEP_REGB_DST_VIR_LINE_WIDTH_Z(x) (((x)&0xffff) << 16 )
158 #define IEP_REGB_SRC_VIR_LINE_WIDTH_Z(x) (((x)&0xffff) << 0 )
161 #define IEP_REGB_SCL_VRT_FCT_Z(x) (((x)&0xffff) << 16 )
162 #define IEP_REGB_SCL_HRZ_FCT_Z(x) (((x)&0xffff) << 0 )
165 #define IEP_REGB_SRC_IMG_HEIGHT_Z(x) (((x)&0x1fff) << 16 )
166 #define IEP_REGB_SRC_IMG_WIDTH_Z(x) (((x)&0x1fff) << 0 )
168 #define IEP_REGB_DST_IMG_HEIGHT_Z(x) (((x)&0x1fff) << 16 )
169 #define IEP_REGB_DST_IMG_WIDTH_Z(x) (((x)&0x1fff) << 0 )
171 /*dst_img_width_tile0/1/2/3*/
172 #define IEP_REGB_DST_IMG_WIDTH_TILE0_Z(x) (((x)&0x3ff ) << 0 )
173 #define IEP_REGB_DST_IMG_WIDTH_TILE1_Z(x) (((x)&0x3ff ) << 0 )
174 #define IEP_REGB_DST_IMG_WIDTH_TILE2_Z(x) (((x)&0x3ff ) << 0 )
175 #define IEP_REGB_DST_IMG_WIDTH_TILE3_Z(x) (((x)&0x3ff ) << 0 )
177 /*iep_enh_yuv_cnfg0*/
178 #define IEP_REGB_SAT_CON_Z(x) (((x)&0x1ff ) << 16 )
179 #define IEP_REGB_CONTRAST_Z(x) (((x)&0xff ) << 8 )
180 #define IEP_REGB_BRIGHTNESS_Z(x) (((x)&0x3f ) << 0 )
181 /*iep_enh_yuv_cnfg1*/
182 #define IEP_REGB_COS_HUE_Z(x) (((x)&0xff ) << 8 )
183 #define IEP_REGB_SIN_HUE_Z(x) (((x)&0xff ) << 0 )
184 /*iep_enh_yuv_cnfg2*/
185 #define IEP_REGB_VIDEO_MODE_Z(x) (((x)&0x3 ) << 24 )
186 #define IEP_REGB_COLOR_BAR_V_Z(x) (((x)&0xff ) << 16 )
187 #define IEP_REGB_COLOR_BAR_U_Z(x) (((x)&0xff ) << 8 )
188 #define IEP_REGB_COLOR_BAR_Y_Z(x) (((x)&0xff ) << 0 )
190 #define IEP_REGB_YUV_DNS_LUMA_SPAT_SEL_Z(x) (((x)&0x3 ) << 30 )
191 #define IEP_REGB_YUV_DNS_LUMA_TEMP_SEL_Z(x) (((x)&0x3 ) << 28 )
192 #define IEP_REGB_YUV_DNS_CHROMA_SPAT_SEL_Z(x) (((x)&0x3 ) << 26 )
193 #define IEP_REGB_YUV_DNS_CHROMA_TEMP_SEL_Z(x) (((x)&0x3 ) << 24 )
194 #define IEP_REGB_ENH_THRESHOLD_Z(x) (((x)&0xff ) << 16 )
195 #define IEP_REGB_ENH_ALPHA_Z(x) (((x)&0x3f ) << 8 )
196 #define IEP_REGB_ENH_RADIUS_Z(x) (((x)&0x3 ) << 0 )
198 #define IEP_REGB_ENH_C_COE_Z(x) (((x)&0x7f ) << 0 )
200 #define IEP_REGB_DIL_MTN_TAB0_0_Z(x) (((x)&0x7f ) << 0 )
201 #define IEP_REGB_DIL_MTN_TAB0_1_Z(x) (((x)&0x7f ) << 8 )
202 #define IEP_REGB_DIL_MTN_TAB0_2_Z(x) (((x)&0x7f ) << 16 )
203 #define IEP_REGB_DIL_MTN_TAB0_3_Z(x) (((x)&0x7f ) << 24 )
205 #define IEP_REGB_DIL_MTN_TAB1_0_Z(x) (((x)&0x7f ) << 0 )
206 #define IEP_REGB_DIL_MTN_TAB1_1_Z(x) (((x)&0x7f ) << 8 )
207 #define IEP_REGB_DIL_MTN_TAB1_2_Z(x) (((x)&0x7f ) << 16 )
208 #define IEP_REGB_DIL_MTN_TAB1_3_Z(x) (((x)&0x7f ) << 24 )
210 #define IEP_REGB_DIL_MTN_TAB2_0_Z(x) (((x)&0x7f ) << 0 )
211 #define IEP_REGB_DIL_MTN_TAB2_1_Z(x) (((x)&0x7f ) << 8 )
212 #define IEP_REGB_DIL_MTN_TAB2_2_Z(x) (((x)&0x7f ) << 16 )
213 #define IEP_REGB_DIL_MTN_TAB2_3_Z(x) (((x)&0x7f ) << 24 )
215 #define IEP_REGB_DIL_MTN_TAB3_0_Z(x) (((x)&0x7f ) << 0 )
216 #define IEP_REGB_DIL_MTN_TAB3_1_Z(x) (((x)&0x7f ) << 8 )
217 #define IEP_REGB_DIL_MTN_TAB3_2_Z(x) (((x)&0x7f ) << 16 )
218 #define IEP_REGB_DIL_MTN_TAB3_3_Z(x) (((x)&0x7f ) << 24 )
220 #define IEP_REGB_DIL_MTN_TAB4_0_Z(x) (((x)&0x7f ) << 0 )
221 #define IEP_REGB_DIL_MTN_TAB4_1_Z(x) (((x)&0x7f ) << 8 )
222 #define IEP_REGB_DIL_MTN_TAB4_2_Z(x) (((x)&0x7f ) << 16 )
223 #define IEP_REGB_DIL_MTN_TAB4_3_Z(x) (((x)&0x7f ) << 24 )
225 #define IEP_REGB_DIL_MTN_TAB5_0_Z(x) (((x)&0x7f ) << 0 )
226 #define IEP_REGB_DIL_MTN_TAB5_1_Z(x) (((x)&0x7f ) << 8 )
227 #define IEP_REGB_DIL_MTN_TAB5_2_Z(x) (((x)&0x7f ) << 16 )
228 #define IEP_REGB_DIL_MTN_TAB5_3_Z(x) (((x)&0x7f ) << 24 )
230 #define IEP_REGB_DIL_MTN_TAB6_0_Z(x) (((x)&0x7f ) << 0 )
231 #define IEP_REGB_DIL_MTN_TAB6_1_Z(x) (((x)&0x7f ) << 8 )
232 #define IEP_REGB_DIL_MTN_TAB6_2_Z(x) (((x)&0x7f ) << 16 )
233 #define IEP_REGB_DIL_MTN_TAB6_3_Z(x) (((x)&0x7f ) << 24 )
235 #define IEP_REGB_DIL_MTN_TAB7_0_Z(x) (((x)&0x7f ) << 0 )
236 #define IEP_REGB_DIL_MTN_TAB7_1_Z(x) (((x)&0x7f ) << 8 )
237 #define IEP_REGB_DIL_MTN_TAB7_2_Z(x) (((x)&0x7f ) << 16 )
238 #define IEP_REGB_DIL_MTN_TAB7_3_Z(x) (((x)&0x7f ) << 24 )
241 #define IEP_REGB_V_REVERSE_DISP_Y (0x1 << 31 )
242 #define IEP_REGB_H_REVERSE_DISP_Y (0x1 << 30 )
243 #define IEP_REGB_SCL_EN_Y (0x1 << 28 )
244 #define IEP_REGB_SCL_SEL_Y (0x3 << 26 )
245 #define IEP_REGB_SCL_UP_COE_SEL_Y (0x3 << 24 )
246 #define IEP_REGB_DIL_EI_SEL_Y (0x1 << 23 )
247 #define IEP_REGB_DIL_EI_RADIUS_Y (0x3 << 21 )
248 #define IEP_REGB_CON_GAM_ORDER_Y (0x1 << 20 )
249 #define IEP_REGB_RGB_ENH_SEL_Y (0x3 << 18 )
250 #define IEP_REGB_RGB_CON_GAM_EN_Y (0x1 << 17 )
251 #define IEP_REGB_RGB_COLOR_ENH_EN_Y (0x1 << 16 )
252 #define IEP_REGB_DIL_EI_SMOOTH_Y (0x1 << 15 )
253 #define IEP_REGB_YUV_ENH_EN_Y (0x1 << 14 )
254 #define IEP_REGB_YUV_DNS_EN_Y (0x1 << 13 )
255 #define IEP_REGB_DIL_EI_MODE_Y (0x1 << 12 )
256 #define IEP_REGB_DIL_HF_EN_Y (0x1 << 11 )
257 #define IEP_REGB_DIL_MODE_Y (0x7 << 8 )
258 #define IEP_REGB_DIL_HF_FCT_Y (0x7F << 1 )
259 #define IEP_REGB_LCDC_PATH_EN_Y (0x1 << 0 )
262 #define IEP_REGB_GLB_ALPHA_Y (0xff << 24 )
263 #define IEP_REGB_RGB2YUV_INPUT_CLIP_Y (0x1 << 23 )
264 #define IEP_REGB_YUV2RGB_INPUT_CLIP_Y (0x1 << 22 )
265 #define IEP_REGB_RGB_TO_YUV_EN_Y (0x1 << 21 )
266 #define IEP_REGB_YUV_TO_RGB_EN_Y (0x1 << 20 )
267 #define IEP_REGB_RGB2YUV_COE_SEL_Y (0x3 << 18 )
268 #define IEP_REGB_YUV2RGB_COE_SEL_Y (0x3 << 16 )
269 #define IEP_REGB_DITHER_DOWN_EN_Y (0x1 << 15 )
270 #define IEP_REGB_DITHER_UP_EN_Y (0x1 << 14 )
271 #define IEP_REGB_DST_YUV_SWAP_Y (0x3 << 12 )
272 #define IEP_REGB_DST_RGB_SWAP_Y (0x3 << 10 )
273 #define IEP_REGB_DST_FMT_Y (0x3 << 8 )
274 #define IEP_REGB_SRC_YUV_SWAP_Y (0x3 << 4 )
275 #define IEP_REGB_SRC_RGB_SWAP_Y (0x3 << 2 )
276 #define IEP_REGB_SRC_FMT_Y (0x3 << 0 )
279 #define IEP_REGB_FRAME_END_INT_CLR_Y (0x1 << 16 )
280 #define IEP_REGB_FRAME_END_INT_EN_Y (0x1 << 8 )
283 #define IEP_REGB_FRM_START_Y (0x1 << 0 )
286 #define IEP_REGB_SOFT_RST_Y (0x1 << 0 )
288 /*iep_vir_img_width*/
289 #define IEP_REGB_DST_VIR_LINE_WIDTH_Y (0xffff << 16 )
290 #define IEP_REGB_SRC_VIR_LINE_WIDTH_Y (0xffff << 0 )
293 #define IEP_REGB_SCL_VRT_FCT_Y (0xffff << 16 )
294 #define IEP_REGB_SCL_HRZ_FCT_Y (0xffff << 0 )
297 #define IEP_REGB_SRC_IMG_HEIGHT_Y (0x1fff << 16 )
298 #define IEP_REGB_SRC_IMG_WIDTH_Y (0x1fff << 0 )
300 #define IEP_REGB_DST_IMG_HEIGHT_Y (0x1fff << 16 )
301 #define IEP_REGB_DST_IMG_WIDTH_Y (0x1fff << 0 )
303 /*dst_img_width_tile0/1/2/3*/
304 #define IEP_REGB_DST_IMG_WIDTH_TILE0_Y (0x3ff << 0 )
305 #define IEP_REGB_DST_IMG_WIDTH_TILE1_Y (0x3ff << 0 )
306 #define IEP_REGB_DST_IMG_WIDTH_TILE2_Y (0x3ff << 0 )
307 #define IEP_REGB_DST_IMG_WIDTH_TILE3_Y (0x3ff << 0 )
309 /*iep_enh_yuv_cnfg0*/
310 #define IEP_REGB_SAT_CON_Y (0x1ff << 16)
311 #define IEP_REGB_CONTRAST_Y (0xff << 8 )
312 #define IEP_REGB_BRIGHTNESS_Y (0x3f << 0 )
313 /*iep_enh_yuv_cnfg1*/
314 #define IEP_REGB_COS_HUE_Y (0xff << 8 )
315 #define IEP_REGB_SIN_HUE_Y (0xff << 0 )
316 /*iep_enh_yuv_cnfg2*/
317 #define IEP_REGB_VIDEO_MODE_Y (0x3 << 24)
318 #define IEP_REGB_COLOR_BAR_V_Y (0xff << 16)
319 #define IEP_REGB_COLOR_BAR_U_Y (0xff << 8 )
320 #define IEP_REGB_COLOR_BAR_Y_Y (0xff << 0 )
322 #define IEP_REGB_YUV_DNS_LUMA_SPAT_SEL_Y (0x3 << 30)
323 #define IEP_REGB_YUV_DNS_LUMA_TEMP_SEL_Y (0x3 << 28)
324 #define IEP_REGB_YUV_DNS_CHROMA_SPAT_SEL_Y (0x3 << 26)
325 #define IEP_REGB_YUV_DNS_CHROMA_TEMP_SEL_Y (0x3 << 24)
326 #define IEP_REGB_ENH_THRESHOLD_Y (0xff << 16)
327 #define IEP_REGB_ENH_ALPHA_Y (0x3f << 8 )
328 #define IEP_REGB_ENH_RADIUS_Y (0x3 << 0 )
330 #define IEP_REGB_ENH_C_COE_Y (0x7f << 0 )
332 #define IEP_REGB_DIL_MTN_TAB0_0_Y (0x7f << 0 )
333 #define IEP_REGB_DIL_MTN_TAB0_1_Y (0x7f << 8 )
334 #define IEP_REGB_DIL_MTN_TAB0_2_Y (0x7f << 16 )
335 #define IEP_REGB_DIL_MTN_TAB0_3_Y (0x7f << 24 )
337 #define IEP_REGB_DIL_MTN_TAB1_0_Y (0x7f << 0 )
338 #define IEP_REGB_DIL_MTN_TAB1_1_Y (0x7f << 8 )
339 #define IEP_REGB_DIL_MTN_TAB1_2_Y (0x7f << 16 )
340 #define IEP_REGB_DIL_MTN_TAB1_3_Y (0x7f << 24 )
342 #define IEP_REGB_DIL_MTN_TAB2_0_Y (0x7f << 0 )
343 #define IEP_REGB_DIL_MTN_TAB2_1_Y (0x7f << 8 )
344 #define IEP_REGB_DIL_MTN_TAB2_2_Y (0x7f << 16 )
345 #define IEP_REGB_DIL_MTN_TAB2_3_Y (0x7f << 24 )
347 #define IEP_REGB_DIL_MTN_TAB3_0_Y (0x7f << 0 )
348 #define IEP_REGB_DIL_MTN_TAB3_1_Y (0x7f << 8 )
349 #define IEP_REGB_DIL_MTN_TAB3_2_Y (0x7f << 16 )
350 #define IEP_REGB_DIL_MTN_TAB3_3_Y (0x7f << 24 )
352 #define IEP_REGB_DIL_MTN_TAB4_0_Y (0x7f << 0 )
353 #define IEP_REGB_DIL_MTN_TAB4_1_Y (0x7f << 8 )
354 #define IEP_REGB_DIL_MTN_TAB4_2_Y (0x7f << 16 )
355 #define IEP_REGB_DIL_MTN_TAB4_3_Y (0x7f << 24 )
357 #define IEP_REGB_DIL_MTN_TAB5_0_Y (0x7f << 0 )
358 #define IEP_REGB_DIL_MTN_TAB5_1_Y (0x7f << 8 )
359 #define IEP_REGB_DIL_MTN_TAB5_2_Y (0x7f << 16 )
360 #define IEP_REGB_DIL_MTN_TAB5_3_Y (0x7f << 24 )
362 #define IEP_REGB_DIL_MTN_TAB6_0_Y (0x7f << 0 )
363 #define IEP_REGB_DIL_MTN_TAB6_1_Y (0x7f << 8 )
364 #define IEP_REGB_DIL_MTN_TAB6_2_Y (0x7f << 16 )
365 #define IEP_REGB_DIL_MTN_TAB6_3_Y (0x7f << 24 )
367 #define IEP_REGB_DIL_MTN_TAB7_0_Y (0x7f << 0 )
368 #define IEP_REGB_DIL_MTN_TAB7_1_Y (0x7f << 8 )
369 #define IEP_REGB_DIL_MTN_TAB7_2_Y (0x7f << 16 )
370 #define IEP_REGB_DIL_MTN_TAB7_3_Y (0x7f << 24 )
372 /*-----------------------------------------------------------------
373 MaskRegBits32(addr, y, z),Register configure
374 -----------------------------------------------------------------*/
376 #define IEP_REGB_V_REVERSE_DISP(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_V_REVERSE_DISP_Y,IEP_REGB_V_REVERSE_DISP_Z(x))
377 #define IEP_REGB_H_REVERSE_DISP(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_H_REVERSE_DISP_Y,IEP_REGB_H_REVERSE_DISP_Z(x))
378 #define IEP_REGB_SCL_EN(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_SCL_EN_Y,IEP_REGB_SCL_EN_Z(x))
379 #define IEP_REGB_SCL_SEL(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_SCL_SEL_Y,IEP_REGB_SCL_SEL_Z(x))
380 #define IEP_REGB_SCL_UP_COE_SEL(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_SCL_UP_COE_SEL_Y,IEP_REGB_SCL_UP_COE_SEL_Z(x))
381 #define IEP_REGB_DIL_EI_SEL(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_DIL_EI_SEL_Y,IEP_REGB_DIL_EI_SEL_Z(x))
382 #define IEP_REGB_DIL_EI_RADIUS(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_DIL_EI_RADIUS_Y,IEP_REGB_DIL_EI_RADIUS_Z(x))
383 #define IEP_REGB_CON_GAM_ORDER(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_CON_GAM_ORDER_Y,IEP_REGB_CON_GAM_ORDER_Z(x))
384 #define IEP_REGB_RGB_ENH_SEL(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_RGB_ENH_SEL_Y,IEP_REGB_RGB_ENH_SEL_Z(x))
385 #define IEP_REGB_RGB_CON_GAM_EN(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_RGB_CON_GAM_EN_Y,IEP_REGB_RGB_CON_GAM_EN_Z(x))
386 #define IEP_REGB_RGB_COLOR_ENH_EN(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_RGB_COLOR_ENH_EN_Y,IEP_REGB_RGB_COLOR_ENH_EN_Z(x))
387 #define IEP_REGB_DIL_EI_SMOOTH(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_DIL_EI_SMOOTH_Y,IEP_REGB_DIL_EI_SMOOTH_Z(x))
388 #define IEP_REGB_YUV_ENH_EN(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_YUV_ENH_EN_Y,IEP_REGB_YUV_ENH_EN_Z(x))
389 #define IEP_REGB_YUV_DNS_EN(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_YUV_DNS_EN_Y,IEP_REGB_YUV_DNS_EN_Z(x))
390 #define IEP_REGB_DIL_EI_MODE(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_DIL_EI_MODE_Y,IEP_REGB_DIL_EI_MODE_Z(x))
391 #define IEP_REGB_DIL_HF_EN(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_DIL_HF_EN_Y,IEP_REGB_DIL_HF_EN_Z(x))
392 #define IEP_REGB_DIL_MODE(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_DIL_MODE_Y,IEP_REGB_DIL_MODE_Z(x))
393 #define IEP_REGB_DIL_HF_FCT(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_DIL_HF_FCT_Y,IEP_REGB_DIL_HF_FCT_Z(x))
394 #define IEP_REGB_LCDC_PATH_EN(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG0,rIEP_CONFIG0,IEP_REGB_LCDC_PATH_EN_Y,IEP_REGB_LCDC_PATH_EN_Z(x))
397 #define IEP_REGB_GLB_ALPHA(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_GLB_ALPHA_Y,IEP_REGB_GLB_ALPHA_Z(x))
398 #define IEP_REGB_RGB2YUV_INPUT_CLIP(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_RGB2YUV_INPUT_CLIP_Y,IEP_REGB_RGB2YUV_INPUT_CLIP_Z(x))
399 #define IEP_REGB_YUV2RGB_INPUT_CLIP(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_YUV2RGB_INPUT_CLIP_Y,IEP_REGB_YUV2RGB_INPUT_CLIP_Z(x))
400 #define IEP_REGB_RGB_TO_YUV_EN(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_RGB_TO_YUV_EN_Y,IEP_REGB_RGB_TO_YUV_EN_Z(x))
401 #define IEP_REGB_YUV_TO_RGB_EN(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_YUV_TO_RGB_EN_Y,IEP_REGB_YUV_TO_RGB_EN_Z(x))
402 #define IEP_REGB_RGB2YUV_COE_SEL(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_RGB2YUV_COE_SEL_Y,IEP_REGB_RGB2YUV_COE_SEL_Z(x))
403 #define IEP_REGB_YUV2RGB_COE_SEL(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_YUV2RGB_COE_SEL_Y,IEP_REGB_YUV2RGB_COE_SEL_Z(x))
404 #define IEP_REGB_DITHER_DOWN_EN(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_DITHER_DOWN_EN_Y,IEP_REGB_DITHER_DOWN_EN_Z(x))
405 #define IEP_REGB_DITHER_UP_EN(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_DITHER_UP_EN_Y,IEP_REGB_DITHER_UP_EN_Z(x))
406 #define IEP_REGB_DST_YUV_SWAP(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_DST_YUV_SWAP_Y,IEP_REGB_DST_YUV_SWAP_Z(x))
407 #define IEP_REGB_DST_RGB_SWAP(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_DST_RGB_SWAP_Y,IEP_REGB_DST_RGB_SWAP_Z(x))
408 #define IEP_REGB_DST_FMT(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_DST_FMT_Y,IEP_REGB_DST_FMT_Z(x))
409 #define IEP_REGB_SRC_YUV_SWAP(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_SRC_YUV_SWAP_Y,IEP_REGB_SRC_YUV_SWAP_Z(x))
410 #define IEP_REGB_SRC_RGB_SWAP(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_SRC_RGB_SWAP_Y,IEP_REGB_SRC_RGB_SWAP_Z(x))
411 #define IEP_REGB_SRC_FMT(base, x) ConfRegBits32(base, RAW_rIEP_CONFIG1,rIEP_CONFIG1,IEP_REGB_SRC_FMT_Y,IEP_REGB_SRC_FMT_Z(x))
414 #define IEP_REGB_FRAME_END_INT_CLR(base, x) MaskRegBits32(base, rIEP_INT,IEP_REGB_FRAME_END_INT_CLR_Y,IEP_REGB_FRAME_END_INT_CLR_Z(x))
415 #define IEP_REGB_FRAME_END_INT_EN(base, x) MaskRegBits32(base, rIEP_INT,IEP_REGB_FRAME_END_INT_EN_Y,IEP_REGB_FRAME_END_INT_EN_Z(x))
418 #define IEP_REGB_FRM_START(base, x) WriteReg32(base, rIEP_FRM_START,x)
421 #define IEP_REGB_SOFT_RST(base, x) WriteReg32(base, rIEP_SOFT_RST,x)
423 /*iep_vir_img_width*/
424 #define IEP_REGB_DST_VIR_LINE_WIDTH(base, x) ConfRegBits32(base, RAW_rIEP_VIR_IMG_WIDTH,rIEP_VIR_IMG_WIDTH,IEP_REGB_DST_VIR_LINE_WIDTH_Y,IEP_REGB_DST_VIR_LINE_WIDTH_Z(x))
425 #define IEP_REGB_SRC_VIR_LINE_WIDTH(base, x) ConfRegBits32(base, RAW_rIEP_VIR_IMG_WIDTH,rIEP_VIR_IMG_WIDTH,IEP_REGB_SRC_VIR_LINE_WIDTH_Y,IEP_REGB_SRC_VIR_LINE_WIDTH_Z(x))
428 #define IEP_REGB_SCL_VRT_FCT(base, x) ConfRegBits32(base, RAW_rIEP_IMG_SCL_FCT,rIEP_IMG_SCL_FCT,IEP_REGB_SCL_VRT_FCT_Y,IEP_REGB_SCL_VRT_FCT_Z(x))
429 #define IEP_REGB_SCL_HRZ_FCT(base, x) ConfRegBits32(base, RAW_rIEP_IMG_SCL_FCT,rIEP_IMG_SCL_FCT,IEP_REGB_SCL_HRZ_FCT_Y,IEP_REGB_SCL_HRZ_FCT_Z(x))
432 #define IEP_REGB_SRC_IMG_HEIGHT(base, x) ConfRegBits32(base, RAW_rIEP_SRC_IMG_SIZE,rIEP_SRC_IMG_SIZE,IEP_REGB_SRC_IMG_HEIGHT_Y,IEP_REGB_SRC_IMG_HEIGHT_Z(x))
433 #define IEP_REGB_SRC_IMG_WIDTH(base, x) ConfRegBits32(base, RAW_rIEP_SRC_IMG_SIZE,rIEP_SRC_IMG_SIZE,IEP_REGB_SRC_IMG_WIDTH_Y,IEP_REGB_SRC_IMG_WIDTH_Z(x))
435 #define IEP_REGB_DST_IMG_HEIGHT(base, x) ConfRegBits32(base, RAW_rIEP_DST_IMG_SIZE,rIEP_DST_IMG_SIZE,IEP_REGB_DST_IMG_HEIGHT_Y,IEP_REGB_DST_IMG_HEIGHT_Z(x))
436 #define IEP_REGB_DST_IMG_WIDTH(base, x) ConfRegBits32(base, RAW_rIEP_DST_IMG_SIZE,rIEP_DST_IMG_SIZE,IEP_REGB_DST_IMG_WIDTH_Y,IEP_REGB_DST_IMG_WIDTH_Z(x))
438 /*dst_img_width_tile0/1/2/3*/
439 #define IEP_REGB_DST_IMG_WIDTH_TILE0(base, x) WriteReg32(base, rIEP_DST_IMG_WIDTH_TILE0,x)
440 #define IEP_REGB_DST_IMG_WIDTH_TILE1(base, x) WriteReg32(base, rIEP_DST_IMG_WIDTH_TILE1,x)
441 #define IEP_REGB_DST_IMG_WIDTH_TILE2(base, x) WriteReg32(base, rIEP_DST_IMG_WIDTH_TILE2,x)
442 #define IEP_REGB_DST_IMG_WIDTH_TILE3(base, x) WriteReg32(base, rIEP_DST_IMG_WIDTH_TILE3,x)
444 /*iep_enh_yuv_cnfg0*/
445 #define IEP_REGB_SAT_CON(base, x) ConfRegBits32(base, RAW_rIEP_ENH_YUV_CNFG_0,rIEP_ENH_YUV_CNFG_0,IEP_REGB_SAT_CON_Y,IEP_REGB_SAT_CON_Z(x))
446 #define IEP_REGB_CONTRAST(base, x) ConfRegBits32(base, RAW_rIEP_ENH_YUV_CNFG_0,rIEP_ENH_YUV_CNFG_0,IEP_REGB_CONTRAST_Y,IEP_REGB_CONTRAST_Z(x))
447 #define IEP_REGB_BRIGHTNESS(base, x) ConfRegBits32(base, RAW_rIEP_ENH_YUV_CNFG_0,rIEP_ENH_YUV_CNFG_0,IEP_REGB_BRIGHTNESS_Y,IEP_REGB_BRIGHTNESS_Z(x))
448 /*iep_enh_yuv_cnfg1*/
449 #define IEP_REGB_COS_HUE(base, x) ConfRegBits32(base, RAW_rIEP_ENH_YUV_CNFG_1,rIEP_ENH_YUV_CNFG_1,IEP_REGB_COS_HUE_Y,IEP_REGB_COS_HUE_Z(x))
450 #define IEP_REGB_SIN_HUE(base, x) ConfRegBits32(base, RAW_rIEP_ENH_YUV_CNFG_1,rIEP_ENH_YUV_CNFG_1,IEP_REGB_SIN_HUE_Y,IEP_REGB_SIN_HUE_Z(x))
451 /*iep_enh_yuv_cnfg2*/
452 #define IEP_REGB_VIDEO_MODE(base, x) ConfRegBits32(base, RAW_rIEP_ENH_YUV_CNFG_2,rIEP_ENH_YUV_CNFG_2,IEP_REGB_VIDEO_MODE_Y,IEP_REGB_VIDEO_MODE_Z(x))
453 #define IEP_REGB_COLOR_BAR_V(base, x) ConfRegBits32(base, RAW_rIEP_ENH_YUV_CNFG_2,rIEP_ENH_YUV_CNFG_2,IEP_REGB_COLOR_BAR_V_Y,IEP_REGB_COLOR_BAR_V_Z(x))
454 #define IEP_REGB_COLOR_BAR_U(base, x) ConfRegBits32(base, RAW_rIEP_ENH_YUV_CNFG_2,rIEP_ENH_YUV_CNFG_2,IEP_REGB_COLOR_BAR_U_Y,IEP_REGB_COLOR_BAR_U_Z(x))
455 #define IEP_REGB_COLOR_BAR_Y(base, x) ConfRegBits32(base, RAW_rIEP_ENH_YUV_CNFG_2,rIEP_ENH_YUV_CNFG_2,IEP_REGB_COLOR_BAR_Y_Y,IEP_REGB_COLOR_BAR_Y_Z(x))
457 #define IEP_REGB_YUV_DNS_LUMA_SPAT_SEL(base, x) ConfRegBits32(base, RAW_rIEP_ENH_RGB_CNFG,rIEP_ENH_RGB_CNFG,IEP_REGB_YUV_DNS_LUMA_SPAT_SEL_Y,IEP_REGB_YUV_DNS_LUMA_SPAT_SEL_Z(x))
458 #define IEP_REGB_YUV_DNS_LUMA_TEMP_SEL(base, x) ConfRegBits32(base, RAW_rIEP_ENH_RGB_CNFG,rIEP_ENH_RGB_CNFG,IEP_REGB_YUV_DNS_LUMA_TEMP_SEL_Y,IEP_REGB_YUV_DNS_LUMA_TEMP_SEL_Z(x))
459 #define IEP_REGB_YUV_DNS_CHROMA_SPAT_SEL(base, x) ConfRegBits32(base, RAW_rIEP_ENH_RGB_CNFG,rIEP_ENH_RGB_CNFG,IEP_REGB_YUV_DNS_CHROMA_SPAT_SEL_Y,IEP_REGB_YUV_DNS_CHROMA_SPAT_SEL_Z(x))
460 #define IEP_REGB_YUV_DNS_CHROMA_TEMP_SEL(base, x) ConfRegBits32(base, RAW_rIEP_ENH_RGB_CNFG,rIEP_ENH_RGB_CNFG,IEP_REGB_YUV_DNS_CHROMA_TEMP_SEL_Y,IEP_REGB_YUV_DNS_CHROMA_TEMP_SEL_Z(x))
461 #define IEP_REGB_ENH_THRESHOLD(base, x) ConfRegBits32(base, RAW_rIEP_ENH_RGB_CNFG,rIEP_ENH_RGB_CNFG,IEP_REGB_ENH_THRESHOLD_Y,IEP_REGB_ENH_THRESHOLD_Z(x))
462 #define IEP_REGB_ENH_ALPHA(base, x) ConfRegBits32(base, RAW_rIEP_ENH_RGB_CNFG,rIEP_ENH_RGB_CNFG,IEP_REGB_ENH_ALPHA_Y,IEP_REGB_ENH_ALPHA_Z(x))
463 #define IEP_REGB_ENH_RADIUS(base, x) ConfRegBits32(base, RAW_rIEP_ENH_RGB_CNFG,rIEP_ENH_RGB_CNFG,IEP_REGB_ENH_RADIUS_Y,IEP_REGB_ENH_RADIUS_Z(x))
465 #define IEP_REGB_ENH_C_COE(base, x) WriteReg32(base, rIEP_ENH_C_COE,x)
467 #define IEP_REGB_SRC_ADDR_YRGB(base, x) WriteReg32(base, rIEP_SRC_ADDR_YRGB, x)
468 #define IEP_REGB_SRC_ADDR_CBCR(base, x) WriteReg32(base, rIEP_SRC_ADDR_CBCR, x)
469 #define IEP_REGB_SRC_ADDR_CR(base, x) WriteReg32(base, rIEP_SRC_ADDR_CR, x)
470 #define IEP_REGB_SRC_ADDR_Y1(base, x) WriteReg32(base, rIEP_SRC_ADDR_Y1, x)
471 #define IEP_REGB_SRC_ADDR_CBCR1(base, x) WriteReg32(base, rIEP_SRC_ADDR_CBCR1, x)
472 #define IEP_REGB_SRC_ADDR_CR1(base, x) WriteReg32(base, rIEP_SRC_ADDR_CR1, x)
473 #define IEP_REGB_SRC_ADDR_Y_ITEMP(base, x) WriteReg32(base, rIEP_SRC_ADDR_Y_ITEMP, x)
474 #define IEP_REGB_SRC_ADDR_CBCR_ITEMP(base, x) WriteReg32(base, rIEP_SRC_ADDR_CBCR_ITEMP, x)
475 #define IEP_REGB_SRC_ADDR_CR_ITEMP(base, x) WriteReg32(base, rIEP_SRC_ADDR_CR_ITEMP, x)
476 #define IEP_REGB_SRC_ADDR_Y_FTEMP(base, x) WriteReg32(base, rIEP_SRC_ADDR_Y_FTEMP, x)
477 #define IEP_REGB_SRC_ADDR_CBCR_FTEMP(base, x) WriteReg32(base, rIEP_SRC_ADDR_CBCR_FTEMP, x)
478 #define IEP_REGB_SRC_ADDR_CR_FTEMP(base, x) WriteReg32(base, rIEP_SRC_ADDR_CR_FTEMP, x)
480 #define IEP_REGB_DST_ADDR_YRGB(base, x) WriteReg32(base, rIEP_DST_ADDR_YRGB,x)
481 #define IEP_REGB_DST_ADDR_CBCR(base, x) WriteReg32(base, rIEP_DST_ADDR_CBCR, x)
482 #define IEP_REGB_DST_ADDR_CR(base, x) WriteReg32(base, rIEP_DST_ADDR_CR, x)
483 #define IEP_REGB_DST_ADDR_Y1(base, x) WriteReg32(base, rIEP_DST_ADDR_Y1, x)
484 #define IEP_REGB_DST_ADDR_CBCR1(base, x) WriteReg32(base, rIEP_DST_ADDR_CBCR1, x)
485 #define IEP_REGB_DST_ADDR_CR1(base, x) WriteReg32(base, rIEP_DST_ADDR_CR1, x)
486 #define IEP_REGB_DST_ADDR_Y_ITEMP(base, x) WriteReg32(base, rIEP_DST_ADDR_Y_ITEMP, x)
487 #define IEP_REGB_DST_ADDR_CBCR_ITEMP(base, x) WriteReg32(base, rIEP_DST_ADDR_CBCR_ITEMP, x)
488 #define IEP_REGB_DST_ADDR_CR_ITEMP(base, x) WriteReg32(base, rIEP_DST_ADDR_CR_ITEMP, x)
489 #define IEP_REGB_DST_ADDR_Y_FTEMP(base, x) WriteReg32(base, rIEP_DST_ADDR_Y_FTEMP, x)
490 #define IEP_REGB_DST_ADDR_CBCR_FTEMP(base, x) WriteReg32(base, rIEP_DST_ADDR_CBCR_FTEMP, x)
491 #define IEP_REGB_DST_ADDR_CR_FTEMP(base, x) WriteReg32(base, rIEP_DST_ADDR_CR_FTEMP, x)
494 #define IEP_REGB_DIL_MTN_TAB0(base, x) WriteReg32(base, rIEP_DIL_MTN_TAB0,x)
495 #define IEP_REGB_DIL_MTN_TAB1(base, x) WriteReg32(base, rIEP_DIL_MTN_TAB1,x)
496 #define IEP_REGB_DIL_MTN_TAB2(base, x) WriteReg32(base, rIEP_DIL_MTN_TAB2,x)
497 #define IEP_REGB_DIL_MTN_TAB3(base, x) WriteReg32(base, rIEP_DIL_MTN_TAB3,x)
498 #define IEP_REGB_DIL_MTN_TAB4(base, x) WriteReg32(base, rIEP_DIL_MTN_TAB4,x)
499 #define IEP_REGB_DIL_MTN_TAB5(base, x) WriteReg32(base, rIEP_DIL_MTN_TAB5,x)
500 #define IEP_REGB_DIL_MTN_TAB6(base, x) WriteReg32(base, rIEP_DIL_MTN_TAB6,x)
501 #define IEP_REGB_DIL_MTN_TAB7(base, x) WriteReg32(base, rIEP_DIL_MTN_TAB7,x)
503 #define IEP_REGB_STATUS(base) ReadReg32(base, rIEP_STATUS)
505 void iep_config_lcdc_path(struct IEP_MSG *iep_msg);
507 /* system control, directly operating the device registers.*/
508 /* parameter @base need to be set to device base address. */
509 void iep_soft_rst(void *base);
510 void iep_config_done(void *base);
511 void iep_config_frm_start(void *base);
512 int iep_probe_int(void *base);
513 void iep_config_frame_end_int_clr(void *base);
514 void iep_config_frame_end_int_en(void *base);
515 struct iep_status iep_get_status(void *base);
516 int iep_get_deinterlace_mode(void *base);
517 void iep_set_deinterlace_mode(int mode, void *base);
518 void iep_switch_input_address(void *base);
520 /* generating a series of iep registers copy to the session private buffer */
521 void iep_config(iep_session *session, struct IEP_MSG *iep_msg);
523 /*#define IEP_PRINT_INFO*/