4 #include<linux/rk_fb.h>
6 #define LcdReadBit(inf, addr, msk) ((inf->regbak.addr=inf->preg->addr)&(msk))
7 #define LcdWrReg(inf, addr, val) inf->preg->addr=inf->regbak.addr=(val)
8 #define LcdRdReg(inf, addr) (inf->preg->addr)
9 #define LcdSetBit(inf, addr, msk) inf->preg->addr=((inf->regbak.addr) |= (msk))
10 #define LcdClrBit(inf, addr, msk) inf->preg->addr=((inf->regbak.addr) &= ~(msk))
11 #define LcdSetRegBit(inf, addr, msk) inf->preg->addr=((inf->preg->addr) |= (msk))
12 #define LcdMskReg(inf, addr, msk, val) (inf->regbak.addr)&=~(msk); inf->preg->addr=(inf->regbak.addr|=(val))
13 #define LCDC_REG_CFG_DONE() LcdWrReg(lcdc_dev, REG_CFG_DONE, 0x01); dsb()
15 /********************************************************************
17 ********************************************************************/
18 /* LCDCµÄ¼Ä´æÆ÷½á¹¹ */
20 typedef volatile struct tagLCDC_REG
22 /* offset 0x00~0xc0 */
23 unsigned int SYS_CFG; //0x00 system config register
24 unsigned int DSP_CTRL; //0x0c display control register
25 unsigned int BG_COLOR; //back ground color register
26 unsigned int ALPHA_CTRL; //alpha control register
27 unsigned int INT_STATUS; //0x10 Interrupt status register
28 unsigned int WIN0_COLOR_KEY_CTRL; //0x1c Win0 blending control register
29 unsigned int WIN1_COLOR_KEY_CTRL; //0x20 Win1 blending control register
30 unsigned int WIN0_YRGB_MST; //0x28 Win0 active YRGB memory start address0
31 unsigned int WIN0_CBR_MST; //0x2c Win0 active Cbr memory start address0
32 unsigned int WIN_VIR; //0x38 WIN0 virtual display width/height
33 unsigned int WIN0_ACT_INFO; //0x3C Win0 active window width/height
34 unsigned int WIN0_DSP_INFO; //0x40 Win0 display width/height on panel
35 unsigned int WIN0_DSP_ST; //0x44 Win0 display start point on panel
36 unsigned int WIN0_SCL_FACTOR_YRGB; //0x48Win0 YRGB scaling factor setting
37 unsigned int WIN0_SCL_FACTOR_CBR; //0x4c Win0 YRGB scaling factor setting
38 unsigned int WIN0_SCL_OFFSET; //0x50 Win0 Cbr scaling start point offset
39 unsigned int WIN1_RGB_MST; //0x54 Win1 active YRGB memory start address
40 unsigned int WIN1_DSP_INFO; //0x64 Win1 display width/height on panel
41 unsigned int WIN1_DSP_ST; //0x68 Win1 display start point on panel
42 unsigned int HWC_MST; //0x88 HWC memory start address
43 unsigned int HWC_DSP_ST; //0x8C HWC display start point on panel
44 unsigned int HWC_COLOR_LUT0; //0x90 Hardware cursor color 2¡¯b01 look up table 0
45 unsigned int HWC_COLOR_LUT1; //0x94 Hardware cursor color 2¡¯b10 look up table 1
46 unsigned int HWC_COLOR_LUT2; //0x98 Hardware cursor color 2¡¯b11 look up table 2
47 unsigned int DSP_HTOTAL_HS_END; //0x9c Panel scanning horizontal width and hsync pulse end point
48 unsigned int DSP_HACT_ST_END; //0xa0 Panel active horizontal scanning start/end point
49 unsigned int DSP_VTOTAL_VS_END; //0xa4 Panel scanning vertical height and vsync pulse end point
50 unsigned int DSP_VACT_ST_END; //0xa8 Panel active vertical scanning start/end point
51 unsigned int SCL_REG0; //scaler register
52 unsigned int SCL_REG1;
53 unsigned int SCL_REG2;
54 unsigned int SCL_REG3;
55 unsigned int SCL_REG4;
56 unsigned int SCL_REG5;
57 unsigned int SCL_REG6;
58 unsigned int SCL_REG7;
59 unsigned int SCL_REG8;
60 unsigned int reserve[3];
61 unsigned int REG_CFG_DONE; //0xc0 REGISTER CONFIG FINISH
63 } LCDC_REG, *pLCDC_REG;
68 #define m_W0_EN (1<<0)
69 #define m_W1_EN (1<<1)
70 #define m_HWC_EN (1<<2)
71 #define m_W0_FORMAT (7<<3)
72 #define m_W1_FORMAT (7<<6)
74 #define m_W0_AXI_OUTSTANDING_DISABLE (1<<16)
75 #define m_W1_AXI_OUTSTANDING_DISABLE (1<<17)
76 #define m_DMA_BURST_LENGTH (3<<18)
77 #define m_LCDC_STANDBY (1<<22)
79 #define m_LCDC_AXICLK_AUTO_ENABLE (1<<24) //eanble for low power
80 #define m_DSP_OUT_ZERO (1<<25)
82 #define v_W0_EN(x) (((x)&1)<<0)
83 #define v_W1_EN(x) (((x)&1)<<1)
84 #define v_HWC_EN(x) (((x)&1)<<2)
85 #define v_W0_FORMAT(x) (((x)&7)<<3)
86 #define v_W1_FORMAT(x) (((x)&7)<<6)
87 #define v_LCDC_STANDBY(x) (((x)&1)<<22)
89 #define v_LCDC_AXICLK_AUTO_ENABLE(x) (((x)&1)<<24)
90 #define v_DSP_OUT_ZERO(x) (((x)&1)<<25)
93 #define v_LCDC_DMA_STOP(x) (((x)&1)<<0)
94 #define v_HWC_RELOAD_EN(x) (((x)&1)<<2)
95 #define v_W0_AXI_OUTSTANDING_DISABLE(x) (((x)&1)<<3)
96 #define v_W1_AXI_OUTSTANDING_DISABLE(x) (((x)&1)<<4)
97 #define v_W2_AXI_OUTSTANDING_DISABLE(x) (((x)&1)<<5)
98 #define v_DMA_BURST_LENGTH(x) (((x)&3)<<6)
99 #define v_WIN0_YRGB_CHANNEL0_ID(x) (((x)&7)<<8)
100 #define v_WIN0_CBR_CHANNEL0_ID(x) (((x)&7)<<11)
101 #define v_WIN0_YRGB_CHANNEL1_ID(x) (((x)&7)<<14)
102 #define v_WIN0_CBR_CHANNEL1_ID(x) (((x)&7)<<17)
103 #define v_WIN1_YRGB_CHANNEL_ID(x) (((x)&7)<<20)
104 #define v_WIN1_CBR_CHANNEL_ID(x) (((x)&7)<<23)
105 #define v_WIN2_CHANNEL_ID(x) (((x)&7)<<26)
106 #define v_HWC_CHANNEL_ID(x) (((x)&7)<<29)
111 #define m_DISPLAY_FORMAT (3<<0)
112 #define m_BLANK_MODE (1<<2)
113 #define m_BLACK_MODE (1<<3)
114 #define m_HSYNC_POLARITY (1<<4)
115 #define m_VSYNC_POLARITY (1<<5)
116 #define m_DEN_POLARITY (1<<6)
117 #define m_DCLK_POLARITY (1<<7)
118 #define m_W0W1_POSITION_SWAP (1<<8)
119 #define m_OUTPUT_BG_SWAP (1<<9)
120 #define m_OUTPUT_RB_SWAP (1<<10)
121 #define m_OUTPUT_RG_SWAP (1<<11)
122 #define m_DITHER_UP_EN (1<<12)
123 #define m_DITHER_DOWN_MODE (1<<13)
124 #define m_DITHER_DOWN_EN (1<<14)
127 #define m_W1_INTERLACE_READ_MODE (1<<15)
128 #define m_W2_INTERLACE_READ_MODE (1<<16)
129 #define m_W0_YRGB_DEFLICK_MODE (1<<17)
130 #define m_W0_CBR_DEFLICK_MODE (1<<18)
131 #define m_W1_YRGB_DEFLICK_MODE (1<<19)
132 #define m_W1_CBR_DEFLICK_MODE (1<<20)
133 #define m_W0_ALPHA_MODE (1<<21)
134 #define m_W1_ALPHA_MODE (1<<22)
135 #define m_W2_ALPHA_MODE (1<<23)
136 #define m_W0_COLOR_SPACE_CONVERSION (3<<24)
137 #define m_W1_COLOR_SPACE_CONVERSION (3<<26)
138 #define m_W2_COLOR_SPACE_CONVERSION (1<<28)
139 #define m_YCRCB_CLIP_EN (1<<29)
140 #define m_CBR_FILTER_656 (1<<30)
142 #define v_DISPLAY_FORMAT(x) (((x)&0x3)<<0)
143 #define v_BLANK_MODE(x) (((x)&1)<<2)
144 #define v_BLACK_MODE(x) (((x)&1)<<3)
145 #define v_HSYNC_POLARITY(x) (((x)&1)<<4)
146 #define v_VSYNC_POLARITY(x) (((x)&1)<<5)
147 #define v_DEN_POLARITY(x) (((x)&1)<<6)
148 #define v_DCLK_POLARITY(x) (((x)&1)<<7)
149 #define v_W0W1_POSITION_SWAP(x) (((x)&1)<<8)
150 #define v_OUTPUT_BG_SWAP(x) (((x)&1)<<9)
151 #define v_OUTPUT_RB_SWAP(x) (((x)&1)<<10)
152 #define v_OUTPUT_RG_SWAP(x) (((x)&1)<<11)
153 #define v_DITHER_UP_EN(x) (((x)&1)<<12)
154 #define v_DITHER_DOWN_MODE(x) (((x)&1)<<13)
155 #define v_DITHER_DOWN_EN(x) (((x)&1)<<14)
157 #define v_INTERLACE_DSP_EN(x) (((x)&1)<<12)
158 #define v_INTERLACE_FIELD_POLARITY(x) (((x)&1)<<13)
159 #define v_W0_INTERLACE_READ_MODE(x) (((x)&1)<<14)
160 #define v_W1_INTERLACE_READ_MODE(x) (((x)&1)<<15)
161 #define v_W2_INTERLACE_READ_MODE(x) (((x)&1)<<16)
162 #define v_W0_YRGB_DEFLICK_MODE(x) (((x)&1)<<17)
163 #define v_W0_CBR_DEFLICK_MODE(x) (((x)&1)<<18)
164 #define v_W1_YRGB_DEFLICK_MODE(x) (((x)&1)<<19)
165 #define v_W1_CBR_DEFLICK_MODE(x) (((x)&1)<<20)
166 #define v_W0_ALPHA_MODE(x) (((x)&1)<<21)
167 #define v_W1_ALPHA_MODE(x) (((x)&1)<<22)
168 #define v_W2_ALPHA_MODE(x) (((x)&1)<<23)
169 #define v_W0_COLOR_SPACE_CONVERSION(x) (((x)&3)<<24)
170 #define v_W1_COLOR_SPACE_CONVERSION(x) (((x)&3)<<26)
171 #define v_W2_COLOR_SPACE_CONVERSION(x) (((x)&1)<<28)
172 #define v_YCRCB_CLIP_EN(x) (((x)&1)<<29)
173 #define v_CBR_FILTER_656(x) (((x)&1)<<30)
176 #define m_BG_COLOR (0xffffff<<0)
177 #define m_BG_B (0xff<<0)
178 #define m_BG_G (0xff<<8)
179 #define m_BG_R (0xff<<16)
180 #define v_BG_COLOR(x) (((x)&0xffffff)<<0)
181 #define v_BG_B(x) (((x)&0xff)<<0)
182 #define v_BG_G(x) (((x)&0xff)<<8)
183 #define v_BG_R(x) (((x)&0xff)<<16)
189 #define m_HWC_BLEND_EN (1<<0)
190 #define m_W2_BLEND_EN (1<<1)
191 #define m_W1_BLEND_EN (1<<2)
192 #define m_W0_BLEND_EN (1<<3)
193 #define m_HWC_BLEND_FACTOR (15<<4)
194 #define m_W2_BLEND_FACTOR (0xff<<8)
195 #define m_W1_BLEND_FACTOR (0xff<<16)
196 #define m_W0_BLEND_FACTOR (0xff<<24)
198 #define v_HWC_BLEND_EN(x) (((x)&1)<<0)
199 #define v_W2_BLEND_EN(x) (((x)&1)<<1)
200 #define v_W1_BLEND_EN(x) (((x)&1)<<2)
201 #define v_W0_BLEND_EN(x) (((x)&1)<<3)
202 #define v_HWC_BLEND_FACTOR(x) (((x)&15)<<4)
203 #define v_W2_BLEND_FACTOR(x) (((x)&0xff)<<8)
204 #define v_W1_BLEND_FACTOR(x) (((x)&0xff)<<16)
205 #define v_W0_BLEND_FACTOR(x) (((x)&0xff)<<24)
208 #define v_HOR_START_INT_STA (1<<0) //status
209 #define v_FRM_START_INT_STA (1<<1)
210 #define v_LINE_FLAG_INT_STA (1<<2)
211 #define v_BUS_ERR_INT_STA (1<<3)
212 #define m_HOR_START_INT_EN (1<<4) //enable
213 #define m_FRM_START_INT_EN (1<<5)
214 #define m_LINE_FLAG_INT_EN (1<<6)
215 #define m_BUS_ERR_INT_EN (1<<7)
216 #define m_HOR_START_INT_CLEAR (1<<8) //auto clear
217 #define m_FRM_START_INT_CLEAR (1<<9)
218 #define m_LINE_FLAG_INT_CLEAR (1<<10)
219 #define m_BUS_ERR_INT_CLEAR (1<<11)
220 #define m_LINE_FLAG_NUM (0xfff<<12)
221 #define v_HOR_START_INT_EN(x) (((x)&1)<<4)
222 #define v_FRM_START_INT_EN(x) (((x)&1)<<5)
223 #define v_LINE_FLAG_INT_EN(x) (((x)&1)<<6)
224 #define v_BUS_ERR_INT_EN(x) (((x)&1)<<7)
225 #define v_HOR_START_INT_CLEAR(x) (((x)&1)<<8)
226 #define v_FRM_START_INT_CLEAR(x) (((x)&1)<<9)
227 #define v_LINE_FLAG_INT_CLEAR(x) (((x)&1)<<10)
228 #define v_BUS_ERR_INT_CLEAR(x) (((x)&1)<<11)
229 #define v_LINE_FLAG_NUM(x) (((x)&0xfff)<<12)
233 #define m_WIN0_VIR (0xfff << 0)
234 #define m_WIN1_VIR (0xfff << 16)
235 //LCDC_WINx_VIR ,x is number of words of win0 virtual width
236 #define v_WIN0_ARGB888_VIRWIDTH(x) (x)
237 #define v_WIN0_RGB888_VIRWIDTH(x) (((x*3)>>2)+((x)%3))
238 #define v_WIN0_RGB565_VIRWIDTH(x) (((x)>>1) + ((x%2)?1:0))
239 #define v_WIN0_YUV_VIRWIDTH(x) (((x)>>2) +((x%4)?1:0))
241 #define v_WIN1_ARGB888_VIRWIDTH(x) (x << 16)
242 #define v_WIN1_RGB888_VIRWIDTH(x) ((((x*3)>>2)+((x)%3)) << 16)
243 #define v_WIN1_RGB565_VIRWIDTH(x) ((((x)>>1) + ((x%2)?1:0)) << 16)
244 #define v_WIN1_YUV_VIRWIDTH(x) ((((x)>>2) +((x%4)?1:0)) << 16 )
247 //LCDC_WIN0_COLOR_KEY_CTRL / LCDC_WIN1_COLOR_KEY_CTRL
248 #define m_KEYCOLOR (0xffffff<<0)
249 #define m_KEYCOLOR_B (0xff<<0)
250 #define m_KEYCOLOR_G (0xff<<8)
251 #define m_KEYCOLOR_R (0xff<<16)
252 #define m_COLORKEY_EN (1<<24)
253 #define v_KEYCOLOR(x) (((x)&0xffffff)<<0)
254 #define v_KEYCOLOR_B(x) (((x)&0xff)<<0)
255 #define v_KEYCOLOR_G(x) (((x)&0xff)<<8)
256 #define v_KEYCOLOR_R(x) (((x)&0xff)<<16)
257 #define v_COLORKEY_EN(x) (((x)&1)<<24)
259 //LCDC_DEFLICKER_SCL_OFFSET
260 #define m_W0_YRGB_VSD_OFFSET (0xff<<0)
261 #define m_W0_YRGB_VSP_OFFSET (0xff<<8)
262 #define m_W1_VSD_OFFSET (0xff<<16)
263 #define m_W1_VSP_OFFSET (0xff<<24)
264 #define v_W0_YRGB_VSD_OFFSET(x) (((x)&0xff)<<0)
265 #define v_W0_YRGB_VSP_OFFSET(x) (((x)&0xff)<<8)
266 #define v_W1_VSD_OFFSET(x) (((x)&0xff)<<16)
267 #define v_W1_VSP_OFFSET(x) (((x)&0xff)<<24)
274 #define m_W0_YRGB_CH_ID (0xF<<0)
275 #define m_W0_CBR_CH_ID (0xF<<4)
276 #define m_W1_YRGB_CH_ID (0xF<<8)
277 #define m_W2_CH_ID (0xF<<12)
278 #define m_HWC_CH_ID (0xF<<16)
279 #define v_W0_YRGB_CH_ID(x) (((x)&0xF)<<0)
280 #define v_W0_CBR_CH_ID(x) (((x)&0xF)<<4)
281 #define v_W1_YRGB_CH_ID(x) (((x)&0xF)<<8)
282 #define v_W2_CH_ID(x) (((x)&0xF)<<12)
283 #define v_HWC_CH_ID(x) (((x)&0xF)<<16)
287 #define m_WORDLO (0xffff<<0)
288 #define m_WORDHI (0xffff<<16)
289 #define v_WORDLO(x) (((x)&0xffff)<<0)
290 #define v_WORDHI(x) (((x)&0xffff)<<16)
293 //LCDC_WINx_SCL_FACTOR_Y/CBCR
294 #define v_X_SCL_FACTOR(x) ((x)<<0)
295 #define v_Y_SCL_FACTOR(x) ((x)<<16)
297 //LCDC_DSP_HTOTAL_HS_END
298 #define v_HSYNC(x) ((x)<<0) //hsync pulse width
299 #define v_HORPRD(x) ((x)<<16) //horizontal period
302 //LCDC_DSP_HACT_ST_END
303 #define v_HAEP(x) ((x)<<0) //horizontal active end point
304 #define v_HASP(x) ((x)<<16) //horizontal active start point
306 //LCDC_DSP_VTOTAL_VS_END
307 #define v_VSYNC(x) ((x)<<0)
308 #define v_VERPRD(x) ((x)<<16)
310 //LCDC_DSP_VACT_ST_END
311 #define v_VAEP(x) ((x)<<0)
312 #define v_VASP(x) ((x)<<16)
316 #define m_ACTWIDTH (0xffff<<0)
317 #define m_ACTHEIGHT (0xffff<<16)
318 #define v_ACTWIDTH(x) (((x)&0xffff)<<0)
319 #define v_ACTHEIGHT(x) (((x)&0xffff)<<16)
321 #define m_VIRST_X (0xffff<<0)
322 #define m_VIRST_Y (0xffff<<16)
323 #define v_VIRST_X(x) (((x)&0xffff)<<0)
324 #define v_VIRST_Y(x) (((x)&0xffff)<<16)
326 #define m_PANELST_X (0x3ff<<0)
327 #define m_PANELST_Y (0x3ff<<16)
328 #define v_PANELST_X(x) (((x)&0x3ff)<<0)
329 #define v_PANELST_Y(x) (((x)&0x3ff)<<16)
331 #define m_PANELWIDTH (0x3ff<<0)
332 #define m_PANELHEIGHT (0x3ff<<16)
333 #define v_PANELWIDTH(x) (((x)&0x3ff)<<0)
334 #define v_PANELHEIGHT(x) (((x)&0x3ff)<<16)
336 #define m_HWC_B (0xff<<0)
337 #define m_HWC_G (0xff<<8)
338 #define m_HWC_R (0xff<<16)
339 #define m_W0_YRGB_HSP_OFFSET (0xff<<24)
340 #define m_W0_YRGB_HSD_OFFSET (0xff<<24)
341 #define v_HWC_B(x) (((x)&0xff)<<0)
342 #define v_HWC_G(x) (((x)&0xff)<<8)
343 #define v_HWC_R(x) (((x)&0xff)<<16)
344 #define v_W0_YRGB_HSP_OFFSET(x) (((x)&0xff)<<24)
345 #define v_W0_YRGB_HSD_OFFSET(x) (((x)&0xff)<<24)
348 #define v_ACT_WIDTH(x) ((x-1)<<0)
349 #define v_ACT_HEIGHT(x) ((x-1)<<16)
352 #define v_DSP_WIDTH(x) ((x-1)<<0)
353 #define v_DSP_HEIGHT(x) ((x-1)<<16)
355 //LCDC_WIN0_DSP_ST //x,y start point of the panel scanning
356 #define v_DSP_STX(x) (x<<0)
357 #define v_DSP_STY(x) (x<<16)
359 //Panel display scanning
360 #define m_PANEL_HSYNC_WIDTH (0x3ff<<0)
361 #define m_PANEL_HORIZONTAL_PERIOD (0x3ff<<16)
362 #define v_PANEL_HSYNC_WIDTH(x) (((x)&0x3ff)<<0)
363 #define v_PANEL_HORIZONTAL_PERIOD(x) (((x)&0x3ff)<<16)
365 #define m_PANEL_END (0x3ff<<0)
366 #define m_PANEL_START (0x3ff<<16)
367 #define v_PANEL_END(x) (((x)&0x3ff)<<0)
368 #define v_PANEL_START(x) (((x)&0x3ff)<<16)
370 #define m_PANEL_VSYNC_WIDTH (0x3ff<<0)
371 #define m_PANEL_VERTICAL_PERIOD (0x3ff<<16)
372 #define v_PANEL_VSYNC_WIDTH(x) (((x)&0x3ff)<<0)
373 #define v_PANEL_VERTICAL_PERIOD(x) (((x)&0x3ff)<<16)
376 #define m_HSCALE_FACTOR (0xffff<<0)
377 #define m_VSCALE_FACTOR (0xffff<<16)
378 #define v_HSCALE_FACTOR(x) (((x)&0xffff)<<0)
379 #define v_VSCALE_FACTOR(x) (((x)&0xffff)<<16)
381 #define m_W0_CBR_HSD_OFFSET (0xff<<0)
382 #define m_W0_CBR_HSP_OFFSET (0xff<<8)
383 #define m_W0_CBR_VSD_OFFSET (0xff<<16)
384 #define m_W0_CBR_VSP_OFFSET (0xff<<24)
385 #define v_W0_CBR_HSD_OFFSET(x) (((x)&0xff)<<0)
386 #define v_W0_CBR_HSP_OFFSET(x) (((x)&0xff)<<8)
387 #define v_W0_CBR_VSD_OFFSET(x) (((x)&0xff)<<16)
388 #define v_W0_CBR_VSP_OFFSET(x) (((x)&0xff)<<24)
392 #define m_SCL_DSP_ZERO (1<<4)
393 #define m_SCL_DEN_INVERT (1<<3)
394 #define m_SCL_SYNC_INVERT (1<<2)
395 #define m_SCL_DCLK_INVERT (1<<1)
396 #define m_SCL_EN (1<<0)
397 #define v_SCL_DSP_ZERO(x) (((x)&1)<<4)
398 #define v_SCL_DEN_INVERT(x) (((x)&1)<<3)
399 #define v_SCL_SYNC_INVERT(x) (((x)&1)<<2)
400 #define v_SCL_DCLK_INVERT(x) (((x)&1)<<1)
401 #define v_SCL_EN(x) (((x)&1)<<0)
404 #define m_SCL_V_FACTOR (0x3fff<<16)
405 #define m_SCL_H_FACTOR (0x3fff<<0)
406 #define v_SCL_V_FACTOR(x) (((x)&0x3fff)<<16)
407 #define v_SCL_H_FACTOR(x) (((x)&0x3fff)<<0)
411 #define m_SCL_DSP_FRAME_VST (0xfff<<16)
412 #define m_SCL_DSP_FRAME_HST (0xfff<<0)
413 #define v_SCL_DSP_FRAME_VST(x) (((x)&0xfff)<<16)
414 #define v_SCL_DSP_FRAME_HST(x) (((x)&0xfff)<<0)
417 #define m_SCL_DSP_HS_END (0xff<<16)
418 #define m_SCL_DSP_HTOTAL (0xfff<<0)
419 #define v_SCL_DSP_HS_END(x) (((x)&0xff)<<16)
420 #define v_SCL_DSP_HTOTAL(x) (((x)&0xfff)<<0)
423 #define m_SCL_DSP_HACT_ST (0x3ff<<16)
424 #define m_SCL_DSP_HACT_END (0xfff<<0)
425 #define v_SCL_DSP_HACT_ST(x) (((x)&0x3ff)<<16)
426 #define v_SCL_DSP_HACT_END(x) (((x)&0xfff)<<0)
429 #define m_SCL_DSP_VS_END (0xff<<16)
430 #define m_SCL_DSP_VTOTAL (0xfff<<0)
431 #define v_SCL_DSP_VS_END(x) (((x)&0xff)<<16)
432 #define v_SCL_DSP_VTOTAL(x) (((x)&0xfff)<<0)
435 #define m_SCL_DSP_VACT_ST (0xff<<16)
436 #define m_SCL_DSP_VACT_END (0xfff<<0)
437 #define v_SCL_DSP_VACT_ST(x) (((x)&0xff)<<16)
438 #define v_SCL_DSP_VACT_END(x) (((x)&0xfff)<<0)
442 #define m_SCL_DSP_HBOR_ST (0x3ff<<16)
443 #define m_SCL_DSP_HBOR_END (0xfff<<0)
444 #define v_SCL_DSP_HBOR_ST(x) (((x)&0x3ff)<<16)
445 #define v_SCL_DSP_HBOR_END(x) (((x)&0xfff)<<0)
449 #define m_SCL_DSP_VBOR_ST (0xff<<16)
450 #define m_SCL_DSP_VBOR_END (0xfff<<0)
451 #define v_SCL_DSP_VBOR_ST(x) (((x)&0xff)<<16)
452 #define v_SCL_DSP_VBOR_END(x) (((x)&0xfff)<<0)
458 #define CalScale(x, y) (((u32)(x)*0x1000)/(y))
459 struct rk2928_lcdc_device{
461 struct rk_lcdc_device_driver driver;
464 LCDC_REG *preg; // LCDC reg base address and backup reg
467 void __iomem *reg_vir_base; // virtual basic address of lcdc register
468 u32 reg_phy_base; // physical basic address of lcdc register
469 u32 len; // physical map length of lcdc register
470 spinlock_t reg_lock; //one time only one process allowed to config the register
471 bool clk_on; //if aclk or hclk is closed ,acess to register is not allowed
472 u8 atv_layer_cnt; //active layer counter,when atv_layer_cnt = 0,disable lcdc
475 struct clk *pd; //lcdc power domain
476 struct clk *hclk; //lcdc AHP clk
477 struct clk *dclk; //lcdc dclk
478 struct clk *aclk; //lcdc share memory frequency
479 struct clk *sclk; //scale clk
480 struct clk *aclk_parent; //lcdc aclk divider frequency source
481 struct clk *aclk_ddr_lcdc; //DDR LCDC AXI clock disable.
482 struct clk *aclk_disp_matrix; //DISPLAY matrix AXI clock disable.
483 struct clk *hclk_cpu_display; //CPU DISPLAY AHB bus clock disable.
484 struct clk *pd_display; // display power domain
490 struct rk2928_lcdc_device lcdc0;
496 volatile u32 y_offset;
497 volatile u32 c_offset;
505 u32 xpos; //size in panel
507 u32 xsize; //start point in panel
509 enum data_format format;
511 wait_queue_head_t wait;
512 struct win_set mirror;
513 struct win_set displ;