drivers/video/rockchip/lcdc/rk3036_lcdc.c

   1 /*
   2  * drivers/video/rockchip/lcdc/rk3036_lcdc.c
   3  *
   4  * Copyright (C) 2014 ROCKCHIP, Inc.
   5  * Author:zhengyang<zhengyang@rock-chips.com>
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/kernel.h>
  19 #include <linux/errno.h>
  20 #include <linux/string.h>
  21 #include <linux/mm.h>
  22 #include <linux/slab.h>
  23 #include <linux/device.h>
  24 #include <linux/delay.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/clk.h>
  29 #include <asm/div64.h>
  30 #include <linux/uaccess.h>
  31 #include <linux/rockchip/cpu.h>
  32 #include <linux/rockchip/iomap.h>
  33 #include <linux/rockchip/grf.h>
  34 #include <linux/rockchip/common.h>
  35 #include <dt-bindings/clock/rk_system_status.h>
  36 #if defined(CONFIG_ION_ROCKCHIP)
  37 #include <linux/rockchip-iovmm.h>
  38 #endif
  39 #include "rk3036_lcdc.h"
  40
  41 static int dbg_thresd;
  42 module_param(dbg_thresd, int, S_IRUGO | S_IWUSR);
  43
  44 #define DBG(level, x...) do {                   \
  45         if (unlikely(dbg_thresd >= level))      \
  46                 dev_info(dev_drv->dev, x);              \
  47         } while (0)
  48
  49 #define grf_writel(offset, v)   do { \
  50         writel_relaxed(v, RK_GRF_VIRT + offset); \
  51         dsb(); \
  52         } while (0)
  53
  54 static struct rk_lcdc_win lcdc_win[] = {
  55         [0] = {
  56                .name = "win0",
  57                .id = 0,
  58                .support_3d = false,
  59                },
  60         [1] = {
  61                .name = "win1",
  62                .id = 1,
  63                .support_3d = false,
  64                },
  65         [2] = {
  66                .name = "hwc",
  67                .id = 2,
  68                .support_3d = false,
  69                },
  70 };
  71
  72 static irqreturn_t rk3036_lcdc_isr(int irq, void *dev_id)
  73 {
  74         struct lcdc_device *lcdc_dev =
  75             (struct lcdc_device *)dev_id;
  76         ktime_t timestamp = ktime_get();
  77         u32 int_reg = lcdc_readl(lcdc_dev, INT_STATUS);
  78
  79         if (int_reg & m_FS_INT_STA) {
  80                 timestamp = ktime_get();
  81                 lcdc_msk_reg(lcdc_dev, INT_STATUS, m_FS_INT_CLEAR,
  82                              v_FS_INT_CLEAR(1));
  83                 /*if (lcdc_dev->driver.wait_fs) {*/
  84                 if (0) {
  85                         spin_lock(&(lcdc_dev->driver.cpl_lock));
  86                         complete(&(lcdc_dev->driver.frame_done));
  87                         spin_unlock(&(lcdc_dev->driver.cpl_lock));
  88                 }
  89                 lcdc_dev->driver.vsync_info.timestamp = timestamp;
  90                 wake_up_interruptible_all(&lcdc_dev->driver.vsync_info.wait);
  91
  92         } else if (int_reg & m_LF_INT_STA) {
  93                 lcdc_msk_reg(lcdc_dev, INT_STATUS, m_LF_INT_CLEAR,
  94                              v_LF_INT_CLEAR(1));
  95         }
  96         return IRQ_HANDLED;
  97 }
  98
  99 static int rk3036_lcdc_clk_enable(struct lcdc_device *lcdc_dev)
 100 {
 101 #ifdef CONFIG_RK_FPGA
 102         lcdc_dev->clk_on = 1;
 103         return 0;
 104 #endif
 105         if (!lcdc_dev->clk_on) {
 106                 clk_prepare_enable(lcdc_dev->hclk);
 107                 clk_prepare_enable(lcdc_dev->dclk);
 108                 clk_prepare_enable(lcdc_dev->aclk);
 109 /*              clk_prepare_enable(lcdc_dev->pd);*/
 110                 spin_lock(&lcdc_dev->reg_lock);
 111                 lcdc_dev->clk_on = 1;
 112                 spin_unlock(&lcdc_dev->reg_lock);
 113         }
 114
 115         return 0;
 116 }
 117
 118 static int rk3036_lcdc_clk_disable(struct lcdc_device *lcdc_dev)
 119 {
 120 #ifdef CONFIG_RK_FPGA
 121         lcdc_dev->clk_on = 0;
 122         return 0;
 123 #endif
 124         if (lcdc_dev->clk_on) {
 125                 spin_lock(&lcdc_dev->reg_lock);
 126                 lcdc_dev->clk_on = 0;
 127                 spin_unlock(&lcdc_dev->reg_lock);
 128                 mdelay(25);
 129                 clk_disable_unprepare(lcdc_dev->dclk);
 130                 clk_disable_unprepare(lcdc_dev->hclk);
 131                 clk_disable_unprepare(lcdc_dev->aclk);
 132 /*              clk_disable_unprepare(lcdc_dev->pd);*/
 133         }
 134
 135         return 0;
 136 }
 137
 138 static int rk3036_lcdc_enable_irq(struct rk_lcdc_driver *dev_drv)
 139 {
 140         u32 mask, val;
 141         struct lcdc_device *lcdc_dev = container_of(dev_drv,
 142                                         struct lcdc_device, driver);
 143         mask = m_FS_INT_CLEAR | m_FS_INT_EN;
 144         val = v_FS_INT_CLEAR(1) | v_FS_INT_EN(1);
 145         lcdc_msk_reg(lcdc_dev, INT_STATUS, mask, val);
 146         return 0;
 147 }
 148 /*
 149 static int rk3036_lcdc_disable_irq(struct lcdc_device *lcdc_dev)
 150 {
 151         u32 mask, val;
 152
 153         spin_lock(&lcdc_dev->reg_lock);
 154         if (likely(lcdc_dev->clk_on)) {
 155                 mask = m_FS_INT_CLEAR | m_FS_INT_EN;
 156                 val = v_FS_INT_CLEAR(0) | v_FS_INT_EN(0);
 157                 lcdc_msk_reg(lcdc_dev, INT_STATUS, mask, val);
 158                 spin_unlock(&lcdc_dev->reg_lock);
 159         } else {
 160                 spin_unlock(&lcdc_dev->reg_lock);
 161         }
 162         mdelay(1);
 163         return 0;
 164 }*/
 165
 166 static void rk_lcdc_read_reg_defalut_cfg(struct lcdc_device
 167                                              *lcdc_dev)
 168 {
 169         int reg = 0;
 170         u32 value = 0;
 171
 172         spin_lock(&lcdc_dev->reg_lock);
 173         for (reg = 0; reg < 0xe0; reg += 4)
 174                 value = lcdc_readl(lcdc_dev, reg);
 175
 176         spin_unlock(&lcdc_dev->reg_lock);
 177 }
 178
 179 static int rk3036_lcdc_alpha_cfg(struct lcdc_device *lcdc_dev)
 180 {
 181         int win0_top = 0;
 182         u32 mask, val;
 183         enum data_format win0_format = lcdc_dev->driver.win[0]->area[0].format;
 184         enum data_format win1_format = lcdc_dev->driver.win[1]->area[0].format;
 185
 186         int win0_alpha_en = ((win0_format == ARGB888) ||
 187                                 (win0_format == ABGR888)) ? 1 : 0;
 188         int win1_alpha_en = ((win1_format == ARGB888) ||
 189                                 (win1_format == ABGR888)) ? 1 : 0;
 190         int atv_layer_cnt = lcdc_dev->driver.win[0]->state +
 191                         lcdc_dev->driver.win[1]->state;
 192         u32 *_pv = (u32 *)lcdc_dev->regsbak;
 193
 194         _pv += (DSP_CTRL0 >> 2);
 195         win0_top = ((*_pv) & (m_WIN0_TOP)) >> 8;
 196
 197         if (win0_top && (atv_layer_cnt >= 2) && (win0_alpha_en)) {
 198                 mask =  m_WIN0_ALPHA_EN | m_WIN1_ALPHA_EN |
 199                         m_WIN1_PREMUL_SCALE;
 200                 val = v_WIN0_ALPHA_EN(1) | v_WIN1_ALPHA_EN(0) |
 201                         v_WIN1_PREMUL_SCALE(0);
 202                 lcdc_msk_reg(lcdc_dev, ALPHA_CTRL, mask, val);
 203
 204                 mask = m_WIN0_ALPHA_MODE | m_PREMUL_ALPHA_ENABLE |
 205                         m_ALPHA_MODE_SEL1;
 206                 val = v_WIN0_ALPHA_MODE(1) | v_PREMUL_ALPHA_ENABLE(1) |
 207                         v_ALPHA_MODE_SEL1(0);
 208                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
 209         } else if ((!win0_top) && (atv_layer_cnt >= 2) &&
 210                    (win1_alpha_en)) {
 211                 mask =  m_WIN0_ALPHA_EN | m_WIN1_ALPHA_EN |
 212                         m_WIN1_PREMUL_SCALE;
 213                 val = v_WIN0_ALPHA_EN(0) | v_WIN1_ALPHA_EN(1) |
 214                         v_WIN1_PREMUL_SCALE(0);
 215                 lcdc_msk_reg(lcdc_dev, ALPHA_CTRL, mask, val);
 216
 217                 mask = m_WIN1_ALPHA_MODE | m_PREMUL_ALPHA_ENABLE |
 218                         m_ALPHA_MODE_SEL1;
 219                 val = v_WIN1_ALPHA_MODE(1) | v_PREMUL_ALPHA_ENABLE(1) |
 220                         v_ALPHA_MODE_SEL1(0);
 221                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
 222         } else {
 223                 mask = m_WIN0_ALPHA_EN | m_WIN1_ALPHA_EN;
 224                 val = v_WIN0_ALPHA_EN(0) | v_WIN1_ALPHA_EN(0);
 225                 lcdc_msk_reg(lcdc_dev, ALPHA_CTRL, mask, val);
 226         }
 227
 228         if (lcdc_dev->driver.win[2]->state == 1) {
 229                 mask =  m_HWC_ALPAH_EN;
 230                 val = v_HWC_ALPAH_EN(1);
 231                 lcdc_msk_reg(lcdc_dev, ALPHA_CTRL, mask, val);
 232
 233                 mask =  m_HWC_ALPHA_MODE;
 234                 val = v_HWC_ALPHA_MODE(1);
 235                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
 236         } else {
 237                 mask =  m_HWC_ALPAH_EN;
 238                 val = v_HWC_ALPAH_EN(0);
 239                 lcdc_msk_reg(lcdc_dev, ALPHA_CTRL, mask, val);
 240         }
 241
 242         return 0;
 243 }
 244
 245 static void lcdc_layer_update_regs(struct lcdc_device *lcdc_dev,
 246                                    struct rk_lcdc_win *win)
 247 {
 248         u32 mask, val;
 249         int hwc_size;
 250
 251         if (win->state == 1) {
 252                 if (win->id == 0) {
 253                         mask = m_WIN0_EN | m_WIN0_FORMAT | m_WIN0_RB_SWAP;
 254                         val = v_WIN0_EN(win->state) |
 255                               v_WIN0_FORMAT(win->area[0].fmt_cfg) |
 256                               v_WIN0_RB_SWAP(win->area[0].swap_rb);
 257                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
 258                         lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_YRGB,
 259                                     v_X_SCL_FACTOR(win->scale_yrgb_x) |
 260                                     v_Y_SCL_FACTOR(win->scale_yrgb_y));
 261                         lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_CBR,
 262                                     v_X_SCL_FACTOR(win->scale_cbcr_x) |
 263                                     v_Y_SCL_FACTOR(win->scale_cbcr_y));
 264                         lcdc_msk_reg(lcdc_dev, WIN0_VIR,
 265                                      m_YRGB_VIR | m_CBBR_VIR,
 266                                      v_YRGB_VIR(win->area[0].y_vir_stride) |
 267                                      v_CBBR_VIR(win->area[0].uv_vir_stride));
 268                         lcdc_writel(lcdc_dev, WIN0_ACT_INFO,
 269                                     v_ACT_WIDTH(win->area[0].xact) |
 270                                     v_ACT_HEIGHT(win->area[0].yact));
 271                         lcdc_writel(lcdc_dev, WIN0_DSP_ST,
 272                                     v_DSP_STX(win->area[0].dsp_stx) |
 273                                     v_DSP_STY(win->area[0].dsp_sty));
 274                         lcdc_writel(lcdc_dev, WIN0_DSP_INFO,
 275                                     v_DSP_WIDTH(win->post_cfg.xsize) |
 276                                     v_DSP_HEIGHT(win->post_cfg.ysize));
 277
 278                         lcdc_writel(lcdc_dev, WIN0_YRGB_MST,
 279                                     win->area[0].y_addr);
 280                         lcdc_writel(lcdc_dev, WIN0_CBR_MST,
 281                                     win->area[0].uv_addr);
 282                 } else if (win->id == 1) {
 283                         mask = m_WIN1_EN | m_WIN1_FORMAT | m_WIN1_RB_SWAP;
 284                         val = v_WIN1_EN(win->state) |
 285                               v_WIN1_FORMAT(win->area[0].fmt_cfg) |
 286                               v_WIN1_RB_SWAP(win->area[0].swap_rb);
 287                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
 288                         lcdc_writel(lcdc_dev, WIN1_SCL_FACTOR_YRGB,
 289                                     v_X_SCL_FACTOR(win->scale_yrgb_x) |
 290                                     v_Y_SCL_FACTOR(win->scale_yrgb_y));
 291
 292                         lcdc_msk_reg(lcdc_dev, WIN1_VIR, m_YRGB_VIR,
 293                                      v_YRGB_VIR(win->area[0].y_vir_stride));
 294                         lcdc_writel(lcdc_dev, WIN1_ACT_INFO,
 295                                     v_ACT_WIDTH(win->area[0].xact) |
 296                                     v_ACT_HEIGHT(win->area[0].yact));
 297                         lcdc_writel(lcdc_dev, WIN1_DSP_INFO,
 298                                     v_DSP_WIDTH(win->post_cfg.xsize) |
 299                                     v_DSP_HEIGHT(win->post_cfg.ysize));
 300                         lcdc_writel(lcdc_dev, WIN1_DSP_ST,
 301                                     v_DSP_STX(win->area[0].dsp_stx) |
 302                                     v_DSP_STY(win->area[0].dsp_sty));
 303                         lcdc_writel(lcdc_dev, WIN1_MST, win->area[0].y_addr);
 304                 } else if (win->id == 2) {
 305                         mask = m_HWC_EN | m_HWC_LODAD_EN;
 306                         val = v_HWC_EN(win->state) | v_HWC_LODAD_EN(1);
 307                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
 308                         if ((win->area[0].xsize == 32) &&
 309                             (win->area[0].ysize == 32))
 310                                 hwc_size = 0;
 311                         else if ((win->area[0].xsize == 64) &&
 312                                  (win->area[0].ysize == 64))
 313                                 hwc_size = 1;
 314                         else
 315                                 dev_err(lcdc_dev->dev,
 316                                         "unsupport hwc size:x=%d,y=%d\n",
 317                                         win->area[0].xsize,
 318                                         win->area[0].ysize);
 319                         lcdc_writel(lcdc_dev, HWC_DSP_ST,
 320                                     v_DSP_STX(win->area[0].dsp_stx) |
 321                                     v_DSP_STY(win->area[0].dsp_sty));
 322                         lcdc_writel(lcdc_dev, HWC_MST, win->area[0].y_addr);
 323                 }
 324         } else {
 325                 win->area[0].y_addr = 0;
 326                 win->area[0].uv_addr = 0;
 327                 if (win->id == 0) {
 328                         lcdc_msk_reg(lcdc_dev,
 329                                      SYS_CTRL, m_WIN0_EN, v_WIN0_EN(0));
 330                         lcdc_writel(lcdc_dev, WIN0_YRGB_MST,
 331                                     win->area[0].y_addr);
 332                         lcdc_writel(lcdc_dev, WIN0_CBR_MST,
 333                                     win->area[0].uv_addr);
 334                 } else if (win->id == 1) {
 335                         lcdc_msk_reg(lcdc_dev,
 336                                      SYS_CTRL, m_WIN1_EN, v_WIN1_EN(0));
 337                         lcdc_writel(lcdc_dev, WIN1_MST, win->area[0].y_addr);
 338                 } else if (win->id == 2) {
 339                         lcdc_msk_reg(lcdc_dev,
 340                                      SYS_CTRL, m_HWC_EN | m_HWC_LODAD_EN,
 341                                      v_HWC_EN(0) | v_HWC_LODAD_EN(0));
 342                         lcdc_writel(lcdc_dev, HWC_MST, win->area[0].y_addr);
 343                 }
 344         }
 345         rk3036_lcdc_alpha_cfg(lcdc_dev);
 346 }
 347
 348 static void lcdc_layer_enable(struct lcdc_device *lcdc_dev,
 349                               unsigned int win_id, bool open)
 350 {
 351         spin_lock(&lcdc_dev->reg_lock);
 352         if (likely(lcdc_dev->clk_on) &&
 353             lcdc_dev->driver.win[win_id]->state != open) {
 354                 if (open) {
 355                         if (!lcdc_dev->atv_layer_cnt) {
 356                                 dev_info(lcdc_dev->dev,
 357                                          "wakeup from standby!\n");
 358                                 lcdc_dev->standby = 0;
 359                         }
 360                         lcdc_dev->atv_layer_cnt |= (1 << win_id);
 361                 } else if ((lcdc_dev->atv_layer_cnt & (1 << win_id)) && (!open)) {
 362                         lcdc_dev->atv_layer_cnt &= ~(1 << win_id);
 363                 }
 364                 lcdc_dev->driver.win[win_id]->state = open;
 365                 if (!open) {
 366                         lcdc_layer_update_regs(lcdc_dev,
 367                                                lcdc_dev->driver.win[win_id]);
 368                         lcdc_cfg_done(lcdc_dev);
 369                 }
 370                 /*if no layer used,disable lcdc*/
 371                 if (!lcdc_dev->atv_layer_cnt) {
 372                         dev_info(lcdc_dev->dev,
 373                                  "no layer is used, go to standby!\n");
 374                         lcdc_dev->standby = 1;
 375                 }
 376         }
 377         spin_unlock(&lcdc_dev->reg_lock);
 378 }
 379 /*
 380 static int rk3036_lcdc_reg_update(struct rk_lcdc_driver *dev_drv)
 381 {
 382         struct lcdc_device *lcdc_dev =
 383             container_of(dev_drv, struct lcdc_device, driver);
 384         struct rk_lcdc_win *win0 = lcdc_dev->driver.win[0];
 385         struct rk_lcdc_win *win1 = lcdc_dev->driver.win[1];
 386         int timeout;
 387         unsigned long flags;
 388
 389         spin_lock(&lcdc_dev->reg_lock);
 390         if (likely(lcdc_dev->clk_on)) {
 391                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_LCDC_STANDBY,
 392                              v_LCDC_STANDBY(lcdc_dev->standby));
 393                 lcdc_layer_update_regs(lcdc_dev, win0);
 394                 lcdc_layer_update_regs(lcdc_dev, win1);
 395                 rk3036_lcdc_alpha_cfg(lcdc_dev);
 396                 lcdc_cfg_done(lcdc_dev);
 397         }
 398         spin_unlock(&lcdc_dev->reg_lock);
 399         if (0) {
 400                 spin_lock_irqsave(&dev_drv->cpl_lock, flags);
 401                 init_completion(&dev_drv->frame_done);
 402                 spin_unlock_irqrestore(&dev_drv->cpl_lock, flags);
 403                 timeout = wait_for_completion_timeout(&dev_drv->frame_done,
 404                                                       msecs_to_jiffies
 405                                                       (dev_drv->cur_screen->ft
 406                                                        + 5));
 407                 if (!timeout && (!dev_drv->frame_done.done)) {
 408                         dev_warn(lcdc_dev->dev,
 409                                  "wait for new frame start time out!\n");
 410                         return -ETIMEDOUT;
 411                 }
 412         }
 413         DBG(2, "%s for lcdc%d\n", __func__, lcdc_dev->id);
 414         return 0;
 415 }
 416 */
 417 static void rk3036_lcdc_reg_restore(struct lcdc_device *lcdc_dev)
 418 {
 419         memcpy((u8 *)lcdc_dev->regs, (u8 *)lcdc_dev->regsbak, 0xe0);
 420 }
 421
 422 static void rk3036_lcdc_mmu_en(struct rk_lcdc_driver *dev_drv)
 423 {
 424         u32 mask, val;
 425         struct lcdc_device *lcdc_dev =
 426             container_of(dev_drv, struct lcdc_device, driver);
 427
 428         /*spin_lock(&lcdc_dev->reg_lock);*/
 429         if (likely(lcdc_dev->clk_on)) {
 430                 mask = m_MMU_EN | m_AXI_MAX_OUTSTANDING_EN |
 431                         m_AXI_OUTSTANDING_MAX_NUM;
 432                 val = v_MMU_EN(1) | v_AXI_OUTSTANDING_MAX_NUM(31) |
 433                         v_AXI_MAX_OUTSTANDING_EN(1);
 434                 lcdc_msk_reg(lcdc_dev, AXI_BUS_CTRL, mask, val);
 435         }
 436         /*spin_unlock(&lcdc_dev->reg_lock);*/
 437 }
 438
 439 static int rk3036_lcdc_set_hwc_lut(struct rk_lcdc_driver *dev_drv,
 440                                    int *hwc_lut, int mode)
 441 {
 442         int i = 0;
 443         int __iomem *c;
 444         int v;
 445         int len = 256*4;
 446
 447         struct lcdc_device *lcdc_dev =
 448                         container_of(dev_drv, struct lcdc_device, driver);
 449         if (dev_drv->hwc_lut == NULL)
 450                 dev_drv->hwc_lut = devm_kzalloc(lcdc_dev->dev, len, GFP_KERNEL);
 451
 452         spin_lock(&lcdc_dev->reg_lock);
 453         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_HWC_LUT_EN, v_HWC_LUT_EN(0));
 454         lcdc_cfg_done(lcdc_dev);
 455         mdelay(25);
 456         for (i = 0; i < 256; i++) {
 457                 if (mode == 1)
 458                         dev_drv->hwc_lut[i] = hwc_lut[i];
 459                 v = dev_drv->hwc_lut[i];
 460                 c = lcdc_dev->hwc_lut_addr_base + i;
 461                 writel_relaxed(v, c);
 462         }
 463         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_HWC_LUT_EN, v_HWC_LUT_EN(1));
 464         lcdc_cfg_done(lcdc_dev);
 465         spin_unlock(&lcdc_dev->reg_lock);
 466         return 0;
 467 }
 468
 469 #if 0
 470 static int rk3036_lcdc_set_dclk(struct rk_lcdc_driver *dev_drv)
 471 {
 472 #ifdef CONFIG_RK_FPGA
 473         return 0;
 474 #endif
 475         int ret, fps;
 476         struct lcdc_device *lcdc_dev =
 477             container_of(dev_drv, struct lcdc_device, driver);
 478         struct rk_screen *screen = dev_drv->cur_screen;
 479
 480         ret = clk_set_rate(lcdc_dev->dclk, screen->mode.pixclock);
 481         if (ret)
 482                 dev_err(dev_drv->dev,
 483                         "set lcdc%d dclk failed\n", lcdc_dev->id);
 484         lcdc_dev->pixclock =
 485                  div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
 486         lcdc_dev->driver.pixclock = lcdc_dev->pixclock;
 487
 488         fps = rk_fb_calc_fps(screen, lcdc_dev->pixclock);
 489         screen->ft = 1000 / fps;
 490         dev_info(lcdc_dev->dev, "%s: dclk:%lu>>fps:%d ",
 491                  lcdc_dev->driver.name, clk_get_rate(lcdc_dev->dclk), fps);
 492         return 0;
 493 }
 494 #endif
 495 /********do basic init*********/
 496 static int rk3036_lcdc_pre_init(struct rk_lcdc_driver *dev_drv)
 497 {
 498         struct lcdc_device *lcdc_dev = container_of(dev_drv,
 499                                 struct lcdc_device, driver);
 500
 501         if (lcdc_dev->pre_init)
 502                 return 0;
 503         lcdc_dev->hclk = devm_clk_get(lcdc_dev->dev, "hclk_lcdc");
 504         lcdc_dev->aclk = devm_clk_get(lcdc_dev->dev, "aclk_lcdc");
 505         lcdc_dev->dclk = devm_clk_get(lcdc_dev->dev, "dclk_lcdc");
 506 /*      lcdc_dev->pd   = devm_clk_get(lcdc_dev->dev, "pd_lcdc"); */
 507
 508         if (/*IS_ERR(lcdc_dev->pd) ||*/ (IS_ERR(lcdc_dev->aclk)) ||
 509             (IS_ERR(lcdc_dev->dclk)) || (IS_ERR(lcdc_dev->hclk))) {
 510                 dev_err(lcdc_dev->dev, "failed to get lcdc%d clk source\n",
 511                         lcdc_dev->id);
 512         }
 513
 514         rk_disp_pwr_enable(dev_drv);
 515         rk3036_lcdc_clk_enable(lcdc_dev);
 516
 517         /*backup reg config at uboot*/
 518         rk_lcdc_read_reg_defalut_cfg(lcdc_dev);
 519         if (lcdc_readl(lcdc_dev, AXI_BUS_CTRL) & m_TVE_DAC_DCLK_EN)
 520                 dev_drv->cur_screen->type = SCREEN_TVOUT;
 521
 522         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_AUTO_GATING_EN,
 523                      v_AUTO_GATING_EN(0));
 524         lcdc_cfg_done(lcdc_dev);
 525         if (dev_drv->iommu_enabled)
 526                 /*disable win0 to workaround iommu pagefault*/
 527                 lcdc_layer_enable(lcdc_dev, 0, 0);
 528         lcdc_dev->pre_init = true;
 529
 530         return 0;
 531 }
 532
 533 static int rk3036_load_screen(struct rk_lcdc_driver *dev_drv, bool initscreen)
 534 {
 535         int ret = -EINVAL;
 536         int fps;
 537         u16 face = 0;
 538         struct lcdc_device *lcdc_dev = container_of(dev_drv,
 539                                                 struct lcdc_device, driver);
 540         struct rk_screen *screen = dev_drv->cur_screen;
 541         u16 right_margin = screen->mode.right_margin;
 542         u16 left_margin = screen->mode.left_margin;
 543         u16 lower_margin = screen->mode.lower_margin;
 544         u16 upper_margin = screen->mode.upper_margin;
 545         u16 x_res = screen->mode.xres;
 546         u16 y_res = screen->mode.yres;
 547         u32 mask, val;
 548
 549         spin_lock(&lcdc_dev->reg_lock);
 550         if (likely(lcdc_dev->clk_on)) {
 551                 switch (screen->type) {
 552                 case SCREEN_HDMI:
 553                         mask = m_HDMI_DCLK_EN;
 554                         val = v_HDMI_DCLK_EN(1);
 555                         if (screen->pixelrepeat) {
 556                                 mask |= m_CORE_CLK_DIV_EN;
 557                                 val |= v_CORE_CLK_DIV_EN(1);
 558                         } else {
 559                                 mask |= m_CORE_CLK_DIV_EN;
 560                                 val |= v_CORE_CLK_DIV_EN(0);
 561                         }
 562                         lcdc_msk_reg(lcdc_dev, AXI_BUS_CTRL, mask, val);
 563                         mask = (1 << 4) | (1 << 5) | (1 << 6);
 564                         val = (screen->pin_hsync << 4) |
 565                                 (screen->pin_vsync << 5) |
 566                                 (screen->pin_den << 6);
 567                         grf_writel(RK3036_GRF_SOC_CON2, (mask << 16) | val);
 568                         break;
 569                 case SCREEN_TVOUT:
 570                         mask = m_TVE_DAC_DCLK_EN;
 571                         val = v_TVE_DAC_DCLK_EN(1);
 572                         if (screen->pixelrepeat) {
 573                                 mask |= m_CORE_CLK_DIV_EN;
 574                                 val |= v_CORE_CLK_DIV_EN(1);
 575                         } else {
 576                                 mask |= m_CORE_CLK_DIV_EN;
 577                                 val |= v_CORE_CLK_DIV_EN(0);
 578                         }
 579                         lcdc_msk_reg(lcdc_dev, AXI_BUS_CTRL, mask, val);
 580                         if ((x_res == 720) && (y_res == 576)) {
 581                                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
 582                                              m_TVE_MODE, v_TVE_MODE(TV_PAL));
 583                         } else if ((x_res == 720) && (y_res == 480)) {
 584                                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
 585                                              m_TVE_MODE, v_TVE_MODE(TV_NTSC));
 586                         } else {
 587                                 dev_err(lcdc_dev->dev,
 588                                         "unsupported video timing!\n");
 589                                 return -1;
 590                         }
 591                         break;
 592                 default:
 593                         dev_err(lcdc_dev->dev, "un supported interface!\n");
 594                         break;
 595                 }
 596
 597                 mask = m_DSP_OUT_FORMAT | m_HSYNC_POL | m_VSYNC_POL |
 598                     m_DEN_POL | m_DCLK_POL;
 599                 val = v_DSP_OUT_FORMAT(face) |
 600                         v_HSYNC_POL(screen->pin_hsync) |
 601                         v_VSYNC_POL(screen->pin_vsync) |
 602                         v_DEN_POL(screen->pin_den) |
 603                         v_DCLK_POL(screen->pin_dclk);
 604                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
 605
 606                 mask = m_BG_COLOR | m_DSP_BG_SWAP | m_DSP_RB_SWAP |
 607                     m_DSP_RG_SWAP | m_DSP_DELTA_SWAP |
 608                     m_DSP_DUMMY_SWAP | m_BLANK_EN;
 609
 610                 val = v_BG_COLOR(0x000000) | v_DSP_BG_SWAP(screen->swap_gb) |
 611                     v_DSP_RB_SWAP(screen->swap_rb) |
 612                     v_DSP_RG_SWAP(screen->swap_rg) |
 613                     v_DSP_DELTA_SWAP(screen->swap_delta) |
 614                                      v_DSP_DUMMY_SWAP(screen->swap_dumy) |
 615                                                       v_BLANK_EN(0) |
 616                                      v_BLACK_EN(0);
 617                 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
 618                 val =
 619                     v_HSYNC(screen->mode.hsync_len) | v_HORPRD(screen->mode.
 620                                                                hsync_len +
 621                                                                left_margin +
 622                                                                x_res +
 623                                                                right_margin);
 624                 lcdc_writel(lcdc_dev, DSP_HTOTAL_HS_END, val);
 625                 val = v_HAEP(screen->mode.hsync_len + left_margin + x_res) |
 626                     v_HASP(screen->mode.hsync_len + left_margin);
 627                 lcdc_writel(lcdc_dev, DSP_HACT_ST_END, val);
 628
 629                 if (screen->mode.vmode & FB_VMODE_INTERLACED) {
 630                         /*First Field Timing*/
 631                         lcdc_writel(lcdc_dev, DSP_VTOTAL_VS_END,
 632                                     v_VSYNC(screen->mode.vsync_len) |
 633                                     v_VERPRD(2 * (screen->mode.vsync_len +
 634                                                   upper_margin + lower_margin)
 635                                              + y_res + 1));
 636                         lcdc_writel(lcdc_dev, DSP_VACT_ST_END,
 637                                     v_VAEP(screen->mode.vsync_len +
 638                                         upper_margin + y_res/2) |
 639                                     v_VASP(screen->mode.vsync_len +
 640                                         upper_margin));
 641                         /*Second Field Timing*/
 642                         lcdc_writel(lcdc_dev, DSP_VS_ST_END_F1,
 643                                     v_VSYNC_ST_F1(screen->mode.vsync_len +
 644                                                   upper_margin + y_res/2 +
 645                                                   lower_margin) |
 646                                     v_VSYNC_END_F1(2 * screen->mode.vsync_len
 647                                                    + upper_margin + y_res/2 +
 648                                                    lower_margin));
 649                         lcdc_writel(lcdc_dev, DSP_VACT_ST_END_F1,
 650                                     v_VAEP(2 * (screen->mode.vsync_len +
 651                                                 upper_margin) + y_res +
 652                                                 lower_margin + 1) |
 653                                     v_VASP(2 * (screen->mode.vsync_len +
 654                                                 upper_margin) + y_res/2 +
 655                                                 lower_margin + 1));
 656
 657                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
 658                                      m_INTERLACE_DSP_EN |
 659                                      m_INTERLACE_DSP_POL |
 660                                      m_WIN1_DIFF_DCLK_EN |
 661                                      m_WIN0_YRGB_DEFLICK_EN |
 662                                      m_WIN0_CBR_DEFLICK_EN |
 663                                      m_WIN0_INTERLACE_EN |
 664                                      m_WIN1_INTERLACE_EN,
 665                                      v_INTERLACE_DSP_EN(1) |
 666                                      v_INTERLACE_DSP_POL(0) |
 667                                      v_WIN1_DIFF_DCLK_EN(1) |
 668                                      v_WIN0_YRGB_DEFLICK_EN(1) |
 669                                      v_WIN0_CBR_DEFLICK_EN(1) |
 670                                      v_WIN0_INTERLACE_EN(1) |
 671                                      v_WIN1_INTERLACE_EN(1));
 672                 } else {
 673                         val = v_VSYNC(screen->mode.vsync_len) |
 674                               v_VERPRD(screen->mode.vsync_len + upper_margin +
 675                                         y_res + lower_margin);
 676                         lcdc_writel(lcdc_dev, DSP_VTOTAL_VS_END, val);
 677
 678                         val = v_VAEP(screen->mode.vsync_len +
 679                                      upper_margin + y_res) |
 680                             v_VASP(screen->mode.vsync_len +
 681                                    screen->mode.upper_margin);
 682                         lcdc_writel(lcdc_dev, DSP_VACT_ST_END, val);
 683
 684                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
 685                                      m_INTERLACE_DSP_EN |
 686                                      m_WIN1_DIFF_DCLK_EN |
 687                                      m_WIN0_YRGB_DEFLICK_EN |
 688                                      m_WIN0_CBR_DEFLICK_EN |
 689                                      m_WIN0_INTERLACE_EN |
 690                                      m_WIN1_INTERLACE_EN,
 691                                      v_INTERLACE_DSP_EN(0) |
 692                                      v_WIN1_DIFF_DCLK_EN(0) |
 693                                      v_WIN0_YRGB_DEFLICK_EN(0) |
 694                                      v_WIN0_CBR_DEFLICK_EN(0) |
 695                                      v_WIN0_INTERLACE_EN(1) |
 696                                      v_WIN1_INTERLACE_EN(1));
 697                 }
 698         }
 699         spin_unlock(&lcdc_dev->reg_lock);
 700
 701         ret = clk_set_rate(lcdc_dev->dclk, screen->mode.pixclock);
 702         if (ret)
 703                 dev_err(dev_drv->dev,
 704                         "set lcdc%d dclk failed\n", lcdc_dev->id);
 705         lcdc_dev->pixclock =
 706             div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
 707         lcdc_dev->driver.pixclock = lcdc_dev->pixclock;
 708
 709         fps = rk_fb_calc_fps(screen, lcdc_dev->pixclock);
 710         screen->ft = 1000 / fps;
 711         dev_info(lcdc_dev->dev, "%s: dclk:%lu>>fps:%d ",
 712                  lcdc_dev->driver.name, clk_get_rate(lcdc_dev->dclk), fps);
 713         if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
 714                 dev_drv->trsm_ops->enable();
 715         if (screen->init)
 716                 screen->init();
 717
 718         return 0;
 719 }
 720
 721 static int rk3036_lcdc_open(struct rk_lcdc_driver *dev_drv, int win_id,
 722                             bool open)
 723 {
 724         struct lcdc_device *lcdc_dev = container_of(dev_drv,
 725                                         struct lcdc_device, driver);
 726
 727         /*enable clk,when first layer open */
 728         if ((open) && (!lcdc_dev->atv_layer_cnt)) {
 729                 rk3036_lcdc_pre_init(dev_drv);
 730                 rk3036_lcdc_clk_enable(lcdc_dev);
 731                 if (dev_drv->iommu_enabled) {
 732                         if (!dev_drv->mmu_dev) {
 733                                 dev_drv->mmu_dev =
 734                                 rk_fb_get_sysmmu_device_by_compatible(
 735                                         dev_drv->mmu_dts_name);
 736                                 if (dev_drv->mmu_dev) {
 737                                         rk_fb_platform_set_sysmmu(dev_drv->mmu_dev,
 738                                                                   dev_drv->dev);
 739                                 } else {
 740                                         dev_err(dev_drv->dev,
 741                                                 "failed to get iommu device\n"
 742                                                 );
 743                                         return -1;
 744                                 }
 745                         }
 746                 }
 747                 rk3036_lcdc_reg_restore(lcdc_dev);
 748                 /*if (dev_drv->iommu_enabled)
 749                         rk3036_lcdc_mmu_en(dev_drv);*/
 750                 if ((support_uboot_display() && (lcdc_dev->prop == PRMRY))) {
 751                         /*rk3036_lcdc_set_dclk(dev_drv);*/
 752                         rk3036_lcdc_enable_irq(dev_drv);
 753                 } else {
 754                         rk3036_load_screen(dev_drv, 1);
 755                 }
 756         }
 757
 758         if (win_id < ARRAY_SIZE(lcdc_win))
 759                 lcdc_layer_enable(lcdc_dev, win_id, open);
 760         else
 761                 dev_err(lcdc_dev->dev, "invalid win id:%d\n", win_id);
 762
 763         /*when all layer closed,disable clk */
 764 /*
 765         if ((!open) && (!lcdc_dev->atv_layer_cnt)) {
 766                 rk3036_lcdc_disable_irq(lcdc_dev);
 767                 rk3036_lcdc_reg_update(dev_drv);
 768                 if (dev_drv->iommu_enabled) {
 769                         if (dev_drv->mmu_dev)
 770                                 rockchip_iovmm_deactivate(dev_drv->dev);
 771                 }
 772                 rk3036_lcdc_clk_disable(lcdc_dev);
 773         }
 774 */
 775         return 0;
 776 }
 777
 778 static int rk3036_lcdc_set_par(struct rk_lcdc_driver *dev_drv, int win_id)
 779 {
 780         struct lcdc_device *lcdc_dev =
 781                         container_of(dev_drv, struct lcdc_device, driver);
 782         struct rk_screen *screen = dev_drv->cur_screen;
 783         struct rk_lcdc_win *win = NULL;
 784         char fmt[9] = "NULL";
 785
 786         if (!screen) {
 787                 dev_err(dev_drv->dev, "screen is null!\n");
 788                 return -ENOENT;
 789         }
 790
 791         if (win_id == 0) {
 792                 win = dev_drv->win[0];
 793         } else if (win_id == 1) {
 794                 win = dev_drv->win[1];
 795         } else if (win_id == 2) {
 796                 win = dev_drv->win[2];
 797         } else {
 798                 dev_err(dev_drv->dev, "un supported win number:%d\n", win_id);
 799                 return -EINVAL;
 800         }
 801
 802         spin_lock(&lcdc_dev->reg_lock);
 803         win->post_cfg.xpos = win->area[0].xpos * (dev_drv->overscan.left +
 804                 dev_drv->overscan.right)/200 + screen->mode.xres *
 805                         (100 - dev_drv->overscan.left) / 200;
 806
 807         win->post_cfg.ypos = win->area[0].ypos * (dev_drv->overscan.top +
 808                 dev_drv->overscan.bottom)/200 +
 809                 screen->mode.yres *
 810                         (100 - dev_drv->overscan.top) / 200;
 811         win->post_cfg.xsize = win->area[0].xsize *
 812                                 (dev_drv->overscan.left +
 813                                 dev_drv->overscan.right)/200;
 814         win->post_cfg.ysize = win->area[0].ysize *
 815                                 (dev_drv->overscan.top +
 816                                 dev_drv->overscan.bottom)/200;
 817
 818         win->area[0].dsp_stx = win->post_cfg.xpos + screen->mode.left_margin +
 819                                 screen->mode.hsync_len;
 820         if (screen->mode.vmode & FB_VMODE_INTERLACED) {
 821                 win->post_cfg.ysize /= 2;
 822                 win->area[0].dsp_sty = win->post_cfg.ypos/2 +
 823                                         screen->mode.upper_margin +
 824                                         screen->mode.vsync_len;
 825         } else {
 826                 win->area[0].dsp_sty = win->post_cfg.ypos +
 827                                         screen->mode.upper_margin +
 828                                         screen->mode.vsync_len;
 829         }
 830         win->scale_yrgb_x = calscale(win->area[0].xact, win->post_cfg.xsize);
 831         win->scale_yrgb_y = calscale(win->area[0].yact, win->post_cfg.ysize);
 832
 833         switch (win->area[0].format) {
 834         case ARGB888:
 835                 win->area[0].fmt_cfg = VOP_FORMAT_ARGB888;
 836                 win->area[0].swap_rb = 0;
 837                 break;
 838         case XBGR888:
 839                 win->area[0].fmt_cfg = VOP_FORMAT_ARGB888;
 840                 win->area[0].swap_rb = 1;
 841                 break;
 842         case ABGR888:
 843                 win->area[0].fmt_cfg = VOP_FORMAT_ARGB888;
 844                 win->area[0].swap_rb = 1;
 845                 break;
 846         case RGB888:
 847                 win->area[0].fmt_cfg = VOP_FORMAT_RGB888;
 848                 win->area[0].swap_rb = 0;
 849                 break;
 850         case RGB565:
 851                 win->area[0].fmt_cfg = VOP_FORMAT_RGB565;
 852                 win->area[0].swap_rb = 0;
 853                 break;
 854         case YUV444:
 855                 if (win_id == 0) {
 856                         win->area[0].fmt_cfg = VOP_FORMAT_YCBCR444;
 857                         win->scale_cbcr_x = calscale(win->area[0].xact,
 858                                                      win->post_cfg.xsize);
 859                         win->scale_cbcr_y = calscale(win->area[0].yact,
 860                                                      win->post_cfg.ysize);
 861                         win->area[0].swap_rb = 0;
 862                 } else {
 863                         dev_err(lcdc_dev->driver.dev,
 864                                 "%s:un supported format!\n",
 865                                 __func__);
 866                 }
 867                 break;
 868         case YUV422:
 869                 if (win_id == 0) {
 870                         win->area[0].fmt_cfg = VOP_FORMAT_YCBCR422;
 871                         win->scale_cbcr_x = calscale((win->area[0].xact / 2),
 872                                                      win->post_cfg.xsize);
 873                         win->scale_cbcr_y = calscale(win->area[0].yact,
 874                                                      win->post_cfg.ysize);
 875                         win->area[0].swap_rb = 0;
 876                 } else {
 877                         dev_err(lcdc_dev->driver.dev,
 878                                 "%s:un supported format!\n",
 879                                 __func__);
 880                 }
 881                 break;
 882         case YUV420:
 883                 if (win_id == 0) {
 884                         win->area[0].fmt_cfg = VOP_FORMAT_YCBCR420;
 885                         win->scale_cbcr_x = calscale(win->area[0].xact / 2,
 886                                                      win->post_cfg.xsize);
 887                         win->scale_cbcr_y = calscale(win->area[0].yact / 2,
 888                                                      win->post_cfg.ysize);
 889                         win->area[0].swap_rb = 0;
 890                 } else {
 891                         dev_err(lcdc_dev->driver.dev,
 892                                 "%s:un supported format!\n",
 893                                 __func__);
 894                 }
 895                 break;
 896         default:
 897                 dev_err(lcdc_dev->driver.dev, "%s:un supported format!\n",
 898                         __func__);
 899                 break;
 900         }
 901         spin_unlock(&lcdc_dev->reg_lock);
 902
 903         DBG(2, "lcdc%d>>%s\n"
 904                 ">>format:%s>>>xact:%d>>yact:%d>>xsize:%d>>ysize:%d\n"
 905                 ">>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n", lcdc_dev->id,
 906                 __func__, get_format_string(win->area[0].format, fmt),
 907                 win->area[0].xact, win->area[0].yact, win->post_cfg.xsize,
 908                 win->post_cfg.ysize, win->area[0].xvir, win->area[0].yvir,
 909                 win->post_cfg.xpos, win->post_cfg.ypos);
 910         return 0;
 911 }
 912
 913 static int rk3036_lcdc_pan_display(struct rk_lcdc_driver *dev_drv, int win_id)
 914 {
 915         struct lcdc_device *lcdc_dev = container_of(dev_drv,
 916                                                 struct lcdc_device, driver);
 917         struct rk_lcdc_win *win = NULL;
 918         struct rk_screen *screen = dev_drv->cur_screen;
 919
 920         if (!screen) {
 921                 dev_err(dev_drv->dev, "screen is null!\n");
 922                 return -ENOENT;
 923         }
 924
 925         if (win_id == 0) {
 926                 win = dev_drv->win[0];
 927         } else if (win_id == 1) {
 928                 win = dev_drv->win[1];
 929         } else if (win_id == 2) {
 930                 win = dev_drv->win[2];
 931         } else {
 932                 dev_err(dev_drv->dev, "invalid win number:%d!\n", win_id);
 933                 return -EINVAL;
 934         }
 935
 936         spin_lock(&lcdc_dev->reg_lock);
 937         if (likely(lcdc_dev->clk_on)) {
 938                 win->area[0].y_addr = win->area[0].smem_start +
 939                                         win->area[0].y_offset;
 940                 win->area[0].uv_addr = win->area[0].cbr_start +
 941                                         win->area[0].c_offset;
 942                 if (win->area[0].y_addr)
 943                         lcdc_layer_update_regs(lcdc_dev, win);
 944                 /*lcdc_cfg_done(lcdc_dev);*/
 945         }
 946         spin_unlock(&lcdc_dev->reg_lock);
 947
 948         DBG(2, "lcdc%d>>%s:y_addr:0x%x>>uv_addr:0x%x>>offset:%d\n",
 949             lcdc_dev->id, __func__, win->area[0].y_addr,
 950             win->area[0].uv_addr, win->area[0].y_offset);
 951          /* this is the first frame of the system,
 952                 enable frame start interrupt*/
 953         if ((dev_drv->first_frame))  {
 954                 dev_drv->first_frame = 0;
 955                 rk3036_lcdc_enable_irq(dev_drv);
 956         }
 957         return 0;
 958 }
 959
 960 static int rk3036_lcdc_ioctl(struct rk_lcdc_driver *dev_drv, unsigned int cmd,
 961                              unsigned long arg, int win_id)
 962 {
 963         struct lcdc_device *lcdc_dev = container_of(dev_drv,
 964                                         struct lcdc_device, driver);
 965         u32 panel_size[2];
 966         void __user *argp = (void __user *)arg;
 967         struct color_key_cfg clr_key_cfg;
 968
 969         switch (cmd) {
 970         case RK_FBIOGET_PANEL_SIZE:
 971                 panel_size[0] = lcdc_dev->screen->mode.xres;
 972                 panel_size[1] = lcdc_dev->screen->mode.yres;
 973                 if (copy_to_user(argp, panel_size, 8))
 974                         return -EFAULT;
 975                 break;
 976         case RK_FBIOPUT_COLOR_KEY_CFG:
 977                 if (copy_from_user(&clr_key_cfg, argp,
 978                                    sizeof(struct color_key_cfg)))
 979                         return -EFAULT;
 980                 lcdc_writel(lcdc_dev, WIN0_COLOR_KEY,
 981                             clr_key_cfg.win0_color_key_cfg);
 982                 lcdc_writel(lcdc_dev, WIN1_COLOR_KEY,
 983                             clr_key_cfg.win1_color_key_cfg);
 984                 break;
 985
 986         default:
 987                 break;
 988         }
 989         return 0;
 990 }
 991
 992 static int rk3036_lcdc_get_win_id(struct rk_lcdc_driver *dev_drv,
 993                                   const char *id)
 994 {
 995         int win_id = 0;
 996
 997         mutex_lock(&dev_drv->fb_win_id_mutex);
 998         if (!strcmp(id, "fb0"))
 999                 win_id = dev_drv->fb0_win_id;
1000         else if (!strcmp(id, "fb1"))
1001                 win_id = dev_drv->fb1_win_id;
1002         else if (!strcmp(id, "fb2"))
1003                 win_id = dev_drv->fb2_win_id;
1004         mutex_unlock(&dev_drv->fb_win_id_mutex);
1005
1006         return win_id;
1007 }
1008
1009 static int rk3036_lcdc_get_win_state(struct rk_lcdc_driver *dev_drv,
1010                                      int win_id,
1011                                      int area_id)
1012 {
1013         return dev_drv->win[win_id]->state;
1014 }
1015
1016 static int rk3036_lcdc_ovl_mgr(struct rk_lcdc_driver *dev_drv, int swap,
1017                                bool set)
1018 {
1019         struct lcdc_device *lcdc_dev =
1020             container_of(dev_drv, struct lcdc_device, driver);
1021         struct rk_lcdc_win *win0 = lcdc_dev->driver.win[0];
1022         struct rk_lcdc_win *win1 = lcdc_dev->driver.win[1];
1023         int ovl, needswap = 0;
1024
1025         if (!swap) {
1026                 if (win0->z_order >= 0 &&
1027                     win1->z_order >= 0 &&
1028                     win0->z_order > win1->z_order)
1029                         needswap = 1;
1030                 else
1031                         needswap = 0;
1032         } else {
1033                 needswap = swap;
1034         }
1035         spin_lock(&lcdc_dev->reg_lock);
1036         if (lcdc_dev->clk_on) {
1037                 if (set) {
1038                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_WIN0_TOP,
1039                                      v_WIN0_TOP(needswap));
1040                         ovl = swap;
1041                 } else {
1042                         ovl = lcdc_read_bit(lcdc_dev, DSP_CTRL0, m_WIN0_TOP);
1043                 }
1044         } else {
1045                 ovl = -EPERM;
1046         }
1047         spin_unlock(&lcdc_dev->reg_lock);
1048
1049         return ovl;
1050 }
1051
1052 static int rk3036_lcdc_early_suspend(struct rk_lcdc_driver *dev_drv)
1053 {
1054         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1055                                         struct lcdc_device, driver);
1056         if (dev_drv->suspend_flag)
1057                 return 0;
1058         dev_drv->suspend_flag = 1;
1059         flush_kthread_worker(&dev_drv->update_regs_worker);
1060
1061         if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable)
1062                 dev_drv->trsm_ops->disable();
1063         spin_lock(&lcdc_dev->reg_lock);
1064         if (likely(lcdc_dev->clk_on)) {
1065                 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_BLANK_EN,
1066                              v_BLANK_EN(1));
1067                 lcdc_msk_reg(lcdc_dev, INT_STATUS, m_FS_INT_CLEAR,
1068                              v_FS_INT_CLEAR(1));
1069                 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_OUT_ZERO,
1070                              v_DSP_OUT_ZERO(1));
1071                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_LCDC_STANDBY,
1072                              v_LCDC_STANDBY(1));
1073                 lcdc_cfg_done(lcdc_dev);
1074                 if (dev_drv->iommu_enabled) {
1075                         if (dev_drv->mmu_dev)
1076                                 rockchip_iovmm_deactivate(dev_drv->dev);
1077                 }
1078                 spin_unlock(&lcdc_dev->reg_lock);
1079         } else {
1080                 spin_unlock(&lcdc_dev->reg_lock);
1081                 return 0;
1082         }
1083         rk3036_lcdc_clk_disable(lcdc_dev);
1084         rk_disp_pwr_disable(dev_drv);
1085         return 0;
1086 }
1087
1088 static int rk3036_lcdc_early_resume(struct rk_lcdc_driver *dev_drv)
1089 {
1090         struct lcdc_device *lcdc_dev =
1091             container_of(dev_drv, struct lcdc_device, driver);
1092
1093         if (!dev_drv->suspend_flag)
1094                 return 0;
1095         rk_disp_pwr_enable(dev_drv);
1096         dev_drv->suspend_flag = 0;
1097
1098         if (lcdc_dev->atv_layer_cnt) {
1099                 rk3036_lcdc_clk_enable(lcdc_dev);
1100                 rk3036_lcdc_reg_restore(lcdc_dev);
1101                 /*set hwc lut*/
1102                 rk3036_lcdc_set_hwc_lut(dev_drv, dev_drv->hwc_lut, 0);
1103
1104                 spin_lock(&lcdc_dev->reg_lock);
1105
1106                 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_OUT_ZERO,
1107                              v_DSP_OUT_ZERO(0));
1108                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_LCDC_STANDBY,
1109                              v_LCDC_STANDBY(0));
1110                 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_BLANK_EN,
1111                              v_BLANK_EN(0));
1112                 lcdc_cfg_done(lcdc_dev);
1113                 if (dev_drv->iommu_enabled) {
1114                         if (dev_drv->mmu_dev)
1115                                 rockchip_iovmm_activate(dev_drv->dev);
1116                 }
1117                 spin_unlock(&lcdc_dev->reg_lock);
1118         }
1119
1120         if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
1121                 dev_drv->trsm_ops->enable();
1122         return 0;
1123 }
1124
1125
1126 static int rk3036_lcdc_blank(struct rk_lcdc_driver *dev_drv,
1127                              int win_id, int blank_mode)
1128 {
1129         switch (blank_mode) {
1130         case FB_BLANK_UNBLANK:
1131                 rk3036_lcdc_early_resume(dev_drv);
1132                 break;
1133         case FB_BLANK_NORMAL:
1134                 rk3036_lcdc_early_suspend(dev_drv);
1135                 break;
1136         default:
1137                 rk3036_lcdc_early_suspend(dev_drv);
1138                 break;
1139         }
1140
1141         dev_info(dev_drv->dev, "blank mode:%d\n", blank_mode);
1142
1143         return 0;
1144 }
1145
1146 static int rk3036_lcdc_cfg_done(struct rk_lcdc_driver *dev_drv)
1147 {
1148         struct lcdc_device *lcdc_dev =
1149             container_of(dev_drv, struct lcdc_device, driver);
1150         int i;
1151         struct rk_lcdc_win *win = NULL;
1152
1153         spin_lock(&lcdc_dev->reg_lock);
1154         if (lcdc_dev->clk_on) {
1155                 if (dev_drv->iommu_enabled) {
1156                         if (!lcdc_dev->iommu_status && dev_drv->mmu_dev) {
1157                                 lcdc_dev->iommu_status = 1;
1158                                 if (support_uboot_display() &&
1159                                     lcdc_dev->prop == PRMRY) {
1160                                         lcdc_msk_reg(lcdc_dev, SYS_CTRL,
1161                                                      m_WIN0_EN,
1162                                                      v_WIN0_EN(0));
1163                                 }
1164                                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_LCDC_STANDBY,
1165                                              v_LCDC_STANDBY(1));
1166                                 lcdc_cfg_done(lcdc_dev);
1167                                 mdelay(50);
1168                                 rockchip_iovmm_activate(dev_drv->dev);
1169                                 rk3036_lcdc_mmu_en(dev_drv);
1170                         }
1171                 }
1172                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_LCDC_STANDBY,
1173                              v_LCDC_STANDBY(lcdc_dev->standby));
1174                 for (i = 0; i < ARRAY_SIZE(lcdc_win); i++) {
1175                         win = dev_drv->win[i];
1176                         if ((win->state == 0) && (win->last_state == 1))
1177                                 lcdc_layer_update_regs(lcdc_dev, win);
1178                         win->last_state = win->state;
1179                 }
1180                 lcdc_cfg_done(lcdc_dev);
1181         }
1182         spin_unlock(&lcdc_dev->reg_lock);
1183         return 0;
1184 }
1185
1186 /*
1187         a:[-30~0]:
1188             sin_hue = sin(a)*256 +0x100;
1189             cos_hue = cos(a)*256;
1190         a:[0~30]
1191             sin_hue = sin(a)*256;
1192             cos_hue = cos(a)*256;
1193 */
1194 static int rk3036_lcdc_get_bcsh_hue(struct rk_lcdc_driver *dev_drv,
1195                                     bcsh_hue_mode mode)
1196 {
1197         struct lcdc_device *lcdc_dev =
1198             container_of(dev_drv, struct lcdc_device, driver);
1199         u32 val;
1200
1201         spin_lock(&lcdc_dev->reg_lock);
1202         if (lcdc_dev->clk_on) {
1203                 val = lcdc_readl(lcdc_dev, BCSH_H);
1204                 switch (mode) {
1205                 case H_SIN:
1206                         val &= m_BCSH_SIN_HUE;
1207                         break;
1208                 case H_COS:
1209                         val &= m_BCSH_COS_HUE;
1210                         val >>= 8;
1211                         break;
1212                 default:
1213                         break;
1214                 }
1215         }
1216         spin_unlock(&lcdc_dev->reg_lock);
1217
1218         return val;
1219 }
1220
1221
1222 static int rk3036_lcdc_set_bcsh_hue(struct rk_lcdc_driver *dev_drv,
1223                                     int sin_hue, int cos_hue)
1224 {
1225         struct lcdc_device *lcdc_dev =
1226             container_of(dev_drv, struct lcdc_device, driver);
1227         u32 mask, val;
1228
1229         spin_lock(&lcdc_dev->reg_lock);
1230         if (lcdc_dev->clk_on) {
1231                 mask = m_BCSH_SIN_HUE | m_BCSH_COS_HUE;
1232                 val = v_BCSH_SIN_HUE(sin_hue) | v_BCSH_COS_HUE(cos_hue);
1233                 lcdc_msk_reg(lcdc_dev, BCSH_H, mask, val);
1234                 lcdc_cfg_done(lcdc_dev);
1235         }
1236         spin_unlock(&lcdc_dev->reg_lock);
1237
1238         return 0;
1239 }
1240
1241 static int rk3036_lcdc_set_bcsh_bcs(struct rk_lcdc_driver *dev_drv,
1242                                     bcsh_bcs_mode mode, int value)
1243 {
1244         struct lcdc_device *lcdc_dev =
1245             container_of(dev_drv, struct lcdc_device, driver);
1246         u32 mask, val;
1247
1248         spin_lock(&lcdc_dev->reg_lock);
1249         if (lcdc_dev->clk_on) {
1250                 switch (mode) {
1251                 case BRIGHTNESS:
1252                 /*from 0 to 255,typical is 128*/
1253                         if (value < 0x20)
1254                                 value += 0x20;
1255                         else if (value >= 0x20)
1256                                 value = value - 0x20;
1257                         mask =  m_BCSH_BRIGHTNESS;
1258                         val = v_BCSH_BRIGHTNESS(value);
1259                         break;
1260                 case CONTRAST:
1261                 /*from 0 to 510,typical is 256*/
1262                         mask =  m_BCSH_CONTRAST;
1263                         val =  v_BCSH_CONTRAST(value);
1264                         break;
1265                 case SAT_CON:
1266                 /*from 0 to 1015,typical is 256*/
1267                         mask = m_BCSH_SAT_CON;
1268                         val = v_BCSH_SAT_CON(value);
1269                         break;
1270                 default:
1271                         break;
1272                 }
1273                 lcdc_msk_reg(lcdc_dev, BCSH_BCS, mask, val);
1274                 lcdc_cfg_done(lcdc_dev);
1275         }
1276         spin_unlock(&lcdc_dev->reg_lock);
1277         return val;
1278 }
1279
1280 static int rk3036_lcdc_get_bcsh_bcs(struct rk_lcdc_driver *dev_drv,
1281                                     bcsh_bcs_mode mode)
1282 {
1283         struct lcdc_device *lcdc_dev =
1284             container_of(dev_drv, struct lcdc_device, driver);
1285         u32 val;
1286
1287         spin_lock(&lcdc_dev->reg_lock);
1288         if (lcdc_dev->clk_on) {
1289                 val = lcdc_readl(lcdc_dev, BCSH_BCS);
1290                 switch (mode) {
1291                 case BRIGHTNESS:
1292                         val &= m_BCSH_BRIGHTNESS;
1293                         if (val > 0x20)
1294                                 val -= 0x20;
1295                         else if (val == 0x20)
1296                                 val = -32;
1297                         break;
1298                 case CONTRAST:
1299                         val &= m_BCSH_CONTRAST;
1300                         val >>= 8;
1301                         break;
1302                 case SAT_CON:
1303                         val &= m_BCSH_SAT_CON;
1304                         val >>= 16;
1305                         break;
1306                 default:
1307                         break;
1308                 }
1309         }
1310         spin_unlock(&lcdc_dev->reg_lock);
1311         return val;
1312 }
1313
1314
1315 static int rk3036_lcdc_open_bcsh(struct rk_lcdc_driver *dev_drv, bool open)
1316 {
1317         struct lcdc_device *lcdc_dev =
1318             container_of(dev_drv, struct lcdc_device, driver);
1319         u32 mask, val;
1320
1321         spin_lock(&lcdc_dev->reg_lock);
1322         if (lcdc_dev->clk_on) {
1323                 if (open) {
1324                         lcdc_writel(lcdc_dev, BCSH_CTRL,
1325                                     v_BCSH_EN(1) | v_BCSH_OUT_MODE(3));
1326                         lcdc_writel(lcdc_dev, BCSH_BCS,
1327                                     v_BCSH_BRIGHTNESS(0x00) |
1328                                     v_BCSH_CONTRAST(0x80) |
1329                                     v_BCSH_SAT_CON(0x80));
1330                         lcdc_writel(lcdc_dev, BCSH_H, v_BCSH_COS_HUE(0x80));
1331                 } else {
1332                         mask = m_BCSH_EN;
1333                         val = v_BCSH_EN(0);
1334                         lcdc_msk_reg(lcdc_dev, BCSH_CTRL, mask, val);
1335                 }
1336                 lcdc_cfg_done(lcdc_dev);
1337         }
1338         spin_unlock(&lcdc_dev->reg_lock);
1339         return 0;
1340 }
1341
1342 static int rk3036_lcdc_set_overscan(struct rk_lcdc_driver *dev_drv,
1343                                     struct overscan *overscan)
1344 {
1345         int i;
1346
1347         dev_drv->overscan = *overscan;
1348         for (i = 0; i < dev_drv->lcdc_win_num; i++) {
1349                 if (dev_drv->win[i] && dev_drv->win[i]->state) {
1350                         rk3036_lcdc_set_par(dev_drv, i);
1351                         rk3036_lcdc_pan_display(dev_drv, i);
1352                 }
1353         }
1354         rk3036_lcdc_cfg_done(dev_drv);
1355         return 0;
1356 }
1357
1358 static int rk3036_fb_win_remap(struct rk_lcdc_driver *dev_drv, u16 order)
1359 {
1360         struct rk_lcdc_win_area area;
1361         int fb2_win_id, fb1_win_id, fb0_win_id;
1362
1363         mutex_lock(&dev_drv->fb_win_id_mutex);
1364         if (order == FB_DEFAULT_ORDER)
1365                 order = FB0_WIN0_FB1_WIN1_FB2_WIN2;
1366
1367         fb2_win_id = order / 100;
1368         fb1_win_id = (order / 10) % 10;
1369         fb0_win_id = order % 10;
1370
1371         if (fb0_win_id != dev_drv->fb0_win_id) {
1372                 area = dev_drv->win[(int)dev_drv->fb0_win_id]->area[0];
1373                 dev_drv->win[(int)dev_drv->fb0_win_id]->area[0] =
1374                         dev_drv->win[fb0_win_id]->area[0];
1375                 dev_drv->win[fb0_win_id]->area[0] = area;
1376                 dev_drv->fb0_win_id = fb0_win_id;
1377         }
1378         dev_drv->fb1_win_id = fb1_win_id;
1379         dev_drv->fb2_win_id = fb2_win_id;
1380
1381         mutex_unlock(&dev_drv->fb_win_id_mutex);
1382
1383         return 0;
1384 }
1385
1386 static int rk3036_lcdc_fps_mgr(struct rk_lcdc_driver *dev_drv, int fps,
1387                                bool set)
1388 {
1389         struct lcdc_device *lcdc_dev =
1390             container_of(dev_drv, struct lcdc_device, driver);
1391         struct rk_screen *screen = dev_drv->cur_screen;
1392         u64 ft = 0;
1393         u32 dotclk;
1394         int ret;
1395         u32 pixclock;
1396         u32 x_total, y_total;
1397
1398         if (set) {
1399                 ft = div_u64(1000000000000llu, fps);
1400                 x_total =
1401                     screen->mode.upper_margin + screen->mode.lower_margin +
1402                     screen->mode.yres + screen->mode.vsync_len;
1403                 y_total =
1404                     screen->mode.left_margin + screen->mode.right_margin +
1405                     screen->mode.xres + screen->mode.hsync_len;
1406                 dev_drv->pixclock = div_u64(ft, x_total * y_total);
1407                 dotclk = div_u64(1000000000000llu, dev_drv->pixclock);
1408                 ret = clk_set_rate(lcdc_dev->dclk, dotclk);
1409         }
1410
1411         pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
1412         lcdc_dev->pixclock = pixclock;
1413         dev_drv->pixclock = pixclock;
1414         fps = rk_fb_calc_fps(lcdc_dev->screen, pixclock);
1415         screen->ft = 1000 / fps;        /*one frame time in ms */
1416
1417         if (set)
1418                 dev_info(dev_drv->dev, "%s:dclk:%lu,fps:%d\n", __func__,
1419                          clk_get_rate(lcdc_dev->dclk), fps);
1420
1421         return fps;
1422 }
1423
1424 static int rk3036_lcdc_poll_vblank(struct rk_lcdc_driver *dev_drv)
1425 {
1426         struct lcdc_device *lcdc_dev =
1427             container_of(dev_drv, struct lcdc_device, driver);
1428         u32 int_reg;
1429         int ret;
1430
1431         if (lcdc_dev->clk_on) {
1432                 int_reg = lcdc_readl(lcdc_dev, INT_STATUS);
1433                 if (int_reg & m_LF_INT_STA) {
1434                         lcdc_msk_reg(lcdc_dev, INT_STATUS, m_LF_INT_CLEAR,
1435                                      v_LF_INT_CLEAR(1));
1436                         ret = RK_LF_STATUS_FC;
1437                 } else {
1438                         ret = RK_LF_STATUS_FR;
1439                 }
1440         } else {
1441                 ret = RK_LF_STATUS_NC;
1442         }
1443
1444         return ret;
1445 }
1446
1447 static int rk3036_lcdc_get_dsp_addr(struct rk_lcdc_driver *dev_drv,
1448                                     unsigned int dsp_addr[][4])
1449 {
1450         struct lcdc_device *lcdc_dev =
1451             container_of(dev_drv, struct lcdc_device, driver);
1452
1453         if (lcdc_dev->clk_on) {
1454                 dsp_addr[0][0] = lcdc_readl(lcdc_dev, WIN0_YRGB_MST);
1455                 dsp_addr[1][0] = lcdc_readl(lcdc_dev, WIN1_MST);
1456         }
1457         return 0;
1458 }
1459
1460 static ssize_t rk3036_lcdc_get_disp_info(struct rk_lcdc_driver *dev_drv,
1461                                          char *buf, int win_id)
1462 {
1463         struct rk_lcdc_win *win = NULL;
1464         char fmt[9] = "NULL";
1465         u32     size;
1466
1467         if (win_id < ARRAY_SIZE(lcdc_win)) {
1468                 win = dev_drv->win[win_id];
1469         } else {
1470                 dev_err(dev_drv->dev, "invalid win number:%d!\n", win_id);
1471                 return 0;
1472         }
1473
1474         size = snprintf(buf, PAGE_SIZE, "win%d: %s\n", win_id,
1475                         get_format_string(win->area[0].format, fmt));
1476         size += snprintf(buf + size, PAGE_SIZE - size,
1477                          "      xact %d yact %d xvir %d yvir %d\n",
1478                 win->area[0].xact, win->area[0].yact,
1479                 win->area[0].xvir, win->area[0].yvir);
1480         size += snprintf(buf + size, PAGE_SIZE - size,
1481                          "      xpos %d ypos %d xsize %d ysize %d\n",
1482                 win->area[0].xpos, win->area[0].ypos,
1483                 win->area[0].xsize, win->area[0].ysize);
1484         size += snprintf(buf + size, PAGE_SIZE - size,
1485                          "      yaddr 0x%x uvaddr 0x%x\n",
1486                 win->area[0].y_addr, win->area[0].uv_addr);
1487         return size;
1488 }
1489
1490 static int rk3036_lcdc_reg_dump(struct rk_lcdc_driver *dev_drv)
1491 {
1492         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1493                                                 struct lcdc_device,
1494                                                 driver);
1495         int *cbase = (int *)lcdc_dev->regs;
1496         int *regsbak = (int *)lcdc_dev->regsbak;
1497         int i, j;
1498
1499         dev_info(dev_drv->dev, "back up reg:\n");
1500         for (i = 0; i <= (0xDC >> 4); i++) {
1501                 for (j = 0; j < 4; j++)
1502                         dev_info(dev_drv->dev, "%08x  ",
1503                                  *(regsbak + i * 4 + j));
1504                 dev_info(dev_drv->dev, "\n");
1505         }
1506
1507         dev_info(dev_drv->dev, "lcdc reg:\n");
1508         for (i = 0; i <= (0xDC >> 4); i++) {
1509                 for (j = 0; j < 4; j++)
1510                         dev_info(dev_drv->dev, "%08x  ",
1511                                  readl_relaxed(cbase + i * 4 + j));
1512                 dev_info(dev_drv->dev, "\n");
1513         }
1514         return 0;
1515 }
1516
1517 static struct rk_lcdc_drv_ops lcdc_drv_ops = {
1518         .open                   = rk3036_lcdc_open,
1519         .load_screen            = rk3036_load_screen,
1520         .set_par                = rk3036_lcdc_set_par,
1521         .pan_display            = rk3036_lcdc_pan_display,
1522         .blank                  = rk3036_lcdc_blank,
1523         .ioctl                  = rk3036_lcdc_ioctl,
1524         .get_win_state          = rk3036_lcdc_get_win_state,
1525         .ovl_mgr                = rk3036_lcdc_ovl_mgr,
1526         .get_disp_info          = rk3036_lcdc_get_disp_info,
1527         .fps_mgr                = rk3036_lcdc_fps_mgr,
1528         .fb_get_win_id          = rk3036_lcdc_get_win_id,
1529         .fb_win_remap           = rk3036_fb_win_remap,
1530         .poll_vblank            = rk3036_lcdc_poll_vblank,
1531         .get_dsp_addr           = rk3036_lcdc_get_dsp_addr,
1532         .cfg_done               = rk3036_lcdc_cfg_done,
1533         .dump_reg               = rk3036_lcdc_reg_dump,
1534         .set_dsp_bcsh_hue       = rk3036_lcdc_set_bcsh_hue,
1535         .set_dsp_bcsh_bcs       = rk3036_lcdc_set_bcsh_bcs,
1536         .get_dsp_bcsh_hue       = rk3036_lcdc_get_bcsh_hue,
1537         .get_dsp_bcsh_bcs       = rk3036_lcdc_get_bcsh_bcs,
1538         .open_bcsh              = rk3036_lcdc_open_bcsh,
1539         .set_overscan           = rk3036_lcdc_set_overscan,
1540         .set_hwc_lut            = rk3036_lcdc_set_hwc_lut,
1541 };
1542
1543 static int rk3036_lcdc_parse_dt(struct lcdc_device *lcdc_dev)
1544 {
1545         struct device_node *np = lcdc_dev->dev->of_node;
1546         int val;
1547
1548         if (of_property_read_u32(np, "rockchip,iommu-enabled", &val))
1549                 lcdc_dev->driver.iommu_enabled = 0;
1550         else
1551                 lcdc_dev->driver.iommu_enabled = val;
1552         if (of_property_read_u32(np, "rockchip,fb-win-map", &val))
1553                 lcdc_dev->driver.fb_win_map = FB_DEFAULT_ORDER;
1554         else
1555                 lcdc_dev->driver.fb_win_map = val;
1556
1557         return 0;
1558 }
1559
1560 static int rk3036_lcdc_probe(struct platform_device *pdev)
1561 {
1562         struct lcdc_device *lcdc_dev = NULL;
1563         struct rk_lcdc_driver *dev_drv;
1564         struct device *dev = &pdev->dev;
1565         struct resource *res;
1566         int ret;
1567
1568         lcdc_dev = devm_kzalloc(dev,
1569                                 sizeof(struct lcdc_device), GFP_KERNEL);
1570         if (!lcdc_dev) {
1571                 dev_err(&pdev->dev, "rk3036 lcdc device kmalloc fail!");
1572                 return -ENOMEM;
1573         }
1574         platform_set_drvdata(pdev, lcdc_dev);
1575         lcdc_dev->dev = dev;
1576         rk3036_lcdc_parse_dt(lcdc_dev);
1577
1578         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1579         lcdc_dev->reg_phy_base = res->start;
1580         lcdc_dev->len = resource_size(res);
1581         lcdc_dev->regs = devm_ioremap_resource(dev, res);
1582         if (IS_ERR(lcdc_dev->regs))
1583                 return PTR_ERR(lcdc_dev->regs);
1584
1585         lcdc_dev->regsbak = devm_kzalloc(dev, lcdc_dev->len, GFP_KERNEL);
1586         if (IS_ERR(lcdc_dev->regsbak))
1587                 return PTR_ERR(lcdc_dev->regsbak);
1588
1589         lcdc_dev->hwc_lut_addr_base = (lcdc_dev->regs + HWC_LUT_ADDR);
1590         lcdc_dev->prop = PRMRY;
1591         dev_set_name(lcdc_dev->dev, "lcdc%d", lcdc_dev->id);
1592         dev_drv = &lcdc_dev->driver;
1593         dev_drv->dev = dev;
1594         dev_drv->prop = PRMRY;
1595         dev_drv->id = lcdc_dev->id;
1596         dev_drv->ops = &lcdc_drv_ops;
1597         dev_drv->lcdc_win_num = ARRAY_SIZE(lcdc_win);
1598         spin_lock_init(&lcdc_dev->reg_lock);
1599
1600         lcdc_dev->irq = platform_get_irq(pdev, 0);
1601         if (lcdc_dev->irq < 0) {
1602                 dev_err(&pdev->dev, "cannot find IRQ for lcdc%d\n",
1603                         lcdc_dev->id);
1604                 return -ENXIO;
1605         }
1606
1607         ret = devm_request_irq(dev, lcdc_dev->irq, rk3036_lcdc_isr,
1608                                IRQF_DISABLED | IRQF_SHARED,
1609                                dev_name(dev), lcdc_dev);
1610         if (ret) {
1611                 dev_err(&pdev->dev, "cannot requeset irq %d - err %d\n",
1612                         lcdc_dev->irq, ret);
1613                 return ret;
1614         }
1615
1616         if (dev_drv->iommu_enabled)
1617                 strcpy(dev_drv->mmu_dts_name, VOP_IOMMU_COMPATIBLE_NAME);
1618
1619         ret = rk_fb_register(dev_drv, lcdc_win, lcdc_dev->id);
1620         if (ret < 0) {
1621                 dev_err(dev, "register fb for lcdc%d failed!\n", lcdc_dev->id);
1622                 return ret;
1623         }
1624         lcdc_dev->screen = dev_drv->screen0;
1625
1626         dev_info(dev, "lcdc probe ok, iommu %s\n",
1627                  dev_drv->iommu_enabled ? "enabled" : "disabled");
1628
1629         return 0;
1630 }
1631
1632 #if defined(CONFIG_PM)
1633 static int rk3036_lcdc_suspend(struct platform_device *pdev,
1634                                pm_message_t state)
1635 {
1636         return 0;
1637 }
1638
1639 static int rk3036_lcdc_resume(struct platform_device *pdev)
1640 {
1641         return 0;
1642 }
1643 #else
1644 #define rk3036_lcdc_suspend NULL
1645 #define rk3036_lcdc_resume  NULL
1646 #endif
1647
1648 static int rk3036_lcdc_remove(struct platform_device *pdev)
1649 {
1650         return 0;
1651 }
1652
1653 static void rk3036_lcdc_shutdown(struct platform_device *pdev)
1654 {
1655 }
1656
1657 #if defined(CONFIG_OF)
1658 static const struct of_device_id rk3036_lcdc_dt_ids[] = {
1659         {.compatible = "rockchip,rk3036-lcdc",},
1660         {}
1661 };
1662 #endif
1663
1664 static struct platform_driver rk3036_lcdc_driver = {
1665         .probe = rk3036_lcdc_probe,
1666         .remove = rk3036_lcdc_remove,
1667         .driver = {
1668                 .name = "rk3036-lcdc",
1669                 .owner = THIS_MODULE,
1670                 .of_match_table = of_match_ptr(rk3036_lcdc_dt_ids),
1671         },
1672         .suspend = rk3036_lcdc_suspend,
1673         .resume = rk3036_lcdc_resume,
1674         .shutdown = rk3036_lcdc_shutdown,
1675 };
1676
1677 static int __init rk3036_lcdc_module_init(void)
1678 {
1679         return platform_driver_register(&rk3036_lcdc_driver);
1680 }
1681
1682 static void __exit rk3036_lcdc_module_exit(void)
1683 {
1684         platform_driver_unregister(&rk3036_lcdc_driver);
1685 }
1686
1687 fs_initcall(rk3036_lcdc_module_init);
1688 module_exit(rk3036_lcdc_module_exit);