drivers/video/rockchip/lcdc/rk3036_lcdc.c

   1 /*
   2  * drivers/video/rockchip/lcdc/rk3036_lcdc.c
   3  *
   4  * Copyright (C) 2014 ROCKCHIP, Inc.
   5  * Author:zhengyang<zhengyang@rock-chips.com>
   6  * This software is licensed under the terms of the GNU General Public
   7  * License version 2, as published by the Free Software Foundation, and
   8  * may be copied, distributed, and modified under those terms.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/kernel.h>
  19 #include <linux/errno.h>
  20 #include <linux/string.h>
  21 #include <linux/mm.h>
  22 #include <linux/slab.h>
  23 #include <linux/device.h>
  24 #include <linux/delay.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/platform_device.h>
  28 #include <linux/clk.h>
  29 #include <asm/div64.h>
  30 #include <linux/uaccess.h>
  31 #include <linux/rockchip/cpu.h>
  32 #include <linux/rockchip/iomap.h>
  33 #include <linux/rockchip/grf.h>
  34 #include <linux/rockchip/common.h>
  35 #include <dt-bindings/clock/rk_system_status.h>
  36 #if defined(CONFIG_ION_ROCKCHIP)
  37 #include <linux/rockchip-iovmm.h>
  38 #endif
  39 #include "rk3036_lcdc.h"
  40
  41 static int dbg_thresd;
  42 module_param(dbg_thresd, int, S_IRUGO | S_IWUSR);
  43
  44 #define DBG(level, x...) do {                   \
  45         if (unlikely(dbg_thresd >= level))      \
  46                 dev_info(dev_drv->dev, x);              \
  47         } while (0)
  48
  49 #define grf_writel(offset, v)   do { \
  50         writel_relaxed(v, RK_GRF_VIRT + offset); \
  51         dsb(); \
  52         } while (0)
  53
  54 static struct rk_lcdc_win lcdc_win[] = {
  55         [0] = {
  56                .name = "win0",
  57                .id = 0,
  58                .support_3d = false,
  59                },
  60         [1] = {
  61                .name = "win1",
  62                .id = 1,
  63                .support_3d = false,
  64                },
  65         [2] = {
  66                .name = "hwc",
  67                .id = 2,
  68                .support_3d = false,
  69                },
  70 };
  71
  72 static irqreturn_t rk3036_lcdc_isr(int irq, void *dev_id)
  73 {
  74         struct lcdc_device *lcdc_dev =
  75             (struct lcdc_device *)dev_id;
  76         ktime_t timestamp = ktime_get();
  77         u32 int_reg = lcdc_readl(lcdc_dev, INT_STATUS);
  78
  79         if (int_reg & m_FS_INT_STA) {
  80                 timestamp = ktime_get();
  81                 lcdc_msk_reg(lcdc_dev, INT_STATUS, m_FS_INT_CLEAR,
  82                              v_FS_INT_CLEAR(1));
  83                 /*if (lcdc_dev->driver.wait_fs) {*/
  84                 if (0) {
  85                         spin_lock(&(lcdc_dev->driver.cpl_lock));
  86                         complete(&(lcdc_dev->driver.frame_done));
  87                         spin_unlock(&(lcdc_dev->driver.cpl_lock));
  88                 }
  89                 lcdc_dev->driver.vsync_info.timestamp = timestamp;
  90                 wake_up_interruptible_all(&lcdc_dev->driver.vsync_info.wait);
  91
  92         } else if (int_reg & m_LF_INT_STA) {
  93                 lcdc_msk_reg(lcdc_dev, INT_STATUS, m_LF_INT_CLEAR,
  94                              v_LF_INT_CLEAR(1));
  95         }
  96         return IRQ_HANDLED;
  97 }
  98
  99 static int rk3036_lcdc_clk_enable(struct lcdc_device *lcdc_dev)
 100 {
 101 #ifdef CONFIG_RK_FPGA
 102         lcdc_dev->clk_on = 1;
 103         return 0;
 104 #endif
 105         if (!lcdc_dev->clk_on) {
 106                 clk_prepare_enable(lcdc_dev->hclk);
 107                 clk_prepare_enable(lcdc_dev->dclk);
 108                 clk_prepare_enable(lcdc_dev->aclk);
 109 /*              clk_prepare_enable(lcdc_dev->pd);*/
 110                 spin_lock(&lcdc_dev->reg_lock);
 111                 lcdc_dev->clk_on = 1;
 112                 spin_unlock(&lcdc_dev->reg_lock);
 113         }
 114
 115         return 0;
 116 }
 117
 118 static int rk3036_lcdc_clk_disable(struct lcdc_device *lcdc_dev)
 119 {
 120 #ifdef CONFIG_RK_FPGA
 121         lcdc_dev->clk_on = 0;
 122         return 0;
 123 #endif
 124         if (lcdc_dev->clk_on) {
 125                 spin_lock(&lcdc_dev->reg_lock);
 126                 lcdc_dev->clk_on = 0;
 127                 spin_unlock(&lcdc_dev->reg_lock);
 128                 mdelay(25);
 129                 clk_disable_unprepare(lcdc_dev->dclk);
 130                 clk_disable_unprepare(lcdc_dev->hclk);
 131                 clk_disable_unprepare(lcdc_dev->aclk);
 132 /*              clk_disable_unprepare(lcdc_dev->pd);*/
 133         }
 134
 135         return 0;
 136 }
 137
 138 static int rk3036_lcdc_enable_irq(struct rk_lcdc_driver *dev_drv)
 139 {
 140         u32 mask, val;
 141         struct lcdc_device *lcdc_dev = container_of(dev_drv,
 142                                         struct lcdc_device, driver);
 143         mask = m_FS_INT_CLEAR | m_FS_INT_EN;
 144         val = v_FS_INT_CLEAR(1) | v_FS_INT_EN(1);
 145         lcdc_msk_reg(lcdc_dev, INT_STATUS, mask, val);
 146         return 0;
 147 }
 148 /*
 149 static int rk3036_lcdc_disable_irq(struct lcdc_device *lcdc_dev)
 150 {
 151         u32 mask, val;
 152
 153         spin_lock(&lcdc_dev->reg_lock);
 154         if (likely(lcdc_dev->clk_on)) {
 155                 mask = m_FS_INT_CLEAR | m_FS_INT_EN;
 156                 val = v_FS_INT_CLEAR(0) | v_FS_INT_EN(0);
 157                 lcdc_msk_reg(lcdc_dev, INT_STATUS, mask, val);
 158                 spin_unlock(&lcdc_dev->reg_lock);
 159         } else {
 160                 spin_unlock(&lcdc_dev->reg_lock);
 161         }
 162         mdelay(1);
 163         return 0;
 164 }*/
 165
 166 static void rk_lcdc_read_reg_defalut_cfg(struct lcdc_device
 167                                              *lcdc_dev)
 168 {
 169         int reg = 0;
 170         u32 value = 0;
 171
 172         spin_lock(&lcdc_dev->reg_lock);
 173         for (reg = 0; reg < 0xe0; reg += 4)
 174                 value = lcdc_readl(lcdc_dev, reg);
 175
 176         spin_unlock(&lcdc_dev->reg_lock);
 177 }
 178
 179 static int rk3036_lcdc_alpha_cfg(struct lcdc_device *lcdc_dev)
 180 {
 181         int win0_top = 0;
 182         u32 mask, val;
 183         enum data_format win0_format = lcdc_dev->driver.win[0]->area[0].format;
 184         enum data_format win1_format = lcdc_dev->driver.win[1]->area[0].format;
 185
 186         int win0_alpha_en = ((win0_format == ARGB888) ||
 187                                 (win0_format == ABGR888)) ? 1 : 0;
 188         int win1_alpha_en = ((win1_format == ARGB888) ||
 189                                 (win1_format == ABGR888)) ? 1 : 0;
 190         int atv_layer_cnt = lcdc_dev->driver.win[0]->state +
 191                         lcdc_dev->driver.win[1]->state;
 192         u32 *_pv = (u32 *)lcdc_dev->regsbak;
 193
 194         _pv += (DSP_CTRL0 >> 2);
 195         win0_top = ((*_pv) & (m_WIN0_TOP)) >> 8;
 196
 197         if (win0_top && (atv_layer_cnt >= 2) && (win0_alpha_en)) {
 198                 mask =  m_WIN0_ALPHA_EN | m_WIN1_ALPHA_EN |
 199                         m_WIN1_PREMUL_SCALE;
 200                 val = v_WIN0_ALPHA_EN(1) | v_WIN1_ALPHA_EN(0) |
 201                         v_WIN1_PREMUL_SCALE(0);
 202                 lcdc_msk_reg(lcdc_dev, ALPHA_CTRL, mask, val);
 203
 204                 mask = m_WIN0_ALPHA_MODE | m_PREMUL_ALPHA_ENABLE |
 205                         m_ALPHA_MODE_SEL1;
 206                 val = v_WIN0_ALPHA_MODE(1) | v_PREMUL_ALPHA_ENABLE(1) |
 207                         v_ALPHA_MODE_SEL1(0);
 208                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
 209         } else if ((!win0_top) && (atv_layer_cnt >= 2) &&
 210                    (win1_alpha_en)) {
 211                 mask =  m_WIN0_ALPHA_EN | m_WIN1_ALPHA_EN |
 212                         m_WIN1_PREMUL_SCALE;
 213                 val = v_WIN0_ALPHA_EN(0) | v_WIN1_ALPHA_EN(1) |
 214                         v_WIN1_PREMUL_SCALE(0);
 215                 lcdc_msk_reg(lcdc_dev, ALPHA_CTRL, mask, val);
 216
 217                 mask = m_WIN1_ALPHA_MODE | m_PREMUL_ALPHA_ENABLE |
 218                         m_ALPHA_MODE_SEL1;
 219                 val = v_WIN1_ALPHA_MODE(1) | v_PREMUL_ALPHA_ENABLE(1) |
 220                         v_ALPHA_MODE_SEL1(0);
 221                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
 222         } else {
 223                 mask = m_WIN0_ALPHA_EN | m_WIN1_ALPHA_EN;
 224                 val = v_WIN0_ALPHA_EN(0) | v_WIN1_ALPHA_EN(0);
 225                 lcdc_msk_reg(lcdc_dev, ALPHA_CTRL, mask, val);
 226         }
 227
 228         if (lcdc_dev->driver.win[2]->state == 1) {
 229                 mask =  m_HWC_ALPAH_EN;
 230                 val = v_HWC_ALPAH_EN(1);
 231                 lcdc_msk_reg(lcdc_dev, ALPHA_CTRL, mask, val);
 232
 233                 mask =  m_HWC_ALPHA_MODE;
 234                 val = v_HWC_ALPHA_MODE(1);
 235                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
 236         } else {
 237                 mask =  m_HWC_ALPAH_EN;
 238                 val = v_HWC_ALPAH_EN(0);
 239                 lcdc_msk_reg(lcdc_dev, ALPHA_CTRL, mask, val);
 240         }
 241
 242         return 0;
 243 }
 244
 245 static void lcdc_layer_update_regs(struct lcdc_device *lcdc_dev,
 246                                    struct rk_lcdc_win *win)
 247 {
 248         u32 mask, val;
 249         int hwc_size;
 250
 251         if (win->state == 1) {
 252                 if (win->id == 0) {
 253                         mask = m_WIN0_EN | m_WIN0_FORMAT | m_WIN0_RB_SWAP;
 254                         val = v_WIN0_EN(win->state) |
 255                               v_WIN0_FORMAT(win->area[0].fmt_cfg) |
 256                               v_WIN0_RB_SWAP(win->area[0].swap_rb);
 257                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
 258                         lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_YRGB,
 259                                     v_X_SCL_FACTOR(win->scale_yrgb_x) |
 260                                     v_Y_SCL_FACTOR(win->scale_yrgb_y));
 261                         lcdc_writel(lcdc_dev, WIN0_SCL_FACTOR_CBR,
 262                                     v_X_SCL_FACTOR(win->scale_cbcr_x) |
 263                                     v_Y_SCL_FACTOR(win->scale_cbcr_y));
 264                         lcdc_msk_reg(lcdc_dev, WIN0_VIR,
 265                                      m_YRGB_VIR | m_CBBR_VIR,
 266                                      v_YRGB_VIR(win->area[0].y_vir_stride) |
 267                                      v_CBBR_VIR(win->area[0].uv_vir_stride));
 268                         lcdc_writel(lcdc_dev, WIN0_ACT_INFO,
 269                                     v_ACT_WIDTH(win->area[0].xact) |
 270                                     v_ACT_HEIGHT(win->area[0].yact));
 271                         lcdc_writel(lcdc_dev, WIN0_DSP_ST,
 272                                     v_DSP_STX(win->area[0].dsp_stx) |
 273                                     v_DSP_STY(win->area[0].dsp_sty));
 274                         lcdc_writel(lcdc_dev, WIN0_DSP_INFO,
 275                                     v_DSP_WIDTH(win->post_cfg.xsize) |
 276                                     v_DSP_HEIGHT(win->post_cfg.ysize));
 277
 278                         lcdc_writel(lcdc_dev, WIN0_YRGB_MST,
 279                                     win->area[0].y_addr);
 280                         lcdc_writel(lcdc_dev, WIN0_CBR_MST,
 281                                     win->area[0].uv_addr);
 282                 } else if (win->id == 1) {
 283                         mask = m_WIN1_EN | m_WIN1_FORMAT | m_WIN1_RB_SWAP;
 284                         val = v_WIN1_EN(win->state) |
 285                               v_WIN1_FORMAT(win->area[0].fmt_cfg) |
 286                               v_WIN1_RB_SWAP(win->area[0].swap_rb);
 287                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
 288                         lcdc_writel(lcdc_dev, WIN1_SCL_FACTOR_YRGB,
 289                                     v_X_SCL_FACTOR(win->scale_yrgb_x) |
 290                                     v_Y_SCL_FACTOR(win->scale_yrgb_y));
 291
 292                         lcdc_msk_reg(lcdc_dev, WIN1_VIR, m_YRGB_VIR,
 293                                      v_YRGB_VIR(win->area[0].y_vir_stride));
 294                         lcdc_writel(lcdc_dev, WIN1_ACT_INFO,
 295                                     v_ACT_WIDTH(win->area[0].xact) |
 296                                     v_ACT_HEIGHT(win->area[0].yact));
 297                         lcdc_writel(lcdc_dev, WIN1_DSP_INFO,
 298                                     v_DSP_WIDTH(win->post_cfg.xsize) |
 299                                     v_DSP_HEIGHT(win->post_cfg.ysize));
 300                         lcdc_writel(lcdc_dev, WIN1_DSP_ST,
 301                                     v_DSP_STX(win->area[0].dsp_stx) |
 302                                     v_DSP_STY(win->area[0].dsp_sty));
 303                         lcdc_writel(lcdc_dev, WIN1_MST, win->area[0].y_addr);
 304                 } else if (win->id == 2) {
 305                         mask = m_HWC_EN | m_HWC_LODAD_EN;
 306                         val = v_HWC_EN(win->state) | v_HWC_LODAD_EN(1);
 307                         lcdc_msk_reg(lcdc_dev, SYS_CTRL, mask, val);
 308                         if ((win->area[0].xsize == 32) &&
 309                             (win->area[0].ysize == 32))
 310                                 hwc_size = 0;
 311                         else if ((win->area[0].xsize == 64) &&
 312                                  (win->area[0].ysize == 64))
 313                                 hwc_size = 1;
 314                         else
 315                                 dev_err(lcdc_dev->dev,
 316                                         "unsupport hwc size:x=%d,y=%d\n",
 317                                         win->area[0].xsize,
 318                                         win->area[0].ysize);
 319                         lcdc_writel(lcdc_dev, HWC_DSP_ST,
 320                                     v_DSP_STX(win->area[0].dsp_stx) |
 321                                     v_DSP_STY(win->area[0].dsp_sty));
 322                         lcdc_writel(lcdc_dev, HWC_MST, win->area[0].y_addr);
 323                 }
 324         } else {
 325                 win->area[0].y_addr = 0;
 326                 win->area[0].uv_addr = 0;
 327                 if (win->id == 0) {
 328                         lcdc_msk_reg(lcdc_dev,
 329                                      SYS_CTRL, m_WIN0_EN, v_WIN0_EN(0));
 330                         lcdc_writel(lcdc_dev, WIN0_YRGB_MST,
 331                                     win->area[0].y_addr);
 332                         lcdc_writel(lcdc_dev, WIN0_CBR_MST,
 333                                     win->area[0].uv_addr);
 334                 } else if (win->id == 1) {
 335                         lcdc_msk_reg(lcdc_dev,
 336                                      SYS_CTRL, m_WIN1_EN, v_WIN1_EN(0));
 337                         lcdc_writel(lcdc_dev, WIN1_MST, win->area[0].y_addr);
 338                 } else if (win->id == 2) {
 339                         lcdc_msk_reg(lcdc_dev,
 340                                      SYS_CTRL, m_HWC_EN | m_HWC_LODAD_EN,
 341                                      v_HWC_EN(0) | v_HWC_LODAD_EN(0));
 342                         lcdc_writel(lcdc_dev, HWC_MST, win->area[0].y_addr);
 343                 }
 344         }
 345         rk3036_lcdc_alpha_cfg(lcdc_dev);
 346 }
 347
 348 static void lcdc_layer_enable(struct lcdc_device *lcdc_dev,
 349                               unsigned int win_id, bool open)
 350 {
 351         spin_lock(&lcdc_dev->reg_lock);
 352         if (likely(lcdc_dev->clk_on) &&
 353             lcdc_dev->driver.win[win_id]->state != open) {
 354                 if (open) {
 355                         if (!lcdc_dev->atv_layer_cnt) {
 356                                 dev_info(lcdc_dev->dev,
 357                                          "wakeup from standby!\n");
 358                                 lcdc_dev->standby = 0;
 359                         }
 360                         lcdc_dev->atv_layer_cnt |= (1 << win_id);
 361                 } else if ((lcdc_dev->atv_layer_cnt & (1 << win_id)) && (!open)) {
 362                         lcdc_dev->atv_layer_cnt &= ~(1 << win_id);
 363                 }
 364                 lcdc_dev->driver.win[win_id]->state = open;
 365                 if (!open) {
 366                         lcdc_layer_update_regs(lcdc_dev,
 367                                                lcdc_dev->driver.win[win_id]);
 368                         lcdc_cfg_done(lcdc_dev);
 369                 }
 370                 /*if no layer used,disable lcdc*/
 371                 if (!lcdc_dev->atv_layer_cnt) {
 372                         dev_info(lcdc_dev->dev,
 373                                  "no layer is used, go to standby!\n");
 374                         lcdc_dev->standby = 1;
 375                 }
 376         }
 377         spin_unlock(&lcdc_dev->reg_lock);
 378 }
 379 /*
 380 static int rk3036_lcdc_reg_update(struct rk_lcdc_driver *dev_drv)
 381 {
 382         struct lcdc_device *lcdc_dev =
 383             container_of(dev_drv, struct lcdc_device, driver);
 384         struct rk_lcdc_win *win0 = lcdc_dev->driver.win[0];
 385         struct rk_lcdc_win *win1 = lcdc_dev->driver.win[1];
 386         int timeout;
 387         unsigned long flags;
 388
 389         spin_lock(&lcdc_dev->reg_lock);
 390         if (likely(lcdc_dev->clk_on)) {
 391                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_LCDC_STANDBY,
 392                              v_LCDC_STANDBY(lcdc_dev->standby));
 393                 lcdc_layer_update_regs(lcdc_dev, win0);
 394                 lcdc_layer_update_regs(lcdc_dev, win1);
 395                 rk3036_lcdc_alpha_cfg(lcdc_dev);
 396                 lcdc_cfg_done(lcdc_dev);
 397         }
 398         spin_unlock(&lcdc_dev->reg_lock);
 399         if (0) {
 400                 spin_lock_irqsave(&dev_drv->cpl_lock, flags);
 401                 init_completion(&dev_drv->frame_done);
 402                 spin_unlock_irqrestore(&dev_drv->cpl_lock, flags);
 403                 timeout = wait_for_completion_timeout(&dev_drv->frame_done,
 404                                                       msecs_to_jiffies
 405                                                       (dev_drv->cur_screen->ft
 406                                                        + 5));
 407                 if (!timeout && (!dev_drv->frame_done.done)) {
 408                         dev_warn(lcdc_dev->dev,
 409                                  "wait for new frame start time out!\n");
 410                         return -ETIMEDOUT;
 411                 }
 412         }
 413         DBG(2, "%s for lcdc%d\n", __func__, lcdc_dev->id);
 414         return 0;
 415 }
 416 */
 417 static void rk3036_lcdc_reg_restore(struct lcdc_device *lcdc_dev)
 418 {
 419         memcpy((u8 *)lcdc_dev->regs, (u8 *)lcdc_dev->regsbak, 0xe0);
 420 }
 421
 422 static void rk3036_lcdc_mmu_en(struct rk_lcdc_driver *dev_drv)
 423 {
 424         u32 mask, val;
 425         struct lcdc_device *lcdc_dev =
 426             container_of(dev_drv, struct lcdc_device, driver);
 427
 428         /*spin_lock(&lcdc_dev->reg_lock);*/
 429         if (likely(lcdc_dev->clk_on)) {
 430                 mask = m_MMU_EN | m_AXI_MAX_OUTSTANDING_EN |
 431                         m_AXI_OUTSTANDING_MAX_NUM;
 432                 val = v_MMU_EN(1) | v_AXI_OUTSTANDING_MAX_NUM(31) |
 433                         v_AXI_MAX_OUTSTANDING_EN(1);
 434                 lcdc_msk_reg(lcdc_dev, AXI_BUS_CTRL, mask, val);
 435         }
 436         /*spin_unlock(&lcdc_dev->reg_lock);*/
 437 }
 438
 439 static int rk3036_lcdc_set_hwc_lut(struct rk_lcdc_driver *dev_drv,
 440                                    int *hwc_lut, int mode)
 441 {
 442         int i = 0;
 443         int __iomem *c;
 444         int v;
 445         int len = 256*4;
 446
 447         struct lcdc_device *lcdc_dev =
 448                         container_of(dev_drv, struct lcdc_device, driver);
 449         if (dev_drv->hwc_lut == NULL)
 450                 dev_drv->hwc_lut = devm_kzalloc(lcdc_dev->dev, len, GFP_KERNEL);
 451
 452         spin_lock(&lcdc_dev->reg_lock);
 453         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_HWC_LUT_EN, v_HWC_LUT_EN(0));
 454         lcdc_cfg_done(lcdc_dev);
 455         mdelay(25);
 456         for (i = 0; i < 256; i++) {
 457                 if (mode == 1)
 458                         dev_drv->hwc_lut[i] = hwc_lut[i];
 459                 v = dev_drv->hwc_lut[i];
 460                 c = lcdc_dev->hwc_lut_addr_base + i;
 461                 writel_relaxed(v, c);
 462         }
 463         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_HWC_LUT_EN, v_HWC_LUT_EN(1));
 464         lcdc_cfg_done(lcdc_dev);
 465         spin_unlock(&lcdc_dev->reg_lock);
 466         return 0;
 467 }
 468
 469 #if 0
 470 static int rk3036_lcdc_set_dclk(struct rk_lcdc_driver *dev_drv)
 471 {
 472 #ifdef CONFIG_RK_FPGA
 473         return 0;
 474 #endif
 475         int ret, fps;
 476         struct lcdc_device *lcdc_dev =
 477             container_of(dev_drv, struct lcdc_device, driver);
 478         struct rk_screen *screen = dev_drv->cur_screen;
 479
 480         ret = clk_set_rate(lcdc_dev->dclk, screen->mode.pixclock);
 481         if (ret)
 482                 dev_err(dev_drv->dev,
 483                         "set lcdc%d dclk failed\n", lcdc_dev->id);
 484         lcdc_dev->pixclock =
 485                  div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
 486         lcdc_dev->driver.pixclock = lcdc_dev->pixclock;
 487
 488         fps = rk_fb_calc_fps(screen, lcdc_dev->pixclock);
 489         screen->ft = 1000 / fps;
 490         dev_info(lcdc_dev->dev, "%s: dclk:%lu>>fps:%d ",
 491                  lcdc_dev->driver.name, clk_get_rate(lcdc_dev->dclk), fps);
 492         return 0;
 493 }
 494 #endif
 495 /********do basic init*********/
 496 static int rk3036_lcdc_pre_init(struct rk_lcdc_driver *dev_drv)
 497 {
 498         struct lcdc_device *lcdc_dev = container_of(dev_drv,
 499                                 struct lcdc_device, driver);
 500
 501         if (lcdc_dev->pre_init)
 502                 return 0;
 503         lcdc_dev->hclk = devm_clk_get(lcdc_dev->dev, "hclk_lcdc");
 504         lcdc_dev->aclk = devm_clk_get(lcdc_dev->dev, "aclk_lcdc");
 505         lcdc_dev->dclk = devm_clk_get(lcdc_dev->dev, "dclk_lcdc");
 506 /*      lcdc_dev->pd   = devm_clk_get(lcdc_dev->dev, "pd_lcdc"); */
 507
 508         if (/*IS_ERR(lcdc_dev->pd) ||*/ (IS_ERR(lcdc_dev->aclk)) ||
 509             (IS_ERR(lcdc_dev->dclk)) || (IS_ERR(lcdc_dev->hclk))) {
 510                 dev_err(lcdc_dev->dev, "failed to get lcdc%d clk source\n",
 511                         lcdc_dev->id);
 512         }
 513
 514         rk_disp_pwr_enable(dev_drv);
 515         rk3036_lcdc_clk_enable(lcdc_dev);
 516
 517         /*backup reg config at uboot*/
 518         rk_lcdc_read_reg_defalut_cfg(lcdc_dev);
 519         if (lcdc_readl(lcdc_dev, AXI_BUS_CTRL) & m_TVE_DAC_DCLK_EN)
 520                 dev_drv->cur_screen->type = SCREEN_TVOUT;
 521
 522         lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_AUTO_GATING_EN,
 523                      v_AUTO_GATING_EN(0));
 524         lcdc_cfg_done(lcdc_dev);
 525         if (dev_drv->iommu_enabled)
 526                 /*disable win0 to workaround iommu pagefault*/
 527                 lcdc_layer_enable(lcdc_dev, 0, 0);
 528         lcdc_dev->pre_init = true;
 529
 530         return 0;
 531 }
 532
 533 static int rk3036_load_screen(struct rk_lcdc_driver *dev_drv, bool initscreen)
 534 {
 535         int ret = -EINVAL;
 536         int fps;
 537         u16 face = 0;
 538         struct lcdc_device *lcdc_dev = container_of(dev_drv,
 539                                                 struct lcdc_device, driver);
 540         struct rk_screen *screen = dev_drv->cur_screen;
 541         u16 right_margin = screen->mode.right_margin;
 542         u16 left_margin = screen->mode.left_margin;
 543         u16 lower_margin = screen->mode.lower_margin;
 544         u16 upper_margin = screen->mode.upper_margin;
 545         u16 x_res = screen->mode.xres;
 546         u16 y_res = screen->mode.yres;
 547         u32 mask, val;
 548
 549         spin_lock(&lcdc_dev->reg_lock);
 550         if (likely(lcdc_dev->clk_on)) {
 551                 switch (screen->type) {
 552                 case SCREEN_HDMI:
 553                         mask = m_HDMI_DCLK_EN;
 554                         val = v_HDMI_DCLK_EN(1);
 555                         if (screen->pixelrepeat) {
 556                                 mask |= m_CORE_CLK_DIV_EN;
 557                                 val |= v_CORE_CLK_DIV_EN(1);
 558                         } else {
 559                                 mask |= m_CORE_CLK_DIV_EN;
 560                                 val |= v_CORE_CLK_DIV_EN(0);
 561                         }
 562                         lcdc_msk_reg(lcdc_dev, AXI_BUS_CTRL, mask, val);
 563                         mask = (1 << 4) | (1 << 5) | (1 << 6);
 564                         val = (screen->pin_hsync << 4) |
 565                                 (screen->pin_vsync << 5) |
 566                                 (screen->pin_den << 6);
 567                         grf_writel(RK3036_GRF_SOC_CON2, (mask << 16) | val);
 568                         break;
 569                 case SCREEN_TVOUT:
 570                         mask = m_TVE_DAC_DCLK_EN;
 571                         val = v_TVE_DAC_DCLK_EN(1);
 572                         if (screen->pixelrepeat) {
 573                                 mask |= m_CORE_CLK_DIV_EN;
 574                                 val |= v_CORE_CLK_DIV_EN(1);
 575                         } else {
 576                                 mask |= m_CORE_CLK_DIV_EN;
 577                                 val |= v_CORE_CLK_DIV_EN(0);
 578                         }
 579                         lcdc_msk_reg(lcdc_dev, AXI_BUS_CTRL, mask, val);
 580                         if ((x_res == 720) && (y_res == 576)) {
 581                                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
 582                                              m_TVE_MODE, v_TVE_MODE(TV_PAL));
 583                         } else if ((x_res == 720) && (y_res == 480)) {
 584                                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
 585                                              m_TVE_MODE, v_TVE_MODE(TV_NTSC));
 586                         } else {
 587                                 dev_err(lcdc_dev->dev,
 588                                         "unsupported video timing!\n");
 589                                 return -1;
 590                         }
 591                         break;
 592                 default:
 593                         dev_err(lcdc_dev->dev, "un supported interface!\n");
 594                         break;
 595                 }
 596
 597                 mask = m_DSP_OUT_FORMAT | m_HSYNC_POL | m_VSYNC_POL |
 598                     m_DEN_POL | m_DCLK_POL;
 599                 val = v_DSP_OUT_FORMAT(face) |
 600                         v_HSYNC_POL(screen->pin_hsync) |
 601                         v_VSYNC_POL(screen->pin_vsync) |
 602                         v_DEN_POL(screen->pin_den) |
 603                         v_DCLK_POL(screen->pin_dclk);
 604                 lcdc_msk_reg(lcdc_dev, DSP_CTRL0, mask, val);
 605
 606                 mask = m_BG_COLOR | m_DSP_BG_SWAP | m_DSP_RB_SWAP |
 607                     m_DSP_RG_SWAP | m_DSP_DELTA_SWAP |
 608                     m_DSP_DUMMY_SWAP | m_BLANK_EN;
 609
 610                 val = v_BG_COLOR(0x000000) | v_DSP_BG_SWAP(screen->swap_gb) |
 611                     v_DSP_RB_SWAP(screen->swap_rb) |
 612                     v_DSP_RG_SWAP(screen->swap_rg) |
 613                     v_DSP_DELTA_SWAP(screen->swap_delta) |
 614                                      v_DSP_DUMMY_SWAP(screen->swap_dumy) |
 615                                                       v_BLANK_EN(0) |
 616                                      v_BLACK_EN(0);
 617                 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, mask, val);
 618                 val =
 619                     v_HSYNC(screen->mode.hsync_len) | v_HORPRD(screen->mode.
 620                                                                hsync_len +
 621                                                                left_margin +
 622                                                                x_res +
 623                                                                right_margin);
 624                 lcdc_writel(lcdc_dev, DSP_HTOTAL_HS_END, val);
 625                 val = v_HAEP(screen->mode.hsync_len + left_margin + x_res) |
 626                     v_HASP(screen->mode.hsync_len + left_margin);
 627                 lcdc_writel(lcdc_dev, DSP_HACT_ST_END, val);
 628
 629                 if (screen->mode.vmode == FB_VMODE_INTERLACED) {
 630                         /*First Field Timing*/
 631                         lcdc_writel(lcdc_dev, DSP_VTOTAL_VS_END,
 632                                     v_VSYNC(screen->mode.vsync_len) |
 633                                     v_VERPRD(2 * (screen->mode.vsync_len +
 634                                                   upper_margin + lower_margin)
 635                                              + y_res + 1));
 636                         lcdc_writel(lcdc_dev, DSP_VACT_ST_END,
 637                                     v_VAEP(screen->mode.vsync_len +
 638                                         upper_margin + y_res/2) |
 639                                     v_VASP(screen->mode.vsync_len +
 640                                         upper_margin));
 641                         /*Second Field Timing*/
 642                         lcdc_writel(lcdc_dev, DSP_VS_ST_END_F1,
 643                                     v_VSYNC_ST_F1(screen->mode.vsync_len +
 644                                                   upper_margin + y_res/2 +
 645                                                   lower_margin) |
 646                                     v_VSYNC_END_F1(2 * screen->mode.vsync_len
 647                                                    + upper_margin + y_res/2 +
 648                                                    lower_margin));
 649                         lcdc_writel(lcdc_dev, DSP_VACT_ST_END_F1,
 650                                     v_VAEP(2 * (screen->mode.vsync_len +
 651                                                 upper_margin) + y_res +
 652                                                 lower_margin + 1) |
 653                                     v_VASP(2 * (screen->mode.vsync_len +
 654                                                 upper_margin) + y_res/2 +
 655                                                 lower_margin + 1));
 656
 657                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
 658                                      m_INTERLACE_DSP_EN |
 659                                      m_INTERLACE_DSP_POL |
 660                                      m_WIN1_DIFF_DCLK_EN |
 661                                      m_WIN0_YRGB_DEFLICK_EN |
 662                                      m_WIN0_CBR_DEFLICK_EN |
 663                                      m_WIN0_INTERLACE_EN |
 664                                      m_WIN1_INTERLACE_EN,
 665                                      v_INTERLACE_DSP_EN(1) |
 666                                      v_INTERLACE_DSP_POL(0) |
 667                                      v_WIN1_DIFF_DCLK_EN(1) |
 668                                      v_WIN0_YRGB_DEFLICK_EN(1) |
 669                                      v_WIN0_CBR_DEFLICK_EN(1) |
 670                                      v_WIN0_INTERLACE_EN(1) |
 671                                      v_WIN1_INTERLACE_EN(1));
 672                 } else {
 673                         val = v_VSYNC(screen->mode.vsync_len) |
 674                               v_VERPRD(screen->mode.vsync_len + upper_margin +
 675                                         y_res + lower_margin);
 676                         lcdc_writel(lcdc_dev, DSP_VTOTAL_VS_END, val);
 677
 678                         val = v_VAEP(screen->mode.vsync_len +
 679                                      upper_margin + y_res) |
 680                             v_VASP(screen->mode.vsync_len +
 681                                    screen->mode.upper_margin);
 682                         lcdc_writel(lcdc_dev, DSP_VACT_ST_END, val);
 683
 684                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0,
 685                                      m_INTERLACE_DSP_EN |
 686                                      m_WIN1_DIFF_DCLK_EN |
 687                                      m_WIN0_YRGB_DEFLICK_EN |
 688                                      m_WIN0_CBR_DEFLICK_EN |
 689                                      m_WIN0_INTERLACE_EN |
 690                                      m_WIN1_INTERLACE_EN,
 691                                      v_INTERLACE_DSP_EN(0) |
 692                                      v_WIN1_DIFF_DCLK_EN(0) |
 693                                      v_WIN0_YRGB_DEFLICK_EN(0) |
 694                                      v_WIN0_CBR_DEFLICK_EN(0) |
 695                                      v_WIN0_INTERLACE_EN(1) |
 696                                      v_WIN1_INTERLACE_EN(1));
 697                 }
 698         }
 699         spin_unlock(&lcdc_dev->reg_lock);
 700
 701         ret = clk_set_rate(lcdc_dev->dclk, screen->mode.pixclock);
 702         if (ret)
 703                 dev_err(dev_drv->dev,
 704                         "set lcdc%d dclk failed\n", lcdc_dev->id);
 705         lcdc_dev->pixclock =
 706             div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
 707         lcdc_dev->driver.pixclock = lcdc_dev->pixclock;
 708
 709         fps = rk_fb_calc_fps(screen, lcdc_dev->pixclock);
 710         screen->ft = 1000 / fps;
 711         dev_info(lcdc_dev->dev, "%s: dclk:%lu>>fps:%d ",
 712                  lcdc_dev->driver.name, clk_get_rate(lcdc_dev->dclk), fps);
 713         if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
 714                 dev_drv->trsm_ops->enable();
 715         if (screen->init)
 716                 screen->init();
 717
 718         return 0;
 719 }
 720
 721 static int rk3036_lcdc_open(struct rk_lcdc_driver *dev_drv, int win_id,
 722                             bool open)
 723 {
 724         struct lcdc_device *lcdc_dev = container_of(dev_drv,
 725                                         struct lcdc_device, driver);
 726
 727         /*enable clk,when first layer open */
 728         if ((open) && (!lcdc_dev->atv_layer_cnt)) {
 729                 rk3036_lcdc_pre_init(dev_drv);
 730                 rk3036_lcdc_clk_enable(lcdc_dev);
 731         #if defined(CONFIG_ROCKCHIP_IOMMU)
 732                 if (dev_drv->iommu_enabled) {
 733                         if (!dev_drv->mmu_dev) {
 734                                 dev_drv->mmu_dev =
 735                                 rk_fb_get_sysmmu_device_by_compatible(
 736                                         dev_drv->mmu_dts_name);
 737                                 if (dev_drv->mmu_dev) {
 738                                         rk_fb_platform_set_sysmmu(dev_drv->mmu_dev,
 739                                                                   dev_drv->dev);
 740                                 } else {
 741                                         dev_err(dev_drv->dev,
 742                                                 "failed to get iommu device\n"
 743                                                 );
 744                                         return -1;
 745                                 }
 746                         }
 747                 }
 748         #endif
 749                 rk3036_lcdc_reg_restore(lcdc_dev);
 750                 /*if (dev_drv->iommu_enabled)
 751                         rk3036_lcdc_mmu_en(dev_drv);*/
 752                 if ((support_uboot_display() && (lcdc_dev->prop == PRMRY))) {
 753                         /*rk3036_lcdc_set_dclk(dev_drv);*/
 754                         rk3036_lcdc_enable_irq(dev_drv);
 755                 } else {
 756                         rk3036_load_screen(dev_drv, 1);
 757                 }
 758         }
 759
 760         if (win_id < ARRAY_SIZE(lcdc_win))
 761                 lcdc_layer_enable(lcdc_dev, win_id, open);
 762         else
 763                 dev_err(lcdc_dev->dev, "invalid win id:%d\n", win_id);
 764
 765         /*when all layer closed,disable clk */
 766 /*
 767         if ((!open) && (!lcdc_dev->atv_layer_cnt)) {
 768                 rk3036_lcdc_disable_irq(lcdc_dev);
 769                 rk3036_lcdc_reg_update(dev_drv);
 770                 #if defined(CONFIG_ROCKCHIP_IOMMU)
 771                 if (dev_drv->iommu_enabled) {
 772                         if (dev_drv->mmu_dev)
 773                                 rockchip_iovmm_deactivate(dev_drv->dev);
 774                 }
 775                 #endif
 776                 rk3036_lcdc_clk_disable(lcdc_dev);
 777         }
 778 */
 779         return 0;
 780 }
 781
 782 static int rk3036_lcdc_set_par(struct rk_lcdc_driver *dev_drv, int win_id)
 783 {
 784         struct lcdc_device *lcdc_dev =
 785                         container_of(dev_drv, struct lcdc_device, driver);
 786         struct rk_screen *screen = dev_drv->cur_screen;
 787         struct rk_lcdc_win *win = NULL;
 788         char fmt[9] = "NULL";
 789
 790         if (!screen) {
 791                 dev_err(dev_drv->dev, "screen is null!\n");
 792                 return -ENOENT;
 793         }
 794
 795         if (win_id == 0) {
 796                 win = dev_drv->win[0];
 797         } else if (win_id == 1) {
 798                 win = dev_drv->win[1];
 799         } else if (win_id == 2) {
 800                 win = dev_drv->win[2];
 801         } else {
 802                 dev_err(dev_drv->dev, "un supported win number:%d\n", win_id);
 803                 return -EINVAL;
 804         }
 805
 806         spin_lock(&lcdc_dev->reg_lock);
 807         win->post_cfg.xpos = win->area[0].xpos * (dev_drv->overscan.left +
 808                 dev_drv->overscan.right)/200 + screen->mode.xres *
 809                         (100 - dev_drv->overscan.left) / 200;
 810
 811         win->post_cfg.ypos = win->area[0].ypos * (dev_drv->overscan.top +
 812                 dev_drv->overscan.bottom)/200 +
 813                 screen->mode.yres *
 814                         (100 - dev_drv->overscan.top) / 200;
 815         win->post_cfg.xsize = win->area[0].xsize *
 816                                 (dev_drv->overscan.left +
 817                                 dev_drv->overscan.right)/200;
 818         win->post_cfg.ysize = win->area[0].ysize *
 819                                 (dev_drv->overscan.top +
 820                                 dev_drv->overscan.bottom)/200;
 821
 822         win->area[0].dsp_stx = win->post_cfg.xpos + screen->mode.left_margin +
 823                                 screen->mode.hsync_len;
 824         if (screen->mode.vmode == FB_VMODE_INTERLACED) {
 825                 win->post_cfg.ysize /= 2;
 826                 win->area[0].dsp_sty = win->post_cfg.ypos/2 +
 827                                         screen->mode.upper_margin +
 828                                         screen->mode.vsync_len;
 829         } else {
 830                 win->area[0].dsp_sty = win->post_cfg.ypos +
 831                                         screen->mode.upper_margin +
 832                                         screen->mode.vsync_len;
 833         }
 834         win->scale_yrgb_x = calscale(win->area[0].xact, win->post_cfg.xsize);
 835         win->scale_yrgb_y = calscale(win->area[0].yact, win->post_cfg.ysize);
 836
 837         switch (win->area[0].format) {
 838         case ARGB888:
 839                 win->area[0].fmt_cfg = VOP_FORMAT_ARGB888;
 840                 win->area[0].swap_rb = 0;
 841                 break;
 842         case XBGR888:
 843                 win->area[0].fmt_cfg = VOP_FORMAT_ARGB888;
 844                 win->area[0].swap_rb = 1;
 845                 break;
 846         case ABGR888:
 847                 win->area[0].fmt_cfg = VOP_FORMAT_ARGB888;
 848                 win->area[0].swap_rb = 1;
 849                 break;
 850         case RGB888:
 851                 win->area[0].fmt_cfg = VOP_FORMAT_RGB888;
 852                 win->area[0].swap_rb = 0;
 853                 break;
 854         case RGB565:
 855                 win->area[0].fmt_cfg = VOP_FORMAT_RGB565;
 856                 win->area[0].swap_rb = 0;
 857                 break;
 858         case YUV444:
 859                 if (win_id == 0) {
 860                         win->area[0].fmt_cfg = VOP_FORMAT_YCBCR444;
 861                         win->scale_cbcr_x = calscale(win->area[0].xact,
 862                                                      win->post_cfg.xsize);
 863                         win->scale_cbcr_y = calscale(win->area[0].yact,
 864                                                      win->post_cfg.ysize);
 865                         win->area[0].swap_rb = 0;
 866                 } else {
 867                         dev_err(lcdc_dev->driver.dev,
 868                                 "%s:un supported format!\n",
 869                                 __func__);
 870                 }
 871                 break;
 872         case YUV422:
 873                 if (win_id == 0) {
 874                         win->area[0].fmt_cfg = VOP_FORMAT_YCBCR422;
 875                         win->scale_cbcr_x = calscale((win->area[0].xact / 2),
 876                                                      win->post_cfg.xsize);
 877                         win->scale_cbcr_y = calscale(win->area[0].yact,
 878                                                      win->post_cfg.ysize);
 879                         win->area[0].swap_rb = 0;
 880                 } else {
 881                         dev_err(lcdc_dev->driver.dev,
 882                                 "%s:un supported format!\n",
 883                                 __func__);
 884                 }
 885                 break;
 886         case YUV420:
 887                 if (win_id == 0) {
 888                         win->area[0].fmt_cfg = VOP_FORMAT_YCBCR420;
 889                         win->scale_cbcr_x = calscale(win->area[0].xact / 2,
 890                                                      win->post_cfg.xsize);
 891                         win->scale_cbcr_y = calscale(win->area[0].yact / 2,
 892                                                      win->post_cfg.ysize);
 893                         win->area[0].swap_rb = 0;
 894                 } else {
 895                         dev_err(lcdc_dev->driver.dev,
 896                                 "%s:un supported format!\n",
 897                                 __func__);
 898                 }
 899                 break;
 900         default:
 901                 dev_err(lcdc_dev->driver.dev, "%s:un supported format!\n",
 902                         __func__);
 903                 break;
 904         }
 905         spin_unlock(&lcdc_dev->reg_lock);
 906
 907         DBG(2, "lcdc%d>>%s\n"
 908                 ">>format:%s>>>xact:%d>>yact:%d>>xsize:%d>>ysize:%d\n"
 909                 ">>xvir:%d>>yvir:%d>>xpos:%d>>ypos:%d>>\n", lcdc_dev->id,
 910                 __func__, get_format_string(win->area[0].format, fmt),
 911                 win->area[0].xact, win->area[0].yact, win->post_cfg.xsize,
 912                 win->post_cfg.ysize, win->area[0].xvir, win->area[0].yvir,
 913                 win->post_cfg.xpos, win->post_cfg.ypos);
 914         return 0;
 915 }
 916
 917 static int rk3036_lcdc_pan_display(struct rk_lcdc_driver *dev_drv, int win_id)
 918 {
 919         struct lcdc_device *lcdc_dev = container_of(dev_drv,
 920                                                 struct lcdc_device, driver);
 921         struct rk_lcdc_win *win = NULL;
 922         struct rk_screen *screen = dev_drv->cur_screen;
 923
 924         if (!screen) {
 925                 dev_err(dev_drv->dev, "screen is null!\n");
 926                 return -ENOENT;
 927         }
 928
 929         if (win_id == 0) {
 930                 win = dev_drv->win[0];
 931         } else if (win_id == 1) {
 932                 win = dev_drv->win[1];
 933         } else if (win_id == 2) {
 934                 win = dev_drv->win[2];
 935         } else {
 936                 dev_err(dev_drv->dev, "invalid win number:%d!\n", win_id);
 937                 return -EINVAL;
 938         }
 939
 940         spin_lock(&lcdc_dev->reg_lock);
 941         if (likely(lcdc_dev->clk_on)) {
 942                 win->area[0].y_addr = win->area[0].smem_start +
 943                                         win->area[0].y_offset;
 944                 win->area[0].uv_addr = win->area[0].cbr_start +
 945                                         win->area[0].c_offset;
 946                 if (win->area[0].y_addr)
 947                         lcdc_layer_update_regs(lcdc_dev, win);
 948                 /*lcdc_cfg_done(lcdc_dev);*/
 949         }
 950         spin_unlock(&lcdc_dev->reg_lock);
 951
 952         DBG(2, "lcdc%d>>%s:y_addr:0x%x>>uv_addr:0x%x>>offset:%d\n",
 953             lcdc_dev->id, __func__, win->area[0].y_addr,
 954             win->area[0].uv_addr, win->area[0].y_offset);
 955          /* this is the first frame of the system,
 956                 enable frame start interrupt*/
 957         if ((dev_drv->first_frame))  {
 958                 dev_drv->first_frame = 0;
 959                 rk3036_lcdc_enable_irq(dev_drv);
 960         }
 961         return 0;
 962 }
 963
 964 static int rk3036_lcdc_ioctl(struct rk_lcdc_driver *dev_drv, unsigned int cmd,
 965                              unsigned long arg, int win_id)
 966 {
 967         struct lcdc_device *lcdc_dev = container_of(dev_drv,
 968                                         struct lcdc_device, driver);
 969         u32 panel_size[2];
 970         void __user *argp = (void __user *)arg;
 971         struct color_key_cfg clr_key_cfg;
 972
 973         switch (cmd) {
 974         case RK_FBIOGET_PANEL_SIZE:
 975                 panel_size[0] = lcdc_dev->screen->mode.xres;
 976                 panel_size[1] = lcdc_dev->screen->mode.yres;
 977                 if (copy_to_user(argp, panel_size, 8))
 978                         return -EFAULT;
 979                 break;
 980         case RK_FBIOPUT_COLOR_KEY_CFG:
 981                 if (copy_from_user(&clr_key_cfg, argp,
 982                                    sizeof(struct color_key_cfg)))
 983                         return -EFAULT;
 984                 lcdc_writel(lcdc_dev, WIN0_COLOR_KEY,
 985                             clr_key_cfg.win0_color_key_cfg);
 986                 lcdc_writel(lcdc_dev, WIN1_COLOR_KEY,
 987                             clr_key_cfg.win1_color_key_cfg);
 988                 break;
 989
 990         default:
 991                 break;
 992         }
 993         return 0;
 994 }
 995
 996 static int rk3036_lcdc_get_win_id(struct rk_lcdc_driver *dev_drv,
 997                                   const char *id)
 998 {
 999         int win_id = 0;
1000
1001         mutex_lock(&dev_drv->fb_win_id_mutex);
1002         if (!strcmp(id, "fb0"))
1003                 win_id = dev_drv->fb0_win_id;
1004         else if (!strcmp(id, "fb1"))
1005                 win_id = dev_drv->fb1_win_id;
1006         else if (!strcmp(id, "fb2"))
1007                 win_id = dev_drv->fb2_win_id;
1008         mutex_unlock(&dev_drv->fb_win_id_mutex);
1009
1010         return win_id;
1011 }
1012
1013 static int rk3036_lcdc_get_win_state(struct rk_lcdc_driver *dev_drv,
1014                                      int win_id)
1015 {
1016         return dev_drv->win[win_id]->state;
1017 }
1018
1019 static int rk3036_lcdc_ovl_mgr(struct rk_lcdc_driver *dev_drv, int swap,
1020                                bool set)
1021 {
1022         struct lcdc_device *lcdc_dev =
1023             container_of(dev_drv, struct lcdc_device, driver);
1024         struct rk_lcdc_win *win0 = lcdc_dev->driver.win[0];
1025         struct rk_lcdc_win *win1 = lcdc_dev->driver.win[1];
1026         int ovl, needswap = 0;
1027
1028         if (!swap) {
1029                 if (win0->z_order >= 0 &&
1030                     win1->z_order >= 0 &&
1031                     win0->z_order > win1->z_order)
1032                         needswap = 1;
1033                 else
1034                         needswap = 0;
1035         } else {
1036                 needswap = swap;
1037         }
1038         spin_lock(&lcdc_dev->reg_lock);
1039         if (lcdc_dev->clk_on) {
1040                 if (set) {
1041                         lcdc_msk_reg(lcdc_dev, DSP_CTRL0, m_WIN0_TOP,
1042                                      v_WIN0_TOP(needswap));
1043                         ovl = swap;
1044                 } else {
1045                         ovl = lcdc_read_bit(lcdc_dev, DSP_CTRL0, m_WIN0_TOP);
1046                 }
1047         } else {
1048                 ovl = -EPERM;
1049         }
1050         spin_unlock(&lcdc_dev->reg_lock);
1051
1052         return ovl;
1053 }
1054
1055 static int rk3036_lcdc_early_suspend(struct rk_lcdc_driver *dev_drv)
1056 {
1057         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1058                                         struct lcdc_device, driver);
1059         if (dev_drv->suspend_flag)
1060                 return 0;
1061         dev_drv->suspend_flag = 1;
1062         flush_kthread_worker(&dev_drv->update_regs_worker);
1063
1064         if (dev_drv->trsm_ops && dev_drv->trsm_ops->disable)
1065                 dev_drv->trsm_ops->disable();
1066         spin_lock(&lcdc_dev->reg_lock);
1067         if (likely(lcdc_dev->clk_on)) {
1068                 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_BLANK_EN,
1069                              v_BLANK_EN(1));
1070                 lcdc_msk_reg(lcdc_dev, INT_STATUS, m_FS_INT_CLEAR,
1071                              v_FS_INT_CLEAR(1));
1072                 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_OUT_ZERO,
1073                              v_DSP_OUT_ZERO(1));
1074                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_LCDC_STANDBY,
1075                              v_LCDC_STANDBY(1));
1076                 lcdc_cfg_done(lcdc_dev);
1077                 if (dev_drv->iommu_enabled) {
1078                         if (dev_drv->mmu_dev)
1079                                 rockchip_iovmm_deactivate(dev_drv->dev);
1080                 }
1081                 spin_unlock(&lcdc_dev->reg_lock);
1082         } else {
1083                 spin_unlock(&lcdc_dev->reg_lock);
1084                 return 0;
1085         }
1086         rk3036_lcdc_clk_disable(lcdc_dev);
1087         rk_disp_pwr_disable(dev_drv);
1088         return 0;
1089 }
1090
1091 static int rk3036_lcdc_early_resume(struct rk_lcdc_driver *dev_drv)
1092 {
1093         struct lcdc_device *lcdc_dev =
1094             container_of(dev_drv, struct lcdc_device, driver);
1095
1096         if (!dev_drv->suspend_flag)
1097                 return 0;
1098         rk_disp_pwr_enable(dev_drv);
1099         dev_drv->suspend_flag = 0;
1100
1101         if (lcdc_dev->atv_layer_cnt) {
1102                 rk3036_lcdc_clk_enable(lcdc_dev);
1103                 rk3036_lcdc_reg_restore(lcdc_dev);
1104                 /*set hwc lut*/
1105                 rk3036_lcdc_set_hwc_lut(dev_drv, dev_drv->hwc_lut, 0);
1106
1107                 spin_lock(&lcdc_dev->reg_lock);
1108
1109                 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_DSP_OUT_ZERO,
1110                              v_DSP_OUT_ZERO(0));
1111                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_LCDC_STANDBY,
1112                              v_LCDC_STANDBY(0));
1113                 lcdc_msk_reg(lcdc_dev, DSP_CTRL1, m_BLANK_EN,
1114                              v_BLANK_EN(0));
1115                 lcdc_cfg_done(lcdc_dev);
1116                 if (dev_drv->iommu_enabled) {
1117                         if (dev_drv->mmu_dev)
1118                                 rockchip_iovmm_activate(dev_drv->dev);
1119                 }
1120                 spin_unlock(&lcdc_dev->reg_lock);
1121         }
1122
1123         if (dev_drv->trsm_ops && dev_drv->trsm_ops->enable)
1124                 dev_drv->trsm_ops->enable();
1125         return 0;
1126 }
1127
1128
1129 static int rk3036_lcdc_blank(struct rk_lcdc_driver *dev_drv,
1130                              int win_id, int blank_mode)
1131 {
1132         switch (blank_mode) {
1133         case FB_BLANK_UNBLANK:
1134                 rk3036_lcdc_early_resume(dev_drv);
1135                 break;
1136         case FB_BLANK_NORMAL:
1137                 rk3036_lcdc_early_suspend(dev_drv);
1138                 break;
1139         default:
1140                 rk3036_lcdc_early_suspend(dev_drv);
1141                 break;
1142         }
1143
1144         dev_info(dev_drv->dev, "blank mode:%d\n", blank_mode);
1145
1146         return 0;
1147 }
1148
1149 static int rk3036_lcdc_cfg_done(struct rk_lcdc_driver *dev_drv)
1150 {
1151         struct lcdc_device *lcdc_dev =
1152             container_of(dev_drv, struct lcdc_device, driver);
1153         int i;
1154         struct rk_lcdc_win *win = NULL;
1155
1156         spin_lock(&lcdc_dev->reg_lock);
1157         if (lcdc_dev->clk_on) {
1158                 #if defined(CONFIG_ROCKCHIP_IOMMU)
1159                 if (dev_drv->iommu_enabled) {
1160                         if (!lcdc_dev->iommu_status && dev_drv->mmu_dev) {
1161                                 lcdc_dev->iommu_status = 1;
1162                                 if (support_uboot_display() &&
1163                                     lcdc_dev->prop == PRMRY) {
1164                                         lcdc_msk_reg(lcdc_dev, SYS_CTRL,
1165                                                      m_WIN0_EN,
1166                                                      v_WIN0_EN(0));
1167                                 }
1168                                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_LCDC_STANDBY,
1169                                              v_LCDC_STANDBY(1));
1170                                 lcdc_cfg_done(lcdc_dev);
1171                                 mdelay(50);
1172                                 rockchip_iovmm_activate(dev_drv->dev);
1173                                 rk3036_lcdc_mmu_en(dev_drv);
1174                         }
1175                 }
1176                 #endif
1177                 lcdc_msk_reg(lcdc_dev, SYS_CTRL, m_LCDC_STANDBY,
1178                              v_LCDC_STANDBY(lcdc_dev->standby));
1179                 for (i = 0; i < ARRAY_SIZE(lcdc_win); i++) {
1180                         win = dev_drv->win[i];
1181                         if ((win->state == 0) && (win->last_state == 1))
1182                                 lcdc_layer_update_regs(lcdc_dev, win);
1183                         win->last_state = win->state;
1184                 }
1185                 lcdc_cfg_done(lcdc_dev);
1186         }
1187         spin_unlock(&lcdc_dev->reg_lock);
1188         return 0;
1189 }
1190
1191 /*
1192         a:[-30~0]:
1193             sin_hue = sin(a)*256 +0x100;
1194             cos_hue = cos(a)*256;
1195         a:[0~30]
1196             sin_hue = sin(a)*256;
1197             cos_hue = cos(a)*256;
1198 */
1199 static int rk3036_lcdc_get_bcsh_hue(struct rk_lcdc_driver *dev_drv,
1200                                     bcsh_hue_mode mode)
1201 {
1202         struct lcdc_device *lcdc_dev =
1203             container_of(dev_drv, struct lcdc_device, driver);
1204         u32 val;
1205
1206         spin_lock(&lcdc_dev->reg_lock);
1207         if (lcdc_dev->clk_on) {
1208                 val = lcdc_readl(lcdc_dev, BCSH_H);
1209                 switch (mode) {
1210                 case H_SIN:
1211                         val &= m_BCSH_SIN_HUE;
1212                         break;
1213                 case H_COS:
1214                         val &= m_BCSH_COS_HUE;
1215                         val >>= 8;
1216                         break;
1217                 default:
1218                         break;
1219                 }
1220         }
1221         spin_unlock(&lcdc_dev->reg_lock);
1222
1223         return val;
1224 }
1225
1226
1227 static int rk3036_lcdc_set_bcsh_hue(struct rk_lcdc_driver *dev_drv,
1228                                     int sin_hue, int cos_hue)
1229 {
1230         struct lcdc_device *lcdc_dev =
1231             container_of(dev_drv, struct lcdc_device, driver);
1232         u32 mask, val;
1233
1234         spin_lock(&lcdc_dev->reg_lock);
1235         if (lcdc_dev->clk_on) {
1236                 mask = m_BCSH_SIN_HUE | m_BCSH_COS_HUE;
1237                 val = v_BCSH_SIN_HUE(sin_hue) | v_BCSH_COS_HUE(cos_hue);
1238                 lcdc_msk_reg(lcdc_dev, BCSH_H, mask, val);
1239                 lcdc_cfg_done(lcdc_dev);
1240         }
1241         spin_unlock(&lcdc_dev->reg_lock);
1242
1243         return 0;
1244 }
1245
1246 static int rk3036_lcdc_set_bcsh_bcs(struct rk_lcdc_driver *dev_drv,
1247                                     bcsh_bcs_mode mode, int value)
1248 {
1249         struct lcdc_device *lcdc_dev =
1250             container_of(dev_drv, struct lcdc_device, driver);
1251         u32 mask, val;
1252
1253         spin_lock(&lcdc_dev->reg_lock);
1254         if (lcdc_dev->clk_on) {
1255                 switch (mode) {
1256                 case BRIGHTNESS:
1257                 /*from 0 to 255,typical is 128*/
1258                         if (value < 0x20)
1259                                 value += 0x20;
1260                         else if (value >= 0x20)
1261                                 value = value - 0x20;
1262                         mask =  m_BCSH_BRIGHTNESS;
1263                         val = v_BCSH_BRIGHTNESS(value);
1264                         break;
1265                 case CONTRAST:
1266                 /*from 0 to 510,typical is 256*/
1267                         mask =  m_BCSH_CONTRAST;
1268                         val =  v_BCSH_CONTRAST(value);
1269                         break;
1270                 case SAT_CON:
1271                 /*from 0 to 1015,typical is 256*/
1272                         mask = m_BCSH_SAT_CON;
1273                         val = v_BCSH_SAT_CON(value);
1274                         break;
1275                 default:
1276                         break;
1277                 }
1278                 lcdc_msk_reg(lcdc_dev, BCSH_BCS, mask, val);
1279                 lcdc_cfg_done(lcdc_dev);
1280         }
1281         spin_unlock(&lcdc_dev->reg_lock);
1282         return val;
1283 }
1284
1285 static int rk3036_lcdc_get_bcsh_bcs(struct rk_lcdc_driver *dev_drv,
1286                                     bcsh_bcs_mode mode)
1287 {
1288         struct lcdc_device *lcdc_dev =
1289             container_of(dev_drv, struct lcdc_device, driver);
1290         u32 val;
1291
1292         spin_lock(&lcdc_dev->reg_lock);
1293         if (lcdc_dev->clk_on) {
1294                 val = lcdc_readl(lcdc_dev, BCSH_BCS);
1295                 switch (mode) {
1296                 case BRIGHTNESS:
1297                         val &= m_BCSH_BRIGHTNESS;
1298                         if (val > 0x20)
1299                                 val -= 0x20;
1300                         else if (val == 0x20)
1301                                 val = -32;
1302                         break;
1303                 case CONTRAST:
1304                         val &= m_BCSH_CONTRAST;
1305                         val >>= 8;
1306                         break;
1307                 case SAT_CON:
1308                         val &= m_BCSH_SAT_CON;
1309                         val >>= 16;
1310                         break;
1311                 default:
1312                         break;
1313                 }
1314         }
1315         spin_unlock(&lcdc_dev->reg_lock);
1316         return val;
1317 }
1318
1319
1320 static int rk3036_lcdc_open_bcsh(struct rk_lcdc_driver *dev_drv, bool open)
1321 {
1322         struct lcdc_device *lcdc_dev =
1323             container_of(dev_drv, struct lcdc_device, driver);
1324         u32 mask, val;
1325
1326         spin_lock(&lcdc_dev->reg_lock);
1327         if (lcdc_dev->clk_on) {
1328                 if (open) {
1329                         lcdc_writel(lcdc_dev, BCSH_CTRL,
1330                                     v_BCSH_EN(1) | v_BCSH_OUT_MODE(3));
1331                         lcdc_writel(lcdc_dev, BCSH_BCS,
1332                                     v_BCSH_BRIGHTNESS(0x00) |
1333                                     v_BCSH_CONTRAST(0x80) |
1334                                     v_BCSH_SAT_CON(0x80));
1335                         lcdc_writel(lcdc_dev, BCSH_H, v_BCSH_COS_HUE(0x80));
1336                 } else {
1337                         mask = m_BCSH_EN;
1338                         val = v_BCSH_EN(0);
1339                         lcdc_msk_reg(lcdc_dev, BCSH_CTRL, mask, val);
1340                 }
1341                 lcdc_cfg_done(lcdc_dev);
1342         }
1343         spin_unlock(&lcdc_dev->reg_lock);
1344         return 0;
1345 }
1346
1347 static int rk3036_lcdc_set_overscan(struct rk_lcdc_driver *dev_drv,
1348                                     struct overscan *overscan)
1349 {
1350         int i;
1351
1352         dev_drv->overscan = *overscan;
1353         for (i = 0; i < dev_drv->lcdc_win_num; i++) {
1354                 if (dev_drv->win[i] && dev_drv->win[i]->state) {
1355                         rk3036_lcdc_set_par(dev_drv, i);
1356                         rk3036_lcdc_pan_display(dev_drv, i);
1357                 }
1358         }
1359         rk3036_lcdc_cfg_done(dev_drv);
1360         return 0;
1361 }
1362
1363 static int rk3036_fb_win_remap(struct rk_lcdc_driver *dev_drv, u16 order)
1364 {
1365         struct rk_lcdc_win_area area;
1366         int fb2_win_id, fb1_win_id, fb0_win_id;
1367
1368         mutex_lock(&dev_drv->fb_win_id_mutex);
1369         if (order == FB_DEFAULT_ORDER)
1370                 order = FB0_WIN0_FB1_WIN1_FB2_WIN2;
1371
1372         fb2_win_id = order / 100;
1373         fb1_win_id = (order / 10) % 10;
1374         fb0_win_id = order % 10;
1375
1376         if (fb0_win_id != dev_drv->fb0_win_id) {
1377                 area = dev_drv->win[(int)dev_drv->fb0_win_id]->area[0];
1378                 dev_drv->win[(int)dev_drv->fb0_win_id]->area[0] =
1379                         dev_drv->win[fb0_win_id]->area[0];
1380                 dev_drv->win[fb0_win_id]->area[0] = area;
1381                 dev_drv->fb0_win_id = fb0_win_id;
1382         }
1383         dev_drv->fb1_win_id = fb1_win_id;
1384         dev_drv->fb2_win_id = fb2_win_id;
1385
1386         mutex_unlock(&dev_drv->fb_win_id_mutex);
1387
1388         return 0;
1389 }
1390
1391 static int rk3036_lcdc_fps_mgr(struct rk_lcdc_driver *dev_drv, int fps,
1392                                bool set)
1393 {
1394         struct lcdc_device *lcdc_dev =
1395             container_of(dev_drv, struct lcdc_device, driver);
1396         struct rk_screen *screen = dev_drv->cur_screen;
1397         u64 ft = 0;
1398         u32 dotclk;
1399         int ret;
1400         u32 pixclock;
1401         u32 x_total, y_total;
1402
1403         if (set) {
1404                 ft = div_u64(1000000000000llu, fps);
1405                 x_total =
1406                     screen->mode.upper_margin + screen->mode.lower_margin +
1407                     screen->mode.yres + screen->mode.vsync_len;
1408                 y_total =
1409                     screen->mode.left_margin + screen->mode.right_margin +
1410                     screen->mode.xres + screen->mode.hsync_len;
1411                 dev_drv->pixclock = div_u64(ft, x_total * y_total);
1412                 dotclk = div_u64(1000000000000llu, dev_drv->pixclock);
1413                 ret = clk_set_rate(lcdc_dev->dclk, dotclk);
1414         }
1415
1416         pixclock = div_u64(1000000000000llu, clk_get_rate(lcdc_dev->dclk));
1417         lcdc_dev->pixclock = pixclock;
1418         dev_drv->pixclock = pixclock;
1419         fps = rk_fb_calc_fps(lcdc_dev->screen, pixclock);
1420         screen->ft = 1000 / fps;        /*one frame time in ms */
1421
1422         if (set)
1423                 dev_info(dev_drv->dev, "%s:dclk:%lu,fps:%d\n", __func__,
1424                          clk_get_rate(lcdc_dev->dclk), fps);
1425
1426         return fps;
1427 }
1428
1429 static int rk3036_lcdc_poll_vblank(struct rk_lcdc_driver *dev_drv)
1430 {
1431         struct lcdc_device *lcdc_dev =
1432             container_of(dev_drv, struct lcdc_device, driver);
1433         u32 int_reg;
1434         int ret;
1435
1436         if (lcdc_dev->clk_on) {
1437                 int_reg = lcdc_readl(lcdc_dev, INT_STATUS);
1438                 if (int_reg & m_LF_INT_STA) {
1439                         lcdc_msk_reg(lcdc_dev, INT_STATUS, m_LF_INT_CLEAR,
1440                                      v_LF_INT_CLEAR(1));
1441                         ret = RK_LF_STATUS_FC;
1442                 } else {
1443                         ret = RK_LF_STATUS_FR;
1444                 }
1445         } else {
1446                 ret = RK_LF_STATUS_NC;
1447         }
1448
1449         return ret;
1450 }
1451
1452 static int rk3036_lcdc_get_dsp_addr(struct rk_lcdc_driver *dev_drv,
1453                                     unsigned int *dsp_addr)
1454 {
1455         struct lcdc_device *lcdc_dev =
1456             container_of(dev_drv, struct lcdc_device, driver);
1457
1458         if (lcdc_dev->clk_on) {
1459                 dsp_addr[0] = lcdc_readl(lcdc_dev, WIN0_YRGB_MST);
1460                 dsp_addr[1] = lcdc_readl(lcdc_dev, WIN1_MST);
1461         }
1462         return 0;
1463 }
1464
1465 static ssize_t rk3036_lcdc_get_disp_info(struct rk_lcdc_driver *dev_drv,
1466                                          char *buf, int win_id)
1467 {
1468         struct rk_lcdc_win *win = NULL;
1469         char fmt[9] = "NULL";
1470         u32     size;
1471
1472         if (win_id < ARRAY_SIZE(lcdc_win)) {
1473                 win = dev_drv->win[win_id];
1474         } else {
1475                 dev_err(dev_drv->dev, "invalid win number:%d!\n", win_id);
1476                 return 0;
1477         }
1478
1479         size = snprintf(buf, PAGE_SIZE, "win%d: %s\n", win_id,
1480                         get_format_string(win->area[0].format, fmt));
1481         size += snprintf(buf + size, PAGE_SIZE - size,
1482                          "      xact %d yact %d xvir %d yvir %d\n",
1483                 win->area[0].xact, win->area[0].yact,
1484                 win->area[0].xvir, win->area[0].yvir);
1485         size += snprintf(buf + size, PAGE_SIZE - size,
1486                          "      xpos %d ypos %d xsize %d ysize %d\n",
1487                 win->area[0].xpos, win->area[0].ypos,
1488                 win->area[0].xsize, win->area[0].ysize);
1489         size += snprintf(buf + size, PAGE_SIZE - size,
1490                          "      yaddr 0x%x uvaddr 0x%x\n",
1491                 win->area[0].y_addr, win->area[0].uv_addr);
1492         return size;
1493 }
1494
1495 static int rk3036_lcdc_reg_dump(struct rk_lcdc_driver *dev_drv)
1496 {
1497         struct lcdc_device *lcdc_dev = container_of(dev_drv,
1498                                                 struct lcdc_device,
1499                                                 driver);
1500         int *cbase = (int *)lcdc_dev->regs;
1501         int *regsbak = (int *)lcdc_dev->regsbak;
1502         int i, j;
1503
1504         dev_info(dev_drv->dev, "back up reg:\n");
1505         for (i = 0; i <= (0xDC >> 4); i++) {
1506                 for (j = 0; j < 4; j++)
1507                         dev_info(dev_drv->dev, "%08x  ",
1508                                  *(regsbak + i * 4 + j));
1509                 dev_info(dev_drv->dev, "\n");
1510         }
1511
1512         dev_info(dev_drv->dev, "lcdc reg:\n");
1513         for (i = 0; i <= (0xDC >> 4); i++) {
1514                 for (j = 0; j < 4; j++)
1515                         dev_info(dev_drv->dev, "%08x  ",
1516                                  readl_relaxed(cbase + i * 4 + j));
1517                 dev_info(dev_drv->dev, "\n");
1518         }
1519         return 0;
1520 }
1521
1522 static struct rk_lcdc_drv_ops lcdc_drv_ops = {
1523         .open                   = rk3036_lcdc_open,
1524         .load_screen            = rk3036_load_screen,
1525         .set_par                = rk3036_lcdc_set_par,
1526         .pan_display            = rk3036_lcdc_pan_display,
1527         .blank                  = rk3036_lcdc_blank,
1528         .ioctl                  = rk3036_lcdc_ioctl,
1529         .get_win_state          = rk3036_lcdc_get_win_state,
1530         .ovl_mgr                = rk3036_lcdc_ovl_mgr,
1531         .get_disp_info          = rk3036_lcdc_get_disp_info,
1532         .fps_mgr                = rk3036_lcdc_fps_mgr,
1533         .fb_get_win_id          = rk3036_lcdc_get_win_id,
1534         .fb_win_remap           = rk3036_fb_win_remap,
1535         .poll_vblank            = rk3036_lcdc_poll_vblank,
1536         .get_dsp_addr           = rk3036_lcdc_get_dsp_addr,
1537         .cfg_done               = rk3036_lcdc_cfg_done,
1538         .dump_reg               = rk3036_lcdc_reg_dump,
1539         .set_dsp_bcsh_hue       = rk3036_lcdc_set_bcsh_hue,
1540         .set_dsp_bcsh_bcs       = rk3036_lcdc_set_bcsh_bcs,
1541         .get_dsp_bcsh_hue       = rk3036_lcdc_get_bcsh_hue,
1542         .get_dsp_bcsh_bcs       = rk3036_lcdc_get_bcsh_bcs,
1543         .open_bcsh              = rk3036_lcdc_open_bcsh,
1544         .set_overscan           = rk3036_lcdc_set_overscan,
1545         .set_hwc_lut            = rk3036_lcdc_set_hwc_lut,
1546 };
1547
1548 static int rk3036_lcdc_parse_dt(struct lcdc_device *lcdc_dev)
1549 {
1550         struct device_node *np = lcdc_dev->dev->of_node;
1551         int val;
1552
1553 #if defined(CONFIG_ROCKCHIP_IOMMU)
1554         if (of_property_read_u32(np, "rockchip,iommu-enabled", &val))
1555                 lcdc_dev->driver.iommu_enabled = 0;
1556         else
1557                 lcdc_dev->driver.iommu_enabled = val;
1558 #else
1559         lcdc_dev->driver.iommu_enabled = 0;
1560 #endif
1561         if (of_property_read_u32(np, "rockchip,fb-win-map", &val))
1562                 lcdc_dev->driver.fb_win_map = FB_DEFAULT_ORDER;
1563         else
1564                 lcdc_dev->driver.fb_win_map = val;
1565
1566         return 0;
1567 }
1568
1569 static int rk3036_lcdc_probe(struct platform_device *pdev)
1570 {
1571         struct lcdc_device *lcdc_dev = NULL;
1572         struct rk_lcdc_driver *dev_drv;
1573         struct device *dev = &pdev->dev;
1574         struct resource *res;
1575         int ret;
1576
1577         lcdc_dev = devm_kzalloc(dev,
1578                                 sizeof(struct lcdc_device), GFP_KERNEL);
1579         if (!lcdc_dev) {
1580                 dev_err(&pdev->dev, "rk3036 lcdc device kmalloc fail!");
1581                 return -ENOMEM;
1582         }
1583         platform_set_drvdata(pdev, lcdc_dev);
1584         lcdc_dev->dev = dev;
1585         rk3036_lcdc_parse_dt(lcdc_dev);
1586
1587         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1588         lcdc_dev->reg_phy_base = res->start;
1589         lcdc_dev->len = resource_size(res);
1590         lcdc_dev->regs = devm_ioremap_resource(dev, res);
1591         if (IS_ERR(lcdc_dev->regs))
1592                 return PTR_ERR(lcdc_dev->regs);
1593
1594         lcdc_dev->regsbak = devm_kzalloc(dev, lcdc_dev->len, GFP_KERNEL);
1595         if (IS_ERR(lcdc_dev->regsbak))
1596                 return PTR_ERR(lcdc_dev->regsbak);
1597
1598         lcdc_dev->hwc_lut_addr_base = (lcdc_dev->regs + HWC_LUT_ADDR);
1599         lcdc_dev->prop = PRMRY;
1600         dev_set_name(lcdc_dev->dev, "lcdc%d", lcdc_dev->id);
1601         dev_drv = &lcdc_dev->driver;
1602         dev_drv->dev = dev;
1603         dev_drv->prop = PRMRY;
1604         dev_drv->id = lcdc_dev->id;
1605         dev_drv->ops = &lcdc_drv_ops;
1606         dev_drv->lcdc_win_num = ARRAY_SIZE(lcdc_win);
1607         spin_lock_init(&lcdc_dev->reg_lock);
1608
1609         lcdc_dev->irq = platform_get_irq(pdev, 0);
1610         if (lcdc_dev->irq < 0) {
1611                 dev_err(&pdev->dev, "cannot find IRQ for lcdc%d\n",
1612                         lcdc_dev->id);
1613                 return -ENXIO;
1614         }
1615
1616         ret = devm_request_irq(dev, lcdc_dev->irq, rk3036_lcdc_isr,
1617                                IRQF_DISABLED | IRQF_SHARED,
1618                                dev_name(dev), lcdc_dev);
1619         if (ret) {
1620                 dev_err(&pdev->dev, "cannot requeset irq %d - err %d\n",
1621                         lcdc_dev->irq, ret);
1622                 return ret;
1623         }
1624
1625         if (dev_drv->iommu_enabled)
1626                 strcpy(dev_drv->mmu_dts_name, VOP_IOMMU_COMPATIBLE_NAME);
1627
1628         ret = rk_fb_register(dev_drv, lcdc_win, lcdc_dev->id);
1629         if (ret < 0) {
1630                 dev_err(dev, "register fb for lcdc%d failed!\n", lcdc_dev->id);
1631                 return ret;
1632         }
1633         lcdc_dev->screen = dev_drv->screen0;
1634
1635         dev_info(dev, "lcdc probe ok, iommu %s\n",
1636                  dev_drv->iommu_enabled ? "enabled" : "disabled");
1637
1638         return 0;
1639 }
1640
1641 #if defined(CONFIG_PM)
1642 static int rk3036_lcdc_suspend(struct platform_device *pdev,
1643                                pm_message_t state)
1644 {
1645         return 0;
1646 }
1647
1648 static int rk3036_lcdc_resume(struct platform_device *pdev)
1649 {
1650         return 0;
1651 }
1652 #else
1653 #define rk3036_lcdc_suspend NULL
1654 #define rk3036_lcdc_resume  NULL
1655 #endif
1656
1657 static int rk3036_lcdc_remove(struct platform_device *pdev)
1658 {
1659         return 0;
1660 }
1661
1662 static void rk3036_lcdc_shutdown(struct platform_device *pdev)
1663 {
1664 }
1665
1666 #if defined(CONFIG_OF)
1667 static const struct of_device_id rk3036_lcdc_dt_ids[] = {
1668         {.compatible = "rockchip,rk3036-lcdc",},
1669         {}
1670 };
1671 #endif
1672
1673 static struct platform_driver rk3036_lcdc_driver = {
1674         .probe = rk3036_lcdc_probe,
1675         .remove = rk3036_lcdc_remove,
1676         .driver = {
1677                 .name = "rk3036-lcdc",
1678                 .owner = THIS_MODULE,
1679                 .of_match_table = of_match_ptr(rk3036_lcdc_dt_ids),
1680         },
1681         .suspend = rk3036_lcdc_suspend,
1682         .resume = rk3036_lcdc_resume,
1683         .shutdown = rk3036_lcdc_shutdown,
1684 };
1685
1686 static int __init rk3036_lcdc_module_init(void)
1687 {
1688         return platform_driver_register(&rk3036_lcdc_driver);
1689 }
1690
1691 static void __exit rk3036_lcdc_module_exit(void)
1692 {
1693         platform_driver_unregister(&rk3036_lcdc_driver);
1694 }
1695
1696 fs_initcall(rk3036_lcdc_module_init);
1697 module_exit(rk3036_lcdc_module_exit);